1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Support of SDHCI platform devices for Microchip PIC32. 4 * 5 * Copyright (C) 2015 Microchip 6 * Andrei Pistirica, Paul Thacker 7 * 8 * Inspired by sdhci-pltfm.c 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/highmem.h> 14 #include <linux/module.h> 15 #include <linux/interrupt.h> 16 #include <linux/irq.h> 17 #include <linux/of.h> 18 #include <linux/platform_data/sdhci-pic32.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/slab.h> 22 #include <linux/mmc/host.h> 23 #include <linux/io.h> 24 #include "sdhci.h" 25 #include "sdhci-pltfm.h" 26 27 #define SDH_SHARED_BUS_CTRL 0x000000E0 28 #define SDH_SHARED_BUS_NR_CLK_PINS_MASK 0x7 29 #define SDH_SHARED_BUS_NR_IRQ_PINS_MASK 0x30 30 #define SDH_SHARED_BUS_CLK_PINS 0x10 31 #define SDH_SHARED_BUS_IRQ_PINS 0x14 32 #define SDH_CAPS_SDH_SLOT_TYPE_MASK 0xC0000000 33 #define SDH_SLOT_TYPE_REMOVABLE 0x0 34 #define SDH_SLOT_TYPE_EMBEDDED 0x1 35 #define SDH_SLOT_TYPE_SHARED_BUS 0x2 36 #define SDHCI_CTRL_CDSSEL 0x80 37 #define SDHCI_CTRL_CDTLVL 0x40 38 39 #define ADMA_FIFO_RD_THSHLD 512 40 #define ADMA_FIFO_WR_THSHLD 512 41 42 struct pic32_sdhci_priv { 43 struct platform_device *pdev; 44 struct clk *sys_clk; 45 struct clk *base_clk; 46 }; 47 48 static unsigned int pic32_sdhci_get_max_clock(struct sdhci_host *host) 49 { 50 struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host); 51 52 return clk_get_rate(sdhci_pdata->base_clk); 53 } 54 55 static void pic32_sdhci_set_bus_width(struct sdhci_host *host, int width) 56 { 57 u8 ctrl; 58 59 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 60 if (width == MMC_BUS_WIDTH_8) { 61 ctrl &= ~SDHCI_CTRL_4BITBUS; 62 if (host->version >= SDHCI_SPEC_300) 63 ctrl |= SDHCI_CTRL_8BITBUS; 64 } else { 65 if (host->version >= SDHCI_SPEC_300) 66 ctrl &= ~SDHCI_CTRL_8BITBUS; 67 if (width == MMC_BUS_WIDTH_4) 68 ctrl |= SDHCI_CTRL_4BITBUS; 69 else 70 ctrl &= ~SDHCI_CTRL_4BITBUS; 71 } 72 73 /* CD select and test bits must be set for errata workaround. */ 74 ctrl &= ~SDHCI_CTRL_CDTLVL; 75 ctrl |= SDHCI_CTRL_CDSSEL; 76 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 77 } 78 79 static unsigned int pic32_sdhci_get_ro(struct sdhci_host *host) 80 { 81 /* 82 * The SDHCI_WRITE_PROTECT bit is unstable on current hardware so we 83 * can't depend on its value in any way. 84 */ 85 return 0; 86 } 87 88 static const struct sdhci_ops pic32_sdhci_ops = { 89 .get_max_clock = pic32_sdhci_get_max_clock, 90 .set_clock = sdhci_set_clock, 91 .set_bus_width = pic32_sdhci_set_bus_width, 92 .reset = sdhci_reset, 93 .set_uhs_signaling = sdhci_set_uhs_signaling, 94 .get_ro = pic32_sdhci_get_ro, 95 }; 96 97 static const struct sdhci_pltfm_data sdhci_pic32_pdata = { 98 .ops = &pic32_sdhci_ops, 99 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 100 .quirks2 = SDHCI_QUIRK2_NO_1_8_V, 101 }; 102 103 static void pic32_sdhci_shared_bus(struct platform_device *pdev) 104 { 105 struct sdhci_host *host = platform_get_drvdata(pdev); 106 u32 bus = readl(host->ioaddr + SDH_SHARED_BUS_CTRL); 107 u32 clk_pins = (bus & SDH_SHARED_BUS_NR_CLK_PINS_MASK) >> 0; 108 u32 irq_pins = (bus & SDH_SHARED_BUS_NR_IRQ_PINS_MASK) >> 4; 109 110 /* select first clock */ 111 if (clk_pins & 1) 112 bus |= (1 << SDH_SHARED_BUS_CLK_PINS); 113 114 /* select first interrupt */ 115 if (irq_pins & 1) 116 bus |= (1 << SDH_SHARED_BUS_IRQ_PINS); 117 118 writel(bus, host->ioaddr + SDH_SHARED_BUS_CTRL); 119 } 120 121 static void pic32_sdhci_probe_platform(struct platform_device *pdev, 122 struct pic32_sdhci_priv *pdata) 123 { 124 u32 caps_slot_type; 125 struct sdhci_host *host = platform_get_drvdata(pdev); 126 127 /* Check card slot connected on shared bus. */ 128 host->caps = readl(host->ioaddr + SDHCI_CAPABILITIES); 129 caps_slot_type = (host->caps & SDH_CAPS_SDH_SLOT_TYPE_MASK) >> 30; 130 if (caps_slot_type == SDH_SLOT_TYPE_SHARED_BUS) 131 pic32_sdhci_shared_bus(pdev); 132 } 133 134 static int pic32_sdhci_probe(struct platform_device *pdev) 135 { 136 struct sdhci_host *host; 137 struct sdhci_pltfm_host *pltfm_host; 138 struct pic32_sdhci_priv *sdhci_pdata; 139 struct pic32_sdhci_platform_data *plat_data; 140 int ret; 141 142 host = sdhci_pltfm_init(pdev, &sdhci_pic32_pdata, 143 sizeof(struct pic32_sdhci_priv)); 144 if (IS_ERR(host)) { 145 ret = PTR_ERR(host); 146 goto err; 147 } 148 149 pltfm_host = sdhci_priv(host); 150 sdhci_pdata = sdhci_pltfm_priv(pltfm_host); 151 152 plat_data = pdev->dev.platform_data; 153 if (plat_data && plat_data->setup_dma) { 154 ret = plat_data->setup_dma(ADMA_FIFO_RD_THSHLD, 155 ADMA_FIFO_WR_THSHLD); 156 if (ret) 157 goto err; 158 } 159 160 sdhci_pdata->sys_clk = devm_clk_get(&pdev->dev, "sys_clk"); 161 if (IS_ERR(sdhci_pdata->sys_clk)) { 162 ret = PTR_ERR(sdhci_pdata->sys_clk); 163 dev_err(&pdev->dev, "Error getting clock\n"); 164 goto err; 165 } 166 167 ret = clk_prepare_enable(sdhci_pdata->sys_clk); 168 if (ret) { 169 dev_err(&pdev->dev, "Error enabling clock\n"); 170 goto err; 171 } 172 173 sdhci_pdata->base_clk = devm_clk_get(&pdev->dev, "base_clk"); 174 if (IS_ERR(sdhci_pdata->base_clk)) { 175 ret = PTR_ERR(sdhci_pdata->base_clk); 176 dev_err(&pdev->dev, "Error getting clock\n"); 177 goto err_sys_clk; 178 } 179 180 ret = clk_prepare_enable(sdhci_pdata->base_clk); 181 if (ret) { 182 dev_err(&pdev->dev, "Error enabling clock\n"); 183 goto err_base_clk; 184 } 185 186 ret = mmc_of_parse(host->mmc); 187 if (ret) 188 goto err_base_clk; 189 190 pic32_sdhci_probe_platform(pdev, sdhci_pdata); 191 192 ret = sdhci_add_host(host); 193 if (ret) 194 goto err_base_clk; 195 196 dev_info(&pdev->dev, "Successfully added sdhci host\n"); 197 return 0; 198 199 err_base_clk: 200 clk_disable_unprepare(sdhci_pdata->base_clk); 201 err_sys_clk: 202 clk_disable_unprepare(sdhci_pdata->sys_clk); 203 err: 204 dev_err(&pdev->dev, "pic32-sdhci probe failed: %d\n", ret); 205 return ret; 206 } 207 208 static void pic32_sdhci_remove(struct platform_device *pdev) 209 { 210 struct sdhci_host *host = platform_get_drvdata(pdev); 211 struct pic32_sdhci_priv *sdhci_pdata = sdhci_priv(host); 212 u32 scratch; 213 214 scratch = readl(host->ioaddr + SDHCI_INT_STATUS); 215 sdhci_remove_host(host, scratch == (u32)~0); 216 clk_disable_unprepare(sdhci_pdata->base_clk); 217 clk_disable_unprepare(sdhci_pdata->sys_clk); 218 } 219 220 static const struct of_device_id pic32_sdhci_id_table[] = { 221 { .compatible = "microchip,pic32mzda-sdhci" }, 222 {} 223 }; 224 MODULE_DEVICE_TABLE(of, pic32_sdhci_id_table); 225 226 static struct platform_driver pic32_sdhci_driver = { 227 .driver = { 228 .name = "pic32-sdhci", 229 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 230 .of_match_table = of_match_ptr(pic32_sdhci_id_table), 231 }, 232 .probe = pic32_sdhci_probe, 233 .remove = pic32_sdhci_remove, 234 }; 235 236 module_platform_driver(pic32_sdhci_driver); 237 238 MODULE_DESCRIPTION("Microchip PIC32 SDHCI driver"); 239 MODULE_AUTHOR("Pistirica Sorin Andrei & Sandeep Sheriker"); 240 MODULE_LICENSE("GPL v2"); 241