1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/iopoll.h> 17 #include "sdhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pci.h" 20 #include "cqhci.h" 21 #include "sdhci-uhs2.h" 22 23 /* Genesys Logic extra registers */ 24 #define SDHCI_GLI_9750_WT 0x800 25 #define SDHCI_GLI_9750_WT_EN BIT(0) 26 #define GLI_9750_WT_EN_ON 0x1 27 #define GLI_9750_WT_EN_OFF 0x0 28 29 #define SDHCI_GLI_9750_CFG2 0x848 30 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 31 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 32 33 #define SDHCI_GLI_9750_DRIVING 0x860 34 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 35 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 36 #define GLI_9750_DRIVING_1_VALUE 0xFFF 37 #define GLI_9750_DRIVING_2_VALUE 0x3 38 #define SDHCI_GLI_9750_SEL_1 BIT(29) 39 #define SDHCI_GLI_9750_SEL_2 BIT(31) 40 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 41 42 #define SDHCI_GLI_9750_PLL 0x864 43 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 44 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 45 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 46 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 47 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 48 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 49 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 50 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 51 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 52 53 #define SDHCI_GLI_9750_PLLSSC 0x86C 54 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 55 56 #define SDHCI_GLI_9750_SW_CTRL 0x874 57 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 58 #define GLI_9750_SW_CTRL_4_VALUE 0x3 59 60 #define SDHCI_GLI_9750_MISC 0x878 61 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 62 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 63 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 64 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 65 #define GLI_9750_MISC_RX_INV_ON 0x1 66 #define GLI_9750_MISC_RX_INV_OFF 0x0 67 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 68 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 69 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 70 71 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 72 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 73 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 74 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 75 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 76 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 77 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 78 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 79 80 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 81 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 82 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 83 84 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 85 86 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 87 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 88 89 #define PCIE_GLI_9763E_VHS 0x884 90 #define GLI_9763E_VHS_REV GENMASK(19, 16) 91 #define GLI_9763E_VHS_REV_R 0x0 92 #define GLI_9763E_VHS_REV_M 0x1 93 #define GLI_9763E_VHS_REV_W 0x2 94 #define PCIE_GLI_9763E_MB 0x888 95 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 96 #define GLI_9763E_MB_ERP_ON BIT(7) 97 #define PCIE_GLI_9763E_SCR 0x8E0 98 #define GLI_9763E_SCR_AXI_REQ BIT(9) 99 100 #define PCIE_GLI_9763E_CFG 0x8A0 101 #define GLI_9763E_CFG_LPSN_DIS BIT(12) 102 103 #define PCIE_GLI_9763E_CFG2 0x8A4 104 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 105 #define GLI_9763E_CFG2_L1DLY_MID 0x54 106 107 #define PCIE_GLI_9763E_MMC_CTRL 0x960 108 #define GLI_9763E_HS400_SLOW BIT(3) 109 110 #define PCIE_GLI_9763E_CLKRXDLY 0x934 111 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 112 #define GLI_9763E_HS400_RXDLY_5 0x5 113 114 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 115 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 116 SDHCI_TRNS_BLK_CNT_EN | \ 117 SDHCI_TRNS_DMA) 118 119 #define PCI_GLI_9755_WT 0x800 120 #define PCI_GLI_9755_WT_EN BIT(0) 121 #define GLI_9755_WT_EN_ON 0x1 122 #define GLI_9755_WT_EN_OFF 0x0 123 124 #define PCI_GLI_9755_PECONF 0x44 125 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 126 #define PCI_GLI_9755_DMACLK BIT(29) 127 #define PCI_GLI_9755_INVERT_CD BIT(30) 128 #define PCI_GLI_9755_INVERT_WP BIT(31) 129 130 #define PCI_GLI_9755_CFG2 0x48 131 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 132 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 133 134 #define PCI_GLI_9755_PLL 0x64 135 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 136 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 137 #define PCI_GLI_9755_PLL_DIR BIT(15) 138 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 139 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 140 141 #define PCI_GLI_9755_PLLSSC 0x68 142 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 143 #define PCI_GLI_9755_PLLSSC_RTL BIT(24) 144 #define GLI_9755_PLLSSC_RTL_VALUE 0x1 145 #define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) 146 #define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 147 #define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) 148 #define GLI_9755_PLLSSC_RECV_VALUE 0x0 149 #define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) 150 #define GLI_9755_PLLSSC_TRAN_VALUE 0x3 151 152 #define PCI_GLI_9755_UHS2_PLL 0x6C 153 #define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) 154 #define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 155 #define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) 156 #define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 157 #define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) 158 #define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 159 160 #define PCI_GLI_9755_SerDes 0x70 161 #define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) 162 #define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 163 #define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) 164 #define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 165 #define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) 166 #define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB 167 #define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 168 #define PCI_GLI_9755_SCP_DIS BIT(19) 169 #define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) 170 #define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC 171 #define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) 172 #define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF 173 174 #define PCI_GLI_9755_MISC 0x78 175 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 176 177 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL 0x508 178 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK BIT(0) 179 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE GENMASK(21, 16) 180 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE 0x05 181 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE 0x3F 182 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE GENMASK(23, 22) 183 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS 0x2 184 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS 0x3 185 186 #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 187 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) 188 189 #define PCIE_GLI_9767_VHS 0x884 190 #define GLI_9767_VHS_REV GENMASK(19, 16) 191 #define GLI_9767_VHS_REV_R 0x0 192 #define GLI_9767_VHS_REV_M 0x1 193 #define GLI_9767_VHS_REV_W 0x2 194 195 #define PCIE_GLI_9767_COM_MAILBOX 0x888 196 #define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1) 197 198 #define PCIE_GLI_9767_CFG 0x8A0 199 #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12) 200 201 #define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8 202 #define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6) 203 #define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10) 204 205 #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0 206 #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0) 207 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12) 208 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7 209 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28) 210 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3 211 212 #define PCIE_GLI_9767_SCR 0x8E0 213 #define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6) 214 #define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7) 215 #define PCIE_GLI_9767_SCR_AXI_REQ BIT(9) 216 #define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10) 217 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16) 218 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17) 219 #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) 220 #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) 221 222 #define PCIE_GLI_9767_RESET_REG 0x8E4 223 #define PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET BIT(0) 224 225 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1 0x90C 226 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR GENMASK(31, 29) 227 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE 0x3 228 229 #define PCIE_GLI_9767_SDHC_CAP 0x91C 230 #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) 231 232 #define PCIE_GLI_9767_SD_PLL_CTL 0x938 233 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0) 234 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12) 235 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16) 236 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19) 237 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24) 238 239 #define PCIE_GLI_9767_SD_PLL_CTL2 0x93C 240 #define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16) 241 242 #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940 243 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0) 244 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) 245 246 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 247 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) 248 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL BIT(8) 249 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) 250 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 251 252 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2 0x948 253 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING GENMASK(22, 21) 254 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE 0x0 255 256 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 257 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) 258 259 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954 260 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0) 261 262 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 263 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) 264 265 #define PCIE_GLI_9767_UHS2_CTL1 0x95C 266 #define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS BIT(5) 267 #define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE 0x1 268 #define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL BIT(6) 269 #define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE 0x1 270 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN GENMASK(10, 7) 271 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE 0x3 272 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV GENMASK(14, 11) 273 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE 0xf 274 #define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS GENMASK(16, 15) 275 #define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE 0x0 276 #define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV GENMASK(18, 17) 277 #define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE 0x0 278 #define PCIE_GLI_9767_UHS2_CTL1_PDRST BIT(25) 279 #define PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE 0x1 280 281 #define PCIE_GLI_9767_UHS2_CTL2 0x964 282 #define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0) 283 #define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb 284 #define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6) 285 #define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1 286 #define PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN BIT(13) 287 #define PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE BIT(14) 288 289 #define GLI_MAX_TUNING_LOOP 40 290 291 /* Genesys Logic chipset */ 292 static void sdhci_gli_mask_replay_timer_timeout(struct pci_dev *pdev) 293 { 294 int aer; 295 u32 value; 296 297 /* mask the replay timer timeout of AER */ 298 aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 299 if (aer) { 300 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); 301 value |= PCI_ERR_COR_REP_TIMER; 302 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); 303 } 304 } 305 306 static inline void gl9750_wt_on(struct sdhci_host *host) 307 { 308 u32 wt_value; 309 u32 wt_enable; 310 311 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 312 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 313 314 if (wt_enable == GLI_9750_WT_EN_ON) 315 return; 316 317 wt_value &= ~SDHCI_GLI_9750_WT_EN; 318 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 319 320 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 321 } 322 323 static inline void gl9750_wt_off(struct sdhci_host *host) 324 { 325 u32 wt_value; 326 u32 wt_enable; 327 328 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 329 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 330 331 if (wt_enable == GLI_9750_WT_EN_OFF) 332 return; 333 334 wt_value &= ~SDHCI_GLI_9750_WT_EN; 335 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 336 337 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 338 } 339 340 static void gli_set_9750(struct sdhci_host *host) 341 { 342 u32 driving_value; 343 u32 pll_value; 344 u32 sw_ctrl_value; 345 u32 misc_value; 346 u32 parameter_value; 347 u32 control_value; 348 u16 ctrl2; 349 350 gl9750_wt_on(host); 351 352 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 353 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 354 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 355 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 356 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 357 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 358 359 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 360 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 361 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 362 GLI_9750_DRIVING_1_VALUE); 363 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 364 GLI_9750_DRIVING_2_VALUE); 365 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 366 driving_value |= SDHCI_GLI_9750_SEL_2; 367 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 368 369 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 370 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 371 GLI_9750_SW_CTRL_4_VALUE); 372 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 373 374 /* reset the tuning flow after reinit and before starting tuning */ 375 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 376 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 377 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 378 GLI_9750_PLL_TX2_INV_VALUE); 379 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 380 GLI_9750_PLL_TX2_DLY_VALUE); 381 382 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 383 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 384 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 385 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 386 GLI_9750_MISC_TX1_INV_VALUE); 387 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 388 GLI_9750_MISC_RX_INV_VALUE); 389 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 390 GLI_9750_MISC_TX1_DLY_VALUE); 391 392 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 393 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 394 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 395 396 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 397 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 398 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 399 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 400 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 401 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 402 403 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 404 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 405 406 /* disable tuned clk */ 407 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 408 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 409 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 410 411 /* enable tuning parameters control */ 412 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 413 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 414 GLI_9750_TUNING_CONTROL_EN_ON); 415 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 416 417 /* write tuning parameters */ 418 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 419 420 /* disable tuning parameters control */ 421 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 422 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 423 GLI_9750_TUNING_CONTROL_EN_OFF); 424 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 425 426 /* clear tuned clk */ 427 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 428 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 429 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 430 431 gl9750_wt_off(host); 432 } 433 434 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 435 { 436 u32 misc_value; 437 438 gl9750_wt_on(host); 439 440 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 441 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 442 if (b) { 443 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 444 GLI_9750_MISC_RX_INV_ON); 445 } else { 446 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 447 GLI_9750_MISC_RX_INV_OFF); 448 } 449 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 450 451 gl9750_wt_off(host); 452 } 453 454 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 455 { 456 int i; 457 int rx_inv; 458 459 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 460 gli_set_9750_rx_inv(host, !!rx_inv); 461 sdhci_start_tuning(host); 462 463 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 464 u16 ctrl; 465 466 sdhci_send_tuning(host, opcode); 467 468 if (!host->tuning_done) { 469 sdhci_abort_tuning(host, opcode); 470 break; 471 } 472 473 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 474 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 475 if (ctrl & SDHCI_CTRL_TUNED_CLK) 476 return 0; /* Success! */ 477 break; 478 } 479 } 480 } 481 if (!host->tuning_done) { 482 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 483 mmc_hostname(host->mmc)); 484 return -ETIMEDOUT; 485 } 486 487 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 488 mmc_hostname(host->mmc)); 489 sdhci_reset_tuning(host); 490 491 return -EAGAIN; 492 } 493 494 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 495 { 496 host->mmc->retune_period = 0; 497 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 498 host->mmc->retune_period = host->tuning_count; 499 500 gli_set_9750(host); 501 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 502 sdhci_end_tuning(host); 503 504 return 0; 505 } 506 507 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 508 { 509 u32 pll; 510 511 gl9750_wt_on(host); 512 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 513 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 514 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 515 gl9750_wt_off(host); 516 } 517 518 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 519 { 520 u32 pll; 521 522 gl9750_wt_on(host); 523 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 524 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 525 SDHCI_GLI_9750_PLL_PDIV | 526 SDHCI_GLI_9750_PLL_DIR); 527 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 528 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 529 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 530 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 531 gl9750_wt_off(host); 532 533 /* wait for pll stable */ 534 mdelay(1); 535 } 536 537 static bool gl9750_ssc_enable(struct sdhci_host *host) 538 { 539 u32 misc; 540 u8 off; 541 542 gl9750_wt_on(host); 543 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 544 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 545 gl9750_wt_off(host); 546 547 return !off; 548 } 549 550 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 551 { 552 u32 pll; 553 u32 ssc; 554 555 gl9750_wt_on(host); 556 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 557 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 558 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 559 SDHCI_GLI_9750_PLLSSC_EN); 560 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 561 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 562 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 563 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 564 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 565 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 566 gl9750_wt_off(host); 567 } 568 569 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 570 { 571 bool enable = gl9750_ssc_enable(host); 572 573 /* set pll to 205MHz and ssc */ 574 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 575 gl9750_set_pll(host, 0x1, 0x246, 0x0); 576 } 577 578 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 579 { 580 bool enable = gl9750_ssc_enable(host); 581 582 /* set pll to 100MHz and ssc */ 583 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 584 gl9750_set_pll(host, 0x1, 0x244, 0x1); 585 } 586 587 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 588 { 589 bool enable = gl9750_ssc_enable(host); 590 591 /* set pll to 50MHz and ssc */ 592 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 593 gl9750_set_pll(host, 0x1, 0x244, 0x3); 594 } 595 596 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 597 { 598 struct mmc_ios *ios = &host->mmc->ios; 599 u16 clk; 600 601 host->mmc->actual_clock = 0; 602 603 gl9750_disable_ssc_pll(host); 604 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 605 606 if (clock == 0) 607 return; 608 609 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 610 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 611 host->mmc->actual_clock = 205000000; 612 gl9750_set_ssc_pll_205mhz(host); 613 } else if (clock == 100000000) { 614 gl9750_set_ssc_pll_100mhz(host); 615 } else if (clock == 50000000) { 616 gl9750_set_ssc_pll_50mhz(host); 617 } 618 619 sdhci_enable_clk(host, clk); 620 } 621 622 static void gl9750_hw_setting(struct sdhci_host *host) 623 { 624 struct sdhci_pci_slot *slot = sdhci_priv(host); 625 struct pci_dev *pdev; 626 u32 value; 627 628 pdev = slot->chip->pdev; 629 630 gl9750_wt_on(host); 631 632 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 633 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 634 /* set ASPM L1 entry delay to 7.9us */ 635 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 636 GLI_9750_CFG2_L1DLY_VALUE); 637 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 638 639 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ 640 pci_set_power_state(pdev, PCI_D3hot); 641 pci_set_power_state(pdev, PCI_D0); 642 643 /* mask the replay timer timeout of AER */ 644 sdhci_gli_mask_replay_timer_timeout(pdev); 645 646 gl9750_wt_off(host); 647 } 648 649 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 650 { 651 int ret; 652 653 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 654 PCI_IRQ_MSI | PCI_IRQ_MSIX); 655 if (ret < 0) { 656 pr_warn("%s: enable PCI MSI failed, error=%d\n", 657 mmc_hostname(slot->host->mmc), ret); 658 return; 659 } 660 661 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 662 } 663 664 static inline void gl9755_wt_on(struct pci_dev *pdev) 665 { 666 u32 wt_value; 667 u32 wt_enable; 668 669 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 670 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 671 672 if (wt_enable == GLI_9755_WT_EN_ON) 673 return; 674 675 wt_value &= ~PCI_GLI_9755_WT_EN; 676 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 677 678 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 679 } 680 681 static inline void gl9755_wt_off(struct pci_dev *pdev) 682 { 683 u32 wt_value; 684 u32 wt_enable; 685 686 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 687 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 688 689 if (wt_enable == GLI_9755_WT_EN_OFF) 690 return; 691 692 wt_value &= ~PCI_GLI_9755_WT_EN; 693 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 694 695 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 696 } 697 698 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 699 { 700 u32 pll; 701 702 gl9755_wt_on(pdev); 703 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 704 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 705 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 706 gl9755_wt_off(pdev); 707 } 708 709 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 710 { 711 u32 pll; 712 713 gl9755_wt_on(pdev); 714 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 715 pll &= ~(PCI_GLI_9755_PLL_LDIV | 716 PCI_GLI_9755_PLL_PDIV | 717 PCI_GLI_9755_PLL_DIR); 718 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 719 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 720 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 721 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 722 gl9755_wt_off(pdev); 723 724 /* wait for pll stable */ 725 mdelay(1); 726 } 727 728 static bool gl9755_ssc_enable(struct pci_dev *pdev) 729 { 730 u32 misc; 731 u8 off; 732 733 gl9755_wt_on(pdev); 734 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 735 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 736 gl9755_wt_off(pdev); 737 738 return !off; 739 } 740 741 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 742 { 743 u32 pll; 744 u32 ssc; 745 746 gl9755_wt_on(pdev); 747 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 748 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 749 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 750 PCI_GLI_9755_PLLSSC_EN); 751 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 752 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 753 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 754 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 755 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 756 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 757 gl9755_wt_off(pdev); 758 } 759 760 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 761 { 762 bool enable = gl9755_ssc_enable(pdev); 763 764 /* set pll to 205MHz and ssc */ 765 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 766 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 767 } 768 769 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 770 { 771 bool enable = gl9755_ssc_enable(pdev); 772 773 /* set pll to 100MHz and ssc */ 774 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 775 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 776 } 777 778 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 779 { 780 bool enable = gl9755_ssc_enable(pdev); 781 782 /* set pll to 50MHz and ssc */ 783 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 784 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 785 } 786 787 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 788 { 789 struct sdhci_pci_slot *slot = sdhci_priv(host); 790 struct mmc_ios *ios = &host->mmc->ios; 791 struct pci_dev *pdev; 792 u16 clk; 793 794 pdev = slot->chip->pdev; 795 host->mmc->actual_clock = 0; 796 797 gl9755_disable_ssc_pll(pdev); 798 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 799 800 if (clock == 0) 801 return; 802 803 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 804 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 805 host->mmc->actual_clock = 205000000; 806 gl9755_set_ssc_pll_205mhz(pdev); 807 } else if (clock == 100000000) { 808 gl9755_set_ssc_pll_100mhz(pdev); 809 } else if (clock == 50000000) { 810 gl9755_set_ssc_pll_50mhz(pdev); 811 } 812 813 sdhci_enable_clk(host, clk); 814 } 815 816 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 817 { 818 struct pci_dev *pdev = slot->chip->pdev; 819 u32 value; 820 821 gl9755_wt_on(pdev); 822 823 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 824 /* 825 * Apple ARM64 platforms using these chips may have 826 * inverted CD/WP detection. 827 */ 828 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 829 value |= PCI_GLI_9755_INVERT_CD; 830 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 831 value |= PCI_GLI_9755_INVERT_WP; 832 value &= ~PCI_GLI_9755_LFCLK; 833 value &= ~PCI_GLI_9755_DMACLK; 834 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 835 836 /* enable short circuit protection */ 837 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 838 value &= ~PCI_GLI_9755_SCP_DIS; 839 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 840 841 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 842 value &= ~PCI_GLI_9755_CFG2_L1DLY; 843 /* set ASPM L1 entry delay to 7.9us */ 844 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 845 GLI_9755_CFG2_L1DLY_VALUE); 846 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 847 848 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 849 pci_set_power_state(pdev, PCI_D3hot); 850 pci_set_power_state(pdev, PCI_D0); 851 852 /* mask the replay timer timeout of AER */ 853 sdhci_gli_mask_replay_timer_timeout(pdev); 854 855 gl9755_wt_off(pdev); 856 } 857 858 static void gl9755_vendor_init(struct sdhci_host *host) 859 { 860 struct sdhci_pci_slot *slot = sdhci_priv(host); 861 struct pci_dev *pdev = slot->chip->pdev; 862 u32 serdes; 863 u32 pllssc; 864 u32 uhs2_pll; 865 866 gl9755_wt_on(pdev); 867 868 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); 869 serdes &= ~PCI_GLI_9755_UHS2_SERDES_TRAN; 870 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, 871 GLI_9755_UHS2_SERDES_TRAN_VALUE); 872 serdes &= ~PCI_GLI_9755_UHS2_SERDES_RECV; 873 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, 874 GLI_9755_UHS2_SERDES_RECV_VALUE); 875 serdes &= ~PCI_GLI_9755_UHS2_SERDES_INTR; 876 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, 877 GLI_9755_UHS2_SERDES_INTR_VALUE); 878 serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1; 879 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, 880 GLI_9755_UHS2_SERDES_ZC1_VALUE); 881 serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2; 882 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, 883 GLI_9755_UHS2_SERDES_ZC2_DEFAULT); 884 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); 885 886 pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); 887 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_SSC; 888 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, 889 GLI_9755_UHS2_PLL_SSC_VALUE); 890 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_DELAY; 891 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, 892 GLI_9755_UHS2_PLL_DELAY_VALUE); 893 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_PDRST; 894 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, 895 GLI_9755_UHS2_PLL_PDRST_VALUE); 896 pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); 897 898 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); 899 pllssc &= ~PCI_GLI_9755_PLLSSC_RTL; 900 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, 901 GLI_9755_PLLSSC_RTL_VALUE); 902 pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASS; 903 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, 904 GLI_9755_PLLSSC_TRANS_PASS_VALUE); 905 pllssc &= ~PCI_GLI_9755_PLLSSC_RECV; 906 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, 907 GLI_9755_PLLSSC_RECV_VALUE); 908 pllssc &= ~PCI_GLI_9755_PLLSSC_TRAN; 909 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, 910 GLI_9755_PLLSSC_TRAN_VALUE); 911 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); 912 913 gl9755_wt_off(pdev); 914 } 915 916 static void sdhci_gli_pre_detect_init(struct sdhci_host *host) 917 { 918 /* Need more time on UHS2 detect flow */ 919 sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); 920 } 921 922 static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bool enable) 923 { 924 u32 mask; 925 926 mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); 927 if (enable) 928 mask |= SDHCI_INT_BUS_POWER; 929 else 930 mask &= ~SDHCI_INT_BUS_POWER; 931 932 sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); 933 934 mask = sdhci_readl(host, SDHCI_INT_ENABLE); 935 if (enable) 936 mask |= SDHCI_INT_BUS_POWER; 937 else 938 mask &= ~SDHCI_INT_BUS_POWER; 939 940 sdhci_writel(host, mask, SDHCI_INT_ENABLE); 941 } 942 943 static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, 944 unsigned short vdd) 945 { 946 u8 pwr = 0; 947 948 if (mode != MMC_POWER_OFF) { 949 pwr = sdhci_get_vdd_value(vdd); 950 if (!pwr) 951 WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); 952 pwr |= SDHCI_VDD2_POWER_180; 953 } 954 955 if (host->pwr == pwr) 956 return; 957 958 host->pwr = pwr; 959 960 if (pwr == 0) { 961 sdhci_gli_overcurrent_event_enable(host, false); 962 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 963 } else { 964 sdhci_gli_overcurrent_event_enable(host, false); 965 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 966 967 pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); 968 969 sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); 970 /* wait stable */ 971 mdelay(5); 972 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 973 /* wait stable */ 974 mdelay(5); 975 sdhci_gli_overcurrent_event_enable(host, true); 976 } 977 } 978 979 static bool sdhci_wait_clock_stable(struct sdhci_host *host) 980 { 981 u16 clk = 0; 982 983 if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), 984 10, 20000, false, host, SDHCI_CLOCK_CONTROL)) { 985 pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); 986 sdhci_dumpregs(host); 987 return false; 988 } 989 return true; 990 } 991 992 static void sdhci_gli_enable_internal_clock(struct sdhci_host *host) 993 { 994 u16 ctrl2; 995 996 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 997 998 sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); 999 1000 if (!((ctrl2 & SDHCI_CTRL_V4_MODE) && 1001 (ctrl2 & SDHCI_CTRL_UHS2_ENABLE))) { 1002 sdhci_wait_clock_stable(host); 1003 sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); 1004 } 1005 } 1006 1007 static int sdhci_gli_wait_software_reset_done(struct sdhci_host *host, u8 mask) 1008 { 1009 u8 rst; 1010 1011 /* hw clears the bit when it's done */ 1012 if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask), 1013 10, 100000, false, host, SDHCI_SOFTWARE_RESET)) { 1014 pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); 1015 sdhci_dumpregs(host); 1016 /* manual clear */ 1017 sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); 1018 return -ETIMEDOUT; 1019 } 1020 1021 return 0; 1022 } 1023 1024 static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) 1025 { 1026 /* do this on UHS2 mode */ 1027 if (host->mmc->uhs2_sd_tran) { 1028 sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); 1029 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1030 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1031 sdhci_uhs2_clear_set_irqs(host, 1032 SDHCI_INT_ALL_MASK, 1033 SDHCI_UHS2_INT_ERROR_MASK); 1034 } 1035 } 1036 1037 static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) 1038 { 1039 /* need internal clock */ 1040 if (mask & SDHCI_RESET_ALL) 1041 sdhci_gli_enable_internal_clock(host); 1042 1043 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1044 1045 /* reset sd-tran on UHS2 mode if need to reset cmd/data */ 1046 if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) 1047 sdhci_gli_uhs2_reset_sd_tran(host); 1048 1049 if (mask & SDHCI_RESET_ALL) 1050 host->clock = 0; 1051 1052 sdhci_gli_wait_software_reset_done(host, mask); 1053 } 1054 1055 static inline void gl9767_vhs_read(struct pci_dev *pdev) 1056 { 1057 u32 vhs_enable; 1058 u32 vhs_value; 1059 1060 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 1061 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 1062 1063 if (vhs_enable == GLI_9767_VHS_REV_R) 1064 return; 1065 1066 vhs_value &= ~GLI_9767_VHS_REV; 1067 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R); 1068 1069 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 1070 } 1071 1072 static inline void gl9767_vhs_write(struct pci_dev *pdev) 1073 { 1074 u32 vhs_enable; 1075 u32 vhs_value; 1076 1077 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 1078 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 1079 1080 if (vhs_enable == GLI_9767_VHS_REV_W) 1081 return; 1082 1083 vhs_value &= ~GLI_9767_VHS_REV; 1084 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W); 1085 1086 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 1087 } 1088 1089 static bool gl9767_ssc_enable(struct pci_dev *pdev) 1090 { 1091 u32 value; 1092 u8 enable; 1093 1094 gl9767_vhs_write(pdev); 1095 1096 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value); 1097 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); 1098 1099 gl9767_vhs_read(pdev); 1100 1101 return enable; 1102 } 1103 1104 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 1105 { 1106 u32 pll; 1107 u32 ssc; 1108 1109 gl9767_vhs_write(pdev); 1110 1111 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1112 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); 1113 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING | 1114 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 1115 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; 1116 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) | 1117 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); 1118 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); 1119 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); 1120 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1121 1122 gl9767_vhs_read(pdev); 1123 } 1124 1125 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 1126 { 1127 u32 pll; 1128 1129 gl9767_vhs_write(pdev); 1130 1131 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1132 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV | 1133 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV | 1134 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN); 1135 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) | 1136 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) | 1137 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir); 1138 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1139 1140 gl9767_vhs_read(pdev); 1141 1142 /* wait for pll stable */ 1143 usleep_range(1000, 1100); 1144 } 1145 1146 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev) 1147 { 1148 bool enable = gl9767_ssc_enable(pdev); 1149 1150 /* set pll to 205MHz and ssc */ 1151 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); 1152 gl9767_set_pll(pdev, 0x1, 0x246, 0x0); 1153 } 1154 1155 static void gl9767_disable_ssc_pll(struct pci_dev *pdev) 1156 { 1157 u32 pll; 1158 1159 gl9767_vhs_write(pdev); 1160 1161 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1162 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 1163 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1164 1165 gl9767_vhs_read(pdev); 1166 } 1167 1168 static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable) 1169 { 1170 u32 value; 1171 1172 gl9767_vhs_write(pdev); 1173 1174 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1175 if (enable) 1176 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1177 else 1178 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1179 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1180 1181 gl9767_vhs_read(pdev); 1182 } 1183 1184 static void sdhci_gl9767_uhs2_phy_reset(struct sdhci_host *host, bool assert) 1185 { 1186 struct sdhci_pci_slot *slot = sdhci_priv(host); 1187 struct pci_dev *pdev = slot->chip->pdev; 1188 u32 value, set, clr; 1189 1190 if (assert) { 1191 /* Assert reset, set RESETN and clean RESETN_VALUE */ 1192 set = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; 1193 clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; 1194 } else { 1195 /* De-assert reset, clean RESETN and set RESETN_VALUE */ 1196 set = PCIE_GLI_9767_UHS2_CTL2_FORCE_RESETN_VALUE; 1197 clr = PCIE_GLI_9767_UHS2_CTL2_FORCE_PHY_RESETN; 1198 } 1199 1200 gl9767_vhs_write(pdev); 1201 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); 1202 value |= set; 1203 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); 1204 value &= ~clr; 1205 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); 1206 gl9767_vhs_read(pdev); 1207 } 1208 1209 static void __gl9767_uhs2_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) 1210 { 1211 u8 pwr = 0; 1212 1213 if (mode != MMC_POWER_OFF) { 1214 pwr = sdhci_get_vdd_value(vdd); 1215 if (!pwr) 1216 WARN(1, "%s: Invalid vdd %#x\n", 1217 mmc_hostname(host->mmc), vdd); 1218 pwr |= SDHCI_VDD2_POWER_180; 1219 } 1220 1221 if (host->pwr == pwr) 1222 return; 1223 1224 host->pwr = pwr; 1225 1226 if (pwr == 0) { 1227 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1228 } else { 1229 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 1230 1231 pwr |= SDHCI_POWER_ON; 1232 sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); 1233 usleep_range(5000, 6250); 1234 1235 /* Assert reset */ 1236 sdhci_gl9767_uhs2_phy_reset(host, true); 1237 pwr |= SDHCI_VDD2_POWER_ON; 1238 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 1239 usleep_range(5000, 6250); 1240 } 1241 } 1242 1243 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) 1244 { 1245 struct sdhci_pci_slot *slot = sdhci_priv(host); 1246 struct mmc_ios *ios = &host->mmc->ios; 1247 struct pci_dev *pdev; 1248 u16 clk; 1249 1250 pdev = slot->chip->pdev; 1251 host->mmc->actual_clock = 0; 1252 1253 gl9767_set_low_power_negotiation(pdev, false); 1254 gl9767_disable_ssc_pll(pdev); 1255 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1256 1257 if (clock == 0) { 1258 gl9767_set_low_power_negotiation(pdev, true); 1259 return; 1260 } 1261 1262 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1263 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 1264 host->mmc->actual_clock = 205000000; 1265 gl9767_set_ssc_pll_205mhz(pdev); 1266 } 1267 1268 sdhci_enable_clk(host, clk); 1269 1270 if (mmc_card_uhs2(host->mmc)) 1271 /* De-assert reset */ 1272 sdhci_gl9767_uhs2_phy_reset(host, false); 1273 1274 gl9767_set_low_power_negotiation(pdev, true); 1275 } 1276 1277 static void sdhci_gl9767_set_card_detect_debounce_time(struct sdhci_host *host) 1278 { 1279 u32 value; 1280 1281 value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1282 value &= ~(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE | 1283 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE); 1284 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) 1285 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, 1286 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE) | 1287 FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, 1288 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS); 1289 else 1290 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, 1291 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE) | 1292 FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, 1293 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS); 1294 sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1295 } 1296 1297 static void sdhci_gl9767_card_event(struct sdhci_host *host) 1298 { 1299 sdhci_gl9767_set_card_detect_debounce_time(host); 1300 } 1301 1302 static void gli_set_9767(struct sdhci_host *host) 1303 { 1304 u32 value; 1305 1306 value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE); 1307 value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; 1308 sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE); 1309 1310 value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1311 value &= ~SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK; 1312 sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1313 1314 sdhci_gl9767_set_card_detect_debounce_time(host); 1315 } 1316 1317 static void gl9767_hw_setting(struct sdhci_pci_slot *slot) 1318 { 1319 struct pci_dev *pdev = slot->chip->pdev; 1320 u32 value; 1321 1322 gl9767_vhs_write(pdev); 1323 1324 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value); 1325 value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 1326 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE | 1327 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL); 1328 1329 value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 1330 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE, 1331 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) | 1332 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL, 1333 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE); 1334 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value); 1335 1336 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value); 1337 value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 | 1338 PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 | 1339 PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN); 1340 1341 value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST | 1342 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST | 1343 PCIE_GLI_9767_SCR_AXI_REQ | 1344 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN | 1345 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF; 1346 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value); 1347 1348 gl9767_vhs_read(pdev); 1349 } 1350 1351 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) 1352 { 1353 struct sdhci_pci_slot *slot = sdhci_priv(host); 1354 struct pci_dev *pdev = slot->chip->pdev; 1355 u32 value; 1356 1357 /* need internal clock */ 1358 if (mask & SDHCI_RESET_ALL) { 1359 sdhci_gli_enable_internal_clock(host); 1360 1361 gl9767_vhs_write(pdev); 1362 1363 pci_read_config_dword(pdev, PCIE_GLI_9767_RESET_REG, &value); 1364 value &= ~PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET; 1365 pci_write_config_dword(pdev, PCIE_GLI_9767_RESET_REG, value); 1366 1367 if (read_poll_timeout_atomic(pci_read_config_dword, value, 1368 !(value & PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET), 1369 1, 5, true, pdev, PCIE_GLI_9767_RESET_REG, &value)) { 1370 pr_warn("%s: %s: Reset SDHC AHB and TL-AMBA failure.\n", 1371 __func__, mmc_hostname(host->mmc)); 1372 gl9767_vhs_read(pdev); 1373 return; 1374 } 1375 gl9767_vhs_read(pdev); 1376 } 1377 1378 if (mmc_card_uhs2(host->mmc)) { 1379 if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) { 1380 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1381 sdhci_gli_uhs2_reset_sd_tran(host); 1382 sdhci_gli_wait_software_reset_done(host, mask); 1383 } else { 1384 sdhci_uhs2_reset(host, mask); 1385 } 1386 } else { 1387 sdhci_reset(host, mask); 1388 } 1389 1390 gli_set_9767(host); 1391 } 1392 1393 static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 1394 { 1395 struct sdhci_host *host = mmc_priv(mmc); 1396 struct sdhci_pci_slot *slot = sdhci_priv(host); 1397 struct pci_dev *pdev; 1398 u32 value; 1399 int i; 1400 1401 pdev = slot->chip->pdev; 1402 1403 if (mmc->ops->get_ro(mmc)) { 1404 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1405 return 0; 1406 } 1407 1408 gl9767_vhs_write(pdev); 1409 1410 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value); 1411 value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN); 1412 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value); 1413 1414 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1415 value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME; 1416 value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME, 1417 PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE); 1418 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1419 1420 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1421 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE; 1422 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value); 1423 1424 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value); 1425 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN; 1426 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value); 1427 1428 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value); 1429 value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN; 1430 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value); 1431 1432 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1433 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1434 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1435 1436 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1437 value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1438 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1439 1440 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1441 value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1442 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1443 1444 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1445 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE; 1446 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1447 1448 for (i = 0; i < 2; i++) { 1449 usleep_range(10000, 10100); 1450 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1451 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) { 1452 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, 1453 value); 1454 break; 1455 } 1456 } 1457 1458 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value); 1459 if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) { 1460 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1461 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE; 1462 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1463 } else { 1464 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1465 1466 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1467 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1468 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1469 1470 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1471 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1472 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1473 } 1474 1475 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1476 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1477 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1478 gl9767_vhs_read(pdev); 1479 1480 return 0; 1481 } 1482 1483 static void gl9767_vendor_init(struct sdhci_host *host) 1484 { 1485 struct sdhci_pci_slot *slot = sdhci_priv(host); 1486 struct pci_dev *pdev = slot->chip->pdev; 1487 u32 value; 1488 1489 gl9767_vhs_write(pdev); 1490 1491 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, &value); 1492 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR, 1493 PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE); 1494 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, value); 1495 1496 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value); 1497 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING, 1498 PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE); 1499 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, value); 1500 1501 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, &value); 1502 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS, 1503 PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) | 1504 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL, 1505 PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE) | 1506 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN, 1507 PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE) | 1508 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV, 1509 PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE) | 1510 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS, 1511 PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE) | 1512 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV, 1513 PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE) | 1514 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRST, 1515 PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE); 1516 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, value); 1517 1518 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); 1519 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC, 1520 PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE) | 1521 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL, 1522 PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE); 1523 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); 1524 1525 gl9767_vhs_read(pdev); 1526 } 1527 1528 static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) 1529 { 1530 struct sdhci_pci_slot *slot = sdhci_priv(host); 1531 struct pci_dev *pdev = slot->chip->pdev; 1532 u32 value; 1533 1534 if (mmc_card_uhs2(host->mmc)) { 1535 gl9767_vhs_write(pdev); 1536 1537 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1538 value |= PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | 1539 PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL; 1540 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1541 1542 gl9767_vhs_read(pdev); 1543 1544 sdhci_gli_overcurrent_event_enable(host, false); 1545 __gl9767_uhs2_set_power(host, mode, vdd); 1546 sdhci_gli_overcurrent_event_enable(host, true); 1547 } else { 1548 gl9767_vhs_write(pdev); 1549 1550 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1551 value &= ~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | 1552 PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL); 1553 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1554 1555 gl9767_vhs_read(pdev); 1556 1557 sdhci_gli_overcurrent_event_enable(host, false); 1558 sdhci_set_power(host, mode, vdd); 1559 sdhci_gli_overcurrent_event_enable(host, true); 1560 } 1561 } 1562 1563 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 1564 { 1565 struct sdhci_host *host = slot->host; 1566 1567 gl9750_hw_setting(host); 1568 gli_pcie_enable_msi(slot); 1569 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1570 sdhci_enable_v4_mode(host); 1571 1572 return 0; 1573 } 1574 1575 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 1576 { 1577 struct sdhci_host *host = slot->host; 1578 1579 gl9755_hw_setting(slot); 1580 gli_pcie_enable_msi(slot); 1581 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1582 sdhci_enable_v4_mode(host); 1583 gl9755_vendor_init(host); 1584 1585 return 0; 1586 } 1587 1588 static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot) 1589 { 1590 struct sdhci_host *host = slot->host; 1591 1592 gli_set_9767(host); 1593 gl9767_hw_setting(slot); 1594 gli_pcie_enable_msi(slot); 1595 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1596 host->mmc->caps2 |= MMC_CAP2_SD_EXP; 1597 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; 1598 sdhci_enable_v4_mode(host); 1599 gl9767_vendor_init(host); 1600 1601 return 0; 1602 } 1603 1604 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 1605 { 1606 /* 1607 * According to Section 3.6.1 signal voltage switch procedure in 1608 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1609 * follows: 1610 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1611 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1612 * period. 1613 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1614 * step (12). 1615 * 1616 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1617 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 1618 * 1619 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 1620 * slightly longer than 5ms before the control register reports that 1621 * 1.8V is ready, and far longer still before the card will actually 1622 * work reliably. 1623 */ 1624 usleep_range(100000, 110000); 1625 } 1626 1627 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host) 1628 { 1629 /* 1630 * According to Section 3.6.1 signal voltage switch procedure in 1631 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1632 * follows: 1633 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1634 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1635 * period. 1636 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1637 * step (12). 1638 * 1639 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1640 * to ensure 1.8V signal enable bit is set by GL9767. 1641 * 1642 */ 1643 usleep_range(5000, 5500); 1644 } 1645 1646 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 1647 { 1648 sdhci_reset(host, mask); 1649 gli_set_9750(host); 1650 } 1651 1652 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 1653 { 1654 u32 value; 1655 1656 value = readl(host->ioaddr + reg); 1657 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 1658 value |= 0xc8; 1659 1660 return value; 1661 } 1662 1663 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 1664 struct mmc_ios *ios) 1665 { 1666 struct sdhci_host *host = mmc_priv(mmc); 1667 u32 val; 1668 1669 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 1670 if (ios->enhanced_strobe) 1671 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 1672 else 1673 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 1674 1675 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 1676 } 1677 1678 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, 1679 bool enable) 1680 { 1681 struct pci_dev *pdev = slot->chip->pdev; 1682 u32 value; 1683 1684 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1685 value &= ~GLI_9763E_VHS_REV; 1686 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1687 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1688 1689 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value); 1690 1691 if (enable) 1692 value &= ~GLI_9763E_CFG_LPSN_DIS; 1693 else 1694 value |= GLI_9763E_CFG_LPSN_DIS; 1695 1696 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value); 1697 1698 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1699 value &= ~GLI_9763E_VHS_REV; 1700 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1701 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1702 } 1703 1704 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 1705 unsigned int timing) 1706 { 1707 u16 ctrl_2; 1708 1709 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1710 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1711 if (timing == MMC_TIMING_MMC_HS200) 1712 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1713 else if (timing == MMC_TIMING_MMC_HS) 1714 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1715 else if (timing == MMC_TIMING_MMC_DDR52) 1716 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1717 else if (timing == MMC_TIMING_MMC_HS400) 1718 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 1719 1720 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1721 } 1722 1723 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 1724 { 1725 sdhci_dumpregs(mmc_priv(mmc)); 1726 } 1727 1728 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 1729 { 1730 struct cqhci_host *cq_host = mmc->cqe_private; 1731 u32 value; 1732 1733 value = cqhci_readl(cq_host, CQHCI_CFG); 1734 value |= CQHCI_ENABLE; 1735 cqhci_writel(cq_host, value, CQHCI_CFG); 1736 } 1737 1738 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 1739 { 1740 struct sdhci_host *host = mmc_priv(mmc); 1741 1742 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1743 sdhci_cqe_enable(mmc); 1744 } 1745 1746 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 1747 { 1748 int cmd_error = 0; 1749 int data_error = 0; 1750 1751 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1752 return intmask; 1753 1754 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1755 1756 return 0; 1757 } 1758 1759 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 1760 { 1761 struct sdhci_host *host = mmc_priv(mmc); 1762 struct cqhci_host *cq_host = mmc->cqe_private; 1763 u32 value; 1764 1765 value = cqhci_readl(cq_host, CQHCI_CFG); 1766 value &= ~CQHCI_ENABLE; 1767 cqhci_writel(cq_host, value, CQHCI_CFG); 1768 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1769 } 1770 1771 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 1772 .enable = sdhci_gl9763e_cqe_enable, 1773 .disable = sdhci_cqe_disable, 1774 .dumpregs = sdhci_gl9763e_dumpregs, 1775 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 1776 .post_disable = sdhci_gl9763e_cqe_post_disable, 1777 }; 1778 1779 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 1780 { 1781 struct device *dev = &slot->chip->pdev->dev; 1782 struct sdhci_host *host = slot->host; 1783 struct cqhci_host *cq_host; 1784 bool dma64; 1785 int ret; 1786 1787 ret = sdhci_setup_host(host); 1788 if (ret) 1789 return ret; 1790 1791 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1792 if (!cq_host) { 1793 ret = -ENOMEM; 1794 goto cleanup; 1795 } 1796 1797 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 1798 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 1799 1800 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1801 if (dma64) 1802 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1803 1804 ret = cqhci_init(cq_host, host->mmc, dma64); 1805 if (ret) 1806 goto cleanup; 1807 1808 ret = __sdhci_add_host(host); 1809 if (ret) 1810 goto cleanup; 1811 1812 /* Disable LPM negotiation to avoid entering L1 state. */ 1813 gl9763e_set_low_power_negotiation(slot, false); 1814 1815 return 0; 1816 1817 cleanup: 1818 sdhci_cleanup_host(host); 1819 return ret; 1820 } 1821 1822 static void gl9763e_hw_setting(struct sdhci_pci_slot *slot) 1823 { 1824 struct pci_dev *pdev = slot->chip->pdev; 1825 u32 value; 1826 1827 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1828 value &= ~GLI_9763E_VHS_REV; 1829 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1830 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1831 1832 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 1833 value |= GLI_9763E_SCR_AXI_REQ; 1834 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 1835 1836 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 1837 value &= ~GLI_9763E_HS400_SLOW; 1838 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 1839 1840 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 1841 value &= ~GLI_9763E_CFG2_L1DLY; 1842 /* set ASPM L1 entry delay to 21us */ 1843 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 1844 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 1845 1846 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 1847 value &= ~GLI_9763E_HS400_RXDLY; 1848 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 1849 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 1850 1851 /* mask the replay timer timeout of AER */ 1852 sdhci_gli_mask_replay_timer_timeout(pdev); 1853 1854 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1855 value &= ~GLI_9763E_VHS_REV; 1856 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1857 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1858 } 1859 1860 #ifdef CONFIG_PM 1861 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 1862 { 1863 struct sdhci_pci_slot *slot = chip->slots[0]; 1864 struct sdhci_host *host = slot->host; 1865 u16 clock; 1866 1867 /* Enable LPM negotiation to allow entering L1 state */ 1868 gl9763e_set_low_power_negotiation(slot, true); 1869 1870 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1871 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 1872 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1873 1874 return 0; 1875 } 1876 1877 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 1878 { 1879 struct sdhci_pci_slot *slot = chip->slots[0]; 1880 struct sdhci_host *host = slot->host; 1881 u16 clock; 1882 1883 if (host->mmc->ios.power_mode != MMC_POWER_ON) 1884 return 0; 1885 1886 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1887 1888 clock |= SDHCI_CLOCK_PLL_EN; 1889 clock &= ~SDHCI_CLOCK_INT_STABLE; 1890 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1891 1892 /* Wait max 150 ms */ 1893 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 1894 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 1895 pr_err("%s: PLL clock never stabilised.\n", 1896 mmc_hostname(host->mmc)); 1897 sdhci_dumpregs(host); 1898 } 1899 1900 clock |= SDHCI_CLOCK_CARD_EN; 1901 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1902 1903 /* Disable LPM negotiation to avoid entering L1 state. */ 1904 gl9763e_set_low_power_negotiation(slot, false); 1905 1906 return 0; 1907 } 1908 #endif 1909 1910 #ifdef CONFIG_PM_SLEEP 1911 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 1912 { 1913 struct sdhci_pci_slot *slot = chip->slots[0]; 1914 1915 pci_free_irq_vectors(slot->chip->pdev); 1916 gli_pcie_enable_msi(slot); 1917 1918 return sdhci_pci_resume_host(chip); 1919 } 1920 1921 static int gl9763e_resume(struct sdhci_pci_chip *chip) 1922 { 1923 struct sdhci_pci_slot *slot = chip->slots[0]; 1924 int ret; 1925 1926 ret = sdhci_pci_gli_resume(chip); 1927 if (ret) 1928 return ret; 1929 1930 ret = cqhci_resume(slot->host->mmc); 1931 if (ret) 1932 return ret; 1933 1934 /* 1935 * Disable LPM negotiation to bring device back in sync 1936 * with its runtime_pm state. 1937 */ 1938 gl9763e_set_low_power_negotiation(slot, false); 1939 1940 return 0; 1941 } 1942 1943 static int gl9763e_suspend(struct sdhci_pci_chip *chip) 1944 { 1945 struct sdhci_pci_slot *slot = chip->slots[0]; 1946 int ret; 1947 1948 /* 1949 * Certain SoCs can suspend only with the bus in low- 1950 * power state, notably x86 SoCs when using S0ix. 1951 * Re-enable LPM negotiation to allow entering L1 state 1952 * and entering system suspend. 1953 */ 1954 gl9763e_set_low_power_negotiation(slot, true); 1955 1956 ret = cqhci_suspend(slot->host->mmc); 1957 if (ret) 1958 goto err_suspend; 1959 1960 ret = sdhci_suspend_host(slot->host); 1961 if (ret) 1962 goto err_suspend_host; 1963 1964 return 0; 1965 1966 err_suspend_host: 1967 cqhci_resume(slot->host->mmc); 1968 err_suspend: 1969 gl9763e_set_low_power_negotiation(slot, false); 1970 return ret; 1971 } 1972 #endif 1973 1974 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 1975 { 1976 struct pci_dev *pdev = slot->chip->pdev; 1977 struct sdhci_host *host = slot->host; 1978 u32 value; 1979 1980 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1981 MMC_CAP_1_8V_DDR | 1982 MMC_CAP_NONREMOVABLE; 1983 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1984 MMC_CAP2_HS400_1_8V | 1985 MMC_CAP2_HS400_ES | 1986 MMC_CAP2_NO_SDIO | 1987 MMC_CAP2_NO_SD; 1988 1989 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1990 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 1991 if (value & GLI_9763E_MB_ERP_ON) 1992 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1993 1994 gli_pcie_enable_msi(slot); 1995 host->mmc_host_ops.hs400_enhanced_strobe = 1996 gl9763e_hs400_enhanced_strobe; 1997 gl9763e_hw_setting(slot); 1998 sdhci_enable_v4_mode(host); 1999 2000 return 0; 2001 } 2002 2003 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 2004 2005 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 2006 { 2007 u32 val = readl(host->ioaddr + (reg & ~3)); 2008 u16 word; 2009 2010 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 2011 return word; 2012 } 2013 2014 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 2015 { 2016 u32 val = readl(host->ioaddr + (reg & ~3)); 2017 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 2018 2019 return byte; 2020 } 2021 2022 static const struct sdhci_ops sdhci_gl9755_ops = { 2023 .read_w = sdhci_gli_readw, 2024 .read_b = sdhci_gli_readb, 2025 .set_clock = sdhci_gl9755_set_clock, 2026 .set_power = gl9755_set_power, 2027 .enable_dma = sdhci_pci_enable_dma, 2028 .set_bus_width = sdhci_set_bus_width, 2029 .reset = sdhci_gl9755_reset, 2030 .set_uhs_signaling = sdhci_set_uhs_signaling, 2031 .voltage_switch = sdhci_gli_voltage_switch, 2032 .dump_uhs2_regs = sdhci_uhs2_dump_regs, 2033 .set_timeout = sdhci_uhs2_set_timeout, 2034 .irq = sdhci_uhs2_irq, 2035 .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, 2036 }; 2037 2038 const struct sdhci_pci_fixes sdhci_gl9755 = { 2039 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2040 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2041 .probe_slot = gli_probe_slot_gl9755, 2042 .add_host = sdhci_pci_uhs2_add_host, 2043 .remove_host = sdhci_pci_uhs2_remove_host, 2044 .ops = &sdhci_gl9755_ops, 2045 #ifdef CONFIG_PM_SLEEP 2046 .resume = sdhci_pci_gli_resume, 2047 #endif 2048 }; 2049 2050 static const struct sdhci_ops sdhci_gl9750_ops = { 2051 .read_w = sdhci_gli_readw, 2052 .read_b = sdhci_gli_readb, 2053 .read_l = sdhci_gl9750_readl, 2054 .set_clock = sdhci_gl9750_set_clock, 2055 .enable_dma = sdhci_pci_enable_dma, 2056 .set_bus_width = sdhci_set_bus_width, 2057 .reset = sdhci_gl9750_reset, 2058 .set_uhs_signaling = sdhci_set_uhs_signaling, 2059 .voltage_switch = sdhci_gli_voltage_switch, 2060 .platform_execute_tuning = gl9750_execute_tuning, 2061 }; 2062 2063 const struct sdhci_pci_fixes sdhci_gl9750 = { 2064 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2065 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2066 .probe_slot = gli_probe_slot_gl9750, 2067 .ops = &sdhci_gl9750_ops, 2068 #ifdef CONFIG_PM_SLEEP 2069 .resume = sdhci_pci_gli_resume, 2070 #endif 2071 }; 2072 2073 static const struct sdhci_ops sdhci_gl9763e_ops = { 2074 .set_clock = sdhci_set_clock, 2075 .enable_dma = sdhci_pci_enable_dma, 2076 .set_bus_width = sdhci_set_bus_width, 2077 .reset = sdhci_and_cqhci_reset, 2078 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 2079 .voltage_switch = sdhci_gli_voltage_switch, 2080 .irq = sdhci_gl9763e_cqhci_irq, 2081 }; 2082 2083 const struct sdhci_pci_fixes sdhci_gl9763e = { 2084 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2085 .probe_slot = gli_probe_slot_gl9763e, 2086 .ops = &sdhci_gl9763e_ops, 2087 #ifdef CONFIG_PM_SLEEP 2088 .resume = gl9763e_resume, 2089 .suspend = gl9763e_suspend, 2090 #endif 2091 #ifdef CONFIG_PM 2092 .runtime_suspend = gl9763e_runtime_suspend, 2093 .runtime_resume = gl9763e_runtime_resume, 2094 .allow_runtime_pm = true, 2095 #endif 2096 .add_host = gl9763e_add_host, 2097 }; 2098 2099 static const struct sdhci_ops sdhci_gl9767_ops = { 2100 .set_clock = sdhci_gl9767_set_clock, 2101 .enable_dma = sdhci_pci_enable_dma, 2102 .set_bus_width = sdhci_set_bus_width, 2103 .reset = sdhci_gl9767_reset, 2104 .set_uhs_signaling = sdhci_set_uhs_signaling, 2105 .voltage_switch = sdhci_gl9767_voltage_switch, 2106 .dump_uhs2_regs = sdhci_uhs2_dump_regs, 2107 .set_timeout = sdhci_uhs2_set_timeout, 2108 .irq = sdhci_uhs2_irq, 2109 .set_power = sdhci_gl9767_set_power, 2110 .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, 2111 .card_event = sdhci_gl9767_card_event, 2112 }; 2113 2114 const struct sdhci_pci_fixes sdhci_gl9767 = { 2115 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2116 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2117 .probe_slot = gli_probe_slot_gl9767, 2118 .add_host = sdhci_pci_uhs2_add_host, 2119 .remove_host = sdhci_pci_uhs2_remove_host, 2120 .ops = &sdhci_gl9767_ops, 2121 #ifdef CONFIG_PM_SLEEP 2122 .resume = sdhci_pci_gli_resume, 2123 #endif 2124 }; 2125