1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/iopoll.h> 17 #include "sdhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pci.h" 20 #include "cqhci.h" 21 22 /* Genesys Logic extra registers */ 23 #define SDHCI_GLI_9750_WT 0x800 24 #define SDHCI_GLI_9750_WT_EN BIT(0) 25 #define GLI_9750_WT_EN_ON 0x1 26 #define GLI_9750_WT_EN_OFF 0x0 27 28 #define SDHCI_GLI_9750_CFG2 0x848 29 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 30 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 31 32 #define SDHCI_GLI_9750_DRIVING 0x860 33 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 34 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 35 #define GLI_9750_DRIVING_1_VALUE 0xFFF 36 #define GLI_9750_DRIVING_2_VALUE 0x3 37 #define SDHCI_GLI_9750_SEL_1 BIT(29) 38 #define SDHCI_GLI_9750_SEL_2 BIT(31) 39 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 40 41 #define SDHCI_GLI_9750_PLL 0x864 42 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 43 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 44 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 45 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 46 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 47 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 48 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 49 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 50 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 51 52 #define SDHCI_GLI_9750_PLLSSC 0x86C 53 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 54 55 #define SDHCI_GLI_9750_SW_CTRL 0x874 56 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 57 #define GLI_9750_SW_CTRL_4_VALUE 0x3 58 59 #define SDHCI_GLI_9750_MISC 0x878 60 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 61 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 62 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 63 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 64 #define GLI_9750_MISC_RX_INV_ON 0x1 65 #define GLI_9750_MISC_RX_INV_OFF 0x0 66 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 67 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 68 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 69 70 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 71 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 72 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 73 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 74 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 75 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 76 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 77 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 78 79 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 80 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 81 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 82 83 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 84 85 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 86 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 87 88 #define PCIE_GLI_9763E_VHS 0x884 89 #define GLI_9763E_VHS_REV GENMASK(19, 16) 90 #define GLI_9763E_VHS_REV_R 0x0 91 #define GLI_9763E_VHS_REV_M 0x1 92 #define GLI_9763E_VHS_REV_W 0x2 93 #define PCIE_GLI_9763E_MB 0x888 94 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 95 #define GLI_9763E_MB_ERP_ON BIT(7) 96 #define PCIE_GLI_9763E_SCR 0x8E0 97 #define GLI_9763E_SCR_AXI_REQ BIT(9) 98 99 #define PCIE_GLI_9763E_CFG 0x8A0 100 #define GLI_9763E_CFG_LPSN_DIS BIT(12) 101 102 #define PCIE_GLI_9763E_CFG2 0x8A4 103 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 104 #define GLI_9763E_CFG2_L1DLY_MID 0x54 105 106 #define PCIE_GLI_9763E_MMC_CTRL 0x960 107 #define GLI_9763E_HS400_SLOW BIT(3) 108 109 #define PCIE_GLI_9763E_CLKRXDLY 0x934 110 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 111 #define GLI_9763E_HS400_RXDLY_5 0x5 112 113 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 114 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 115 SDHCI_TRNS_BLK_CNT_EN | \ 116 SDHCI_TRNS_DMA) 117 118 #define PCI_GLI_9755_WT 0x800 119 #define PCI_GLI_9755_WT_EN BIT(0) 120 #define GLI_9755_WT_EN_ON 0x1 121 #define GLI_9755_WT_EN_OFF 0x0 122 123 #define PCI_GLI_9755_PECONF 0x44 124 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 125 #define PCI_GLI_9755_DMACLK BIT(29) 126 #define PCI_GLI_9755_INVERT_CD BIT(30) 127 #define PCI_GLI_9755_INVERT_WP BIT(31) 128 129 #define PCI_GLI_9755_CFG2 0x48 130 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 131 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 132 133 #define PCI_GLI_9755_PLL 0x64 134 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 135 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 136 #define PCI_GLI_9755_PLL_DIR BIT(15) 137 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 138 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 139 140 #define PCI_GLI_9755_PLLSSC 0x68 141 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 142 143 #define PCI_GLI_9755_SerDes 0x70 144 #define PCI_GLI_9755_SCP_DIS BIT(19) 145 146 #define PCI_GLI_9755_MISC 0x78 147 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 148 149 #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 150 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) 151 152 #define PCIE_GLI_9767_VHS 0x884 153 #define GLI_9767_VHS_REV GENMASK(19, 16) 154 #define GLI_9767_VHS_REV_R 0x0 155 #define GLI_9767_VHS_REV_M 0x1 156 #define GLI_9767_VHS_REV_W 0x2 157 158 #define PCIE_GLI_9767_COM_MAILBOX 0x888 159 #define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1) 160 161 #define PCIE_GLI_9767_CFG 0x8A0 162 #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12) 163 164 #define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8 165 #define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6) 166 #define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10) 167 168 #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0 169 #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0) 170 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12) 171 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7 172 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28) 173 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3 174 175 #define PCIE_GLI_9767_SCR 0x8E0 176 #define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6) 177 #define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7) 178 #define PCIE_GLI_9767_SCR_AXI_REQ BIT(9) 179 #define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10) 180 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16) 181 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17) 182 #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) 183 #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) 184 185 #define PCIE_GLI_9767_SDHC_CAP 0x91C 186 #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) 187 188 #define PCIE_GLI_9767_SD_PLL_CTL 0x938 189 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0) 190 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12) 191 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16) 192 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19) 193 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24) 194 195 #define PCIE_GLI_9767_SD_PLL_CTL2 0x93C 196 #define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16) 197 198 #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940 199 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0) 200 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) 201 202 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 203 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) 204 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 205 206 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 207 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) 208 209 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954 210 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0) 211 212 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 213 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) 214 215 #define GLI_MAX_TUNING_LOOP 40 216 217 /* Genesys Logic chipset */ 218 static inline void gl9750_wt_on(struct sdhci_host *host) 219 { 220 u32 wt_value; 221 u32 wt_enable; 222 223 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 224 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 225 226 if (wt_enable == GLI_9750_WT_EN_ON) 227 return; 228 229 wt_value &= ~SDHCI_GLI_9750_WT_EN; 230 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 231 232 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 233 } 234 235 static inline void gl9750_wt_off(struct sdhci_host *host) 236 { 237 u32 wt_value; 238 u32 wt_enable; 239 240 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 241 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 242 243 if (wt_enable == GLI_9750_WT_EN_OFF) 244 return; 245 246 wt_value &= ~SDHCI_GLI_9750_WT_EN; 247 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 248 249 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 250 } 251 252 static void gli_set_9750(struct sdhci_host *host) 253 { 254 u32 driving_value; 255 u32 pll_value; 256 u32 sw_ctrl_value; 257 u32 misc_value; 258 u32 parameter_value; 259 u32 control_value; 260 u16 ctrl2; 261 262 gl9750_wt_on(host); 263 264 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 265 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 266 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 267 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 268 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 269 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 270 271 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 272 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 273 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 274 GLI_9750_DRIVING_1_VALUE); 275 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 276 GLI_9750_DRIVING_2_VALUE); 277 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 278 driving_value |= SDHCI_GLI_9750_SEL_2; 279 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 280 281 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 282 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 283 GLI_9750_SW_CTRL_4_VALUE); 284 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 285 286 /* reset the tuning flow after reinit and before starting tuning */ 287 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 288 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 289 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 290 GLI_9750_PLL_TX2_INV_VALUE); 291 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 292 GLI_9750_PLL_TX2_DLY_VALUE); 293 294 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 295 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 296 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 297 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 298 GLI_9750_MISC_TX1_INV_VALUE); 299 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 300 GLI_9750_MISC_RX_INV_VALUE); 301 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 302 GLI_9750_MISC_TX1_DLY_VALUE); 303 304 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 305 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 306 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 307 308 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 309 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 310 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 311 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 312 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 313 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 314 315 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 316 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 317 318 /* disable tuned clk */ 319 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 320 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 321 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 322 323 /* enable tuning parameters control */ 324 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 325 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 326 GLI_9750_TUNING_CONTROL_EN_ON); 327 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 328 329 /* write tuning parameters */ 330 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 331 332 /* disable tuning parameters control */ 333 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 334 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 335 GLI_9750_TUNING_CONTROL_EN_OFF); 336 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 337 338 /* clear tuned clk */ 339 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 340 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 341 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 342 343 gl9750_wt_off(host); 344 } 345 346 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 347 { 348 u32 misc_value; 349 350 gl9750_wt_on(host); 351 352 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 353 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 354 if (b) { 355 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 356 GLI_9750_MISC_RX_INV_ON); 357 } else { 358 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 359 GLI_9750_MISC_RX_INV_OFF); 360 } 361 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 362 363 gl9750_wt_off(host); 364 } 365 366 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 367 { 368 int i; 369 int rx_inv; 370 371 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 372 gli_set_9750_rx_inv(host, !!rx_inv); 373 sdhci_start_tuning(host); 374 375 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 376 u16 ctrl; 377 378 sdhci_send_tuning(host, opcode); 379 380 if (!host->tuning_done) { 381 sdhci_abort_tuning(host, opcode); 382 break; 383 } 384 385 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 386 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 387 if (ctrl & SDHCI_CTRL_TUNED_CLK) 388 return 0; /* Success! */ 389 break; 390 } 391 } 392 } 393 if (!host->tuning_done) { 394 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 395 mmc_hostname(host->mmc)); 396 return -ETIMEDOUT; 397 } 398 399 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 400 mmc_hostname(host->mmc)); 401 sdhci_reset_tuning(host); 402 403 return -EAGAIN; 404 } 405 406 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 407 { 408 host->mmc->retune_period = 0; 409 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 410 host->mmc->retune_period = host->tuning_count; 411 412 gli_set_9750(host); 413 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 414 sdhci_end_tuning(host); 415 416 return 0; 417 } 418 419 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 420 { 421 u32 pll; 422 423 gl9750_wt_on(host); 424 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 425 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 426 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 427 gl9750_wt_off(host); 428 } 429 430 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 431 { 432 u32 pll; 433 434 gl9750_wt_on(host); 435 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 436 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 437 SDHCI_GLI_9750_PLL_PDIV | 438 SDHCI_GLI_9750_PLL_DIR); 439 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 440 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 441 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 442 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 443 gl9750_wt_off(host); 444 445 /* wait for pll stable */ 446 mdelay(1); 447 } 448 449 static bool gl9750_ssc_enable(struct sdhci_host *host) 450 { 451 u32 misc; 452 u8 off; 453 454 gl9750_wt_on(host); 455 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 456 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 457 gl9750_wt_off(host); 458 459 return !off; 460 } 461 462 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 463 { 464 u32 pll; 465 u32 ssc; 466 467 gl9750_wt_on(host); 468 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 469 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 470 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 471 SDHCI_GLI_9750_PLLSSC_EN); 472 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 473 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 474 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 475 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 476 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 477 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 478 gl9750_wt_off(host); 479 } 480 481 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 482 { 483 bool enable = gl9750_ssc_enable(host); 484 485 /* set pll to 205MHz and ssc */ 486 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 487 gl9750_set_pll(host, 0x1, 0x246, 0x0); 488 } 489 490 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 491 { 492 bool enable = gl9750_ssc_enable(host); 493 494 /* set pll to 100MHz and ssc */ 495 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 496 gl9750_set_pll(host, 0x1, 0x244, 0x1); 497 } 498 499 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 500 { 501 bool enable = gl9750_ssc_enable(host); 502 503 /* set pll to 50MHz and ssc */ 504 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 505 gl9750_set_pll(host, 0x1, 0x244, 0x3); 506 } 507 508 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 509 { 510 struct mmc_ios *ios = &host->mmc->ios; 511 u16 clk; 512 513 host->mmc->actual_clock = 0; 514 515 gl9750_disable_ssc_pll(host); 516 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 517 518 if (clock == 0) 519 return; 520 521 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 522 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 523 host->mmc->actual_clock = 205000000; 524 gl9750_set_ssc_pll_205mhz(host); 525 } else if (clock == 100000000) { 526 gl9750_set_ssc_pll_100mhz(host); 527 } else if (clock == 50000000) { 528 gl9750_set_ssc_pll_50mhz(host); 529 } 530 531 sdhci_enable_clk(host, clk); 532 } 533 534 static void gl9750_hw_setting(struct sdhci_host *host) 535 { 536 struct sdhci_pci_slot *slot = sdhci_priv(host); 537 struct pci_dev *pdev; 538 int aer; 539 u32 value; 540 541 pdev = slot->chip->pdev; 542 543 gl9750_wt_on(host); 544 545 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 546 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 547 /* set ASPM L1 entry delay to 7.9us */ 548 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 549 GLI_9750_CFG2_L1DLY_VALUE); 550 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 551 552 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ 553 pci_set_power_state(pdev, PCI_D3hot); 554 pci_set_power_state(pdev, PCI_D0); 555 556 /* mask the replay timer timeout of AER */ 557 aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 558 if (aer) { 559 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); 560 value |= PCI_ERR_COR_REP_TIMER; 561 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); 562 } 563 564 gl9750_wt_off(host); 565 } 566 567 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 568 { 569 int ret; 570 571 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 572 PCI_IRQ_MSI | PCI_IRQ_MSIX); 573 if (ret < 0) { 574 pr_warn("%s: enable PCI MSI failed, error=%d\n", 575 mmc_hostname(slot->host->mmc), ret); 576 return; 577 } 578 579 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 580 } 581 582 static inline void gl9755_wt_on(struct pci_dev *pdev) 583 { 584 u32 wt_value; 585 u32 wt_enable; 586 587 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 588 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 589 590 if (wt_enable == GLI_9755_WT_EN_ON) 591 return; 592 593 wt_value &= ~PCI_GLI_9755_WT_EN; 594 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 595 596 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 597 } 598 599 static inline void gl9755_wt_off(struct pci_dev *pdev) 600 { 601 u32 wt_value; 602 u32 wt_enable; 603 604 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 605 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 606 607 if (wt_enable == GLI_9755_WT_EN_OFF) 608 return; 609 610 wt_value &= ~PCI_GLI_9755_WT_EN; 611 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 612 613 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 614 } 615 616 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 617 { 618 u32 pll; 619 620 gl9755_wt_on(pdev); 621 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 622 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 623 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 624 gl9755_wt_off(pdev); 625 } 626 627 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 628 { 629 u32 pll; 630 631 gl9755_wt_on(pdev); 632 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 633 pll &= ~(PCI_GLI_9755_PLL_LDIV | 634 PCI_GLI_9755_PLL_PDIV | 635 PCI_GLI_9755_PLL_DIR); 636 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 637 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 638 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 639 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 640 gl9755_wt_off(pdev); 641 642 /* wait for pll stable */ 643 mdelay(1); 644 } 645 646 static bool gl9755_ssc_enable(struct pci_dev *pdev) 647 { 648 u32 misc; 649 u8 off; 650 651 gl9755_wt_on(pdev); 652 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 653 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 654 gl9755_wt_off(pdev); 655 656 return !off; 657 } 658 659 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 660 { 661 u32 pll; 662 u32 ssc; 663 664 gl9755_wt_on(pdev); 665 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 666 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 667 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 668 PCI_GLI_9755_PLLSSC_EN); 669 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 670 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 671 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 672 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 673 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 674 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 675 gl9755_wt_off(pdev); 676 } 677 678 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 679 { 680 bool enable = gl9755_ssc_enable(pdev); 681 682 /* set pll to 205MHz and ssc */ 683 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 684 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 685 } 686 687 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 688 { 689 bool enable = gl9755_ssc_enable(pdev); 690 691 /* set pll to 100MHz and ssc */ 692 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 693 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 694 } 695 696 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 697 { 698 bool enable = gl9755_ssc_enable(pdev); 699 700 /* set pll to 50MHz and ssc */ 701 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 702 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 703 } 704 705 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 706 { 707 struct sdhci_pci_slot *slot = sdhci_priv(host); 708 struct mmc_ios *ios = &host->mmc->ios; 709 struct pci_dev *pdev; 710 u16 clk; 711 712 pdev = slot->chip->pdev; 713 host->mmc->actual_clock = 0; 714 715 gl9755_disable_ssc_pll(pdev); 716 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 717 718 if (clock == 0) 719 return; 720 721 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 722 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 723 host->mmc->actual_clock = 205000000; 724 gl9755_set_ssc_pll_205mhz(pdev); 725 } else if (clock == 100000000) { 726 gl9755_set_ssc_pll_100mhz(pdev); 727 } else if (clock == 50000000) { 728 gl9755_set_ssc_pll_50mhz(pdev); 729 } 730 731 sdhci_enable_clk(host, clk); 732 } 733 734 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 735 { 736 struct pci_dev *pdev = slot->chip->pdev; 737 int aer; 738 u32 value; 739 740 gl9755_wt_on(pdev); 741 742 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 743 /* 744 * Apple ARM64 platforms using these chips may have 745 * inverted CD/WP detection. 746 */ 747 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 748 value |= PCI_GLI_9755_INVERT_CD; 749 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 750 value |= PCI_GLI_9755_INVERT_WP; 751 value &= ~PCI_GLI_9755_LFCLK; 752 value &= ~PCI_GLI_9755_DMACLK; 753 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 754 755 /* enable short circuit protection */ 756 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 757 value &= ~PCI_GLI_9755_SCP_DIS; 758 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 759 760 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 761 value &= ~PCI_GLI_9755_CFG2_L1DLY; 762 /* set ASPM L1 entry delay to 7.9us */ 763 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 764 GLI_9755_CFG2_L1DLY_VALUE); 765 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 766 767 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 768 pci_set_power_state(pdev, PCI_D3hot); 769 pci_set_power_state(pdev, PCI_D0); 770 771 /* mask the replay timer timeout of AER */ 772 aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 773 if (aer) { 774 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); 775 value |= PCI_ERR_COR_REP_TIMER; 776 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); 777 } 778 779 gl9755_wt_off(pdev); 780 } 781 782 static inline void gl9767_vhs_read(struct pci_dev *pdev) 783 { 784 u32 vhs_enable; 785 u32 vhs_value; 786 787 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 788 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 789 790 if (vhs_enable == GLI_9767_VHS_REV_R) 791 return; 792 793 vhs_value &= ~GLI_9767_VHS_REV; 794 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R); 795 796 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 797 } 798 799 static inline void gl9767_vhs_write(struct pci_dev *pdev) 800 { 801 u32 vhs_enable; 802 u32 vhs_value; 803 804 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 805 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 806 807 if (vhs_enable == GLI_9767_VHS_REV_W) 808 return; 809 810 vhs_value &= ~GLI_9767_VHS_REV; 811 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W); 812 813 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 814 } 815 816 static bool gl9767_ssc_enable(struct pci_dev *pdev) 817 { 818 u32 value; 819 u8 enable; 820 821 gl9767_vhs_write(pdev); 822 823 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value); 824 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); 825 826 gl9767_vhs_read(pdev); 827 828 return enable; 829 } 830 831 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 832 { 833 u32 pll; 834 u32 ssc; 835 836 gl9767_vhs_write(pdev); 837 838 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 839 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); 840 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING | 841 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 842 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; 843 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) | 844 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); 845 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); 846 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); 847 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 848 849 gl9767_vhs_read(pdev); 850 } 851 852 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 853 { 854 u32 pll; 855 856 gl9767_vhs_write(pdev); 857 858 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 859 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV | 860 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV | 861 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN); 862 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) | 863 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) | 864 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir); 865 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 866 867 gl9767_vhs_read(pdev); 868 869 /* wait for pll stable */ 870 usleep_range(1000, 1100); 871 } 872 873 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev) 874 { 875 bool enable = gl9767_ssc_enable(pdev); 876 877 /* set pll to 205MHz and ssc */ 878 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); 879 gl9767_set_pll(pdev, 0x1, 0x246, 0x0); 880 } 881 882 static void gl9767_disable_ssc_pll(struct pci_dev *pdev) 883 { 884 u32 pll; 885 886 gl9767_vhs_write(pdev); 887 888 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 889 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 890 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 891 892 gl9767_vhs_read(pdev); 893 } 894 895 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) 896 { 897 struct sdhci_pci_slot *slot = sdhci_priv(host); 898 struct mmc_ios *ios = &host->mmc->ios; 899 struct pci_dev *pdev; 900 u32 value; 901 u16 clk; 902 903 pdev = slot->chip->pdev; 904 host->mmc->actual_clock = 0; 905 906 gl9767_vhs_write(pdev); 907 908 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 909 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 910 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 911 912 gl9767_disable_ssc_pll(pdev); 913 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 914 915 if (clock == 0) 916 return; 917 918 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 919 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 920 host->mmc->actual_clock = 205000000; 921 gl9767_set_ssc_pll_205mhz(pdev); 922 } 923 924 sdhci_enable_clk(host, clk); 925 926 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 927 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 928 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 929 930 gl9767_vhs_read(pdev); 931 } 932 933 static void gli_set_9767(struct sdhci_host *host) 934 { 935 u32 value; 936 937 value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE); 938 value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; 939 sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE); 940 } 941 942 static void gl9767_hw_setting(struct sdhci_pci_slot *slot) 943 { 944 struct pci_dev *pdev = slot->chip->pdev; 945 u32 value; 946 947 gl9767_vhs_write(pdev); 948 949 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value); 950 value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 951 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE | 952 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL); 953 954 value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 955 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE, 956 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) | 957 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL, 958 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE); 959 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value); 960 961 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value); 962 value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 | 963 PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 | 964 PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN); 965 966 value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST | 967 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST | 968 PCIE_GLI_9767_SCR_AXI_REQ | 969 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN | 970 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF; 971 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value); 972 973 gl9767_vhs_read(pdev); 974 } 975 976 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) 977 { 978 sdhci_reset(host, mask); 979 gli_set_9767(host); 980 } 981 982 static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 983 { 984 struct sdhci_host *host = mmc_priv(mmc); 985 struct sdhci_pci_slot *slot = sdhci_priv(host); 986 struct pci_dev *pdev; 987 u32 value; 988 int i; 989 990 pdev = slot->chip->pdev; 991 992 if (mmc->ops->get_ro(mmc)) { 993 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 994 return 0; 995 } 996 997 gl9767_vhs_write(pdev); 998 999 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value); 1000 value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN); 1001 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value); 1002 1003 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1004 value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME; 1005 value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME, 1006 PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE); 1007 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1008 1009 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1010 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE; 1011 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value); 1012 1013 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value); 1014 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN; 1015 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value); 1016 1017 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value); 1018 value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN; 1019 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value); 1020 1021 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1022 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1023 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1024 1025 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1026 value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1027 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1028 1029 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1030 value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1031 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1032 1033 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1034 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE; 1035 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1036 1037 for (i = 0; i < 2; i++) { 1038 usleep_range(10000, 10100); 1039 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1040 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) { 1041 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, 1042 value); 1043 break; 1044 } 1045 } 1046 1047 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value); 1048 if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) { 1049 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1050 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE; 1051 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1052 } else { 1053 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1054 1055 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1056 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1057 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1058 1059 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1060 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1061 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1062 } 1063 1064 gl9767_vhs_read(pdev); 1065 1066 return 0; 1067 } 1068 1069 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 1070 { 1071 struct sdhci_host *host = slot->host; 1072 1073 gl9750_hw_setting(host); 1074 gli_pcie_enable_msi(slot); 1075 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1076 sdhci_enable_v4_mode(host); 1077 1078 return 0; 1079 } 1080 1081 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 1082 { 1083 struct sdhci_host *host = slot->host; 1084 1085 gl9755_hw_setting(slot); 1086 gli_pcie_enable_msi(slot); 1087 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1088 sdhci_enable_v4_mode(host); 1089 1090 return 0; 1091 } 1092 1093 static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot) 1094 { 1095 struct sdhci_host *host = slot->host; 1096 1097 gli_set_9767(host); 1098 gl9767_hw_setting(slot); 1099 gli_pcie_enable_msi(slot); 1100 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1101 host->mmc->caps2 |= MMC_CAP2_SD_EXP; 1102 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; 1103 sdhci_enable_v4_mode(host); 1104 1105 return 0; 1106 } 1107 1108 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 1109 { 1110 /* 1111 * According to Section 3.6.1 signal voltage switch procedure in 1112 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1113 * follows: 1114 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1115 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1116 * period. 1117 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1118 * step (12). 1119 * 1120 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1121 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 1122 * 1123 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 1124 * slightly longer than 5ms before the control register reports that 1125 * 1.8V is ready, and far longer still before the card will actually 1126 * work reliably. 1127 */ 1128 usleep_range(100000, 110000); 1129 } 1130 1131 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host) 1132 { 1133 /* 1134 * According to Section 3.6.1 signal voltage switch procedure in 1135 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1136 * follows: 1137 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1138 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1139 * period. 1140 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1141 * step (12). 1142 * 1143 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1144 * to ensure 1.8V signal enable bit is set by GL9767. 1145 * 1146 */ 1147 usleep_range(5000, 5500); 1148 } 1149 1150 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 1151 { 1152 sdhci_reset(host, mask); 1153 gli_set_9750(host); 1154 } 1155 1156 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 1157 { 1158 u32 value; 1159 1160 value = readl(host->ioaddr + reg); 1161 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 1162 value |= 0xc8; 1163 1164 return value; 1165 } 1166 1167 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 1168 struct mmc_ios *ios) 1169 { 1170 struct sdhci_host *host = mmc_priv(mmc); 1171 u32 val; 1172 1173 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 1174 if (ios->enhanced_strobe) 1175 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 1176 else 1177 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 1178 1179 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 1180 } 1181 1182 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, 1183 bool enable) 1184 { 1185 struct pci_dev *pdev = slot->chip->pdev; 1186 u32 value; 1187 1188 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1189 value &= ~GLI_9763E_VHS_REV; 1190 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1191 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1192 1193 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value); 1194 1195 if (enable) 1196 value &= ~GLI_9763E_CFG_LPSN_DIS; 1197 else 1198 value |= GLI_9763E_CFG_LPSN_DIS; 1199 1200 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value); 1201 1202 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1203 value &= ~GLI_9763E_VHS_REV; 1204 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1205 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1206 } 1207 1208 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 1209 unsigned int timing) 1210 { 1211 u16 ctrl_2; 1212 1213 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1214 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1215 if (timing == MMC_TIMING_MMC_HS200) 1216 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1217 else if (timing == MMC_TIMING_MMC_HS) 1218 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1219 else if (timing == MMC_TIMING_MMC_DDR52) 1220 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1221 else if (timing == MMC_TIMING_MMC_HS400) 1222 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 1223 1224 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1225 } 1226 1227 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 1228 { 1229 sdhci_dumpregs(mmc_priv(mmc)); 1230 } 1231 1232 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 1233 { 1234 struct cqhci_host *cq_host = mmc->cqe_private; 1235 u32 value; 1236 1237 value = cqhci_readl(cq_host, CQHCI_CFG); 1238 value |= CQHCI_ENABLE; 1239 cqhci_writel(cq_host, value, CQHCI_CFG); 1240 } 1241 1242 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 1243 { 1244 struct sdhci_host *host = mmc_priv(mmc); 1245 1246 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1247 sdhci_cqe_enable(mmc); 1248 } 1249 1250 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 1251 { 1252 int cmd_error = 0; 1253 int data_error = 0; 1254 1255 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1256 return intmask; 1257 1258 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1259 1260 return 0; 1261 } 1262 1263 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 1264 { 1265 struct sdhci_host *host = mmc_priv(mmc); 1266 struct cqhci_host *cq_host = mmc->cqe_private; 1267 u32 value; 1268 1269 value = cqhci_readl(cq_host, CQHCI_CFG); 1270 value &= ~CQHCI_ENABLE; 1271 cqhci_writel(cq_host, value, CQHCI_CFG); 1272 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1273 } 1274 1275 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 1276 .enable = sdhci_gl9763e_cqe_enable, 1277 .disable = sdhci_cqe_disable, 1278 .dumpregs = sdhci_gl9763e_dumpregs, 1279 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 1280 .post_disable = sdhci_gl9763e_cqe_post_disable, 1281 }; 1282 1283 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 1284 { 1285 struct device *dev = &slot->chip->pdev->dev; 1286 struct sdhci_host *host = slot->host; 1287 struct cqhci_host *cq_host; 1288 bool dma64; 1289 int ret; 1290 1291 ret = sdhci_setup_host(host); 1292 if (ret) 1293 return ret; 1294 1295 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1296 if (!cq_host) { 1297 ret = -ENOMEM; 1298 goto cleanup; 1299 } 1300 1301 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 1302 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 1303 1304 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1305 if (dma64) 1306 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1307 1308 ret = cqhci_init(cq_host, host->mmc, dma64); 1309 if (ret) 1310 goto cleanup; 1311 1312 ret = __sdhci_add_host(host); 1313 if (ret) 1314 goto cleanup; 1315 1316 /* Disable LPM negotiation to avoid entering L1 state. */ 1317 gl9763e_set_low_power_negotiation(slot, false); 1318 1319 return 0; 1320 1321 cleanup: 1322 sdhci_cleanup_host(host); 1323 return ret; 1324 } 1325 1326 static void gli_set_gl9763e(struct sdhci_pci_slot *slot) 1327 { 1328 struct pci_dev *pdev = slot->chip->pdev; 1329 u32 value; 1330 1331 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1332 value &= ~GLI_9763E_VHS_REV; 1333 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1334 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1335 1336 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 1337 value |= GLI_9763E_SCR_AXI_REQ; 1338 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 1339 1340 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 1341 value &= ~GLI_9763E_HS400_SLOW; 1342 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 1343 1344 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 1345 value &= ~GLI_9763E_CFG2_L1DLY; 1346 /* set ASPM L1 entry delay to 21us */ 1347 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 1348 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 1349 1350 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 1351 value &= ~GLI_9763E_HS400_RXDLY; 1352 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 1353 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 1354 1355 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1356 value &= ~GLI_9763E_VHS_REV; 1357 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1358 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1359 } 1360 1361 #ifdef CONFIG_PM 1362 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 1363 { 1364 struct sdhci_pci_slot *slot = chip->slots[0]; 1365 struct sdhci_host *host = slot->host; 1366 u16 clock; 1367 1368 /* Enable LPM negotiation to allow entering L1 state */ 1369 gl9763e_set_low_power_negotiation(slot, true); 1370 1371 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1372 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 1373 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1374 1375 return 0; 1376 } 1377 1378 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 1379 { 1380 struct sdhci_pci_slot *slot = chip->slots[0]; 1381 struct sdhci_host *host = slot->host; 1382 u16 clock; 1383 1384 if (host->mmc->ios.power_mode != MMC_POWER_ON) 1385 return 0; 1386 1387 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1388 1389 clock |= SDHCI_CLOCK_PLL_EN; 1390 clock &= ~SDHCI_CLOCK_INT_STABLE; 1391 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1392 1393 /* Wait max 150 ms */ 1394 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 1395 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 1396 pr_err("%s: PLL clock never stabilised.\n", 1397 mmc_hostname(host->mmc)); 1398 sdhci_dumpregs(host); 1399 } 1400 1401 clock |= SDHCI_CLOCK_CARD_EN; 1402 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1403 1404 /* Disable LPM negotiation to avoid entering L1 state. */ 1405 gl9763e_set_low_power_negotiation(slot, false); 1406 1407 return 0; 1408 } 1409 #endif 1410 1411 #ifdef CONFIG_PM_SLEEP 1412 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 1413 { 1414 struct sdhci_pci_slot *slot = chip->slots[0]; 1415 1416 pci_free_irq_vectors(slot->chip->pdev); 1417 gli_pcie_enable_msi(slot); 1418 1419 return sdhci_pci_resume_host(chip); 1420 } 1421 1422 static int gl9763e_resume(struct sdhci_pci_chip *chip) 1423 { 1424 struct sdhci_pci_slot *slot = chip->slots[0]; 1425 int ret; 1426 1427 ret = sdhci_pci_gli_resume(chip); 1428 if (ret) 1429 return ret; 1430 1431 ret = cqhci_resume(slot->host->mmc); 1432 if (ret) 1433 return ret; 1434 1435 /* 1436 * Disable LPM negotiation to bring device back in sync 1437 * with its runtime_pm state. 1438 */ 1439 gl9763e_set_low_power_negotiation(slot, false); 1440 1441 return 0; 1442 } 1443 1444 static int gl9763e_suspend(struct sdhci_pci_chip *chip) 1445 { 1446 struct sdhci_pci_slot *slot = chip->slots[0]; 1447 int ret; 1448 1449 /* 1450 * Certain SoCs can suspend only with the bus in low- 1451 * power state, notably x86 SoCs when using S0ix. 1452 * Re-enable LPM negotiation to allow entering L1 state 1453 * and entering system suspend. 1454 */ 1455 gl9763e_set_low_power_negotiation(slot, true); 1456 1457 ret = cqhci_suspend(slot->host->mmc); 1458 if (ret) 1459 goto err_suspend; 1460 1461 ret = sdhci_suspend_host(slot->host); 1462 if (ret) 1463 goto err_suspend_host; 1464 1465 return 0; 1466 1467 err_suspend_host: 1468 cqhci_resume(slot->host->mmc); 1469 err_suspend: 1470 gl9763e_set_low_power_negotiation(slot, false); 1471 return ret; 1472 } 1473 #endif 1474 1475 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 1476 { 1477 struct pci_dev *pdev = slot->chip->pdev; 1478 struct sdhci_host *host = slot->host; 1479 u32 value; 1480 1481 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1482 MMC_CAP_1_8V_DDR | 1483 MMC_CAP_NONREMOVABLE; 1484 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1485 MMC_CAP2_HS400_1_8V | 1486 MMC_CAP2_HS400_ES | 1487 MMC_CAP2_NO_SDIO | 1488 MMC_CAP2_NO_SD; 1489 1490 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1491 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 1492 if (value & GLI_9763E_MB_ERP_ON) 1493 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1494 1495 gli_pcie_enable_msi(slot); 1496 host->mmc_host_ops.hs400_enhanced_strobe = 1497 gl9763e_hs400_enhanced_strobe; 1498 gli_set_gl9763e(slot); 1499 sdhci_enable_v4_mode(host); 1500 1501 return 0; 1502 } 1503 1504 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 1505 1506 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 1507 { 1508 u32 val = readl(host->ioaddr + (reg & ~3)); 1509 u16 word; 1510 1511 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 1512 return word; 1513 } 1514 1515 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 1516 { 1517 u32 val = readl(host->ioaddr + (reg & ~3)); 1518 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 1519 1520 return byte; 1521 } 1522 1523 static const struct sdhci_ops sdhci_gl9755_ops = { 1524 .read_w = sdhci_gli_readw, 1525 .read_b = sdhci_gli_readb, 1526 .set_clock = sdhci_gl9755_set_clock, 1527 .enable_dma = sdhci_pci_enable_dma, 1528 .set_bus_width = sdhci_set_bus_width, 1529 .reset = sdhci_reset, 1530 .set_uhs_signaling = sdhci_set_uhs_signaling, 1531 .voltage_switch = sdhci_gli_voltage_switch, 1532 }; 1533 1534 const struct sdhci_pci_fixes sdhci_gl9755 = { 1535 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1536 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1537 .probe_slot = gli_probe_slot_gl9755, 1538 .ops = &sdhci_gl9755_ops, 1539 #ifdef CONFIG_PM_SLEEP 1540 .resume = sdhci_pci_gli_resume, 1541 #endif 1542 }; 1543 1544 static const struct sdhci_ops sdhci_gl9750_ops = { 1545 .read_w = sdhci_gli_readw, 1546 .read_b = sdhci_gli_readb, 1547 .read_l = sdhci_gl9750_readl, 1548 .set_clock = sdhci_gl9750_set_clock, 1549 .enable_dma = sdhci_pci_enable_dma, 1550 .set_bus_width = sdhci_set_bus_width, 1551 .reset = sdhci_gl9750_reset, 1552 .set_uhs_signaling = sdhci_set_uhs_signaling, 1553 .voltage_switch = sdhci_gli_voltage_switch, 1554 .platform_execute_tuning = gl9750_execute_tuning, 1555 }; 1556 1557 const struct sdhci_pci_fixes sdhci_gl9750 = { 1558 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1559 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1560 .probe_slot = gli_probe_slot_gl9750, 1561 .ops = &sdhci_gl9750_ops, 1562 #ifdef CONFIG_PM_SLEEP 1563 .resume = sdhci_pci_gli_resume, 1564 #endif 1565 }; 1566 1567 static const struct sdhci_ops sdhci_gl9763e_ops = { 1568 .set_clock = sdhci_set_clock, 1569 .enable_dma = sdhci_pci_enable_dma, 1570 .set_bus_width = sdhci_set_bus_width, 1571 .reset = sdhci_and_cqhci_reset, 1572 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 1573 .voltage_switch = sdhci_gli_voltage_switch, 1574 .irq = sdhci_gl9763e_cqhci_irq, 1575 }; 1576 1577 const struct sdhci_pci_fixes sdhci_gl9763e = { 1578 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1579 .probe_slot = gli_probe_slot_gl9763e, 1580 .ops = &sdhci_gl9763e_ops, 1581 #ifdef CONFIG_PM_SLEEP 1582 .resume = gl9763e_resume, 1583 .suspend = gl9763e_suspend, 1584 #endif 1585 #ifdef CONFIG_PM 1586 .runtime_suspend = gl9763e_runtime_suspend, 1587 .runtime_resume = gl9763e_runtime_resume, 1588 .allow_runtime_pm = true, 1589 #endif 1590 .add_host = gl9763e_add_host, 1591 }; 1592 1593 static const struct sdhci_ops sdhci_gl9767_ops = { 1594 .set_clock = sdhci_gl9767_set_clock, 1595 .enable_dma = sdhci_pci_enable_dma, 1596 .set_bus_width = sdhci_set_bus_width, 1597 .reset = sdhci_gl9767_reset, 1598 .set_uhs_signaling = sdhci_set_uhs_signaling, 1599 .voltage_switch = sdhci_gl9767_voltage_switch, 1600 }; 1601 1602 const struct sdhci_pci_fixes sdhci_gl9767 = { 1603 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1604 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1605 .probe_slot = gli_probe_slot_gl9767, 1606 .ops = &sdhci_gl9767_ops, 1607 #ifdef CONFIG_PM_SLEEP 1608 .resume = sdhci_pci_gli_resume, 1609 #endif 1610 }; 1611