1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2019 Genesys Logic, Inc. 4 * 5 * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw> 6 * 7 * Version: v0.9.0 (2019-08-08) 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/bits.h> 12 #include <linux/pci.h> 13 #include <linux/mmc/mmc.h> 14 #include <linux/delay.h> 15 #include <linux/of.h> 16 #include <linux/iopoll.h> 17 #include "sdhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pci.h" 20 #include "cqhci.h" 21 #include "sdhci-uhs2.h" 22 23 /* Genesys Logic extra registers */ 24 #define SDHCI_GLI_9750_WT 0x800 25 #define SDHCI_GLI_9750_WT_EN BIT(0) 26 #define GLI_9750_WT_EN_ON 0x1 27 #define GLI_9750_WT_EN_OFF 0x0 28 29 #define SDHCI_GLI_9750_CFG2 0x848 30 #define SDHCI_GLI_9750_CFG2_L1DLY GENMASK(28, 24) 31 #define GLI_9750_CFG2_L1DLY_VALUE 0x1F 32 33 #define SDHCI_GLI_9750_DRIVING 0x860 34 #define SDHCI_GLI_9750_DRIVING_1 GENMASK(11, 0) 35 #define SDHCI_GLI_9750_DRIVING_2 GENMASK(27, 26) 36 #define GLI_9750_DRIVING_1_VALUE 0xFFF 37 #define GLI_9750_DRIVING_2_VALUE 0x3 38 #define SDHCI_GLI_9750_SEL_1 BIT(29) 39 #define SDHCI_GLI_9750_SEL_2 BIT(31) 40 #define SDHCI_GLI_9750_ALL_RST (BIT(24)|BIT(25)|BIT(28)|BIT(30)) 41 42 #define SDHCI_GLI_9750_PLL 0x864 43 #define SDHCI_GLI_9750_PLL_LDIV GENMASK(9, 0) 44 #define SDHCI_GLI_9750_PLL_PDIV GENMASK(14, 12) 45 #define SDHCI_GLI_9750_PLL_DIR BIT(15) 46 #define SDHCI_GLI_9750_PLL_TX2_INV BIT(23) 47 #define SDHCI_GLI_9750_PLL_TX2_DLY GENMASK(22, 20) 48 #define GLI_9750_PLL_TX2_INV_VALUE 0x1 49 #define GLI_9750_PLL_TX2_DLY_VALUE 0x0 50 #define SDHCI_GLI_9750_PLLSSC_STEP GENMASK(28, 24) 51 #define SDHCI_GLI_9750_PLLSSC_EN BIT(31) 52 53 #define SDHCI_GLI_9750_PLLSSC 0x86C 54 #define SDHCI_GLI_9750_PLLSSC_PPM GENMASK(31, 16) 55 56 #define SDHCI_GLI_9750_SW_CTRL 0x874 57 #define SDHCI_GLI_9750_SW_CTRL_4 GENMASK(7, 6) 58 #define GLI_9750_SW_CTRL_4_VALUE 0x3 59 60 #define SDHCI_GLI_9750_MISC 0x878 61 #define SDHCI_GLI_9750_MISC_TX1_INV BIT(2) 62 #define SDHCI_GLI_9750_MISC_RX_INV BIT(3) 63 #define SDHCI_GLI_9750_MISC_TX1_DLY GENMASK(6, 4) 64 #define GLI_9750_MISC_TX1_INV_VALUE 0x0 65 #define GLI_9750_MISC_RX_INV_ON 0x1 66 #define GLI_9750_MISC_RX_INV_OFF 0x0 67 #define GLI_9750_MISC_RX_INV_VALUE GLI_9750_MISC_RX_INV_OFF 68 #define GLI_9750_MISC_TX1_DLY_VALUE 0x5 69 #define SDHCI_GLI_9750_MISC_SSC_OFF BIT(26) 70 71 #define SDHCI_GLI_9750_TUNING_CONTROL 0x540 72 #define SDHCI_GLI_9750_TUNING_CONTROL_EN BIT(4) 73 #define GLI_9750_TUNING_CONTROL_EN_ON 0x1 74 #define GLI_9750_TUNING_CONTROL_EN_OFF 0x0 75 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1 BIT(16) 76 #define SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2 GENMASK(20, 19) 77 #define GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE 0x1 78 #define GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE 0x2 79 80 #define SDHCI_GLI_9750_TUNING_PARAMETERS 0x544 81 #define SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY GENMASK(2, 0) 82 #define GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE 0x1 83 84 #define SDHCI_GLI_9763E_CTRL_HS400 0x7 85 86 #define SDHCI_GLI_9763E_HS400_ES_REG 0x52C 87 #define SDHCI_GLI_9763E_HS400_ES_BIT BIT(8) 88 89 #define PCIE_GLI_9763E_VHS 0x884 90 #define GLI_9763E_VHS_REV GENMASK(19, 16) 91 #define GLI_9763E_VHS_REV_R 0x0 92 #define GLI_9763E_VHS_REV_M 0x1 93 #define GLI_9763E_VHS_REV_W 0x2 94 #define PCIE_GLI_9763E_MB 0x888 95 #define GLI_9763E_MB_CMDQ_OFF BIT(19) 96 #define GLI_9763E_MB_ERP_ON BIT(7) 97 #define PCIE_GLI_9763E_SCR 0x8E0 98 #define GLI_9763E_SCR_AXI_REQ BIT(9) 99 100 #define PCIE_GLI_9763E_CFG 0x8A0 101 #define GLI_9763E_CFG_LPSN_DIS BIT(12) 102 103 #define PCIE_GLI_9763E_CFG2 0x8A4 104 #define GLI_9763E_CFG2_L1DLY GENMASK(28, 19) 105 #define GLI_9763E_CFG2_L1DLY_MID 0x54 106 107 #define PCIE_GLI_9763E_MMC_CTRL 0x960 108 #define GLI_9763E_HS400_SLOW BIT(3) 109 110 #define PCIE_GLI_9763E_CLKRXDLY 0x934 111 #define GLI_9763E_HS400_RXDLY GENMASK(31, 28) 112 #define GLI_9763E_HS400_RXDLY_5 0x5 113 114 #define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200 115 #define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 116 SDHCI_TRNS_BLK_CNT_EN | \ 117 SDHCI_TRNS_DMA) 118 119 #define PCI_GLI_9755_WT 0x800 120 #define PCI_GLI_9755_WT_EN BIT(0) 121 #define GLI_9755_WT_EN_ON 0x1 122 #define GLI_9755_WT_EN_OFF 0x0 123 124 #define PCI_GLI_9755_PECONF 0x44 125 #define PCI_GLI_9755_LFCLK GENMASK(14, 12) 126 #define PCI_GLI_9755_DMACLK BIT(29) 127 #define PCI_GLI_9755_INVERT_CD BIT(30) 128 #define PCI_GLI_9755_INVERT_WP BIT(31) 129 130 #define PCI_GLI_9755_CFG2 0x48 131 #define PCI_GLI_9755_CFG2_L1DLY GENMASK(28, 24) 132 #define GLI_9755_CFG2_L1DLY_VALUE 0x1F 133 134 #define PCI_GLI_9755_PLL 0x64 135 #define PCI_GLI_9755_PLL_LDIV GENMASK(9, 0) 136 #define PCI_GLI_9755_PLL_PDIV GENMASK(14, 12) 137 #define PCI_GLI_9755_PLL_DIR BIT(15) 138 #define PCI_GLI_9755_PLLSSC_STEP GENMASK(28, 24) 139 #define PCI_GLI_9755_PLLSSC_EN BIT(31) 140 141 #define PCI_GLI_9755_PLLSSC 0x68 142 #define PCI_GLI_9755_PLLSSC_PPM GENMASK(15, 0) 143 #define PCI_GLI_9755_PLLSSC_RTL BIT(24) 144 #define GLI_9755_PLLSSC_RTL_VALUE 0x1 145 #define PCI_GLI_9755_PLLSSC_TRANS_PASS BIT(27) 146 #define GLI_9755_PLLSSC_TRANS_PASS_VALUE 0x1 147 #define PCI_GLI_9755_PLLSSC_RECV GENMASK(29, 28) 148 #define GLI_9755_PLLSSC_RECV_VALUE 0x0 149 #define PCI_GLI_9755_PLLSSC_TRAN GENMASK(31, 30) 150 #define GLI_9755_PLLSSC_TRAN_VALUE 0x3 151 152 #define PCI_GLI_9755_UHS2_PLL 0x6C 153 #define PCI_GLI_9755_UHS2_PLL_SSC GENMASK(9, 8) 154 #define GLI_9755_UHS2_PLL_SSC_VALUE 0x0 155 #define PCI_GLI_9755_UHS2_PLL_DELAY BIT(18) 156 #define GLI_9755_UHS2_PLL_DELAY_VALUE 0x1 157 #define PCI_GLI_9755_UHS2_PLL_PDRST BIT(27) 158 #define GLI_9755_UHS2_PLL_PDRST_VALUE 0x1 159 160 #define PCI_GLI_9755_SerDes 0x70 161 #define PCI_GLI_9755_UHS2_SERDES_INTR GENMASK(2, 0) 162 #define GLI_9755_UHS2_SERDES_INTR_VALUE 0x3 163 #define PCI_GLI_9755_UHS2_SERDES_ZC1 BIT(3) 164 #define GLI_9755_UHS2_SERDES_ZC1_VALUE 0x0 165 #define PCI_GLI_9755_UHS2_SERDES_ZC2 GENMASK(7, 4) 166 #define GLI_9755_UHS2_SERDES_ZC2_DEFAULT 0xB 167 #define GLI_9755_UHS2_SERDES_ZC2_SANDISK 0x0 168 #define PCI_GLI_9755_SCP_DIS BIT(19) 169 #define PCI_GLI_9755_UHS2_SERDES_TRAN GENMASK(27, 24) 170 #define GLI_9755_UHS2_SERDES_TRAN_VALUE 0xC 171 #define PCI_GLI_9755_UHS2_SERDES_RECV GENMASK(31, 28) 172 #define GLI_9755_UHS2_SERDES_RECV_VALUE 0xF 173 174 #define PCI_GLI_9755_MISC 0x78 175 #define PCI_GLI_9755_MISC_SSC_OFF BIT(26) 176 177 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL 0x508 178 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK BIT(0) 179 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE GENMASK(21, 16) 180 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE 0x05 181 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE 0x3F 182 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE GENMASK(23, 22) 183 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS 0x2 184 #define SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS 0x3 185 186 #define SDHCI_GLI_9767_GM_BURST_SIZE 0x510 187 #define SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET BIT(8) 188 189 #define PCIE_GLI_9767_VHS 0x884 190 #define GLI_9767_VHS_REV GENMASK(19, 16) 191 #define GLI_9767_VHS_REV_R 0x0 192 #define GLI_9767_VHS_REV_M 0x1 193 #define GLI_9767_VHS_REV_W 0x2 194 195 #define PCIE_GLI_9767_COM_MAILBOX 0x888 196 #define PCIE_GLI_9767_COM_MAILBOX_SSC_EN BIT(1) 197 198 #define PCIE_GLI_9767_CFG 0x8A0 199 #define PCIE_GLI_9767_CFG_LOW_PWR_OFF BIT(12) 200 201 #define PCIE_GLI_9767_COMBO_MUX_CTL 0x8C8 202 #define PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN BIT(6) 203 #define PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN BIT(10) 204 205 #define PCIE_GLI_9767_PWR_MACRO_CTL 0x8D0 206 #define PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE GENMASK(3, 0) 207 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE GENMASK(15, 12) 208 #define PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE 0x7 209 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL GENMASK(29, 28) 210 #define PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE 0x3 211 212 #define PCIE_GLI_9767_SCR 0x8E0 213 #define PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST BIT(6) 214 #define PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST BIT(7) 215 #define PCIE_GLI_9767_SCR_AXI_REQ BIT(9) 216 #define PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN BIT(10) 217 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 BIT(16) 218 #define PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 BIT(17) 219 #define PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF BIT(21) 220 #define PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN BIT(30) 221 222 #define PCIE_GLI_9767_RESET_REG 0x8E4 223 #define PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET BIT(0) 224 225 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1 0x90C 226 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR GENMASK(31, 29) 227 #define PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE 0x3 228 229 #define PCIE_GLI_9767_SDHC_CAP 0x91C 230 #define PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT BIT(5) 231 232 #define PCIE_GLI_9767_SD_PLL_CTL 0x938 233 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV GENMASK(9, 0) 234 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV GENMASK(15, 12) 235 #define PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN BIT(16) 236 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_EN BIT(19) 237 #define PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING GENMASK(28, 24) 238 239 #define PCIE_GLI_9767_SD_PLL_CTL2 0x93C 240 #define PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM GENMASK(31, 16) 241 242 #define PCIE_GLI_9767_SD_EXPRESS_CTL 0x940 243 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE BIT(0) 244 #define PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE BIT(1) 245 246 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL 0x944 247 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 BIT(5) 248 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL BIT(8) 249 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME GENMASK(23, 16) 250 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE 0x64 251 252 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2 0x948 253 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING GENMASK(22, 21) 254 #define PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE 0x0 255 256 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2 0x950 257 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE BIT(0) 258 259 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2 0x954 260 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN BIT(0) 261 262 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2 0x958 263 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN BIT(0) 264 265 #define PCIE_GLI_9767_UHS2_CTL1 0x95C 266 #define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS BIT(5) 267 #define PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE 0x1 268 #define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL BIT(6) 269 #define PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE 0x1 270 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN GENMASK(10, 7) 271 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE 0x3 272 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV GENMASK(14, 11) 273 #define PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE 0xf 274 #define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS GENMASK(16, 15) 275 #define PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE 0x0 276 #define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV GENMASK(18, 17) 277 #define PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE 0x0 278 #define PCIE_GLI_9767_UHS2_CTL1_PDRST BIT(25) 279 #define PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE 0x1 280 281 #define PCIE_GLI_9767_UHS2_CTL2 0x964 282 #define PCIE_GLI_9767_UHS2_CTL2_ZC GENMASK(3, 0) 283 #define PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE 0xb 284 #define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL BIT(6) 285 #define PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE 0x1 286 287 #define GLI_MAX_TUNING_LOOP 40 288 289 /* Genesys Logic chipset */ 290 static void sdhci_gli_mask_replay_timer_timeout(struct pci_dev *pdev) 291 { 292 int aer; 293 u32 value; 294 295 /* mask the replay timer timeout of AER */ 296 aer = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ERR); 297 if (aer) { 298 pci_read_config_dword(pdev, aer + PCI_ERR_COR_MASK, &value); 299 value |= PCI_ERR_COR_REP_TIMER; 300 pci_write_config_dword(pdev, aer + PCI_ERR_COR_MASK, value); 301 } 302 } 303 304 static inline void gl9750_wt_on(struct sdhci_host *host) 305 { 306 u32 wt_value; 307 u32 wt_enable; 308 309 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 310 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 311 312 if (wt_enable == GLI_9750_WT_EN_ON) 313 return; 314 315 wt_value &= ~SDHCI_GLI_9750_WT_EN; 316 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); 317 318 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 319 } 320 321 static inline void gl9750_wt_off(struct sdhci_host *host) 322 { 323 u32 wt_value; 324 u32 wt_enable; 325 326 wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT); 327 wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value); 328 329 if (wt_enable == GLI_9750_WT_EN_OFF) 330 return; 331 332 wt_value &= ~SDHCI_GLI_9750_WT_EN; 333 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); 334 335 sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT); 336 } 337 338 static void gli_set_9750(struct sdhci_host *host) 339 { 340 u32 driving_value; 341 u32 pll_value; 342 u32 sw_ctrl_value; 343 u32 misc_value; 344 u32 parameter_value; 345 u32 control_value; 346 u16 ctrl2; 347 348 gl9750_wt_on(host); 349 350 driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING); 351 pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL); 352 sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL); 353 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 354 parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS); 355 control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL); 356 357 driving_value &= ~(SDHCI_GLI_9750_DRIVING_1); 358 driving_value &= ~(SDHCI_GLI_9750_DRIVING_2); 359 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, 360 GLI_9750_DRIVING_1_VALUE); 361 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, 362 GLI_9750_DRIVING_2_VALUE); 363 driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST); 364 driving_value |= SDHCI_GLI_9750_SEL_2; 365 sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING); 366 367 sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4; 368 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, 369 GLI_9750_SW_CTRL_4_VALUE); 370 sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL); 371 372 /* reset the tuning flow after reinit and before starting tuning */ 373 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV; 374 pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY; 375 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, 376 GLI_9750_PLL_TX2_INV_VALUE); 377 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, 378 GLI_9750_PLL_TX2_DLY_VALUE); 379 380 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV; 381 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 382 misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY; 383 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, 384 GLI_9750_MISC_TX1_INV_VALUE); 385 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 386 GLI_9750_MISC_RX_INV_VALUE); 387 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, 388 GLI_9750_MISC_TX1_DLY_VALUE); 389 390 parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY; 391 parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY, 392 GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE); 393 394 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1; 395 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2; 396 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1, 397 GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE); 398 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2, 399 GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE); 400 401 sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL); 402 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 403 404 /* disable tuned clk */ 405 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 406 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 407 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 408 409 /* enable tuning parameters control */ 410 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 411 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 412 GLI_9750_TUNING_CONTROL_EN_ON); 413 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 414 415 /* write tuning parameters */ 416 sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS); 417 418 /* disable tuning parameters control */ 419 control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN; 420 control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN, 421 GLI_9750_TUNING_CONTROL_EN_OFF); 422 sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL); 423 424 /* clear tuned clk */ 425 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 426 ctrl2 &= ~SDHCI_CTRL_TUNED_CLK; 427 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); 428 429 gl9750_wt_off(host); 430 } 431 432 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b) 433 { 434 u32 misc_value; 435 436 gl9750_wt_on(host); 437 438 misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC); 439 misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV; 440 if (b) { 441 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 442 GLI_9750_MISC_RX_INV_ON); 443 } else { 444 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, 445 GLI_9750_MISC_RX_INV_OFF); 446 } 447 sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC); 448 449 gl9750_wt_off(host); 450 } 451 452 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode) 453 { 454 int i; 455 int rx_inv; 456 457 for (rx_inv = 0; rx_inv < 2; rx_inv++) { 458 gli_set_9750_rx_inv(host, !!rx_inv); 459 sdhci_start_tuning(host); 460 461 for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) { 462 u16 ctrl; 463 464 sdhci_send_tuning(host, opcode); 465 466 if (!host->tuning_done) { 467 sdhci_abort_tuning(host, opcode); 468 break; 469 } 470 471 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); 472 if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) { 473 if (ctrl & SDHCI_CTRL_TUNED_CLK) 474 return 0; /* Success! */ 475 break; 476 } 477 } 478 } 479 if (!host->tuning_done) { 480 pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n", 481 mmc_hostname(host->mmc)); 482 return -ETIMEDOUT; 483 } 484 485 pr_info("%s: Tuning failed, falling back to fixed sampling clock\n", 486 mmc_hostname(host->mmc)); 487 sdhci_reset_tuning(host); 488 489 return -EAGAIN; 490 } 491 492 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode) 493 { 494 host->mmc->retune_period = 0; 495 if (host->tuning_mode == SDHCI_TUNING_MODE_1) 496 host->mmc->retune_period = host->tuning_count; 497 498 gli_set_9750(host); 499 host->tuning_err = __sdhci_execute_tuning_9750(host, opcode); 500 sdhci_end_tuning(host); 501 502 return 0; 503 } 504 505 static void gl9750_disable_ssc_pll(struct sdhci_host *host) 506 { 507 u32 pll; 508 509 gl9750_wt_on(host); 510 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 511 pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN); 512 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 513 gl9750_wt_off(host); 514 } 515 516 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv) 517 { 518 u32 pll; 519 520 gl9750_wt_on(host); 521 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 522 pll &= ~(SDHCI_GLI_9750_PLL_LDIV | 523 SDHCI_GLI_9750_PLL_PDIV | 524 SDHCI_GLI_9750_PLL_DIR); 525 pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) | 526 FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) | 527 FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir); 528 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 529 gl9750_wt_off(host); 530 531 /* wait for pll stable */ 532 mdelay(1); 533 } 534 535 static bool gl9750_ssc_enable(struct sdhci_host *host) 536 { 537 u32 misc; 538 u8 off; 539 540 gl9750_wt_on(host); 541 misc = sdhci_readl(host, SDHCI_GLI_9750_MISC); 542 off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc); 543 gl9750_wt_off(host); 544 545 return !off; 546 } 547 548 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm) 549 { 550 u32 pll; 551 u32 ssc; 552 553 gl9750_wt_on(host); 554 pll = sdhci_readl(host, SDHCI_GLI_9750_PLL); 555 ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC); 556 pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP | 557 SDHCI_GLI_9750_PLLSSC_EN); 558 ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM; 559 pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) | 560 FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable); 561 ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm); 562 sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC); 563 sdhci_writel(host, pll, SDHCI_GLI_9750_PLL); 564 gl9750_wt_off(host); 565 } 566 567 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host) 568 { 569 bool enable = gl9750_ssc_enable(host); 570 571 /* set pll to 205MHz and ssc */ 572 gl9750_set_ssc(host, enable, 0xF, 0x5A1D); 573 gl9750_set_pll(host, 0x1, 0x246, 0x0); 574 } 575 576 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host) 577 { 578 bool enable = gl9750_ssc_enable(host); 579 580 /* set pll to 100MHz and ssc */ 581 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 582 gl9750_set_pll(host, 0x1, 0x244, 0x1); 583 } 584 585 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host) 586 { 587 bool enable = gl9750_ssc_enable(host); 588 589 /* set pll to 50MHz and ssc */ 590 gl9750_set_ssc(host, enable, 0xE, 0x51EC); 591 gl9750_set_pll(host, 0x1, 0x244, 0x3); 592 } 593 594 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock) 595 { 596 struct mmc_ios *ios = &host->mmc->ios; 597 u16 clk; 598 599 host->mmc->actual_clock = 0; 600 601 gl9750_disable_ssc_pll(host); 602 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 603 604 if (clock == 0) 605 return; 606 607 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 608 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 609 host->mmc->actual_clock = 205000000; 610 gl9750_set_ssc_pll_205mhz(host); 611 } else if (clock == 100000000) { 612 gl9750_set_ssc_pll_100mhz(host); 613 } else if (clock == 50000000) { 614 gl9750_set_ssc_pll_50mhz(host); 615 } 616 617 sdhci_enable_clk(host, clk); 618 } 619 620 static void gl9750_hw_setting(struct sdhci_host *host) 621 { 622 struct sdhci_pci_slot *slot = sdhci_priv(host); 623 struct pci_dev *pdev; 624 u32 value; 625 626 pdev = slot->chip->pdev; 627 628 gl9750_wt_on(host); 629 630 value = sdhci_readl(host, SDHCI_GLI_9750_CFG2); 631 value &= ~SDHCI_GLI_9750_CFG2_L1DLY; 632 /* set ASPM L1 entry delay to 7.9us */ 633 value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY, 634 GLI_9750_CFG2_L1DLY_VALUE); 635 sdhci_writel(host, value, SDHCI_GLI_9750_CFG2); 636 637 /* toggle PM state to allow GL9750 to enter ASPM L1.2 */ 638 pci_set_power_state(pdev, PCI_D3hot); 639 pci_set_power_state(pdev, PCI_D0); 640 641 /* mask the replay timer timeout of AER */ 642 sdhci_gli_mask_replay_timer_timeout(pdev); 643 644 gl9750_wt_off(host); 645 } 646 647 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot) 648 { 649 int ret; 650 651 ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1, 652 PCI_IRQ_MSI | PCI_IRQ_MSIX); 653 if (ret < 0) { 654 pr_warn("%s: enable PCI MSI failed, error=%d\n", 655 mmc_hostname(slot->host->mmc), ret); 656 return; 657 } 658 659 slot->host->irq = pci_irq_vector(slot->chip->pdev, 0); 660 } 661 662 static inline void gl9755_wt_on(struct pci_dev *pdev) 663 { 664 u32 wt_value; 665 u32 wt_enable; 666 667 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 668 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 669 670 if (wt_enable == GLI_9755_WT_EN_ON) 671 return; 672 673 wt_value &= ~PCI_GLI_9755_WT_EN; 674 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON); 675 676 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 677 } 678 679 static inline void gl9755_wt_off(struct pci_dev *pdev) 680 { 681 u32 wt_value; 682 u32 wt_enable; 683 684 pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value); 685 wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value); 686 687 if (wt_enable == GLI_9755_WT_EN_OFF) 688 return; 689 690 wt_value &= ~PCI_GLI_9755_WT_EN; 691 wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF); 692 693 pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value); 694 } 695 696 static void gl9755_disable_ssc_pll(struct pci_dev *pdev) 697 { 698 u32 pll; 699 700 gl9755_wt_on(pdev); 701 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 702 pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN); 703 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 704 gl9755_wt_off(pdev); 705 } 706 707 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 708 { 709 u32 pll; 710 711 gl9755_wt_on(pdev); 712 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 713 pll &= ~(PCI_GLI_9755_PLL_LDIV | 714 PCI_GLI_9755_PLL_PDIV | 715 PCI_GLI_9755_PLL_DIR); 716 pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) | 717 FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) | 718 FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir); 719 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 720 gl9755_wt_off(pdev); 721 722 /* wait for pll stable */ 723 mdelay(1); 724 } 725 726 static bool gl9755_ssc_enable(struct pci_dev *pdev) 727 { 728 u32 misc; 729 u8 off; 730 731 gl9755_wt_on(pdev); 732 pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc); 733 off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc); 734 gl9755_wt_off(pdev); 735 736 return !off; 737 } 738 739 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 740 { 741 u32 pll; 742 u32 ssc; 743 744 gl9755_wt_on(pdev); 745 pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll); 746 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc); 747 pll &= ~(PCI_GLI_9755_PLLSSC_STEP | 748 PCI_GLI_9755_PLLSSC_EN); 749 ssc &= ~PCI_GLI_9755_PLLSSC_PPM; 750 pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) | 751 FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable); 752 ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm); 753 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc); 754 pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll); 755 gl9755_wt_off(pdev); 756 } 757 758 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev) 759 { 760 bool enable = gl9755_ssc_enable(pdev); 761 762 /* set pll to 205MHz and ssc */ 763 gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D); 764 gl9755_set_pll(pdev, 0x1, 0x246, 0x0); 765 } 766 767 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev) 768 { 769 bool enable = gl9755_ssc_enable(pdev); 770 771 /* set pll to 100MHz and ssc */ 772 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 773 gl9755_set_pll(pdev, 0x1, 0x244, 0x1); 774 } 775 776 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev) 777 { 778 bool enable = gl9755_ssc_enable(pdev); 779 780 /* set pll to 50MHz and ssc */ 781 gl9755_set_ssc(pdev, enable, 0xE, 0x51EC); 782 gl9755_set_pll(pdev, 0x1, 0x244, 0x3); 783 } 784 785 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock) 786 { 787 struct sdhci_pci_slot *slot = sdhci_priv(host); 788 struct mmc_ios *ios = &host->mmc->ios; 789 struct pci_dev *pdev; 790 u16 clk; 791 792 pdev = slot->chip->pdev; 793 host->mmc->actual_clock = 0; 794 795 gl9755_disable_ssc_pll(pdev); 796 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 797 798 if (clock == 0) 799 return; 800 801 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 802 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 803 host->mmc->actual_clock = 205000000; 804 gl9755_set_ssc_pll_205mhz(pdev); 805 } else if (clock == 100000000) { 806 gl9755_set_ssc_pll_100mhz(pdev); 807 } else if (clock == 50000000) { 808 gl9755_set_ssc_pll_50mhz(pdev); 809 } 810 811 sdhci_enable_clk(host, clk); 812 } 813 814 static void gl9755_hw_setting(struct sdhci_pci_slot *slot) 815 { 816 struct pci_dev *pdev = slot->chip->pdev; 817 u32 value; 818 819 gl9755_wt_on(pdev); 820 821 pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value); 822 /* 823 * Apple ARM64 platforms using these chips may have 824 * inverted CD/WP detection. 825 */ 826 if (of_property_read_bool(pdev->dev.of_node, "cd-inverted")) 827 value |= PCI_GLI_9755_INVERT_CD; 828 if (of_property_read_bool(pdev->dev.of_node, "wp-inverted")) 829 value |= PCI_GLI_9755_INVERT_WP; 830 value &= ~PCI_GLI_9755_LFCLK; 831 value &= ~PCI_GLI_9755_DMACLK; 832 pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value); 833 834 /* enable short circuit protection */ 835 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value); 836 value &= ~PCI_GLI_9755_SCP_DIS; 837 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value); 838 839 pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value); 840 value &= ~PCI_GLI_9755_CFG2_L1DLY; 841 /* set ASPM L1 entry delay to 7.9us */ 842 value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY, 843 GLI_9755_CFG2_L1DLY_VALUE); 844 pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value); 845 846 /* toggle PM state to allow GL9755 to enter ASPM L1.2 */ 847 pci_set_power_state(pdev, PCI_D3hot); 848 pci_set_power_state(pdev, PCI_D0); 849 850 /* mask the replay timer timeout of AER */ 851 sdhci_gli_mask_replay_timer_timeout(pdev); 852 853 gl9755_wt_off(pdev); 854 } 855 856 static void gl9755_vendor_init(struct sdhci_host *host) 857 { 858 struct sdhci_pci_slot *slot = sdhci_priv(host); 859 struct pci_dev *pdev = slot->chip->pdev; 860 u32 serdes; 861 u32 pllssc; 862 u32 uhs2_pll; 863 864 gl9755_wt_on(pdev); 865 866 pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &serdes); 867 serdes &= ~PCI_GLI_9755_UHS2_SERDES_TRAN; 868 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_TRAN, 869 GLI_9755_UHS2_SERDES_TRAN_VALUE); 870 serdes &= ~PCI_GLI_9755_UHS2_SERDES_RECV; 871 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_RECV, 872 GLI_9755_UHS2_SERDES_RECV_VALUE); 873 serdes &= ~PCI_GLI_9755_UHS2_SERDES_INTR; 874 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_INTR, 875 GLI_9755_UHS2_SERDES_INTR_VALUE); 876 serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC1; 877 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC1, 878 GLI_9755_UHS2_SERDES_ZC1_VALUE); 879 serdes &= ~PCI_GLI_9755_UHS2_SERDES_ZC2; 880 serdes |= FIELD_PREP(PCI_GLI_9755_UHS2_SERDES_ZC2, 881 GLI_9755_UHS2_SERDES_ZC2_DEFAULT); 882 pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, serdes); 883 884 pci_read_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, &uhs2_pll); 885 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_SSC; 886 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_SSC, 887 GLI_9755_UHS2_PLL_SSC_VALUE); 888 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_DELAY; 889 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_DELAY, 890 GLI_9755_UHS2_PLL_DELAY_VALUE); 891 uhs2_pll &= ~PCI_GLI_9755_UHS2_PLL_PDRST; 892 uhs2_pll |= FIELD_PREP(PCI_GLI_9755_UHS2_PLL_PDRST, 893 GLI_9755_UHS2_PLL_PDRST_VALUE); 894 pci_write_config_dword(pdev, PCI_GLI_9755_UHS2_PLL, uhs2_pll); 895 896 pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &pllssc); 897 pllssc &= ~PCI_GLI_9755_PLLSSC_RTL; 898 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RTL, 899 GLI_9755_PLLSSC_RTL_VALUE); 900 pllssc &= ~PCI_GLI_9755_PLLSSC_TRANS_PASS; 901 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRANS_PASS, 902 GLI_9755_PLLSSC_TRANS_PASS_VALUE); 903 pllssc &= ~PCI_GLI_9755_PLLSSC_RECV; 904 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_RECV, 905 GLI_9755_PLLSSC_RECV_VALUE); 906 pllssc &= ~PCI_GLI_9755_PLLSSC_TRAN; 907 pllssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_TRAN, 908 GLI_9755_PLLSSC_TRAN_VALUE); 909 pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, pllssc); 910 911 gl9755_wt_off(pdev); 912 } 913 914 static void sdhci_gli_pre_detect_init(struct sdhci_host *host) 915 { 916 /* Need more time on UHS2 detect flow */ 917 sdhci_writeb(host, 0xA7, SDHCI_UHS2_TIMER_CTRL); 918 } 919 920 static void sdhci_gli_overcurrent_event_enable(struct sdhci_host *host, bool enable) 921 { 922 u32 mask; 923 924 mask = sdhci_readl(host, SDHCI_SIGNAL_ENABLE); 925 if (enable) 926 mask |= SDHCI_INT_BUS_POWER; 927 else 928 mask &= ~SDHCI_INT_BUS_POWER; 929 930 sdhci_writel(host, mask, SDHCI_SIGNAL_ENABLE); 931 932 mask = sdhci_readl(host, SDHCI_INT_ENABLE); 933 if (enable) 934 mask |= SDHCI_INT_BUS_POWER; 935 else 936 mask &= ~SDHCI_INT_BUS_POWER; 937 938 sdhci_writel(host, mask, SDHCI_INT_ENABLE); 939 } 940 941 static void gl9755_set_power(struct sdhci_host *host, unsigned char mode, 942 unsigned short vdd) 943 { 944 u8 pwr = 0; 945 946 if (mode != MMC_POWER_OFF) { 947 pwr = sdhci_get_vdd_value(vdd); 948 if (!pwr) 949 WARN(1, "%s: Invalid vdd %#x\n", mmc_hostname(host->mmc), vdd); 950 pwr |= SDHCI_VDD2_POWER_180; 951 } 952 953 if (host->pwr == pwr) 954 return; 955 956 host->pwr = pwr; 957 958 if (pwr == 0) { 959 sdhci_gli_overcurrent_event_enable(host, false); 960 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 961 } else { 962 sdhci_gli_overcurrent_event_enable(host, false); 963 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 964 965 pwr |= (SDHCI_POWER_ON | SDHCI_VDD2_POWER_ON); 966 967 sdhci_writeb(host, pwr & 0xf, SDHCI_POWER_CONTROL); 968 /* wait stable */ 969 mdelay(5); 970 sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); 971 /* wait stable */ 972 mdelay(5); 973 sdhci_gli_overcurrent_event_enable(host, true); 974 } 975 } 976 977 static bool sdhci_wait_clock_stable(struct sdhci_host *host) 978 { 979 u16 clk = 0; 980 981 if (read_poll_timeout_atomic(sdhci_readw, clk, (clk & SDHCI_CLOCK_INT_STABLE), 982 10, 20000, false, host, SDHCI_CLOCK_CONTROL)) { 983 pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc)); 984 sdhci_dumpregs(host); 985 return false; 986 } 987 return true; 988 } 989 990 static void sdhci_gli_enable_internal_clock(struct sdhci_host *host) 991 { 992 u16 ctrl2; 993 994 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 995 996 sdhci_writew(host, SDHCI_CLOCK_INT_EN, SDHCI_CLOCK_CONTROL); 997 998 if (!((ctrl2 & SDHCI_CTRL_V4_MODE) && 999 (ctrl2 & SDHCI_CTRL_UHS2_ENABLE))) { 1000 sdhci_wait_clock_stable(host); 1001 sdhci_writew(host, SDHCI_CTRL_V4_MODE, SDHCI_HOST_CONTROL2); 1002 } 1003 } 1004 1005 static int sdhci_gli_wait_software_reset_done(struct sdhci_host *host, u8 mask) 1006 { 1007 u8 rst; 1008 1009 /* hw clears the bit when it's done */ 1010 if (read_poll_timeout_atomic(sdhci_readb, rst, !(rst & mask), 1011 10, 100000, false, host, SDHCI_SOFTWARE_RESET)) { 1012 pr_err("%s: Reset 0x%x never completed.\n", mmc_hostname(host->mmc), (int)mask); 1013 sdhci_dumpregs(host); 1014 /* manual clear */ 1015 sdhci_writeb(host, 0, SDHCI_SOFTWARE_RESET); 1016 return -ETIMEDOUT; 1017 } 1018 1019 return 0; 1020 } 1021 1022 static void sdhci_gli_uhs2_reset_sd_tran(struct sdhci_host *host) 1023 { 1024 /* do this on UHS2 mode */ 1025 if (host->mmc->uhs2_sd_tran) { 1026 sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD); 1027 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1028 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1029 sdhci_uhs2_clear_set_irqs(host, 1030 SDHCI_INT_ALL_MASK, 1031 SDHCI_UHS2_INT_ERROR_MASK); 1032 } 1033 } 1034 1035 static void sdhci_gl9755_reset(struct sdhci_host *host, u8 mask) 1036 { 1037 /* need internal clock */ 1038 if (mask & SDHCI_RESET_ALL) 1039 sdhci_gli_enable_internal_clock(host); 1040 1041 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1042 1043 /* reset sd-tran on UHS2 mode if need to reset cmd/data */ 1044 if ((mask & SDHCI_RESET_CMD) | (mask & SDHCI_RESET_DATA)) 1045 sdhci_gli_uhs2_reset_sd_tran(host); 1046 1047 if (mask & SDHCI_RESET_ALL) 1048 host->clock = 0; 1049 1050 sdhci_gli_wait_software_reset_done(host, mask); 1051 } 1052 1053 static inline void gl9767_vhs_read(struct pci_dev *pdev) 1054 { 1055 u32 vhs_enable; 1056 u32 vhs_value; 1057 1058 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 1059 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 1060 1061 if (vhs_enable == GLI_9767_VHS_REV_R) 1062 return; 1063 1064 vhs_value &= ~GLI_9767_VHS_REV; 1065 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R); 1066 1067 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 1068 } 1069 1070 static inline void gl9767_vhs_write(struct pci_dev *pdev) 1071 { 1072 u32 vhs_enable; 1073 u32 vhs_value; 1074 1075 pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value); 1076 vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value); 1077 1078 if (vhs_enable == GLI_9767_VHS_REV_W) 1079 return; 1080 1081 vhs_value &= ~GLI_9767_VHS_REV; 1082 vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W); 1083 1084 pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value); 1085 } 1086 1087 static bool gl9767_ssc_enable(struct pci_dev *pdev) 1088 { 1089 u32 value; 1090 u8 enable; 1091 1092 gl9767_vhs_write(pdev); 1093 1094 pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value); 1095 enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value); 1096 1097 gl9767_vhs_read(pdev); 1098 1099 return enable; 1100 } 1101 1102 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm) 1103 { 1104 u32 pll; 1105 u32 ssc; 1106 1107 gl9767_vhs_write(pdev); 1108 1109 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1110 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc); 1111 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING | 1112 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 1113 ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM; 1114 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) | 1115 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable); 1116 ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm); 1117 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc); 1118 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1119 1120 gl9767_vhs_read(pdev); 1121 } 1122 1123 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv) 1124 { 1125 u32 pll; 1126 1127 gl9767_vhs_write(pdev); 1128 1129 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1130 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV | 1131 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV | 1132 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN); 1133 pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) | 1134 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) | 1135 FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir); 1136 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1137 1138 gl9767_vhs_read(pdev); 1139 1140 /* wait for pll stable */ 1141 usleep_range(1000, 1100); 1142 } 1143 1144 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev) 1145 { 1146 bool enable = gl9767_ssc_enable(pdev); 1147 1148 /* set pll to 205MHz and ssc */ 1149 gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3); 1150 gl9767_set_pll(pdev, 0x1, 0x246, 0x0); 1151 } 1152 1153 static void gl9767_disable_ssc_pll(struct pci_dev *pdev) 1154 { 1155 u32 pll; 1156 1157 gl9767_vhs_write(pdev); 1158 1159 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll); 1160 pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN); 1161 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll); 1162 1163 gl9767_vhs_read(pdev); 1164 } 1165 1166 static void gl9767_set_low_power_negotiation(struct pci_dev *pdev, bool enable) 1167 { 1168 u32 value; 1169 1170 gl9767_vhs_write(pdev); 1171 1172 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1173 if (enable) 1174 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1175 else 1176 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1177 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1178 1179 gl9767_vhs_read(pdev); 1180 } 1181 1182 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock) 1183 { 1184 struct sdhci_pci_slot *slot = sdhci_priv(host); 1185 struct mmc_ios *ios = &host->mmc->ios; 1186 struct pci_dev *pdev; 1187 u16 clk; 1188 1189 pdev = slot->chip->pdev; 1190 host->mmc->actual_clock = 0; 1191 1192 gl9767_set_low_power_negotiation(pdev, false); 1193 gl9767_disable_ssc_pll(pdev); 1194 sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); 1195 1196 if (clock == 0) { 1197 gl9767_set_low_power_negotiation(pdev, true); 1198 return; 1199 } 1200 1201 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 1202 if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) { 1203 host->mmc->actual_clock = 205000000; 1204 gl9767_set_ssc_pll_205mhz(pdev); 1205 } 1206 1207 sdhci_enable_clk(host, clk); 1208 gl9767_set_low_power_negotiation(pdev, true); 1209 } 1210 1211 static void sdhci_gl9767_set_card_detect_debounce_time(struct sdhci_host *host) 1212 { 1213 u32 value; 1214 1215 value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1216 value &= ~(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE | 1217 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE); 1218 if (sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT) 1219 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, 1220 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_IN_VALUE) | 1221 FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, 1222 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_1MS); 1223 else 1224 value |= FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE, 1225 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_PLUG_OUT_VALUE) | 1226 FIELD_PREP(SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE, 1227 SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_DEBOUNCE_SCALE_10MS); 1228 sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1229 } 1230 1231 static void sdhci_gl9767_card_event(struct sdhci_host *host) 1232 { 1233 sdhci_gl9767_set_card_detect_debounce_time(host); 1234 } 1235 1236 static void gli_set_9767(struct sdhci_host *host) 1237 { 1238 u32 value; 1239 1240 value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE); 1241 value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET; 1242 sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE); 1243 1244 value = sdhci_readl(host, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1245 value &= ~SDHCI_GLI_9767_SD_HOST_OPERATION_CTL_CMD_CONFLICT_CHECK; 1246 sdhci_writel(host, value, SDHCI_GLI_9767_SD_HOST_OPERATION_CTL); 1247 1248 sdhci_gl9767_set_card_detect_debounce_time(host); 1249 } 1250 1251 static void gl9767_hw_setting(struct sdhci_pci_slot *slot) 1252 { 1253 struct pci_dev *pdev = slot->chip->pdev; 1254 u32 value; 1255 1256 gl9767_vhs_write(pdev); 1257 1258 pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value); 1259 value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 1260 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE | 1261 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL); 1262 1263 value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE | 1264 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE, 1265 PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) | 1266 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL, 1267 PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE); 1268 pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value); 1269 1270 pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value); 1271 value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 | 1272 PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 | 1273 PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN); 1274 1275 value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST | 1276 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST | 1277 PCIE_GLI_9767_SCR_AXI_REQ | 1278 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN | 1279 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF; 1280 pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value); 1281 1282 gl9767_vhs_read(pdev); 1283 } 1284 1285 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask) 1286 { 1287 struct sdhci_pci_slot *slot = sdhci_priv(host); 1288 struct pci_dev *pdev = slot->chip->pdev; 1289 u32 value; 1290 1291 /* need internal clock */ 1292 if (mask & SDHCI_RESET_ALL) { 1293 sdhci_gli_enable_internal_clock(host); 1294 1295 gl9767_vhs_write(pdev); 1296 1297 pci_read_config_dword(pdev, PCIE_GLI_9767_RESET_REG, &value); 1298 value &= ~PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET; 1299 pci_write_config_dword(pdev, PCIE_GLI_9767_RESET_REG, value); 1300 1301 if (read_poll_timeout_atomic(pci_read_config_dword, value, 1302 !(value & PCIE_GLI_9767_RESET_REG_SD_HOST_SW_RESET), 1303 1, 5, true, pdev, PCIE_GLI_9767_RESET_REG, &value)) { 1304 pr_warn("%s: %s: Reset SDHC AHB and TL-AMBA failure.\n", 1305 __func__, mmc_hostname(host->mmc)); 1306 gl9767_vhs_read(pdev); 1307 return; 1308 } 1309 gl9767_vhs_read(pdev); 1310 } 1311 1312 if (mmc_card_uhs2(host->mmc)) { 1313 if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) { 1314 sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); 1315 sdhci_gli_uhs2_reset_sd_tran(host); 1316 sdhci_gli_wait_software_reset_done(host, mask); 1317 } else { 1318 sdhci_uhs2_reset(host, mask); 1319 } 1320 } else { 1321 sdhci_reset(host, mask); 1322 } 1323 1324 gli_set_9767(host); 1325 } 1326 1327 static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 1328 { 1329 struct sdhci_host *host = mmc_priv(mmc); 1330 struct sdhci_pci_slot *slot = sdhci_priv(host); 1331 struct pci_dev *pdev; 1332 u32 value; 1333 int i; 1334 1335 pdev = slot->chip->pdev; 1336 1337 if (mmc->ops->get_ro(mmc)) { 1338 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1339 return 0; 1340 } 1341 1342 gl9767_vhs_write(pdev); 1343 1344 pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value); 1345 value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN); 1346 pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value); 1347 1348 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1349 value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME; 1350 value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME, 1351 PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE); 1352 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1353 1354 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1355 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE; 1356 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value); 1357 1358 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value); 1359 value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN; 1360 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value); 1361 1362 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value); 1363 value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN; 1364 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value); 1365 1366 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1367 value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1368 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1369 1370 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1371 value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1372 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1373 1374 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1375 value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1376 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1377 1378 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1379 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE; 1380 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1381 1382 for (i = 0; i < 2; i++) { 1383 usleep_range(10000, 10100); 1384 pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value); 1385 if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) { 1386 pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, 1387 value); 1388 break; 1389 } 1390 } 1391 1392 pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value); 1393 if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) { 1394 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value); 1395 value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE; 1396 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value); 1397 } else { 1398 mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V); 1399 1400 value = sdhci_readb(host, SDHCI_POWER_CONTROL); 1401 value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON); 1402 sdhci_writeb(host, value, SDHCI_POWER_CONTROL); 1403 1404 value = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1405 value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN); 1406 sdhci_writew(host, value, SDHCI_CLOCK_CONTROL); 1407 } 1408 1409 pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value); 1410 value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF; 1411 pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value); 1412 gl9767_vhs_read(pdev); 1413 1414 return 0; 1415 } 1416 1417 static void gl9767_vendor_init(struct sdhci_host *host) 1418 { 1419 struct sdhci_pci_slot *slot = sdhci_priv(host); 1420 struct pci_dev *pdev = slot->chip->pdev; 1421 u32 value; 1422 1423 gl9767_vhs_write(pdev); 1424 1425 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, &value); 1426 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR, 1427 PCIE_GLI_9767_UHS2_PHY_SET_REG1_SERDES_INTR_VALUE); 1428 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG1, value); 1429 1430 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, &value); 1431 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING, 1432 PCIE_GLI_9767_UHS2_PHY_SET_REG2_SSC_PPM_SETTING_VALUE); 1433 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_PHY_SET_REG2, value); 1434 1435 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, &value); 1436 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS, 1437 PCIE_GLI_9767_UHS2_CTL1_TRANS_PASS_VALUE) | 1438 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL, 1439 PCIE_GLI_9767_UHS2_CTL1_DECODING_CTL_VALUE) | 1440 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN, 1441 PCIE_GLI_9767_UHS2_CTL1_SERDES_TRAN_VALUE) | 1442 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV, 1443 PCIE_GLI_9767_UHS2_CTL1_SERDES_RECV_VALUE) | 1444 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS, 1445 PCIE_GLI_9767_UHS2_CTL1_DIR_TRANS_VALUE) | 1446 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_DIR_RECV, 1447 PCIE_GLI_9767_UHS2_CTL1_DIR_RECV_VALUE) | 1448 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL1_PDRST, 1449 PCIE_GLI_9767_UHS2_CTL1_PDRST_VALUE); 1450 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL1, value); 1451 1452 pci_read_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, &value); 1453 value |= FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC, 1454 PCIE_GLI_9767_UHS2_CTL2_ZC_VALUE) | 1455 FIELD_PREP(PCIE_GLI_9767_UHS2_CTL2_ZC_CTL, 1456 PCIE_GLI_9767_UHS2_CTL2_ZC_CTL_VALUE); 1457 pci_write_config_dword(pdev, PCIE_GLI_9767_UHS2_CTL2, value); 1458 1459 gl9767_vhs_read(pdev); 1460 } 1461 1462 static void sdhci_gl9767_set_power(struct sdhci_host *host, unsigned char mode, unsigned short vdd) 1463 { 1464 struct sdhci_pci_slot *slot = sdhci_priv(host); 1465 struct pci_dev *pdev = slot->chip->pdev; 1466 u32 value; 1467 1468 if (mmc_card_uhs2(host->mmc)) { 1469 gl9767_vhs_write(pdev); 1470 1471 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1472 value |= PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | 1473 PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL; 1474 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1475 1476 gl9767_vhs_read(pdev); 1477 1478 sdhci_gli_overcurrent_event_enable(host, false); 1479 sdhci_uhs2_set_power(host, mode, vdd); 1480 sdhci_gli_overcurrent_event_enable(host, true); 1481 } else { 1482 gl9767_vhs_write(pdev); 1483 1484 pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value); 1485 value &= ~(PCIE_GLI_9767_SD_DATA_MULTI_CTL_SELECT_UHS2 | 1486 PCIE_GLI_9767_SD_DATA_MULTI_CTL_UHS2_SWITCH_CTL); 1487 pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value); 1488 1489 gl9767_vhs_read(pdev); 1490 1491 sdhci_gli_overcurrent_event_enable(host, false); 1492 sdhci_set_power(host, mode, vdd); 1493 sdhci_gli_overcurrent_event_enable(host, true); 1494 } 1495 } 1496 1497 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot) 1498 { 1499 struct sdhci_host *host = slot->host; 1500 1501 gl9750_hw_setting(host); 1502 gli_pcie_enable_msi(slot); 1503 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1504 sdhci_enable_v4_mode(host); 1505 1506 return 0; 1507 } 1508 1509 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot) 1510 { 1511 struct sdhci_host *host = slot->host; 1512 1513 gl9755_hw_setting(slot); 1514 gli_pcie_enable_msi(slot); 1515 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1516 sdhci_enable_v4_mode(host); 1517 gl9755_vendor_init(host); 1518 1519 return 0; 1520 } 1521 1522 static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot) 1523 { 1524 struct sdhci_host *host = slot->host; 1525 1526 gli_set_9767(host); 1527 gl9767_hw_setting(slot); 1528 gli_pcie_enable_msi(slot); 1529 slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO; 1530 host->mmc->caps2 |= MMC_CAP2_SD_EXP; 1531 host->mmc_host_ops.init_sd_express = gl9767_init_sd_express; 1532 sdhci_enable_v4_mode(host); 1533 gl9767_vendor_init(host); 1534 1535 return 0; 1536 } 1537 1538 static void sdhci_gli_voltage_switch(struct sdhci_host *host) 1539 { 1540 /* 1541 * According to Section 3.6.1 signal voltage switch procedure in 1542 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1543 * follows: 1544 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1545 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1546 * period. 1547 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1548 * step (12). 1549 * 1550 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1551 * to ensure 1.8V signal enable bit is set by GL9750/GL9755. 1552 * 1553 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires 1554 * slightly longer than 5ms before the control register reports that 1555 * 1.8V is ready, and far longer still before the card will actually 1556 * work reliably. 1557 */ 1558 usleep_range(100000, 110000); 1559 } 1560 1561 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host) 1562 { 1563 /* 1564 * According to Section 3.6.1 signal voltage switch procedure in 1565 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as 1566 * follows: 1567 * (6) Set 1.8V Signal Enable in the Host Control 2 register. 1568 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this 1569 * period. 1570 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to 1571 * step (12). 1572 * 1573 * Wait 5ms after set 1.8V signal enable in Host Control 2 register 1574 * to ensure 1.8V signal enable bit is set by GL9767. 1575 * 1576 */ 1577 usleep_range(5000, 5500); 1578 } 1579 1580 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask) 1581 { 1582 sdhci_reset(host, mask); 1583 gli_set_9750(host); 1584 } 1585 1586 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg) 1587 { 1588 u32 value; 1589 1590 value = readl(host->ioaddr + reg); 1591 if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff))) 1592 value |= 0xc8; 1593 1594 return value; 1595 } 1596 1597 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc, 1598 struct mmc_ios *ios) 1599 { 1600 struct sdhci_host *host = mmc_priv(mmc); 1601 u32 val; 1602 1603 val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG); 1604 if (ios->enhanced_strobe) 1605 val |= SDHCI_GLI_9763E_HS400_ES_BIT; 1606 else 1607 val &= ~SDHCI_GLI_9763E_HS400_ES_BIT; 1608 1609 sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG); 1610 } 1611 1612 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, 1613 bool enable) 1614 { 1615 struct pci_dev *pdev = slot->chip->pdev; 1616 u32 value; 1617 1618 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1619 value &= ~GLI_9763E_VHS_REV; 1620 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1621 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1622 1623 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value); 1624 1625 if (enable) 1626 value &= ~GLI_9763E_CFG_LPSN_DIS; 1627 else 1628 value |= GLI_9763E_CFG_LPSN_DIS; 1629 1630 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value); 1631 1632 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1633 value &= ~GLI_9763E_VHS_REV; 1634 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1635 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1636 } 1637 1638 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host, 1639 unsigned int timing) 1640 { 1641 u16 ctrl_2; 1642 1643 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1644 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1645 if (timing == MMC_TIMING_MMC_HS200) 1646 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1647 else if (timing == MMC_TIMING_MMC_HS) 1648 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1649 else if (timing == MMC_TIMING_MMC_DDR52) 1650 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1651 else if (timing == MMC_TIMING_MMC_HS400) 1652 ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400; 1653 1654 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1655 } 1656 1657 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc) 1658 { 1659 sdhci_dumpregs(mmc_priv(mmc)); 1660 } 1661 1662 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc) 1663 { 1664 struct cqhci_host *cq_host = mmc->cqe_private; 1665 u32 value; 1666 1667 value = cqhci_readl(cq_host, CQHCI_CFG); 1668 value |= CQHCI_ENABLE; 1669 cqhci_writel(cq_host, value, CQHCI_CFG); 1670 } 1671 1672 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc) 1673 { 1674 struct sdhci_host *host = mmc_priv(mmc); 1675 1676 sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 1677 sdhci_cqe_enable(mmc); 1678 } 1679 1680 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask) 1681 { 1682 int cmd_error = 0; 1683 int data_error = 0; 1684 1685 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1686 return intmask; 1687 1688 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1689 1690 return 0; 1691 } 1692 1693 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc) 1694 { 1695 struct sdhci_host *host = mmc_priv(mmc); 1696 struct cqhci_host *cq_host = mmc->cqe_private; 1697 u32 value; 1698 1699 value = cqhci_readl(cq_host, CQHCI_CFG); 1700 value &= ~CQHCI_ENABLE; 1701 cqhci_writel(cq_host, value, CQHCI_CFG); 1702 sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); 1703 } 1704 1705 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = { 1706 .enable = sdhci_gl9763e_cqe_enable, 1707 .disable = sdhci_cqe_disable, 1708 .dumpregs = sdhci_gl9763e_dumpregs, 1709 .pre_enable = sdhci_gl9763e_cqe_pre_enable, 1710 .post_disable = sdhci_gl9763e_cqe_post_disable, 1711 }; 1712 1713 static int gl9763e_add_host(struct sdhci_pci_slot *slot) 1714 { 1715 struct device *dev = &slot->chip->pdev->dev; 1716 struct sdhci_host *host = slot->host; 1717 struct cqhci_host *cq_host; 1718 bool dma64; 1719 int ret; 1720 1721 ret = sdhci_setup_host(host); 1722 if (ret) 1723 return ret; 1724 1725 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 1726 if (!cq_host) { 1727 ret = -ENOMEM; 1728 goto cleanup; 1729 } 1730 1731 cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR; 1732 cq_host->ops = &sdhci_gl9763e_cqhci_ops; 1733 1734 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1735 if (dma64) 1736 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1737 1738 ret = cqhci_init(cq_host, host->mmc, dma64); 1739 if (ret) 1740 goto cleanup; 1741 1742 ret = __sdhci_add_host(host); 1743 if (ret) 1744 goto cleanup; 1745 1746 /* Disable LPM negotiation to avoid entering L1 state. */ 1747 gl9763e_set_low_power_negotiation(slot, false); 1748 1749 return 0; 1750 1751 cleanup: 1752 sdhci_cleanup_host(host); 1753 return ret; 1754 } 1755 1756 static void gl9763e_hw_setting(struct sdhci_pci_slot *slot) 1757 { 1758 struct pci_dev *pdev = slot->chip->pdev; 1759 u32 value; 1760 1761 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1762 value &= ~GLI_9763E_VHS_REV; 1763 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W); 1764 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1765 1766 pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value); 1767 value |= GLI_9763E_SCR_AXI_REQ; 1768 pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value); 1769 1770 pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value); 1771 value &= ~GLI_9763E_HS400_SLOW; 1772 pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value); 1773 1774 pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value); 1775 value &= ~GLI_9763E_CFG2_L1DLY; 1776 /* set ASPM L1 entry delay to 21us */ 1777 value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID); 1778 pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value); 1779 1780 pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value); 1781 value &= ~GLI_9763E_HS400_RXDLY; 1782 value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5); 1783 pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value); 1784 1785 /* mask the replay timer timeout of AER */ 1786 sdhci_gli_mask_replay_timer_timeout(pdev); 1787 1788 pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value); 1789 value &= ~GLI_9763E_VHS_REV; 1790 value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R); 1791 pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value); 1792 } 1793 1794 #ifdef CONFIG_PM 1795 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip) 1796 { 1797 struct sdhci_pci_slot *slot = chip->slots[0]; 1798 struct sdhci_host *host = slot->host; 1799 u16 clock; 1800 1801 /* Enable LPM negotiation to allow entering L1 state */ 1802 gl9763e_set_low_power_negotiation(slot, true); 1803 1804 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1805 clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN); 1806 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1807 1808 return 0; 1809 } 1810 1811 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip) 1812 { 1813 struct sdhci_pci_slot *slot = chip->slots[0]; 1814 struct sdhci_host *host = slot->host; 1815 u16 clock; 1816 1817 if (host->mmc->ios.power_mode != MMC_POWER_ON) 1818 return 0; 1819 1820 clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1821 1822 clock |= SDHCI_CLOCK_PLL_EN; 1823 clock &= ~SDHCI_CLOCK_INT_STABLE; 1824 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1825 1826 /* Wait max 150 ms */ 1827 if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE), 1828 1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) { 1829 pr_err("%s: PLL clock never stabilised.\n", 1830 mmc_hostname(host->mmc)); 1831 sdhci_dumpregs(host); 1832 } 1833 1834 clock |= SDHCI_CLOCK_CARD_EN; 1835 sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL); 1836 1837 /* Disable LPM negotiation to avoid entering L1 state. */ 1838 gl9763e_set_low_power_negotiation(slot, false); 1839 1840 return 0; 1841 } 1842 #endif 1843 1844 #ifdef CONFIG_PM_SLEEP 1845 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip) 1846 { 1847 struct sdhci_pci_slot *slot = chip->slots[0]; 1848 1849 pci_free_irq_vectors(slot->chip->pdev); 1850 gli_pcie_enable_msi(slot); 1851 1852 return sdhci_pci_resume_host(chip); 1853 } 1854 1855 static int gl9763e_resume(struct sdhci_pci_chip *chip) 1856 { 1857 struct sdhci_pci_slot *slot = chip->slots[0]; 1858 int ret; 1859 1860 ret = sdhci_pci_gli_resume(chip); 1861 if (ret) 1862 return ret; 1863 1864 ret = cqhci_resume(slot->host->mmc); 1865 if (ret) 1866 return ret; 1867 1868 /* 1869 * Disable LPM negotiation to bring device back in sync 1870 * with its runtime_pm state. 1871 */ 1872 gl9763e_set_low_power_negotiation(slot, false); 1873 1874 return 0; 1875 } 1876 1877 static int gl9763e_suspend(struct sdhci_pci_chip *chip) 1878 { 1879 struct sdhci_pci_slot *slot = chip->slots[0]; 1880 int ret; 1881 1882 /* 1883 * Certain SoCs can suspend only with the bus in low- 1884 * power state, notably x86 SoCs when using S0ix. 1885 * Re-enable LPM negotiation to allow entering L1 state 1886 * and entering system suspend. 1887 */ 1888 gl9763e_set_low_power_negotiation(slot, true); 1889 1890 ret = cqhci_suspend(slot->host->mmc); 1891 if (ret) 1892 goto err_suspend; 1893 1894 ret = sdhci_suspend_host(slot->host); 1895 if (ret) 1896 goto err_suspend_host; 1897 1898 return 0; 1899 1900 err_suspend_host: 1901 cqhci_resume(slot->host->mmc); 1902 err_suspend: 1903 gl9763e_set_low_power_negotiation(slot, false); 1904 return ret; 1905 } 1906 #endif 1907 1908 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot) 1909 { 1910 struct pci_dev *pdev = slot->chip->pdev; 1911 struct sdhci_host *host = slot->host; 1912 u32 value; 1913 1914 host->mmc->caps |= MMC_CAP_8_BIT_DATA | 1915 MMC_CAP_1_8V_DDR | 1916 MMC_CAP_NONREMOVABLE; 1917 host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR | 1918 MMC_CAP2_HS400_1_8V | 1919 MMC_CAP2_HS400_ES | 1920 MMC_CAP2_NO_SDIO | 1921 MMC_CAP2_NO_SD; 1922 1923 pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value); 1924 if (!(value & GLI_9763E_MB_CMDQ_OFF)) 1925 if (value & GLI_9763E_MB_ERP_ON) 1926 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1927 1928 gli_pcie_enable_msi(slot); 1929 host->mmc_host_ops.hs400_enhanced_strobe = 1930 gl9763e_hs400_enhanced_strobe; 1931 gl9763e_hw_setting(slot); 1932 sdhci_enable_v4_mode(host); 1933 1934 return 0; 1935 } 1936 1937 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18) 1938 1939 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg) 1940 { 1941 u32 val = readl(host->ioaddr + (reg & ~3)); 1942 u16 word; 1943 1944 word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff; 1945 return word; 1946 } 1947 1948 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg) 1949 { 1950 u32 val = readl(host->ioaddr + (reg & ~3)); 1951 u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff; 1952 1953 return byte; 1954 } 1955 1956 static const struct sdhci_ops sdhci_gl9755_ops = { 1957 .read_w = sdhci_gli_readw, 1958 .read_b = sdhci_gli_readb, 1959 .set_clock = sdhci_gl9755_set_clock, 1960 .set_power = gl9755_set_power, 1961 .enable_dma = sdhci_pci_enable_dma, 1962 .set_bus_width = sdhci_set_bus_width, 1963 .reset = sdhci_gl9755_reset, 1964 .set_uhs_signaling = sdhci_set_uhs_signaling, 1965 .voltage_switch = sdhci_gli_voltage_switch, 1966 .dump_uhs2_regs = sdhci_uhs2_dump_regs, 1967 .set_timeout = sdhci_uhs2_set_timeout, 1968 .irq = sdhci_uhs2_irq, 1969 .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, 1970 }; 1971 1972 const struct sdhci_pci_fixes sdhci_gl9755 = { 1973 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1974 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 1975 .probe_slot = gli_probe_slot_gl9755, 1976 .add_host = sdhci_pci_uhs2_add_host, 1977 .remove_host = sdhci_pci_uhs2_remove_host, 1978 .ops = &sdhci_gl9755_ops, 1979 #ifdef CONFIG_PM_SLEEP 1980 .resume = sdhci_pci_gli_resume, 1981 #endif 1982 }; 1983 1984 static const struct sdhci_ops sdhci_gl9750_ops = { 1985 .read_w = sdhci_gli_readw, 1986 .read_b = sdhci_gli_readb, 1987 .read_l = sdhci_gl9750_readl, 1988 .set_clock = sdhci_gl9750_set_clock, 1989 .enable_dma = sdhci_pci_enable_dma, 1990 .set_bus_width = sdhci_set_bus_width, 1991 .reset = sdhci_gl9750_reset, 1992 .set_uhs_signaling = sdhci_set_uhs_signaling, 1993 .voltage_switch = sdhci_gli_voltage_switch, 1994 .platform_execute_tuning = gl9750_execute_tuning, 1995 }; 1996 1997 const struct sdhci_pci_fixes sdhci_gl9750 = { 1998 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1999 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2000 .probe_slot = gli_probe_slot_gl9750, 2001 .ops = &sdhci_gl9750_ops, 2002 #ifdef CONFIG_PM_SLEEP 2003 .resume = sdhci_pci_gli_resume, 2004 #endif 2005 }; 2006 2007 static const struct sdhci_ops sdhci_gl9763e_ops = { 2008 .set_clock = sdhci_set_clock, 2009 .enable_dma = sdhci_pci_enable_dma, 2010 .set_bus_width = sdhci_set_bus_width, 2011 .reset = sdhci_and_cqhci_reset, 2012 .set_uhs_signaling = sdhci_set_gl9763e_signaling, 2013 .voltage_switch = sdhci_gli_voltage_switch, 2014 .irq = sdhci_gl9763e_cqhci_irq, 2015 }; 2016 2017 const struct sdhci_pci_fixes sdhci_gl9763e = { 2018 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2019 .probe_slot = gli_probe_slot_gl9763e, 2020 .ops = &sdhci_gl9763e_ops, 2021 #ifdef CONFIG_PM_SLEEP 2022 .resume = gl9763e_resume, 2023 .suspend = gl9763e_suspend, 2024 #endif 2025 #ifdef CONFIG_PM 2026 .runtime_suspend = gl9763e_runtime_suspend, 2027 .runtime_resume = gl9763e_runtime_resume, 2028 .allow_runtime_pm = true, 2029 #endif 2030 .add_host = gl9763e_add_host, 2031 }; 2032 2033 static const struct sdhci_ops sdhci_gl9767_ops = { 2034 .set_clock = sdhci_gl9767_set_clock, 2035 .enable_dma = sdhci_pci_enable_dma, 2036 .set_bus_width = sdhci_set_bus_width, 2037 .reset = sdhci_gl9767_reset, 2038 .set_uhs_signaling = sdhci_set_uhs_signaling, 2039 .voltage_switch = sdhci_gl9767_voltage_switch, 2040 .dump_uhs2_regs = sdhci_uhs2_dump_regs, 2041 .set_timeout = sdhci_uhs2_set_timeout, 2042 .irq = sdhci_uhs2_irq, 2043 .set_power = sdhci_gl9767_set_power, 2044 .uhs2_pre_detect_init = sdhci_gli_pre_detect_init, 2045 .card_event = sdhci_gl9767_card_event, 2046 }; 2047 2048 const struct sdhci_pci_fixes sdhci_gl9767 = { 2049 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 2050 .quirks2 = SDHCI_QUIRK2_BROKEN_DDR50, 2051 .probe_slot = gli_probe_slot_gl9767, 2052 .add_host = sdhci_pci_uhs2_add_host, 2053 .remove_host = sdhci_pci_uhs2_remove_host, 2054 .ops = &sdhci_gl9767_ops, 2055 #ifdef CONFIG_PM_SLEEP 2056 .resume = sdhci_pci_gli_resume, 2057 #endif 2058 }; 2059