xref: /linux/drivers/mmc/host/sdhci-pci-gli.c (revision 031fba65fc202abf1f193e321be7a2c274fd88ba)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright (C) 2019 Genesys Logic, Inc.
4  *
5  * Authors: Ben Chuang <ben.chuang@genesyslogic.com.tw>
6  *
7  * Version: v0.9.0 (2019-08-08)
8  */
9 
10 #include <linux/bitfield.h>
11 #include <linux/bits.h>
12 #include <linux/pci.h>
13 #include <linux/mmc/mmc.h>
14 #include <linux/delay.h>
15 #include <linux/of.h>
16 #include <linux/iopoll.h>
17 #include "sdhci.h"
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pci.h"
20 #include "cqhci.h"
21 
22 /*  Genesys Logic extra registers */
23 #define SDHCI_GLI_9750_WT         0x800
24 #define   SDHCI_GLI_9750_WT_EN      BIT(0)
25 #define   GLI_9750_WT_EN_ON	    0x1
26 #define   GLI_9750_WT_EN_OFF	    0x0
27 
28 #define PCI_GLI_9750_PM_CTRL	0xFC
29 #define   PCI_GLI_9750_PM_STATE	  GENMASK(1, 0)
30 
31 #define SDHCI_GLI_9750_CFG2          0x848
32 #define   SDHCI_GLI_9750_CFG2_L1DLY    GENMASK(28, 24)
33 #define   GLI_9750_CFG2_L1DLY_VALUE    0x1F
34 
35 #define SDHCI_GLI_9750_DRIVING      0x860
36 #define   SDHCI_GLI_9750_DRIVING_1    GENMASK(11, 0)
37 #define   SDHCI_GLI_9750_DRIVING_2    GENMASK(27, 26)
38 #define   GLI_9750_DRIVING_1_VALUE    0xFFF
39 #define   GLI_9750_DRIVING_2_VALUE    0x3
40 #define   SDHCI_GLI_9750_SEL_1        BIT(29)
41 #define   SDHCI_GLI_9750_SEL_2        BIT(31)
42 #define   SDHCI_GLI_9750_ALL_RST      (BIT(24)|BIT(25)|BIT(28)|BIT(30))
43 
44 #define SDHCI_GLI_9750_PLL	      0x864
45 #define   SDHCI_GLI_9750_PLL_LDIV       GENMASK(9, 0)
46 #define   SDHCI_GLI_9750_PLL_PDIV       GENMASK(14, 12)
47 #define   SDHCI_GLI_9750_PLL_DIR        BIT(15)
48 #define   SDHCI_GLI_9750_PLL_TX2_INV    BIT(23)
49 #define   SDHCI_GLI_9750_PLL_TX2_DLY    GENMASK(22, 20)
50 #define   GLI_9750_PLL_TX2_INV_VALUE    0x1
51 #define   GLI_9750_PLL_TX2_DLY_VALUE    0x0
52 #define   SDHCI_GLI_9750_PLLSSC_STEP    GENMASK(28, 24)
53 #define   SDHCI_GLI_9750_PLLSSC_EN      BIT(31)
54 
55 #define SDHCI_GLI_9750_PLLSSC        0x86C
56 #define   SDHCI_GLI_9750_PLLSSC_PPM    GENMASK(31, 16)
57 
58 #define SDHCI_GLI_9750_SW_CTRL      0x874
59 #define   SDHCI_GLI_9750_SW_CTRL_4    GENMASK(7, 6)
60 #define   GLI_9750_SW_CTRL_4_VALUE    0x3
61 
62 #define SDHCI_GLI_9750_MISC            0x878
63 #define   SDHCI_GLI_9750_MISC_TX1_INV    BIT(2)
64 #define   SDHCI_GLI_9750_MISC_RX_INV     BIT(3)
65 #define   SDHCI_GLI_9750_MISC_TX1_DLY    GENMASK(6, 4)
66 #define   GLI_9750_MISC_TX1_INV_VALUE    0x0
67 #define   GLI_9750_MISC_RX_INV_ON        0x1
68 #define   GLI_9750_MISC_RX_INV_OFF       0x0
69 #define   GLI_9750_MISC_RX_INV_VALUE     GLI_9750_MISC_RX_INV_OFF
70 #define   GLI_9750_MISC_TX1_DLY_VALUE    0x5
71 #define   SDHCI_GLI_9750_MISC_SSC_OFF    BIT(26)
72 
73 #define SDHCI_GLI_9750_TUNING_CONTROL	          0x540
74 #define   SDHCI_GLI_9750_TUNING_CONTROL_EN          BIT(4)
75 #define   GLI_9750_TUNING_CONTROL_EN_ON             0x1
76 #define   GLI_9750_TUNING_CONTROL_EN_OFF            0x0
77 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1    BIT(16)
78 #define   SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2    GENMASK(20, 19)
79 #define   GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE    0x1
80 #define   GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE    0x2
81 
82 #define SDHCI_GLI_9750_TUNING_PARAMETERS           0x544
83 #define   SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY    GENMASK(2, 0)
84 #define   GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE    0x1
85 
86 #define SDHCI_GLI_9763E_CTRL_HS400  0x7
87 
88 #define SDHCI_GLI_9763E_HS400_ES_REG      0x52C
89 #define   SDHCI_GLI_9763E_HS400_ES_BIT      BIT(8)
90 
91 #define PCIE_GLI_9763E_VHS	 0x884
92 #define   GLI_9763E_VHS_REV	   GENMASK(19, 16)
93 #define   GLI_9763E_VHS_REV_R      0x0
94 #define   GLI_9763E_VHS_REV_M      0x1
95 #define   GLI_9763E_VHS_REV_W      0x2
96 #define PCIE_GLI_9763E_MB	 0x888
97 #define   GLI_9763E_MB_CMDQ_OFF	   BIT(19)
98 #define   GLI_9763E_MB_ERP_ON      BIT(7)
99 #define PCIE_GLI_9763E_SCR	 0x8E0
100 #define   GLI_9763E_SCR_AXI_REQ	   BIT(9)
101 
102 #define PCIE_GLI_9763E_CFG       0x8A0
103 #define   GLI_9763E_CFG_LPSN_DIS   BIT(12)
104 
105 #define PCIE_GLI_9763E_CFG2      0x8A4
106 #define   GLI_9763E_CFG2_L1DLY     GENMASK(28, 19)
107 #define   GLI_9763E_CFG2_L1DLY_MID 0x54
108 
109 #define PCIE_GLI_9763E_MMC_CTRL  0x960
110 #define   GLI_9763E_HS400_SLOW     BIT(3)
111 
112 #define PCIE_GLI_9763E_CLKRXDLY  0x934
113 #define   GLI_9763E_HS400_RXDLY    GENMASK(31, 28)
114 #define   GLI_9763E_HS400_RXDLY_5  0x5
115 
116 #define SDHCI_GLI_9763E_CQE_BASE_ADDR	 0x200
117 #define GLI_9763E_CQE_TRNS_MODE	   (SDHCI_TRNS_MULTI | \
118 				    SDHCI_TRNS_BLK_CNT_EN | \
119 				    SDHCI_TRNS_DMA)
120 
121 #define PCI_GLI_9755_WT       0x800
122 #define   PCI_GLI_9755_WT_EN    BIT(0)
123 #define   GLI_9755_WT_EN_ON     0x1
124 #define   GLI_9755_WT_EN_OFF    0x0
125 
126 #define PCI_GLI_9755_PECONF   0x44
127 #define   PCI_GLI_9755_LFCLK    GENMASK(14, 12)
128 #define   PCI_GLI_9755_DMACLK   BIT(29)
129 #define   PCI_GLI_9755_INVERT_CD  BIT(30)
130 #define   PCI_GLI_9755_INVERT_WP  BIT(31)
131 
132 #define PCI_GLI_9755_CFG2          0x48
133 #define   PCI_GLI_9755_CFG2_L1DLY    GENMASK(28, 24)
134 #define   GLI_9755_CFG2_L1DLY_VALUE  0x1F
135 
136 #define PCI_GLI_9755_PLL            0x64
137 #define   PCI_GLI_9755_PLL_LDIV       GENMASK(9, 0)
138 #define   PCI_GLI_9755_PLL_PDIV       GENMASK(14, 12)
139 #define   PCI_GLI_9755_PLL_DIR        BIT(15)
140 #define   PCI_GLI_9755_PLLSSC_STEP    GENMASK(28, 24)
141 #define   PCI_GLI_9755_PLLSSC_EN      BIT(31)
142 
143 #define PCI_GLI_9755_PLLSSC        0x68
144 #define   PCI_GLI_9755_PLLSSC_PPM    GENMASK(15, 0)
145 
146 #define PCI_GLI_9755_SerDes  0x70
147 #define PCI_GLI_9755_SCP_DIS   BIT(19)
148 
149 #define PCI_GLI_9755_MISC	    0x78
150 #define   PCI_GLI_9755_MISC_SSC_OFF    BIT(26)
151 
152 #define PCI_GLI_9755_PM_CTRL     0xFC
153 #define   PCI_GLI_9755_PM_STATE    GENMASK(1, 0)
154 
155 #define SDHCI_GLI_9767_GM_BURST_SIZE			0x510
156 #define   SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET	  BIT(8)
157 
158 #define PCIE_GLI_9767_VHS	0x884
159 #define   GLI_9767_VHS_REV	  GENMASK(19, 16)
160 #define   GLI_9767_VHS_REV_R	  0x0
161 #define   GLI_9767_VHS_REV_M	  0x1
162 #define   GLI_9767_VHS_REV_W	  0x2
163 
164 #define PCIE_GLI_9767_COM_MAILBOX		0x888
165 #define   PCIE_GLI_9767_COM_MAILBOX_SSC_EN	  BIT(1)
166 
167 #define PCIE_GLI_9767_CFG		0x8A0
168 #define   PCIE_GLI_9767_CFG_LOW_PWR_OFF	  BIT(12)
169 
170 #define PCIE_GLI_9767_COMBO_MUX_CTL			0x8C8
171 #define   PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN		  BIT(6)
172 #define   PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN	  BIT(10)
173 
174 #define PCIE_GLI_9767_PWR_MACRO_CTL					0x8D0
175 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE			  GENMASK(3, 0)
176 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE		  GENMASK(15, 12)
177 #define   PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE	  0x7
178 #define   PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL		  GENMASK(29, 28)
179 #define   PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE		  0x3
180 
181 #define PCIE_GLI_9767_SCR				0x8E0
182 #define   PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST		  BIT(6)
183 #define   PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST		  BIT(7)
184 #define   PCIE_GLI_9767_SCR_AXI_REQ			  BIT(9)
185 #define   PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN	  BIT(10)
186 #define   PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0	  BIT(16)
187 #define   PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1	  BIT(17)
188 #define   PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF		  BIT(21)
189 #define   PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN	  BIT(30)
190 
191 #define PCIE_GLI_9767_SDHC_CAP			0x91C
192 #define   PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT	  BIT(5)
193 
194 #define PCIE_GLI_9767_SD_PLL_CTL			0x938
195 #define   PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV		  GENMASK(9, 0)
196 #define   PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV		  GENMASK(15, 12)
197 #define   PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN		  BIT(16)
198 #define   PCIE_GLI_9767_SD_PLL_CTL_SSC_EN		  BIT(19)
199 #define   PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING	  GENMASK(28, 24)
200 
201 #define PCIE_GLI_9767_SD_PLL_CTL2		0x93C
202 #define   PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM	  GENMASK(31, 16)
203 
204 #define PCIE_GLI_9767_SD_EXPRESS_CTL			0x940
205 #define   PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE		  BIT(0)
206 #define   PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE	  BIT(1)
207 
208 #define PCIE_GLI_9767_SD_DATA_MULTI_CTL				0x944
209 #define   PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME	  GENMASK(23, 16)
210 #define   PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE	  0x64
211 
212 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2			0x950
213 #define   PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE	  BIT(0)
214 
215 #define PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2				0x954
216 #define   PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN	  BIT(0)
217 
218 #define PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2				0x958
219 #define   PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN	  BIT(0)
220 
221 #define GLI_MAX_TUNING_LOOP 40
222 
223 /* Genesys Logic chipset */
224 static inline void gl9750_wt_on(struct sdhci_host *host)
225 {
226 	u32 wt_value;
227 	u32 wt_enable;
228 
229 	wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
230 	wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
231 
232 	if (wt_enable == GLI_9750_WT_EN_ON)
233 		return;
234 
235 	wt_value &= ~SDHCI_GLI_9750_WT_EN;
236 	wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON);
237 
238 	sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
239 }
240 
241 static inline void gl9750_wt_off(struct sdhci_host *host)
242 {
243 	u32 wt_value;
244 	u32 wt_enable;
245 
246 	wt_value = sdhci_readl(host, SDHCI_GLI_9750_WT);
247 	wt_enable = FIELD_GET(SDHCI_GLI_9750_WT_EN, wt_value);
248 
249 	if (wt_enable == GLI_9750_WT_EN_OFF)
250 		return;
251 
252 	wt_value &= ~SDHCI_GLI_9750_WT_EN;
253 	wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF);
254 
255 	sdhci_writel(host, wt_value, SDHCI_GLI_9750_WT);
256 }
257 
258 static void gli_set_9750(struct sdhci_host *host)
259 {
260 	u32 driving_value;
261 	u32 pll_value;
262 	u32 sw_ctrl_value;
263 	u32 misc_value;
264 	u32 parameter_value;
265 	u32 control_value;
266 	u16 ctrl2;
267 
268 	gl9750_wt_on(host);
269 
270 	driving_value = sdhci_readl(host, SDHCI_GLI_9750_DRIVING);
271 	pll_value = sdhci_readl(host, SDHCI_GLI_9750_PLL);
272 	sw_ctrl_value = sdhci_readl(host, SDHCI_GLI_9750_SW_CTRL);
273 	misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
274 	parameter_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_PARAMETERS);
275 	control_value = sdhci_readl(host, SDHCI_GLI_9750_TUNING_CONTROL);
276 
277 	driving_value &= ~(SDHCI_GLI_9750_DRIVING_1);
278 	driving_value &= ~(SDHCI_GLI_9750_DRIVING_2);
279 	driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1,
280 				    GLI_9750_DRIVING_1_VALUE);
281 	driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2,
282 				    GLI_9750_DRIVING_2_VALUE);
283 	driving_value &= ~(SDHCI_GLI_9750_SEL_1|SDHCI_GLI_9750_SEL_2|SDHCI_GLI_9750_ALL_RST);
284 	driving_value |= SDHCI_GLI_9750_SEL_2;
285 	sdhci_writel(host, driving_value, SDHCI_GLI_9750_DRIVING);
286 
287 	sw_ctrl_value &= ~SDHCI_GLI_9750_SW_CTRL_4;
288 	sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4,
289 				    GLI_9750_SW_CTRL_4_VALUE);
290 	sdhci_writel(host, sw_ctrl_value, SDHCI_GLI_9750_SW_CTRL);
291 
292 	/* reset the tuning flow after reinit and before starting tuning */
293 	pll_value &= ~SDHCI_GLI_9750_PLL_TX2_INV;
294 	pll_value &= ~SDHCI_GLI_9750_PLL_TX2_DLY;
295 	pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV,
296 				GLI_9750_PLL_TX2_INV_VALUE);
297 	pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY,
298 				GLI_9750_PLL_TX2_DLY_VALUE);
299 
300 	misc_value &= ~SDHCI_GLI_9750_MISC_TX1_INV;
301 	misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
302 	misc_value &= ~SDHCI_GLI_9750_MISC_TX1_DLY;
303 	misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV,
304 				 GLI_9750_MISC_TX1_INV_VALUE);
305 	misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
306 				 GLI_9750_MISC_RX_INV_VALUE);
307 	misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY,
308 				 GLI_9750_MISC_TX1_DLY_VALUE);
309 
310 	parameter_value &= ~SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY;
311 	parameter_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_PARAMETERS_RX_DLY,
312 				      GLI_9750_TUNING_PARAMETERS_RX_DLY_VALUE);
313 
314 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1;
315 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2;
316 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_1,
317 				    GLI_9750_TUNING_CONTROL_GLITCH_1_VALUE);
318 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_GLITCH_2,
319 				    GLI_9750_TUNING_CONTROL_GLITCH_2_VALUE);
320 
321 	sdhci_writel(host, pll_value, SDHCI_GLI_9750_PLL);
322 	sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
323 
324 	/* disable tuned clk */
325 	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
326 	ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
327 	sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
328 
329 	/* enable tuning parameters control */
330 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
331 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
332 				    GLI_9750_TUNING_CONTROL_EN_ON);
333 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
334 
335 	/* write tuning parameters */
336 	sdhci_writel(host, parameter_value, SDHCI_GLI_9750_TUNING_PARAMETERS);
337 
338 	/* disable tuning parameters control */
339 	control_value &= ~SDHCI_GLI_9750_TUNING_CONTROL_EN;
340 	control_value |= FIELD_PREP(SDHCI_GLI_9750_TUNING_CONTROL_EN,
341 				    GLI_9750_TUNING_CONTROL_EN_OFF);
342 	sdhci_writel(host, control_value, SDHCI_GLI_9750_TUNING_CONTROL);
343 
344 	/* clear tuned clk */
345 	ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
346 	ctrl2 &= ~SDHCI_CTRL_TUNED_CLK;
347 	sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2);
348 
349 	gl9750_wt_off(host);
350 }
351 
352 static void gli_set_9750_rx_inv(struct sdhci_host *host, bool b)
353 {
354 	u32 misc_value;
355 
356 	gl9750_wt_on(host);
357 
358 	misc_value = sdhci_readl(host, SDHCI_GLI_9750_MISC);
359 	misc_value &= ~SDHCI_GLI_9750_MISC_RX_INV;
360 	if (b) {
361 		misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
362 					 GLI_9750_MISC_RX_INV_ON);
363 	} else {
364 		misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV,
365 					 GLI_9750_MISC_RX_INV_OFF);
366 	}
367 	sdhci_writel(host, misc_value, SDHCI_GLI_9750_MISC);
368 
369 	gl9750_wt_off(host);
370 }
371 
372 static int __sdhci_execute_tuning_9750(struct sdhci_host *host, u32 opcode)
373 {
374 	int i;
375 	int rx_inv;
376 
377 	for (rx_inv = 0; rx_inv < 2; rx_inv++) {
378 		gli_set_9750_rx_inv(host, !!rx_inv);
379 		sdhci_start_tuning(host);
380 
381 		for (i = 0; i < GLI_MAX_TUNING_LOOP; i++) {
382 			u16 ctrl;
383 
384 			sdhci_send_tuning(host, opcode);
385 
386 			if (!host->tuning_done) {
387 				sdhci_abort_tuning(host, opcode);
388 				break;
389 			}
390 
391 			ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
392 			if (!(ctrl & SDHCI_CTRL_EXEC_TUNING)) {
393 				if (ctrl & SDHCI_CTRL_TUNED_CLK)
394 					return 0; /* Success! */
395 				break;
396 			}
397 		}
398 	}
399 	if (!host->tuning_done) {
400 		pr_info("%s: Tuning timeout, falling back to fixed sampling clock\n",
401 			mmc_hostname(host->mmc));
402 		return -ETIMEDOUT;
403 	}
404 
405 	pr_info("%s: Tuning failed, falling back to fixed sampling clock\n",
406 		mmc_hostname(host->mmc));
407 	sdhci_reset_tuning(host);
408 
409 	return -EAGAIN;
410 }
411 
412 static int gl9750_execute_tuning(struct sdhci_host *host, u32 opcode)
413 {
414 	host->mmc->retune_period = 0;
415 	if (host->tuning_mode == SDHCI_TUNING_MODE_1)
416 		host->mmc->retune_period = host->tuning_count;
417 
418 	gli_set_9750(host);
419 	host->tuning_err = __sdhci_execute_tuning_9750(host, opcode);
420 	sdhci_end_tuning(host);
421 
422 	return 0;
423 }
424 
425 static void gl9750_disable_ssc_pll(struct sdhci_host *host)
426 {
427 	u32 pll;
428 
429 	gl9750_wt_on(host);
430 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
431 	pll &= ~(SDHCI_GLI_9750_PLL_DIR | SDHCI_GLI_9750_PLLSSC_EN);
432 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
433 	gl9750_wt_off(host);
434 }
435 
436 static void gl9750_set_pll(struct sdhci_host *host, u8 dir, u16 ldiv, u8 pdiv)
437 {
438 	u32 pll;
439 
440 	gl9750_wt_on(host);
441 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
442 	pll &= ~(SDHCI_GLI_9750_PLL_LDIV |
443 		 SDHCI_GLI_9750_PLL_PDIV |
444 		 SDHCI_GLI_9750_PLL_DIR);
445 	pll |= FIELD_PREP(SDHCI_GLI_9750_PLL_LDIV, ldiv) |
446 	       FIELD_PREP(SDHCI_GLI_9750_PLL_PDIV, pdiv) |
447 	       FIELD_PREP(SDHCI_GLI_9750_PLL_DIR, dir);
448 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
449 	gl9750_wt_off(host);
450 
451 	/* wait for pll stable */
452 	mdelay(1);
453 }
454 
455 static bool gl9750_ssc_enable(struct sdhci_host *host)
456 {
457 	u32 misc;
458 	u8 off;
459 
460 	gl9750_wt_on(host);
461 	misc = sdhci_readl(host, SDHCI_GLI_9750_MISC);
462 	off = FIELD_GET(SDHCI_GLI_9750_MISC_SSC_OFF, misc);
463 	gl9750_wt_off(host);
464 
465 	return !off;
466 }
467 
468 static void gl9750_set_ssc(struct sdhci_host *host, u8 enable, u8 step, u16 ppm)
469 {
470 	u32 pll;
471 	u32 ssc;
472 
473 	gl9750_wt_on(host);
474 	pll = sdhci_readl(host, SDHCI_GLI_9750_PLL);
475 	ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);
476 	pll &= ~(SDHCI_GLI_9750_PLLSSC_STEP |
477 		 SDHCI_GLI_9750_PLLSSC_EN);
478 	ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;
479 	pll |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_STEP, step) |
480 	       FIELD_PREP(SDHCI_GLI_9750_PLLSSC_EN, enable);
481 	ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);
482 	sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);
483 	sdhci_writel(host, pll, SDHCI_GLI_9750_PLL);
484 	gl9750_wt_off(host);
485 }
486 
487 static void gl9750_set_ssc_pll_205mhz(struct sdhci_host *host)
488 {
489 	bool enable = gl9750_ssc_enable(host);
490 
491 	/* set pll to 205MHz and ssc */
492 	gl9750_set_ssc(host, enable, 0xF, 0x5A1D);
493 	gl9750_set_pll(host, 0x1, 0x246, 0x0);
494 }
495 
496 static void gl9750_set_ssc_pll_100mhz(struct sdhci_host *host)
497 {
498 	bool enable = gl9750_ssc_enable(host);
499 
500 	/* set pll to 100MHz and ssc */
501 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);
502 	gl9750_set_pll(host, 0x1, 0x244, 0x1);
503 }
504 
505 static void gl9750_set_ssc_pll_50mhz(struct sdhci_host *host)
506 {
507 	bool enable = gl9750_ssc_enable(host);
508 
509 	/* set pll to 50MHz and ssc */
510 	gl9750_set_ssc(host, enable, 0xE, 0x51EC);
511 	gl9750_set_pll(host, 0x1, 0x244, 0x3);
512 }
513 
514 static void sdhci_gl9750_set_clock(struct sdhci_host *host, unsigned int clock)
515 {
516 	struct mmc_ios *ios = &host->mmc->ios;
517 	u16 clk;
518 
519 	host->mmc->actual_clock = 0;
520 
521 	gl9750_disable_ssc_pll(host);
522 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
523 
524 	if (clock == 0)
525 		return;
526 
527 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
528 	if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
529 		host->mmc->actual_clock = 205000000;
530 		gl9750_set_ssc_pll_205mhz(host);
531 	} else if (clock == 100000000) {
532 		gl9750_set_ssc_pll_100mhz(host);
533 	} else if (clock == 50000000) {
534 		gl9750_set_ssc_pll_50mhz(host);
535 	}
536 
537 	sdhci_enable_clk(host, clk);
538 }
539 
540 static void gl9750_hw_setting(struct sdhci_host *host)
541 {
542 	struct sdhci_pci_slot *slot = sdhci_priv(host);
543 	struct pci_dev *pdev;
544 	u32 value;
545 
546 	pdev = slot->chip->pdev;
547 
548 	gl9750_wt_on(host);
549 
550 	value = sdhci_readl(host, SDHCI_GLI_9750_CFG2);
551 	value &= ~SDHCI_GLI_9750_CFG2_L1DLY;
552 	/* set ASPM L1 entry delay to 7.9us */
553 	value |= FIELD_PREP(SDHCI_GLI_9750_CFG2_L1DLY,
554 			    GLI_9750_CFG2_L1DLY_VALUE);
555 	sdhci_writel(host, value, SDHCI_GLI_9750_CFG2);
556 
557 	/* toggle PM state to allow GL9750 to enter ASPM L1.2 */
558 	pci_read_config_dword(pdev, PCI_GLI_9750_PM_CTRL, &value);
559 	value |= PCI_GLI_9750_PM_STATE;
560 	pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
561 	value &= ~PCI_GLI_9750_PM_STATE;
562 	pci_write_config_dword(pdev, PCI_GLI_9750_PM_CTRL, value);
563 
564 	gl9750_wt_off(host);
565 }
566 
567 static void gli_pcie_enable_msi(struct sdhci_pci_slot *slot)
568 {
569 	int ret;
570 
571 	ret = pci_alloc_irq_vectors(slot->chip->pdev, 1, 1,
572 				    PCI_IRQ_MSI | PCI_IRQ_MSIX);
573 	if (ret < 0) {
574 		pr_warn("%s: enable PCI MSI failed, error=%d\n",
575 		       mmc_hostname(slot->host->mmc), ret);
576 		return;
577 	}
578 
579 	slot->host->irq = pci_irq_vector(slot->chip->pdev, 0);
580 }
581 
582 static inline void gl9755_wt_on(struct pci_dev *pdev)
583 {
584 	u32 wt_value;
585 	u32 wt_enable;
586 
587 	pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
588 	wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
589 
590 	if (wt_enable == GLI_9755_WT_EN_ON)
591 		return;
592 
593 	wt_value &= ~PCI_GLI_9755_WT_EN;
594 	wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_ON);
595 
596 	pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
597 }
598 
599 static inline void gl9755_wt_off(struct pci_dev *pdev)
600 {
601 	u32 wt_value;
602 	u32 wt_enable;
603 
604 	pci_read_config_dword(pdev, PCI_GLI_9755_WT, &wt_value);
605 	wt_enable = FIELD_GET(PCI_GLI_9755_WT_EN, wt_value);
606 
607 	if (wt_enable == GLI_9755_WT_EN_OFF)
608 		return;
609 
610 	wt_value &= ~PCI_GLI_9755_WT_EN;
611 	wt_value |= FIELD_PREP(PCI_GLI_9755_WT_EN, GLI_9755_WT_EN_OFF);
612 
613 	pci_write_config_dword(pdev, PCI_GLI_9755_WT, wt_value);
614 }
615 
616 static void gl9755_disable_ssc_pll(struct pci_dev *pdev)
617 {
618 	u32 pll;
619 
620 	gl9755_wt_on(pdev);
621 	pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
622 	pll &= ~(PCI_GLI_9755_PLL_DIR | PCI_GLI_9755_PLLSSC_EN);
623 	pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
624 	gl9755_wt_off(pdev);
625 }
626 
627 static void gl9755_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
628 {
629 	u32 pll;
630 
631 	gl9755_wt_on(pdev);
632 	pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
633 	pll &= ~(PCI_GLI_9755_PLL_LDIV |
634 		 PCI_GLI_9755_PLL_PDIV |
635 		 PCI_GLI_9755_PLL_DIR);
636 	pll |= FIELD_PREP(PCI_GLI_9755_PLL_LDIV, ldiv) |
637 	       FIELD_PREP(PCI_GLI_9755_PLL_PDIV, pdiv) |
638 	       FIELD_PREP(PCI_GLI_9755_PLL_DIR, dir);
639 	pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
640 	gl9755_wt_off(pdev);
641 
642 	/* wait for pll stable */
643 	mdelay(1);
644 }
645 
646 static bool gl9755_ssc_enable(struct pci_dev *pdev)
647 {
648 	u32 misc;
649 	u8 off;
650 
651 	gl9755_wt_on(pdev);
652 	pci_read_config_dword(pdev, PCI_GLI_9755_MISC, &misc);
653 	off = FIELD_GET(PCI_GLI_9755_MISC_SSC_OFF, misc);
654 	gl9755_wt_off(pdev);
655 
656 	return !off;
657 }
658 
659 static void gl9755_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
660 {
661 	u32 pll;
662 	u32 ssc;
663 
664 	gl9755_wt_on(pdev);
665 	pci_read_config_dword(pdev, PCI_GLI_9755_PLL, &pll);
666 	pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);
667 	pll &= ~(PCI_GLI_9755_PLLSSC_STEP |
668 		 PCI_GLI_9755_PLLSSC_EN);
669 	ssc &= ~PCI_GLI_9755_PLLSSC_PPM;
670 	pll |= FIELD_PREP(PCI_GLI_9755_PLLSSC_STEP, step) |
671 	       FIELD_PREP(PCI_GLI_9755_PLLSSC_EN, enable);
672 	ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);
673 	pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);
674 	pci_write_config_dword(pdev, PCI_GLI_9755_PLL, pll);
675 	gl9755_wt_off(pdev);
676 }
677 
678 static void gl9755_set_ssc_pll_205mhz(struct pci_dev *pdev)
679 {
680 	bool enable = gl9755_ssc_enable(pdev);
681 
682 	/* set pll to 205MHz and ssc */
683 	gl9755_set_ssc(pdev, enable, 0xF, 0x5A1D);
684 	gl9755_set_pll(pdev, 0x1, 0x246, 0x0);
685 }
686 
687 static void gl9755_set_ssc_pll_100mhz(struct pci_dev *pdev)
688 {
689 	bool enable = gl9755_ssc_enable(pdev);
690 
691 	/* set pll to 100MHz and ssc */
692 	gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
693 	gl9755_set_pll(pdev, 0x1, 0x244, 0x1);
694 }
695 
696 static void gl9755_set_ssc_pll_50mhz(struct pci_dev *pdev)
697 {
698 	bool enable = gl9755_ssc_enable(pdev);
699 
700 	/* set pll to 50MHz and ssc */
701 	gl9755_set_ssc(pdev, enable, 0xE, 0x51EC);
702 	gl9755_set_pll(pdev, 0x1, 0x244, 0x3);
703 }
704 
705 static void sdhci_gl9755_set_clock(struct sdhci_host *host, unsigned int clock)
706 {
707 	struct sdhci_pci_slot *slot = sdhci_priv(host);
708 	struct mmc_ios *ios = &host->mmc->ios;
709 	struct pci_dev *pdev;
710 	u16 clk;
711 
712 	pdev = slot->chip->pdev;
713 	host->mmc->actual_clock = 0;
714 
715 	gl9755_disable_ssc_pll(pdev);
716 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
717 
718 	if (clock == 0)
719 		return;
720 
721 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
722 	if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
723 		host->mmc->actual_clock = 205000000;
724 		gl9755_set_ssc_pll_205mhz(pdev);
725 	} else if (clock == 100000000) {
726 		gl9755_set_ssc_pll_100mhz(pdev);
727 	} else if (clock == 50000000) {
728 		gl9755_set_ssc_pll_50mhz(pdev);
729 	}
730 
731 	sdhci_enable_clk(host, clk);
732 }
733 
734 static void gl9755_hw_setting(struct sdhci_pci_slot *slot)
735 {
736 	struct pci_dev *pdev = slot->chip->pdev;
737 	u32 value;
738 
739 	gl9755_wt_on(pdev);
740 
741 	pci_read_config_dword(pdev, PCI_GLI_9755_PECONF, &value);
742 	/*
743 	 * Apple ARM64 platforms using these chips may have
744 	 * inverted CD/WP detection.
745 	 */
746 	if (of_property_read_bool(pdev->dev.of_node, "cd-inverted"))
747 		value |= PCI_GLI_9755_INVERT_CD;
748 	if (of_property_read_bool(pdev->dev.of_node, "wp-inverted"))
749 		value |= PCI_GLI_9755_INVERT_WP;
750 	value &= ~PCI_GLI_9755_LFCLK;
751 	value &= ~PCI_GLI_9755_DMACLK;
752 	pci_write_config_dword(pdev, PCI_GLI_9755_PECONF, value);
753 
754 	/* enable short circuit protection */
755 	pci_read_config_dword(pdev, PCI_GLI_9755_SerDes, &value);
756 	value &= ~PCI_GLI_9755_SCP_DIS;
757 	pci_write_config_dword(pdev, PCI_GLI_9755_SerDes, value);
758 
759 	pci_read_config_dword(pdev, PCI_GLI_9755_CFG2, &value);
760 	value &= ~PCI_GLI_9755_CFG2_L1DLY;
761 	/* set ASPM L1 entry delay to 7.9us */
762 	value |= FIELD_PREP(PCI_GLI_9755_CFG2_L1DLY,
763 			    GLI_9755_CFG2_L1DLY_VALUE);
764 	pci_write_config_dword(pdev, PCI_GLI_9755_CFG2, value);
765 
766 	/* toggle PM state to allow GL9755 to enter ASPM L1.2 */
767 	pci_read_config_dword(pdev, PCI_GLI_9755_PM_CTRL, &value);
768 	value |= PCI_GLI_9755_PM_STATE;
769 	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
770 	value &= ~PCI_GLI_9755_PM_STATE;
771 	pci_write_config_dword(pdev, PCI_GLI_9755_PM_CTRL, value);
772 
773 	gl9755_wt_off(pdev);
774 }
775 
776 static inline void gl9767_vhs_read(struct pci_dev *pdev)
777 {
778 	u32 vhs_enable;
779 	u32 vhs_value;
780 
781 	pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
782 	vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
783 
784 	if (vhs_enable == GLI_9767_VHS_REV_R)
785 		return;
786 
787 	vhs_value &= ~GLI_9767_VHS_REV;
788 	vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_R);
789 
790 	pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
791 }
792 
793 static inline void gl9767_vhs_write(struct pci_dev *pdev)
794 {
795 	u32 vhs_enable;
796 	u32 vhs_value;
797 
798 	pci_read_config_dword(pdev, PCIE_GLI_9767_VHS, &vhs_value);
799 	vhs_enable = FIELD_GET(GLI_9767_VHS_REV, vhs_value);
800 
801 	if (vhs_enable == GLI_9767_VHS_REV_W)
802 		return;
803 
804 	vhs_value &= ~GLI_9767_VHS_REV;
805 	vhs_value |= FIELD_PREP(GLI_9767_VHS_REV, GLI_9767_VHS_REV_W);
806 
807 	pci_write_config_dword(pdev, PCIE_GLI_9767_VHS, vhs_value);
808 }
809 
810 static bool gl9767_ssc_enable(struct pci_dev *pdev)
811 {
812 	u32 value;
813 	u8 enable;
814 
815 	gl9767_vhs_write(pdev);
816 
817 	pci_read_config_dword(pdev, PCIE_GLI_9767_COM_MAILBOX, &value);
818 	enable = FIELD_GET(PCIE_GLI_9767_COM_MAILBOX_SSC_EN, value);
819 
820 	gl9767_vhs_read(pdev);
821 
822 	return enable;
823 }
824 
825 static void gl9767_set_ssc(struct pci_dev *pdev, u8 enable, u8 step, u16 ppm)
826 {
827 	u32 pll;
828 	u32 ssc;
829 
830 	gl9767_vhs_write(pdev);
831 
832 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
833 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);
834 	pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING |
835 		 PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
836 	ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;
837 	pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_STEP_SETTING, step) |
838 	       FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_SSC_EN, enable);
839 	ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);
840 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);
841 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
842 
843 	gl9767_vhs_read(pdev);
844 }
845 
846 static void gl9767_set_pll(struct pci_dev *pdev, u8 dir, u16 ldiv, u8 pdiv)
847 {
848 	u32 pll;
849 
850 	gl9767_vhs_write(pdev);
851 
852 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
853 	pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV |
854 		 PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV |
855 		 PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN);
856 	pll |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_LDIV, ldiv) |
857 	       FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_PDIV, pdiv) |
858 	       FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN, dir);
859 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
860 
861 	gl9767_vhs_read(pdev);
862 
863 	/* wait for pll stable */
864 	usleep_range(1000, 1100);
865 }
866 
867 static void gl9767_set_ssc_pll_205mhz(struct pci_dev *pdev)
868 {
869 	bool enable = gl9767_ssc_enable(pdev);
870 
871 	/* set pll to 205MHz and ssc */
872 	gl9767_set_ssc(pdev, enable, 0x1F, 0xF5C3);
873 	gl9767_set_pll(pdev, 0x1, 0x246, 0x0);
874 }
875 
876 static void gl9767_disable_ssc_pll(struct pci_dev *pdev)
877 {
878 	u32 pll;
879 
880 	gl9767_vhs_write(pdev);
881 
882 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, &pll);
883 	pll &= ~(PCIE_GLI_9767_SD_PLL_CTL_PLL_DIR_EN | PCIE_GLI_9767_SD_PLL_CTL_SSC_EN);
884 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL, pll);
885 
886 	gl9767_vhs_read(pdev);
887 }
888 
889 static void sdhci_gl9767_set_clock(struct sdhci_host *host, unsigned int clock)
890 {
891 	struct sdhci_pci_slot *slot = sdhci_priv(host);
892 	struct mmc_ios *ios = &host->mmc->ios;
893 	struct pci_dev *pdev;
894 	u32 value;
895 	u16 clk;
896 
897 	pdev = slot->chip->pdev;
898 	host->mmc->actual_clock = 0;
899 
900 	gl9767_vhs_write(pdev);
901 
902 	pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
903 	value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
904 	pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
905 
906 	gl9767_disable_ssc_pll(pdev);
907 	sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
908 
909 	if (clock == 0)
910 		return;
911 
912 	clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
913 	if (clock == 200000000 && ios->timing == MMC_TIMING_UHS_SDR104) {
914 		host->mmc->actual_clock = 205000000;
915 		gl9767_set_ssc_pll_205mhz(pdev);
916 	}
917 
918 	sdhci_enable_clk(host, clk);
919 
920 	pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
921 	value &= ~PCIE_GLI_9767_CFG_LOW_PWR_OFF;
922 	pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
923 
924 	gl9767_vhs_read(pdev);
925 }
926 
927 static void gli_set_9767(struct sdhci_host *host)
928 {
929 	u32 value;
930 
931 	value = sdhci_readl(host, SDHCI_GLI_9767_GM_BURST_SIZE);
932 	value &= ~SDHCI_GLI_9767_GM_BURST_SIZE_AXI_ALWAYS_SET;
933 	sdhci_writel(host, value, SDHCI_GLI_9767_GM_BURST_SIZE);
934 }
935 
936 static void gl9767_hw_setting(struct sdhci_pci_slot *slot)
937 {
938 	struct pci_dev *pdev = slot->chip->pdev;
939 	u32 value;
940 
941 	gl9767_vhs_write(pdev);
942 
943 	pci_read_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, &value);
944 	value &= ~(PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
945 		   PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE |
946 		   PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL);
947 
948 	value |= PCIE_GLI_9767_PWR_MACRO_CTL_LOW_VOLTAGE |
949 		 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE,
950 			    PCIE_GLI_9767_PWR_MACRO_CTL_LD0_LOW_OUTPUT_VOLTAGE_VALUE) |
951 		 FIELD_PREP(PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL,
952 			    PCIE_GLI_9767_PWR_MACRO_CTL_RCLK_AMPLITUDE_CTL_VALUE);
953 	pci_write_config_dword(pdev, PCIE_GLI_9767_PWR_MACRO_CTL, value);
954 
955 	pci_read_config_dword(pdev, PCIE_GLI_9767_SCR, &value);
956 	value &= ~(PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE0 |
957 		   PCIE_GLI_9767_SCR_SYSTEM_CLK_SELECT_MODE1 |
958 		   PCIE_GLI_9767_SCR_CFG_RST_DATA_LINK_DOWN);
959 
960 	value |= PCIE_GLI_9767_SCR_AUTO_AXI_W_BURST |
961 		 PCIE_GLI_9767_SCR_AUTO_AXI_R_BURST |
962 		 PCIE_GLI_9767_SCR_AXI_REQ |
963 		 PCIE_GLI_9767_SCR_CARD_DET_PWR_SAVING_EN |
964 		 PCIE_GLI_9767_SCR_CORE_PWR_D3_OFF;
965 	pci_write_config_dword(pdev, PCIE_GLI_9767_SCR, value);
966 
967 	gl9767_vhs_read(pdev);
968 }
969 
970 static void sdhci_gl9767_reset(struct sdhci_host *host, u8 mask)
971 {
972 	sdhci_reset(host, mask);
973 	gli_set_9767(host);
974 }
975 
976 static int gl9767_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios)
977 {
978 	struct sdhci_host *host = mmc_priv(mmc);
979 	struct sdhci_pci_slot *slot = sdhci_priv(host);
980 	struct pci_dev *pdev;
981 	u32 value;
982 	int i;
983 
984 	pdev = slot->chip->pdev;
985 
986 	if (mmc->ops->get_ro(mmc)) {
987 		mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
988 		return 0;
989 	}
990 
991 	gl9767_vhs_write(pdev);
992 
993 	pci_read_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, &value);
994 	value &= ~(PCIE_GLI_9767_COMBO_MUX_CTL_RST_EN | PCIE_GLI_9767_COMBO_MUX_CTL_WAIT_PERST_EN);
995 	pci_write_config_dword(pdev, PCIE_GLI_9767_COMBO_MUX_CTL, value);
996 
997 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, &value);
998 	value &= ~PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME;
999 	value |= FIELD_PREP(PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME,
1000 			    PCIE_GLI_9767_SD_DATA_MULTI_CTL_DISCONNECT_TIME_VALUE);
1001 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_DATA_MULTI_CTL, value);
1002 
1003 	pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1004 	value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE;
1005 	pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, value);
1006 
1007 	pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, &value);
1008 	value |= PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2_SDEI_COMPLETE_STATUS_EN;
1009 	pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_EN_REG2, value);
1010 
1011 	pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, &value);
1012 	value |= PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2_SDEI_COMPLETE_SIGNAL_EN;
1013 	pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_SIGNAL_EN_REG2, value);
1014 
1015 	pci_read_config_dword(pdev, PCIE_GLI_9767_CFG, &value);
1016 	value |= PCIE_GLI_9767_CFG_LOW_PWR_OFF;
1017 	pci_write_config_dword(pdev, PCIE_GLI_9767_CFG, value);
1018 
1019 	value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1020 	value &= ~(SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
1021 	sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1022 
1023 	value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1024 	value |= (SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
1025 	sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1026 
1027 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1028 	value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SDEI_EXE;
1029 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1030 
1031 	for (i = 0; i < 2; i++) {
1032 		usleep_range(10000, 10100);
1033 		pci_read_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2, &value);
1034 		if (value & PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2_SDEI_COMPLETE) {
1035 			pci_write_config_dword(pdev, PCIE_GLI_9767_NORMAL_ERR_INT_STATUS_REG2,
1036 					       value);
1037 			break;
1038 		}
1039 	}
1040 
1041 	pci_read_config_dword(pdev, PCIE_GLI_9767_SDHC_CAP, &value);
1042 	if (value & PCIE_GLI_9767_SDHC_CAP_SDEI_RESULT) {
1043 		pci_read_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, &value);
1044 		value |= PCIE_GLI_9767_SD_EXPRESS_CTL_SD_EXPRESS_MODE;
1045 		pci_write_config_dword(pdev, PCIE_GLI_9767_SD_EXPRESS_CTL, value);
1046 	} else {
1047 		mmc->ios.timing &= ~(MMC_TIMING_SD_EXP | MMC_TIMING_SD_EXP_1_2V);
1048 
1049 		value = sdhci_readb(host, SDHCI_POWER_CONTROL);
1050 		value &= ~(SDHCI_VDD2_POWER_180 | SDHCI_VDD2_POWER_ON);
1051 		sdhci_writeb(host, value, SDHCI_POWER_CONTROL);
1052 
1053 		value = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1054 		value |= (SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_PLL_EN);
1055 		sdhci_writew(host, value, SDHCI_CLOCK_CONTROL);
1056 	}
1057 
1058 	gl9767_vhs_read(pdev);
1059 
1060 	return 0;
1061 }
1062 
1063 static int gli_probe_slot_gl9750(struct sdhci_pci_slot *slot)
1064 {
1065 	struct sdhci_host *host = slot->host;
1066 
1067 	gl9750_hw_setting(host);
1068 	gli_pcie_enable_msi(slot);
1069 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1070 	sdhci_enable_v4_mode(host);
1071 
1072 	return 0;
1073 }
1074 
1075 static int gli_probe_slot_gl9755(struct sdhci_pci_slot *slot)
1076 {
1077 	struct sdhci_host *host = slot->host;
1078 
1079 	gl9755_hw_setting(slot);
1080 	gli_pcie_enable_msi(slot);
1081 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1082 	sdhci_enable_v4_mode(host);
1083 
1084 	return 0;
1085 }
1086 
1087 static int gli_probe_slot_gl9767(struct sdhci_pci_slot *slot)
1088 {
1089 	struct sdhci_host *host = slot->host;
1090 
1091 	gli_set_9767(host);
1092 	gl9767_hw_setting(slot);
1093 	gli_pcie_enable_msi(slot);
1094 	slot->host->mmc->caps2 |= MMC_CAP2_NO_SDIO;
1095 	host->mmc->caps2 |= MMC_CAP2_SD_EXP;
1096 	host->mmc_host_ops.init_sd_express = gl9767_init_sd_express;
1097 	sdhci_enable_v4_mode(host);
1098 
1099 	return 0;
1100 }
1101 
1102 static void sdhci_gli_voltage_switch(struct sdhci_host *host)
1103 {
1104 	/*
1105 	 * According to Section 3.6.1 signal voltage switch procedure in
1106 	 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1107 	 * follows:
1108 	 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1109 	 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1110 	 *     period.
1111 	 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1112 	 *     step (12).
1113 	 *
1114 	 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1115 	 * to ensure 1.8V signal enable bit is set by GL9750/GL9755.
1116 	 *
1117 	 * ...however, the controller in the NUC10i3FNK4 (a 9755) requires
1118 	 * slightly longer than 5ms before the control register reports that
1119 	 * 1.8V is ready, and far longer still before the card will actually
1120 	 * work reliably.
1121 	 */
1122 	usleep_range(100000, 110000);
1123 }
1124 
1125 static void sdhci_gl9767_voltage_switch(struct sdhci_host *host)
1126 {
1127 	/*
1128 	 * According to Section 3.6.1 signal voltage switch procedure in
1129 	 * SD Host Controller Simplified Spec. 4.20, steps 6~8 are as
1130 	 * follows:
1131 	 * (6) Set 1.8V Signal Enable in the Host Control 2 register.
1132 	 * (7) Wait 5ms. 1.8V voltage regulator shall be stable within this
1133 	 *     period.
1134 	 * (8) If 1.8V Signal Enable is cleared by Host Controller, go to
1135 	 *     step (12).
1136 	 *
1137 	 * Wait 5ms after set 1.8V signal enable in Host Control 2 register
1138 	 * to ensure 1.8V signal enable bit is set by GL9767.
1139 	 *
1140 	 */
1141 	usleep_range(5000, 5500);
1142 }
1143 
1144 static void sdhci_gl9750_reset(struct sdhci_host *host, u8 mask)
1145 {
1146 	sdhci_reset(host, mask);
1147 	gli_set_9750(host);
1148 }
1149 
1150 static u32 sdhci_gl9750_readl(struct sdhci_host *host, int reg)
1151 {
1152 	u32 value;
1153 
1154 	value = readl(host->ioaddr + reg);
1155 	if (unlikely(reg == SDHCI_MAX_CURRENT && !(value & 0xff)))
1156 		value |= 0xc8;
1157 
1158 	return value;
1159 }
1160 
1161 static void gl9763e_hs400_enhanced_strobe(struct mmc_host *mmc,
1162 					  struct mmc_ios *ios)
1163 {
1164 	struct sdhci_host *host = mmc_priv(mmc);
1165 	u32 val;
1166 
1167 	val = sdhci_readl(host, SDHCI_GLI_9763E_HS400_ES_REG);
1168 	if (ios->enhanced_strobe)
1169 		val |= SDHCI_GLI_9763E_HS400_ES_BIT;
1170 	else
1171 		val &= ~SDHCI_GLI_9763E_HS400_ES_BIT;
1172 
1173 	sdhci_writel(host, val, SDHCI_GLI_9763E_HS400_ES_REG);
1174 }
1175 
1176 static void sdhci_set_gl9763e_signaling(struct sdhci_host *host,
1177 					unsigned int timing)
1178 {
1179 	u16 ctrl_2;
1180 
1181 	ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1182 	ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1183 	if (timing == MMC_TIMING_MMC_HS200)
1184 		ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1185 	else if (timing == MMC_TIMING_MMC_HS)
1186 		ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1187 	else if (timing == MMC_TIMING_MMC_DDR52)
1188 		ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1189 	else if (timing == MMC_TIMING_MMC_HS400)
1190 		ctrl_2 |= SDHCI_GLI_9763E_CTRL_HS400;
1191 
1192 	sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1193 }
1194 
1195 static void sdhci_gl9763e_dumpregs(struct mmc_host *mmc)
1196 {
1197 	sdhci_dumpregs(mmc_priv(mmc));
1198 }
1199 
1200 static void sdhci_gl9763e_cqe_pre_enable(struct mmc_host *mmc)
1201 {
1202 	struct cqhci_host *cq_host = mmc->cqe_private;
1203 	u32 value;
1204 
1205 	value = cqhci_readl(cq_host, CQHCI_CFG);
1206 	value |= CQHCI_ENABLE;
1207 	cqhci_writel(cq_host, value, CQHCI_CFG);
1208 }
1209 
1210 static void sdhci_gl9763e_cqe_enable(struct mmc_host *mmc)
1211 {
1212 	struct sdhci_host *host = mmc_priv(mmc);
1213 
1214 	sdhci_writew(host, GLI_9763E_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE);
1215 	sdhci_cqe_enable(mmc);
1216 }
1217 
1218 static u32 sdhci_gl9763e_cqhci_irq(struct sdhci_host *host, u32 intmask)
1219 {
1220 	int cmd_error = 0;
1221 	int data_error = 0;
1222 
1223 	if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
1224 		return intmask;
1225 
1226 	cqhci_irq(host->mmc, intmask, cmd_error, data_error);
1227 
1228 	return 0;
1229 }
1230 
1231 static void sdhci_gl9763e_cqe_post_disable(struct mmc_host *mmc)
1232 {
1233 	struct sdhci_host *host = mmc_priv(mmc);
1234 	struct cqhci_host *cq_host = mmc->cqe_private;
1235 	u32 value;
1236 
1237 	value = cqhci_readl(cq_host, CQHCI_CFG);
1238 	value &= ~CQHCI_ENABLE;
1239 	cqhci_writel(cq_host, value, CQHCI_CFG);
1240 	sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE);
1241 }
1242 
1243 static const struct cqhci_host_ops sdhci_gl9763e_cqhci_ops = {
1244 	.enable         = sdhci_gl9763e_cqe_enable,
1245 	.disable        = sdhci_cqe_disable,
1246 	.dumpregs       = sdhci_gl9763e_dumpregs,
1247 	.pre_enable     = sdhci_gl9763e_cqe_pre_enable,
1248 	.post_disable   = sdhci_gl9763e_cqe_post_disable,
1249 };
1250 
1251 static int gl9763e_add_host(struct sdhci_pci_slot *slot)
1252 {
1253 	struct device *dev = &slot->chip->pdev->dev;
1254 	struct sdhci_host *host = slot->host;
1255 	struct cqhci_host *cq_host;
1256 	bool dma64;
1257 	int ret;
1258 
1259 	ret = sdhci_setup_host(host);
1260 	if (ret)
1261 		return ret;
1262 
1263 	cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL);
1264 	if (!cq_host) {
1265 		ret = -ENOMEM;
1266 		goto cleanup;
1267 	}
1268 
1269 	cq_host->mmio = host->ioaddr + SDHCI_GLI_9763E_CQE_BASE_ADDR;
1270 	cq_host->ops = &sdhci_gl9763e_cqhci_ops;
1271 
1272 	dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
1273 	if (dma64)
1274 		cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
1275 
1276 	ret = cqhci_init(cq_host, host->mmc, dma64);
1277 	if (ret)
1278 		goto cleanup;
1279 
1280 	ret = __sdhci_add_host(host);
1281 	if (ret)
1282 		goto cleanup;
1283 
1284 	return 0;
1285 
1286 cleanup:
1287 	sdhci_cleanup_host(host);
1288 	return ret;
1289 }
1290 
1291 static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
1292 {
1293 	struct pci_dev *pdev = slot->chip->pdev;
1294 	u32 value;
1295 
1296 	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1297 	value &= ~GLI_9763E_VHS_REV;
1298 	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
1299 	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1300 
1301 	pci_read_config_dword(pdev, PCIE_GLI_9763E_SCR, &value);
1302 	value |= GLI_9763E_SCR_AXI_REQ;
1303 	pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
1304 
1305 	pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
1306 	value &= ~GLI_9763E_HS400_SLOW;
1307 	pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
1308 
1309 	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG2, &value);
1310 	value &= ~GLI_9763E_CFG2_L1DLY;
1311 	/* set ASPM L1 entry delay to 21us */
1312 	value |= FIELD_PREP(GLI_9763E_CFG2_L1DLY, GLI_9763E_CFG2_L1DLY_MID);
1313 	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG2, value);
1314 
1315 	pci_read_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, &value);
1316 	value &= ~GLI_9763E_HS400_RXDLY;
1317 	value |= FIELD_PREP(GLI_9763E_HS400_RXDLY, GLI_9763E_HS400_RXDLY_5);
1318 	pci_write_config_dword(pdev, PCIE_GLI_9763E_CLKRXDLY, value);
1319 
1320 	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1321 	value &= ~GLI_9763E_VHS_REV;
1322 	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
1323 	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1324 }
1325 
1326 #ifdef CONFIG_PM
1327 static void gl9763e_set_low_power_negotiation(struct sdhci_pci_slot *slot, bool enable)
1328 {
1329 	struct pci_dev *pdev = slot->chip->pdev;
1330 	u32 value;
1331 
1332 	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1333 	value &= ~GLI_9763E_VHS_REV;
1334 	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_W);
1335 	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1336 
1337 	pci_read_config_dword(pdev, PCIE_GLI_9763E_CFG, &value);
1338 
1339 	if (enable)
1340 		value &= ~GLI_9763E_CFG_LPSN_DIS;
1341 	else
1342 		value |= GLI_9763E_CFG_LPSN_DIS;
1343 
1344 	pci_write_config_dword(pdev, PCIE_GLI_9763E_CFG, value);
1345 
1346 	pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
1347 	value &= ~GLI_9763E_VHS_REV;
1348 	value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);
1349 	pci_write_config_dword(pdev, PCIE_GLI_9763E_VHS, value);
1350 }
1351 
1352 static int gl9763e_runtime_suspend(struct sdhci_pci_chip *chip)
1353 {
1354 	struct sdhci_pci_slot *slot = chip->slots[0];
1355 	struct sdhci_host *host = slot->host;
1356 	u16 clock;
1357 
1358 	/* Enable LPM negotiation to allow entering L1 state */
1359 	gl9763e_set_low_power_negotiation(slot, true);
1360 
1361 	clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1362 	clock &= ~(SDHCI_CLOCK_PLL_EN | SDHCI_CLOCK_CARD_EN);
1363 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1364 
1365 	return 0;
1366 }
1367 
1368 static int gl9763e_runtime_resume(struct sdhci_pci_chip *chip)
1369 {
1370 	struct sdhci_pci_slot *slot = chip->slots[0];
1371 	struct sdhci_host *host = slot->host;
1372 	u16 clock;
1373 
1374 	if (host->mmc->ios.power_mode != MMC_POWER_ON)
1375 		return 0;
1376 
1377 	clock = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
1378 
1379 	clock |= SDHCI_CLOCK_PLL_EN;
1380 	clock &= ~SDHCI_CLOCK_INT_STABLE;
1381 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1382 
1383 	/* Wait max 150 ms */
1384 	if (read_poll_timeout(sdhci_readw, clock, (clock & SDHCI_CLOCK_INT_STABLE),
1385 			      1000, 150000, false, host, SDHCI_CLOCK_CONTROL)) {
1386 		pr_err("%s: PLL clock never stabilised.\n",
1387 		       mmc_hostname(host->mmc));
1388 		sdhci_dumpregs(host);
1389 	}
1390 
1391 	clock |= SDHCI_CLOCK_CARD_EN;
1392 	sdhci_writew(host, clock, SDHCI_CLOCK_CONTROL);
1393 
1394 	/* Disable LPM negotiation to avoid entering L1 state. */
1395 	gl9763e_set_low_power_negotiation(slot, false);
1396 
1397 	return 0;
1398 }
1399 #endif
1400 
1401 #ifdef CONFIG_PM_SLEEP
1402 static int sdhci_pci_gli_resume(struct sdhci_pci_chip *chip)
1403 {
1404 	struct sdhci_pci_slot *slot = chip->slots[0];
1405 
1406 	pci_free_irq_vectors(slot->chip->pdev);
1407 	gli_pcie_enable_msi(slot);
1408 
1409 	return sdhci_pci_resume_host(chip);
1410 }
1411 
1412 static int gl9763e_resume(struct sdhci_pci_chip *chip)
1413 {
1414 	struct sdhci_pci_slot *slot = chip->slots[0];
1415 	int ret;
1416 
1417 	ret = sdhci_pci_gli_resume(chip);
1418 	if (ret)
1419 		return ret;
1420 
1421 	ret = cqhci_resume(slot->host->mmc);
1422 	if (ret)
1423 		return ret;
1424 
1425 	/*
1426 	 * Disable LPM negotiation to bring device back in sync
1427 	 * with its runtime_pm state.
1428 	 */
1429 	gl9763e_set_low_power_negotiation(slot, false);
1430 
1431 	return 0;
1432 }
1433 
1434 static int gl9763e_suspend(struct sdhci_pci_chip *chip)
1435 {
1436 	struct sdhci_pci_slot *slot = chip->slots[0];
1437 	int ret;
1438 
1439 	/*
1440 	 * Certain SoCs can suspend only with the bus in low-
1441 	 * power state, notably x86 SoCs when using S0ix.
1442 	 * Re-enable LPM negotiation to allow entering L1 state
1443 	 * and entering system suspend.
1444 	 */
1445 	gl9763e_set_low_power_negotiation(slot, true);
1446 
1447 	ret = cqhci_suspend(slot->host->mmc);
1448 	if (ret)
1449 		goto err_suspend;
1450 
1451 	ret = sdhci_suspend_host(slot->host);
1452 	if (ret)
1453 		goto err_suspend_host;
1454 
1455 	return 0;
1456 
1457 err_suspend_host:
1458 	cqhci_resume(slot->host->mmc);
1459 err_suspend:
1460 	gl9763e_set_low_power_negotiation(slot, false);
1461 	return ret;
1462 }
1463 #endif
1464 
1465 static int gli_probe_slot_gl9763e(struct sdhci_pci_slot *slot)
1466 {
1467 	struct pci_dev *pdev = slot->chip->pdev;
1468 	struct sdhci_host *host = slot->host;
1469 	u32 value;
1470 
1471 	host->mmc->caps |= MMC_CAP_8_BIT_DATA |
1472 			   MMC_CAP_1_8V_DDR |
1473 			   MMC_CAP_NONREMOVABLE;
1474 	host->mmc->caps2 |= MMC_CAP2_HS200_1_8V_SDR |
1475 			    MMC_CAP2_HS400_1_8V |
1476 			    MMC_CAP2_HS400_ES |
1477 			    MMC_CAP2_NO_SDIO |
1478 			    MMC_CAP2_NO_SD;
1479 
1480 	pci_read_config_dword(pdev, PCIE_GLI_9763E_MB, &value);
1481 	if (!(value & GLI_9763E_MB_CMDQ_OFF))
1482 		if (value & GLI_9763E_MB_ERP_ON)
1483 			host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
1484 
1485 	gli_pcie_enable_msi(slot);
1486 	host->mmc_host_ops.hs400_enhanced_strobe =
1487 					gl9763e_hs400_enhanced_strobe;
1488 	gli_set_gl9763e(slot);
1489 	sdhci_enable_v4_mode(host);
1490 
1491 	return 0;
1492 }
1493 
1494 #define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
1495 
1496 static u16 sdhci_gli_readw(struct sdhci_host *host, int reg)
1497 {
1498 	u32 val = readl(host->ioaddr + (reg & ~3));
1499 	u16 word;
1500 
1501 	word = (val >> REG_OFFSET_IN_BITS(reg)) & 0xffff;
1502 	return word;
1503 }
1504 
1505 static u8 sdhci_gli_readb(struct sdhci_host *host, int reg)
1506 {
1507 	u32 val = readl(host->ioaddr + (reg & ~3));
1508 	u8 byte = (val >> REG_OFFSET_IN_BITS(reg)) & 0xff;
1509 
1510 	return byte;
1511 }
1512 
1513 static const struct sdhci_ops sdhci_gl9755_ops = {
1514 	.read_w			= sdhci_gli_readw,
1515 	.read_b			= sdhci_gli_readb,
1516 	.set_clock		= sdhci_gl9755_set_clock,
1517 	.enable_dma		= sdhci_pci_enable_dma,
1518 	.set_bus_width		= sdhci_set_bus_width,
1519 	.reset			= sdhci_reset,
1520 	.set_uhs_signaling	= sdhci_set_uhs_signaling,
1521 	.voltage_switch		= sdhci_gli_voltage_switch,
1522 };
1523 
1524 const struct sdhci_pci_fixes sdhci_gl9755 = {
1525 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1526 	.quirks2	= SDHCI_QUIRK2_BROKEN_DDR50,
1527 	.probe_slot	= gli_probe_slot_gl9755,
1528 	.ops            = &sdhci_gl9755_ops,
1529 #ifdef CONFIG_PM_SLEEP
1530 	.resume         = sdhci_pci_gli_resume,
1531 #endif
1532 };
1533 
1534 static const struct sdhci_ops sdhci_gl9750_ops = {
1535 	.read_w			= sdhci_gli_readw,
1536 	.read_b			= sdhci_gli_readb,
1537 	.read_l                 = sdhci_gl9750_readl,
1538 	.set_clock		= sdhci_gl9750_set_clock,
1539 	.enable_dma		= sdhci_pci_enable_dma,
1540 	.set_bus_width		= sdhci_set_bus_width,
1541 	.reset			= sdhci_gl9750_reset,
1542 	.set_uhs_signaling	= sdhci_set_uhs_signaling,
1543 	.voltage_switch		= sdhci_gli_voltage_switch,
1544 	.platform_execute_tuning = gl9750_execute_tuning,
1545 };
1546 
1547 const struct sdhci_pci_fixes sdhci_gl9750 = {
1548 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1549 	.quirks2	= SDHCI_QUIRK2_BROKEN_DDR50,
1550 	.probe_slot	= gli_probe_slot_gl9750,
1551 	.ops            = &sdhci_gl9750_ops,
1552 #ifdef CONFIG_PM_SLEEP
1553 	.resume         = sdhci_pci_gli_resume,
1554 #endif
1555 };
1556 
1557 static const struct sdhci_ops sdhci_gl9763e_ops = {
1558 	.set_clock		= sdhci_set_clock,
1559 	.enable_dma		= sdhci_pci_enable_dma,
1560 	.set_bus_width		= sdhci_set_bus_width,
1561 	.reset			= sdhci_and_cqhci_reset,
1562 	.set_uhs_signaling	= sdhci_set_gl9763e_signaling,
1563 	.voltage_switch		= sdhci_gli_voltage_switch,
1564 	.irq                    = sdhci_gl9763e_cqhci_irq,
1565 };
1566 
1567 const struct sdhci_pci_fixes sdhci_gl9763e = {
1568 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1569 	.probe_slot	= gli_probe_slot_gl9763e,
1570 	.ops            = &sdhci_gl9763e_ops,
1571 #ifdef CONFIG_PM_SLEEP
1572 	.resume		= gl9763e_resume,
1573 	.suspend	= gl9763e_suspend,
1574 #endif
1575 #ifdef CONFIG_PM
1576 	.runtime_suspend = gl9763e_runtime_suspend,
1577 	.runtime_resume  = gl9763e_runtime_resume,
1578 	.allow_runtime_pm = true,
1579 #endif
1580 	.add_host       = gl9763e_add_host,
1581 };
1582 
1583 static const struct sdhci_ops sdhci_gl9767_ops = {
1584 	.set_clock		 = sdhci_gl9767_set_clock,
1585 	.enable_dma		 = sdhci_pci_enable_dma,
1586 	.set_bus_width		 = sdhci_set_bus_width,
1587 	.reset			 = sdhci_gl9767_reset,
1588 	.set_uhs_signaling	 = sdhci_set_uhs_signaling,
1589 	.voltage_switch		 = sdhci_gl9767_voltage_switch,
1590 };
1591 
1592 const struct sdhci_pci_fixes sdhci_gl9767 = {
1593 	.quirks		= SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC,
1594 	.quirks2	= SDHCI_QUIRK2_BROKEN_DDR50,
1595 	.probe_slot	= gli_probe_slot_gl9767,
1596 	.ops		= &sdhci_gl9767_ops,
1597 #ifdef CONFIG_PM_SLEEP
1598 	.resume		= sdhci_pci_gli_resume,
1599 #endif
1600 };
1601