1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/scatterlist.h> 21 #include <linux/io.h> 22 #include <linux/iopoll.h> 23 #include <linux/gpio.h> 24 #include <linux/gpio/machine.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/pm_qos.h> 27 #include <linux/debugfs.h> 28 #include <linux/acpi.h> 29 #include <linux/dmi.h> 30 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #ifdef CONFIG_X86 36 #include <asm/iosf_mbi.h> 37 #endif 38 39 #include "cqhci.h" 40 41 #include "sdhci.h" 42 #include "sdhci-cqhci.h" 43 #include "sdhci-pci.h" 44 #include "sdhci-uhs2.h" 45 46 static void sdhci_pci_hw_reset(struct sdhci_host *host); 47 48 #ifdef CONFIG_PM_SLEEP 49 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 50 { 51 mmc_pm_flag_t pm_flags = 0; 52 bool cap_cd_wake = false; 53 int i; 54 55 for (i = 0; i < chip->num_slots; i++) { 56 struct sdhci_pci_slot *slot = chip->slots[i]; 57 58 if (slot) { 59 pm_flags |= slot->host->mmc->pm_flags; 60 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 61 cap_cd_wake = true; 62 } 63 } 64 65 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 66 return device_wakeup_enable(&chip->pdev->dev); 67 else if (!cap_cd_wake) 68 device_wakeup_disable(&chip->pdev->dev); 69 70 return 0; 71 } 72 73 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 74 { 75 int i, ret; 76 77 sdhci_pci_init_wakeup(chip); 78 79 for (i = 0; i < chip->num_slots; i++) { 80 struct sdhci_pci_slot *slot = chip->slots[i]; 81 struct sdhci_host *host; 82 83 if (!slot) 84 continue; 85 86 host = slot->host; 87 88 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 89 mmc_retune_needed(host->mmc); 90 91 ret = sdhci_suspend_host(host); 92 if (ret) 93 goto err_pci_suspend; 94 95 if (device_may_wakeup(&chip->pdev->dev)) 96 mmc_gpio_set_cd_wake(host->mmc, true); 97 } 98 99 return 0; 100 101 err_pci_suspend: 102 while (--i >= 0) 103 sdhci_resume_host(chip->slots[i]->host); 104 return ret; 105 } 106 107 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 108 { 109 struct sdhci_pci_slot *slot; 110 int i, ret; 111 112 for (i = 0; i < chip->num_slots; i++) { 113 slot = chip->slots[i]; 114 if (!slot) 115 continue; 116 117 ret = sdhci_resume_host(slot->host); 118 if (ret) 119 return ret; 120 121 mmc_gpio_set_cd_wake(slot->host->mmc, false); 122 } 123 124 return 0; 125 } 126 127 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 128 { 129 int ret; 130 131 ret = cqhci_suspend(chip->slots[0]->host->mmc); 132 if (ret) 133 return ret; 134 135 return sdhci_pci_suspend_host(chip); 136 } 137 138 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 139 { 140 int ret; 141 142 ret = sdhci_pci_resume_host(chip); 143 if (ret) 144 return ret; 145 146 return cqhci_resume(chip->slots[0]->host->mmc); 147 } 148 #endif 149 150 #ifdef CONFIG_PM 151 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 152 { 153 struct sdhci_pci_slot *slot; 154 struct sdhci_host *host; 155 int i, ret; 156 157 for (i = 0; i < chip->num_slots; i++) { 158 slot = chip->slots[i]; 159 if (!slot) 160 continue; 161 162 host = slot->host; 163 164 ret = sdhci_runtime_suspend_host(host); 165 if (ret) 166 goto err_pci_runtime_suspend; 167 168 if (chip->rpm_retune && 169 host->tuning_mode != SDHCI_TUNING_MODE_3) 170 mmc_retune_needed(host->mmc); 171 } 172 173 return 0; 174 175 err_pci_runtime_suspend: 176 while (--i >= 0) 177 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 178 return ret; 179 } 180 181 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 182 { 183 struct sdhci_pci_slot *slot; 184 int i, ret; 185 186 for (i = 0; i < chip->num_slots; i++) { 187 slot = chip->slots[i]; 188 if (!slot) 189 continue; 190 191 ret = sdhci_runtime_resume_host(slot->host, 0); 192 if (ret) 193 return ret; 194 } 195 196 return 0; 197 } 198 199 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 200 { 201 int ret; 202 203 ret = cqhci_suspend(chip->slots[0]->host->mmc); 204 if (ret) 205 return ret; 206 207 return sdhci_pci_runtime_suspend_host(chip); 208 } 209 210 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 211 { 212 int ret; 213 214 ret = sdhci_pci_runtime_resume_host(chip); 215 if (ret) 216 return ret; 217 218 return cqhci_resume(chip->slots[0]->host->mmc); 219 } 220 #endif 221 222 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 223 { 224 int cmd_error = 0; 225 int data_error = 0; 226 227 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 228 return intmask; 229 230 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 231 232 return 0; 233 } 234 235 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 236 { 237 sdhci_dumpregs(mmc_priv(mmc)); 238 } 239 240 /*****************************************************************************\ 241 * * 242 * Hardware specific quirk handling * 243 * * 244 \*****************************************************************************/ 245 246 static int ricoh_probe(struct sdhci_pci_chip *chip) 247 { 248 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 249 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 250 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 251 return 0; 252 } 253 254 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 255 { 256 u32 caps = 257 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 258 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 259 SDHCI_TIMEOUT_CLK_UNIT | 260 SDHCI_CAN_VDD_330 | 261 SDHCI_CAN_DO_HISPD | 262 SDHCI_CAN_DO_SDMA; 263 u32 caps1 = 0; 264 265 __sdhci_read_caps(slot->host, NULL, &caps, &caps1); 266 return 0; 267 } 268 269 #ifdef CONFIG_PM_SLEEP 270 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 271 { 272 /* Apply a delay to allow controller to settle */ 273 /* Otherwise it becomes confused if card state changed 274 during suspend */ 275 msleep(500); 276 return sdhci_pci_resume_host(chip); 277 } 278 #endif 279 280 static const struct sdhci_pci_fixes sdhci_ricoh = { 281 .probe = ricoh_probe, 282 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 283 SDHCI_QUIRK_FORCE_DMA | 284 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 285 }; 286 287 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 288 .probe_slot = ricoh_mmc_probe_slot, 289 #ifdef CONFIG_PM_SLEEP 290 .resume = ricoh_mmc_resume, 291 #endif 292 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 293 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 294 SDHCI_QUIRK_NO_CARD_NO_RESET, 295 }; 296 297 static void ene_714_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 298 { 299 struct sdhci_host *host = mmc_priv(mmc); 300 301 sdhci_set_ios(mmc, ios); 302 303 /* 304 * Some (ENE) controllers misbehave on some ios operations, 305 * signalling timeout and CRC errors even on CMD0. Resetting 306 * it on each ios seems to solve the problem. 307 */ 308 if (!(host->flags & SDHCI_DEVICE_DEAD)) 309 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 310 } 311 312 static int ene_714_probe_slot(struct sdhci_pci_slot *slot) 313 { 314 slot->host->mmc_host_ops.set_ios = ene_714_set_ios; 315 return 0; 316 } 317 318 static const struct sdhci_pci_fixes sdhci_ene_712 = { 319 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 320 SDHCI_QUIRK_BROKEN_DMA, 321 }; 322 323 static const struct sdhci_pci_fixes sdhci_ene_714 = { 324 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 325 SDHCI_QUIRK_BROKEN_DMA, 326 .probe_slot = ene_714_probe_slot, 327 }; 328 329 static const struct sdhci_pci_fixes sdhci_cafe = { 330 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 331 SDHCI_QUIRK_NO_BUSY_IRQ | 332 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 333 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 334 }; 335 336 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 337 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 338 }; 339 340 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 341 { 342 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 343 return 0; 344 } 345 346 /* 347 * ADMA operation is disabled for Moorestown platform due to 348 * hardware bugs. 349 */ 350 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 351 { 352 /* 353 * slots number is fixed here for MRST as SDIO3/5 are never used and 354 * have hardware bugs. 355 */ 356 chip->num_slots = 1; 357 return 0; 358 } 359 360 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 361 { 362 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 363 return 0; 364 } 365 366 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 367 { 368 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 369 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 370 return 0; 371 } 372 373 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 374 { 375 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 376 return 0; 377 } 378 379 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 380 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 381 .probe_slot = mrst_hc_probe_slot, 382 }; 383 384 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 385 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 386 .probe = mrst_hc_probe, 387 }; 388 389 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 390 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 391 .allow_runtime_pm = true, 392 .own_cd_for_runtime_pm = true, 393 }; 394 395 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 396 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 397 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 398 .allow_runtime_pm = true, 399 .probe_slot = mfd_sdio_probe_slot, 400 }; 401 402 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 403 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 404 .allow_runtime_pm = true, 405 .probe_slot = mfd_emmc_probe_slot, 406 }; 407 408 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 409 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 410 .probe_slot = pch_hc_probe_slot, 411 }; 412 413 #ifdef CONFIG_X86 414 415 #define BYT_IOSF_SCCEP 0x63 416 #define BYT_IOSF_OCP_NETCTRL0 0x1078 417 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 418 419 static void byt_ocp_setting(struct pci_dev *pdev) 420 { 421 u32 val = 0; 422 423 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 424 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 425 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 426 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 427 return; 428 429 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 430 &val)) { 431 dev_err(&pdev->dev, "%s read error\n", __func__); 432 return; 433 } 434 435 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 436 return; 437 438 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 439 440 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 441 val)) { 442 dev_err(&pdev->dev, "%s write error\n", __func__); 443 return; 444 } 445 446 dev_dbg(&pdev->dev, "%s completed\n", __func__); 447 } 448 449 #else 450 451 static inline void byt_ocp_setting(struct pci_dev *pdev) 452 { 453 } 454 455 #endif 456 457 enum { 458 INTEL_DSM_FNS = 0, 459 INTEL_DSM_V18_SWITCH = 3, 460 INTEL_DSM_V33_SWITCH = 4, 461 INTEL_DSM_DRV_STRENGTH = 9, 462 INTEL_DSM_D3_RETUNE = 10, 463 }; 464 465 struct intel_host { 466 u32 dsm_fns; 467 int drv_strength; 468 bool d3_retune; 469 bool rpm_retune_ok; 470 bool needs_pwr_off; 471 u32 glk_rx_ctrl1; 472 u32 glk_tun_val; 473 u32 active_ltr; 474 u32 idle_ltr; 475 }; 476 477 static const guid_t intel_dsm_guid = 478 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 479 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 480 481 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 482 unsigned int fn, u32 *result) 483 { 484 union acpi_object *obj; 485 int err = 0; 486 size_t len; 487 488 obj = acpi_evaluate_dsm_typed(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL, 489 ACPI_TYPE_BUFFER); 490 if (!obj) 491 return -EOPNOTSUPP; 492 493 if (obj->buffer.length < 1) { 494 err = -EINVAL; 495 goto out; 496 } 497 498 len = min_t(size_t, obj->buffer.length, 4); 499 500 *result = 0; 501 memcpy(result, obj->buffer.pointer, len); 502 out: 503 ACPI_FREE(obj); 504 505 return err; 506 } 507 508 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 509 unsigned int fn, u32 *result) 510 { 511 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 512 return -EOPNOTSUPP; 513 514 return __intel_dsm(intel_host, dev, fn, result); 515 } 516 517 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 518 struct mmc_host *mmc) 519 { 520 int err; 521 u32 val; 522 523 intel_host->d3_retune = true; 524 525 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 526 if (err) { 527 pr_debug("%s: DSM not supported, error %d\n", 528 mmc_hostname(mmc), err); 529 return; 530 } 531 532 pr_debug("%s: DSM function mask %#x\n", 533 mmc_hostname(mmc), intel_host->dsm_fns); 534 535 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 536 intel_host->drv_strength = err ? 0 : val; 537 538 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 539 intel_host->d3_retune = err ? true : !!val; 540 } 541 542 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 543 { 544 u8 reg; 545 546 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 547 reg |= 0x10; 548 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 549 /* For eMMC, minimum is 1us but give it 9us for good measure */ 550 udelay(9); 551 reg &= ~0x10; 552 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 553 /* For eMMC, minimum is 200us but give it 300us for good measure */ 554 usleep_range(300, 1000); 555 } 556 557 static int intel_select_drive_strength(struct mmc_card *card, 558 unsigned int max_dtr, int host_drv, 559 int card_drv, int *drv_type) 560 { 561 struct sdhci_host *host = mmc_priv(card->host); 562 struct sdhci_pci_slot *slot = sdhci_priv(host); 563 struct intel_host *intel_host = sdhci_pci_priv(slot); 564 565 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 566 return 0; 567 568 return intel_host->drv_strength; 569 } 570 571 static int bxt_get_cd(struct mmc_host *mmc) 572 { 573 int gpio_cd = mmc_gpio_get_cd(mmc); 574 575 if (!gpio_cd) 576 return 0; 577 578 return sdhci_get_cd_nogpio(mmc); 579 } 580 581 static int mrfld_get_cd(struct mmc_host *mmc) 582 { 583 return sdhci_get_cd_nogpio(mmc); 584 } 585 586 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 587 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 588 589 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 590 unsigned short vdd) 591 { 592 struct sdhci_pci_slot *slot = sdhci_priv(host); 593 struct intel_host *intel_host = sdhci_pci_priv(slot); 594 int cntr; 595 u8 reg; 596 597 /* 598 * Bus power may control card power, but a full reset still may not 599 * reset the power, whereas a direct write to SDHCI_POWER_CONTROL can. 600 * That might be needed to initialize correctly, if the card was left 601 * powered on previously. 602 */ 603 if (intel_host->needs_pwr_off) { 604 intel_host->needs_pwr_off = false; 605 if (mode != MMC_POWER_OFF) { 606 sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); 607 usleep_range(10000, 12500); 608 } 609 } 610 611 sdhci_set_power(host, mode, vdd); 612 613 if (mode == MMC_POWER_OFF) 614 return; 615 616 /* 617 * Bus power might not enable after D3 -> D0 transition due to the 618 * present state not yet having propagated. Retry for up to 2ms. 619 */ 620 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 621 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 622 if (reg & SDHCI_POWER_ON) 623 break; 624 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 625 reg |= SDHCI_POWER_ON; 626 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 627 } 628 } 629 630 static void sdhci_intel_set_uhs_signaling(struct sdhci_host *host, 631 unsigned int timing) 632 { 633 /* Set UHS timing to SDR25 for High Speed mode */ 634 if (timing == MMC_TIMING_MMC_HS || timing == MMC_TIMING_SD_HS) 635 timing = MMC_TIMING_UHS_SDR25; 636 sdhci_set_uhs_signaling(host, timing); 637 } 638 639 #define INTEL_HS400_ES_REG 0x78 640 #define INTEL_HS400_ES_BIT BIT(0) 641 642 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 643 struct mmc_ios *ios) 644 { 645 struct sdhci_host *host = mmc_priv(mmc); 646 u32 val; 647 648 val = sdhci_readl(host, INTEL_HS400_ES_REG); 649 if (ios->enhanced_strobe) 650 val |= INTEL_HS400_ES_BIT; 651 else 652 val &= ~INTEL_HS400_ES_BIT; 653 sdhci_writel(host, val, INTEL_HS400_ES_REG); 654 } 655 656 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 657 struct mmc_ios *ios) 658 { 659 struct device *dev = mmc_dev(mmc); 660 struct sdhci_host *host = mmc_priv(mmc); 661 struct sdhci_pci_slot *slot = sdhci_priv(host); 662 struct intel_host *intel_host = sdhci_pci_priv(slot); 663 unsigned int fn; 664 u32 result = 0; 665 int err; 666 667 err = sdhci_start_signal_voltage_switch(mmc, ios); 668 if (err) 669 return err; 670 671 switch (ios->signal_voltage) { 672 case MMC_SIGNAL_VOLTAGE_330: 673 fn = INTEL_DSM_V33_SWITCH; 674 break; 675 case MMC_SIGNAL_VOLTAGE_180: 676 fn = INTEL_DSM_V18_SWITCH; 677 break; 678 default: 679 return 0; 680 } 681 682 err = intel_dsm(intel_host, dev, fn, &result); 683 pr_debug("%s: %s DSM fn %u error %d result %u\n", 684 mmc_hostname(mmc), __func__, fn, err, result); 685 686 return 0; 687 } 688 689 static const struct sdhci_ops sdhci_intel_byt_ops = { 690 .set_clock = sdhci_set_clock, 691 .set_power = sdhci_intel_set_power, 692 .enable_dma = sdhci_pci_enable_dma, 693 .set_bus_width = sdhci_set_bus_width, 694 .reset = sdhci_reset, 695 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 696 .hw_reset = sdhci_pci_hw_reset, 697 }; 698 699 static const struct sdhci_ops sdhci_intel_glk_ops = { 700 .set_clock = sdhci_set_clock, 701 .set_power = sdhci_intel_set_power, 702 .enable_dma = sdhci_pci_enable_dma, 703 .set_bus_width = sdhci_set_bus_width, 704 .reset = sdhci_and_cqhci_reset, 705 .set_uhs_signaling = sdhci_intel_set_uhs_signaling, 706 .hw_reset = sdhci_pci_hw_reset, 707 .irq = sdhci_cqhci_irq, 708 }; 709 710 static void byt_read_dsm(struct sdhci_pci_slot *slot) 711 { 712 struct intel_host *intel_host = sdhci_pci_priv(slot); 713 struct device *dev = &slot->chip->pdev->dev; 714 struct mmc_host *mmc = slot->host->mmc; 715 716 intel_dsm_init(intel_host, dev, mmc); 717 slot->chip->rpm_retune = intel_host->d3_retune; 718 } 719 720 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 721 { 722 int err = sdhci_execute_tuning(mmc, opcode); 723 struct sdhci_host *host = mmc_priv(mmc); 724 725 if (err) 726 return err; 727 728 /* 729 * Tuning can leave the IP in an active state (Buffer Read Enable bit 730 * set) which prevents the entry to low power states (i.e. S0i3). Data 731 * reset will clear it. 732 */ 733 sdhci_reset(host, SDHCI_RESET_DATA); 734 735 return 0; 736 } 737 738 #define INTEL_ACTIVELTR 0x804 739 #define INTEL_IDLELTR 0x808 740 741 #define INTEL_LTR_REQ BIT(15) 742 #define INTEL_LTR_SCALE_MASK GENMASK(11, 10) 743 #define INTEL_LTR_SCALE_1US (2 << 10) 744 #define INTEL_LTR_SCALE_32US (3 << 10) 745 #define INTEL_LTR_VALUE_MASK GENMASK(9, 0) 746 747 static void intel_cache_ltr(struct sdhci_pci_slot *slot) 748 { 749 struct intel_host *intel_host = sdhci_pci_priv(slot); 750 struct sdhci_host *host = slot->host; 751 752 intel_host->active_ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 753 intel_host->idle_ltr = readl(host->ioaddr + INTEL_IDLELTR); 754 } 755 756 static void intel_ltr_set(struct device *dev, s32 val) 757 { 758 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 759 struct sdhci_pci_slot *slot = chip->slots[0]; 760 struct intel_host *intel_host = sdhci_pci_priv(slot); 761 struct sdhci_host *host = slot->host; 762 u32 ltr; 763 764 pm_runtime_get_sync(dev); 765 766 /* 767 * Program latency tolerance (LTR) accordingly what has been asked 768 * by the PM QoS layer or disable it in case we were passed 769 * negative value or PM_QOS_LATENCY_ANY. 770 */ 771 ltr = readl(host->ioaddr + INTEL_ACTIVELTR); 772 773 if (val == PM_QOS_LATENCY_ANY || val < 0) { 774 ltr &= ~INTEL_LTR_REQ; 775 } else { 776 ltr |= INTEL_LTR_REQ; 777 ltr &= ~INTEL_LTR_SCALE_MASK; 778 ltr &= ~INTEL_LTR_VALUE_MASK; 779 780 if (val > INTEL_LTR_VALUE_MASK) { 781 val >>= 5; 782 if (val > INTEL_LTR_VALUE_MASK) 783 val = INTEL_LTR_VALUE_MASK; 784 ltr |= INTEL_LTR_SCALE_32US | val; 785 } else { 786 ltr |= INTEL_LTR_SCALE_1US | val; 787 } 788 } 789 790 if (ltr == intel_host->active_ltr) 791 goto out; 792 793 writel(ltr, host->ioaddr + INTEL_ACTIVELTR); 794 writel(ltr, host->ioaddr + INTEL_IDLELTR); 795 796 /* Cache the values into lpss structure */ 797 intel_cache_ltr(slot); 798 out: 799 pm_runtime_put_autosuspend(dev); 800 } 801 802 static bool intel_use_ltr(struct sdhci_pci_chip *chip) 803 { 804 switch (chip->pdev->device) { 805 case PCI_DEVICE_ID_INTEL_BYT_EMMC: 806 case PCI_DEVICE_ID_INTEL_BYT_EMMC2: 807 case PCI_DEVICE_ID_INTEL_BYT_SDIO: 808 case PCI_DEVICE_ID_INTEL_BYT_SD: 809 case PCI_DEVICE_ID_INTEL_BSW_EMMC: 810 case PCI_DEVICE_ID_INTEL_BSW_SDIO: 811 case PCI_DEVICE_ID_INTEL_BSW_SD: 812 return false; 813 default: 814 return true; 815 } 816 } 817 818 static void intel_ltr_expose(struct sdhci_pci_chip *chip) 819 { 820 struct device *dev = &chip->pdev->dev; 821 822 if (!intel_use_ltr(chip)) 823 return; 824 825 dev->power.set_latency_tolerance = intel_ltr_set; 826 dev_pm_qos_expose_latency_tolerance(dev); 827 } 828 829 static void intel_ltr_hide(struct sdhci_pci_chip *chip) 830 { 831 struct device *dev = &chip->pdev->dev; 832 833 if (!intel_use_ltr(chip)) 834 return; 835 836 dev_pm_qos_hide_latency_tolerance(dev); 837 dev->power.set_latency_tolerance = NULL; 838 } 839 840 static void byt_probe_slot(struct sdhci_pci_slot *slot) 841 { 842 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 843 struct device *dev = &slot->chip->pdev->dev; 844 struct mmc_host *mmc = slot->host->mmc; 845 846 byt_read_dsm(slot); 847 848 byt_ocp_setting(slot->chip->pdev); 849 850 ops->execute_tuning = intel_execute_tuning; 851 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 852 853 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 854 855 if (!mmc->slotno) { 856 slot->chip->slots[mmc->slotno] = slot; 857 intel_ltr_expose(slot->chip); 858 } 859 } 860 861 static void byt_add_debugfs(struct sdhci_pci_slot *slot) 862 { 863 struct intel_host *intel_host = sdhci_pci_priv(slot); 864 struct mmc_host *mmc = slot->host->mmc; 865 struct dentry *dir = mmc->debugfs_root; 866 867 if (!intel_use_ltr(slot->chip)) 868 return; 869 870 debugfs_create_x32("active_ltr", 0444, dir, &intel_host->active_ltr); 871 debugfs_create_x32("idle_ltr", 0444, dir, &intel_host->idle_ltr); 872 873 intel_cache_ltr(slot); 874 } 875 876 static int byt_add_host(struct sdhci_pci_slot *slot) 877 { 878 int ret = sdhci_add_host(slot->host); 879 880 if (!ret) 881 byt_add_debugfs(slot); 882 return ret; 883 } 884 885 static void byt_remove_slot(struct sdhci_pci_slot *slot, int dead) 886 { 887 struct mmc_host *mmc = slot->host->mmc; 888 889 if (!mmc->slotno) 890 intel_ltr_hide(slot->chip); 891 } 892 893 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 894 { 895 byt_probe_slot(slot); 896 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 897 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 898 MMC_CAP_CMD_DURING_TFR | 899 MMC_CAP_WAIT_WHILE_BUSY; 900 slot->hw_reset = sdhci_pci_int_hw_reset; 901 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 902 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 903 slot->host->mmc_host_ops.select_drive_strength = 904 intel_select_drive_strength; 905 return 0; 906 } 907 908 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 909 { 910 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 911 (dmi_match(DMI_BIOS_VENDOR, "LENOVO") || 912 dmi_match(DMI_SYS_VENDOR, "IRBIS")); 913 } 914 915 static bool jsl_broken_hs400es(struct sdhci_pci_slot *slot) 916 { 917 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_JSL_EMMC && 918 dmi_match(DMI_BIOS_VENDOR, "ASUSTeK COMPUTER INC."); 919 } 920 921 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 922 { 923 int ret = byt_emmc_probe_slot(slot); 924 925 if (!glk_broken_cqhci(slot)) 926 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 927 928 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 929 if (!jsl_broken_hs400es(slot)) { 930 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES; 931 slot->host->mmc_host_ops.hs400_enhanced_strobe = 932 intel_hs400_enhanced_strobe; 933 } 934 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 935 } 936 937 return ret; 938 } 939 940 static const struct cqhci_host_ops glk_cqhci_ops = { 941 .enable = sdhci_cqe_enable, 942 .disable = sdhci_cqe_disable, 943 .dumpregs = sdhci_pci_dumpregs, 944 }; 945 946 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 947 { 948 struct device *dev = &slot->chip->pdev->dev; 949 struct sdhci_host *host = slot->host; 950 struct cqhci_host *cq_host; 951 bool dma64; 952 int ret; 953 954 ret = sdhci_setup_host(host); 955 if (ret) 956 return ret; 957 958 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 959 if (!cq_host) { 960 ret = -ENOMEM; 961 goto cleanup; 962 } 963 964 cq_host->mmio = host->ioaddr + 0x200; 965 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 966 cq_host->ops = &glk_cqhci_ops; 967 968 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 969 if (dma64) 970 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 971 972 ret = cqhci_init(cq_host, host->mmc, dma64); 973 if (ret) 974 goto cleanup; 975 976 ret = __sdhci_add_host(host); 977 if (ret) 978 goto cleanup; 979 980 byt_add_debugfs(slot); 981 982 return 0; 983 984 cleanup: 985 sdhci_cleanup_host(host); 986 return ret; 987 } 988 989 #ifdef CONFIG_PM 990 #define GLK_RX_CTRL1 0x834 991 #define GLK_TUN_VAL 0x840 992 #define GLK_PATH_PLL GENMASK(13, 8) 993 #define GLK_DLY GENMASK(6, 0) 994 /* Workaround firmware failing to restore the tuning value */ 995 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 996 { 997 struct sdhci_pci_slot *slot = chip->slots[0]; 998 struct intel_host *intel_host = sdhci_pci_priv(slot); 999 struct sdhci_host *host = slot->host; 1000 u32 glk_rx_ctrl1; 1001 u32 glk_tun_val; 1002 u32 dly; 1003 1004 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 1005 return; 1006 1007 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 1008 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 1009 1010 if (susp) { 1011 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 1012 intel_host->glk_tun_val = glk_tun_val; 1013 return; 1014 } 1015 1016 if (!intel_host->glk_tun_val) 1017 return; 1018 1019 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 1020 intel_host->rpm_retune_ok = true; 1021 return; 1022 } 1023 1024 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 1025 (intel_host->glk_tun_val << 1)); 1026 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 1027 return; 1028 1029 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 1030 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 1031 1032 intel_host->rpm_retune_ok = true; 1033 chip->rpm_retune = true; 1034 mmc_retune_needed(host->mmc); 1035 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 1036 } 1037 1038 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 1039 { 1040 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 1041 !chip->rpm_retune) 1042 glk_rpm_retune_wa(chip, susp); 1043 } 1044 1045 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 1046 { 1047 glk_rpm_retune_chk(chip, true); 1048 1049 return sdhci_cqhci_runtime_suspend(chip); 1050 } 1051 1052 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 1053 { 1054 glk_rpm_retune_chk(chip, false); 1055 1056 return sdhci_cqhci_runtime_resume(chip); 1057 } 1058 #endif 1059 1060 #ifdef CONFIG_ACPI 1061 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 1062 { 1063 acpi_status status; 1064 unsigned long long max_freq; 1065 1066 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 1067 "MXFQ", NULL, &max_freq); 1068 if (ACPI_FAILURE(status)) { 1069 dev_err(&slot->chip->pdev->dev, 1070 "MXFQ not found in acpi table\n"); 1071 return -EINVAL; 1072 } 1073 1074 slot->host->mmc->f_max = max_freq * 1000000; 1075 1076 return 0; 1077 } 1078 #else 1079 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 1080 { 1081 return 0; 1082 } 1083 #endif 1084 1085 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1086 { 1087 int err; 1088 1089 byt_probe_slot(slot); 1090 1091 err = ni_set_max_freq(slot); 1092 if (err) 1093 return err; 1094 1095 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1096 MMC_CAP_WAIT_WHILE_BUSY; 1097 return 0; 1098 } 1099 1100 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 1101 { 1102 byt_probe_slot(slot); 1103 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 1104 MMC_CAP_WAIT_WHILE_BUSY; 1105 return 0; 1106 } 1107 1108 static void byt_needs_pwr_off(struct sdhci_pci_slot *slot) 1109 { 1110 struct intel_host *intel_host = sdhci_pci_priv(slot); 1111 u8 reg = sdhci_readb(slot->host, SDHCI_POWER_CONTROL); 1112 1113 intel_host->needs_pwr_off = reg & SDHCI_POWER_ON; 1114 } 1115 1116 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 1117 { 1118 byt_probe_slot(slot); 1119 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 1120 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 1121 slot->cd_idx = 0; 1122 slot->cd_override_level = true; 1123 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 1124 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 1125 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 1126 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 1127 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 1128 1129 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 1130 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 1131 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 1132 1133 byt_needs_pwr_off(slot); 1134 1135 return 0; 1136 } 1137 1138 #ifdef CONFIG_PM_SLEEP 1139 1140 static int byt_resume(struct sdhci_pci_chip *chip) 1141 { 1142 byt_ocp_setting(chip->pdev); 1143 1144 return sdhci_pci_resume_host(chip); 1145 } 1146 1147 #endif 1148 1149 #ifdef CONFIG_PM 1150 1151 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1152 { 1153 byt_ocp_setting(chip->pdev); 1154 1155 return sdhci_pci_runtime_resume_host(chip); 1156 } 1157 1158 #endif 1159 1160 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1161 #ifdef CONFIG_PM_SLEEP 1162 .resume = byt_resume, 1163 #endif 1164 #ifdef CONFIG_PM 1165 .runtime_resume = byt_runtime_resume, 1166 #endif 1167 .allow_runtime_pm = true, 1168 .probe_slot = byt_emmc_probe_slot, 1169 .add_host = byt_add_host, 1170 .remove_slot = byt_remove_slot, 1171 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1172 SDHCI_QUIRK_NO_LED, 1173 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1174 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1175 SDHCI_QUIRK2_STOP_WITH_TC, 1176 .ops = &sdhci_intel_byt_ops, 1177 .priv_size = sizeof(struct intel_host), 1178 }; 1179 1180 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1181 .allow_runtime_pm = true, 1182 .probe_slot = glk_emmc_probe_slot, 1183 .add_host = glk_emmc_add_host, 1184 .remove_slot = byt_remove_slot, 1185 #ifdef CONFIG_PM_SLEEP 1186 .suspend = sdhci_cqhci_suspend, 1187 .resume = sdhci_cqhci_resume, 1188 #endif 1189 #ifdef CONFIG_PM 1190 .runtime_suspend = glk_runtime_suspend, 1191 .runtime_resume = glk_runtime_resume, 1192 #endif 1193 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1194 SDHCI_QUIRK_NO_LED, 1195 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1196 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1197 SDHCI_QUIRK2_STOP_WITH_TC, 1198 .ops = &sdhci_intel_glk_ops, 1199 .priv_size = sizeof(struct intel_host), 1200 }; 1201 1202 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1203 #ifdef CONFIG_PM_SLEEP 1204 .resume = byt_resume, 1205 #endif 1206 #ifdef CONFIG_PM 1207 .runtime_resume = byt_runtime_resume, 1208 #endif 1209 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1210 SDHCI_QUIRK_NO_LED, 1211 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1212 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1213 .allow_runtime_pm = true, 1214 .probe_slot = ni_byt_sdio_probe_slot, 1215 .add_host = byt_add_host, 1216 .remove_slot = byt_remove_slot, 1217 .ops = &sdhci_intel_byt_ops, 1218 .priv_size = sizeof(struct intel_host), 1219 }; 1220 1221 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1222 #ifdef CONFIG_PM_SLEEP 1223 .resume = byt_resume, 1224 #endif 1225 #ifdef CONFIG_PM 1226 .runtime_resume = byt_runtime_resume, 1227 #endif 1228 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1229 SDHCI_QUIRK_NO_LED, 1230 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1231 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1232 .allow_runtime_pm = true, 1233 .probe_slot = byt_sdio_probe_slot, 1234 .add_host = byt_add_host, 1235 .remove_slot = byt_remove_slot, 1236 .ops = &sdhci_intel_byt_ops, 1237 .priv_size = sizeof(struct intel_host), 1238 }; 1239 1240 /* DMI quirks for devices with missing or broken CD GPIO info */ 1241 static const struct gpiod_lookup_table vexia_edu_atla10_cd_gpios = { 1242 .dev_id = "0000:00:12.0", 1243 .table = { 1244 GPIO_LOOKUP("INT33FC:00", 38, "cd", GPIO_ACTIVE_HIGH), 1245 { } 1246 }, 1247 }; 1248 1249 static const struct dmi_system_id sdhci_intel_byt_cd_gpio_override[] = { 1250 { 1251 /* Vexia Edu Atla 10 tablet 9V version */ 1252 .matches = { 1253 DMI_MATCH(DMI_BOARD_VENDOR, "AMI Corporation"), 1254 DMI_MATCH(DMI_BOARD_NAME, "Aptio CRB"), 1255 /* Above strings are too generic, also match on BIOS date */ 1256 DMI_MATCH(DMI_BIOS_DATE, "08/25/2014"), 1257 }, 1258 .driver_data = (void *)&vexia_edu_atla10_cd_gpios, 1259 }, 1260 { } 1261 }; 1262 1263 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1264 #ifdef CONFIG_PM_SLEEP 1265 .resume = byt_resume, 1266 #endif 1267 #ifdef CONFIG_PM 1268 .runtime_resume = byt_runtime_resume, 1269 #endif 1270 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1271 SDHCI_QUIRK_NO_LED, 1272 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1273 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1274 SDHCI_QUIRK2_STOP_WITH_TC, 1275 .allow_runtime_pm = true, 1276 .own_cd_for_runtime_pm = true, 1277 .probe_slot = byt_sd_probe_slot, 1278 .add_host = byt_add_host, 1279 .remove_slot = byt_remove_slot, 1280 .ops = &sdhci_intel_byt_ops, 1281 .cd_gpio_override = sdhci_intel_byt_cd_gpio_override, 1282 .priv_size = sizeof(struct intel_host), 1283 }; 1284 1285 /* Define Host controllers for Intel Merrifield platform */ 1286 #define INTEL_MRFLD_EMMC_0 0 1287 #define INTEL_MRFLD_EMMC_1 1 1288 #define INTEL_MRFLD_SD 2 1289 #define INTEL_MRFLD_SDIO 3 1290 1291 #ifdef CONFIG_ACPI 1292 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1293 { 1294 struct acpi_device *device; 1295 1296 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1297 if (device) 1298 acpi_device_fix_up_power_extended(device); 1299 } 1300 #else 1301 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1302 #endif 1303 1304 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1305 { 1306 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1307 1308 switch (func) { 1309 case INTEL_MRFLD_EMMC_0: 1310 case INTEL_MRFLD_EMMC_1: 1311 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1312 MMC_CAP_8_BIT_DATA | 1313 MMC_CAP_1_8V_DDR; 1314 break; 1315 case INTEL_MRFLD_SD: 1316 slot->cd_idx = 0; 1317 slot->cd_override_level = true; 1318 /* 1319 * There are two PCB designs of SD card slot with the opposite 1320 * card detection sense. Quirk this out by ignoring GPIO state 1321 * completely in the custom ->get_cd() callback. 1322 */ 1323 slot->host->mmc_host_ops.get_cd = mrfld_get_cd; 1324 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1325 break; 1326 case INTEL_MRFLD_SDIO: 1327 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1328 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1329 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1330 MMC_CAP_POWER_OFF_CARD; 1331 break; 1332 default: 1333 return -ENODEV; 1334 } 1335 1336 intel_mrfld_mmc_fix_up_power_slot(slot); 1337 return 0; 1338 } 1339 1340 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1341 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1342 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1343 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1344 .allow_runtime_pm = true, 1345 .probe_slot = intel_mrfld_mmc_probe_slot, 1346 }; 1347 1348 #define JMB388_SAMPLE_COUNT 5 1349 1350 static int jmicron_jmb388_get_ro(struct mmc_host *mmc) 1351 { 1352 int i, ro_count; 1353 1354 ro_count = 0; 1355 for (i = 0; i < JMB388_SAMPLE_COUNT; i++) { 1356 if (sdhci_get_ro(mmc) > 0) { 1357 if (++ro_count > JMB388_SAMPLE_COUNT / 2) 1358 return 1; 1359 } 1360 msleep(30); 1361 } 1362 return 0; 1363 } 1364 1365 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1366 { 1367 u8 scratch; 1368 int ret; 1369 1370 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1371 if (ret) 1372 goto fail; 1373 1374 /* 1375 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1376 * [bit 1:2] and enable over current debouncing [bit 6]. 1377 */ 1378 if (on) 1379 scratch |= 0x47; 1380 else 1381 scratch &= ~0x47; 1382 1383 ret = pci_write_config_byte(chip->pdev, 0xAE, scratch); 1384 1385 fail: 1386 return pcibios_err_to_errno(ret); 1387 } 1388 1389 static int jmicron_probe(struct sdhci_pci_chip *chip) 1390 { 1391 int ret; 1392 u16 mmcdev = 0; 1393 1394 if (chip->pdev->revision == 0) { 1395 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1396 SDHCI_QUIRK_32BIT_DMA_SIZE | 1397 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1398 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1399 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1400 } 1401 1402 /* 1403 * JMicron chips can have two interfaces to the same hardware 1404 * in order to work around limitations in Microsoft's driver. 1405 * We need to make sure we only bind to one of them. 1406 * 1407 * This code assumes two things: 1408 * 1409 * 1. The PCI code adds subfunctions in order. 1410 * 1411 * 2. The MMC interface has a lower subfunction number 1412 * than the SD interface. 1413 */ 1414 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1415 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1416 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1417 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1418 1419 if (mmcdev) { 1420 struct pci_dev *sd_dev; 1421 1422 sd_dev = NULL; 1423 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1424 mmcdev, sd_dev)) != NULL) { 1425 if ((PCI_SLOT(chip->pdev->devfn) == 1426 PCI_SLOT(sd_dev->devfn)) && 1427 (chip->pdev->bus == sd_dev->bus)) 1428 break; 1429 } 1430 1431 if (sd_dev) { 1432 pci_dev_put(sd_dev); 1433 dev_info(&chip->pdev->dev, "Refusing to bind to " 1434 "secondary interface.\n"); 1435 return -ENODEV; 1436 } 1437 } 1438 1439 /* 1440 * JMicron chips need a bit of a nudge to enable the power 1441 * output pins. 1442 */ 1443 ret = jmicron_pmos(chip, 1); 1444 if (ret) { 1445 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1446 return ret; 1447 } 1448 1449 return 0; 1450 } 1451 1452 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1453 { 1454 u8 scratch; 1455 1456 scratch = readb(host->ioaddr + 0xC0); 1457 1458 if (on) 1459 scratch |= 0x01; 1460 else 1461 scratch &= ~0x01; 1462 1463 writeb(scratch, host->ioaddr + 0xC0); 1464 } 1465 1466 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1467 { 1468 if (slot->chip->pdev->revision == 0) { 1469 u16 version; 1470 1471 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1472 version = (version & SDHCI_VENDOR_VER_MASK) >> 1473 SDHCI_VENDOR_VER_SHIFT; 1474 1475 /* 1476 * Older versions of the chip have lots of nasty glitches 1477 * in the ADMA engine. It's best just to avoid it 1478 * completely. 1479 */ 1480 if (version < 0xAC) 1481 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1482 } 1483 1484 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1485 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1486 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1487 MMC_VDD_29_30 | MMC_VDD_30_31 | 1488 MMC_VDD_165_195; /* allow 1.8V */ 1489 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1490 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1491 } 1492 1493 /* 1494 * The secondary interface requires a bit set to get the 1495 * interrupts. 1496 */ 1497 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1498 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1499 jmicron_enable_mmc(slot->host, 1); 1500 1501 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1502 1503 /* Handle unstable RO-detection on JM388 chips */ 1504 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1505 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1506 slot->host->mmc_host_ops.get_ro = jmicron_jmb388_get_ro; 1507 1508 return 0; 1509 } 1510 1511 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1512 { 1513 if (dead) 1514 return; 1515 1516 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1517 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1518 jmicron_enable_mmc(slot->host, 0); 1519 } 1520 1521 #ifdef CONFIG_PM_SLEEP 1522 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1523 { 1524 int i, ret; 1525 1526 ret = sdhci_pci_suspend_host(chip); 1527 if (ret) 1528 return ret; 1529 1530 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1531 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1532 for (i = 0; i < chip->num_slots; i++) 1533 jmicron_enable_mmc(chip->slots[i]->host, 0); 1534 } 1535 1536 return 0; 1537 } 1538 1539 static int jmicron_resume(struct sdhci_pci_chip *chip) 1540 { 1541 int ret, i; 1542 1543 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1544 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1545 for (i = 0; i < chip->num_slots; i++) 1546 jmicron_enable_mmc(chip->slots[i]->host, 1); 1547 } 1548 1549 ret = jmicron_pmos(chip, 1); 1550 if (ret) { 1551 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1552 return ret; 1553 } 1554 1555 return sdhci_pci_resume_host(chip); 1556 } 1557 #endif 1558 1559 static const struct sdhci_pci_fixes sdhci_jmicron = { 1560 .probe = jmicron_probe, 1561 1562 .probe_slot = jmicron_probe_slot, 1563 .remove_slot = jmicron_remove_slot, 1564 1565 #ifdef CONFIG_PM_SLEEP 1566 .suspend = jmicron_suspend, 1567 .resume = jmicron_resume, 1568 #endif 1569 }; 1570 1571 /* SysKonnect CardBus2SDIO extra registers */ 1572 #define SYSKT_CTRL 0x200 1573 #define SYSKT_RDFIFO_STAT 0x204 1574 #define SYSKT_WRFIFO_STAT 0x208 1575 #define SYSKT_POWER_DATA 0x20c 1576 #define SYSKT_POWER_330 0xef 1577 #define SYSKT_POWER_300 0xf8 1578 #define SYSKT_POWER_184 0xcc 1579 #define SYSKT_POWER_CMD 0x20d 1580 #define SYSKT_POWER_START (1 << 7) 1581 #define SYSKT_POWER_STATUS 0x20e 1582 #define SYSKT_POWER_STATUS_OK (1 << 0) 1583 #define SYSKT_BOARD_REV 0x210 1584 #define SYSKT_CHIP_REV 0x211 1585 #define SYSKT_CONF_DATA 0x212 1586 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1587 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1588 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1589 1590 static int syskt_probe(struct sdhci_pci_chip *chip) 1591 { 1592 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1593 chip->pdev->class &= ~0x0000FF; 1594 chip->pdev->class |= PCI_SDHCI_IFDMA; 1595 } 1596 return 0; 1597 } 1598 1599 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1600 { 1601 int tm, ps; 1602 1603 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1604 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1605 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1606 "board rev %d.%d, chip rev %d.%d\n", 1607 board_rev >> 4, board_rev & 0xf, 1608 chip_rev >> 4, chip_rev & 0xf); 1609 if (chip_rev >= 0x20) 1610 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1611 1612 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1613 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1614 udelay(50); 1615 tm = 10; /* Wait max 1 ms */ 1616 do { 1617 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1618 if (ps & SYSKT_POWER_STATUS_OK) 1619 break; 1620 udelay(100); 1621 } while (--tm); 1622 if (!tm) { 1623 dev_err(&slot->chip->pdev->dev, 1624 "power regulator never stabilized"); 1625 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1626 return -ENODEV; 1627 } 1628 1629 return 0; 1630 } 1631 1632 static const struct sdhci_pci_fixes sdhci_syskt = { 1633 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1634 .probe = syskt_probe, 1635 .probe_slot = syskt_probe_slot, 1636 }; 1637 1638 static int via_probe(struct sdhci_pci_chip *chip) 1639 { 1640 if (chip->pdev->revision == 0x10) 1641 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1642 1643 return 0; 1644 } 1645 1646 static const struct sdhci_pci_fixes sdhci_via = { 1647 .probe = via_probe, 1648 }; 1649 1650 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1651 { 1652 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1653 return 0; 1654 } 1655 1656 static const struct sdhci_pci_fixes sdhci_rtsx = { 1657 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1658 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1659 SDHCI_QUIRK2_BROKEN_DDR50, 1660 .probe_slot = rtsx_probe_slot, 1661 }; 1662 1663 /*AMD chipset generation*/ 1664 enum amd_chipset_gen { 1665 AMD_CHIPSET_BEFORE_ML, 1666 AMD_CHIPSET_CZ, 1667 AMD_CHIPSET_NL, 1668 AMD_CHIPSET_UNKNOWN, 1669 }; 1670 1671 /* AMD registers */ 1672 #define AMD_SD_AUTO_PATTERN 0xB8 1673 #define AMD_MSLEEP_DURATION 4 1674 #define AMD_SD_MISC_CONTROL 0xD0 1675 #define AMD_MAX_TUNE_VALUE 0x0B 1676 #define AMD_AUTO_TUNE_SEL 0x10800 1677 #define AMD_FIFO_PTR 0x30 1678 #define AMD_BIT_MASK 0x1F 1679 1680 static void amd_tuning_reset(struct sdhci_host *host) 1681 { 1682 unsigned int val; 1683 1684 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1685 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1686 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1687 1688 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1689 val &= ~SDHCI_CTRL_EXEC_TUNING; 1690 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1691 } 1692 1693 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1694 { 1695 unsigned int val; 1696 1697 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1698 val &= ~AMD_BIT_MASK; 1699 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1700 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1701 } 1702 1703 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1704 { 1705 unsigned int val; 1706 1707 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1708 val |= AMD_FIFO_PTR; 1709 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1710 } 1711 1712 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1713 { 1714 struct sdhci_pci_slot *slot = sdhci_priv(host); 1715 struct pci_dev *pdev = slot->chip->pdev; 1716 u8 valid_win = 0; 1717 u8 valid_win_max = 0; 1718 u8 valid_win_end = 0; 1719 u8 ctrl, tune_around; 1720 1721 amd_tuning_reset(host); 1722 1723 for (tune_around = 0; tune_around < 12; tune_around++) { 1724 amd_config_tuning_phase(pdev, tune_around); 1725 1726 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1727 valid_win = 0; 1728 msleep(AMD_MSLEEP_DURATION); 1729 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1730 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1731 } else if (++valid_win > valid_win_max) { 1732 valid_win_max = valid_win; 1733 valid_win_end = tune_around; 1734 } 1735 } 1736 1737 if (!valid_win_max) { 1738 dev_err(&pdev->dev, "no tuning point found\n"); 1739 return -EIO; 1740 } 1741 1742 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1743 1744 amd_enable_manual_tuning(pdev); 1745 1746 host->mmc->retune_period = 0; 1747 1748 return 0; 1749 } 1750 1751 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1752 { 1753 struct sdhci_host *host = mmc_priv(mmc); 1754 1755 /* AMD requires custom HS200 tuning */ 1756 if (host->timing == MMC_TIMING_MMC_HS200) 1757 return amd_execute_tuning_hs200(host, opcode); 1758 1759 /* Otherwise perform standard SDHCI tuning */ 1760 return sdhci_execute_tuning(mmc, opcode); 1761 } 1762 1763 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1764 { 1765 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1766 1767 ops->execute_tuning = amd_execute_tuning; 1768 1769 return 0; 1770 } 1771 1772 static int amd_probe(struct sdhci_pci_chip *chip) 1773 { 1774 struct pci_dev *smbus_dev; 1775 enum amd_chipset_gen gen; 1776 1777 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1778 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1779 if (smbus_dev) { 1780 gen = AMD_CHIPSET_BEFORE_ML; 1781 } else { 1782 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1783 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1784 if (smbus_dev) { 1785 if (smbus_dev->revision < 0x51) 1786 gen = AMD_CHIPSET_CZ; 1787 else 1788 gen = AMD_CHIPSET_NL; 1789 } else { 1790 gen = AMD_CHIPSET_UNKNOWN; 1791 } 1792 } 1793 1794 pci_dev_put(smbus_dev); 1795 1796 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1797 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1798 1799 return 0; 1800 } 1801 1802 static u32 sdhci_read_present_state(struct sdhci_host *host) 1803 { 1804 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1805 } 1806 1807 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1808 { 1809 struct sdhci_pci_slot *slot = sdhci_priv(host); 1810 struct pci_dev *pdev = slot->chip->pdev; 1811 u32 present_state; 1812 1813 /* 1814 * SDHC 0x7906 requires a hard reset to clear all internal state. 1815 * Otherwise it can get into a bad state where the DATA lines are always 1816 * read as zeros. 1817 */ 1818 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1819 pci_clear_master(pdev); 1820 1821 pci_save_state(pdev); 1822 1823 pci_set_power_state(pdev, PCI_D3cold); 1824 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1825 pdev->current_state); 1826 pci_set_power_state(pdev, PCI_D0); 1827 1828 pci_restore_state(pdev); 1829 1830 /* 1831 * SDHCI_RESET_ALL says the card detect logic should not be 1832 * reset, but since we need to reset the entire controller 1833 * we should wait until the card detect logic has stabilized. 1834 * 1835 * This normally takes about 40ms. 1836 */ 1837 readx_poll_timeout( 1838 sdhci_read_present_state, 1839 host, 1840 present_state, 1841 present_state & SDHCI_CD_STABLE, 1842 10000, 1843 100000 1844 ); 1845 } 1846 1847 return sdhci_reset(host, mask); 1848 } 1849 1850 static const struct sdhci_ops amd_sdhci_pci_ops = { 1851 .set_clock = sdhci_set_clock, 1852 .enable_dma = sdhci_pci_enable_dma, 1853 .set_bus_width = sdhci_set_bus_width, 1854 .reset = amd_sdhci_reset, 1855 .set_uhs_signaling = sdhci_set_uhs_signaling, 1856 }; 1857 1858 static const struct sdhci_pci_fixes sdhci_amd = { 1859 .probe = amd_probe, 1860 .ops = &amd_sdhci_pci_ops, 1861 .probe_slot = amd_probe_slot, 1862 }; 1863 1864 static const struct pci_device_id pci_ids[] = { 1865 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1866 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1867 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1868 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1869 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1870 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1871 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1872 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1873 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1874 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1875 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1876 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1877 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1878 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1879 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1880 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1881 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1882 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1883 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1884 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1885 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1886 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1887 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1888 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1889 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1890 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1891 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1892 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1893 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1894 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1895 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1896 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1897 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1898 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1899 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1900 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1901 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1902 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1903 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1904 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1905 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1906 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1907 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1908 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1909 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1910 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1911 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1912 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1913 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1914 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1915 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1916 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1917 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1918 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1919 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1920 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1921 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1922 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1923 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1924 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1925 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1926 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1927 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1928 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1929 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1930 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1931 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1932 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1933 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1934 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1935 SDHCI_PCI_DEVICE(INTEL, LKF_EMMC, intel_glk_emmc), 1936 SDHCI_PCI_DEVICE(INTEL, LKF_SD, intel_byt_sd), 1937 SDHCI_PCI_DEVICE(INTEL, ADL_EMMC, intel_glk_emmc), 1938 SDHCI_PCI_DEVICE(O2, 8120, o2), 1939 SDHCI_PCI_DEVICE(O2, 8220, o2), 1940 SDHCI_PCI_DEVICE(O2, 8221, o2), 1941 SDHCI_PCI_DEVICE(O2, 8320, o2), 1942 SDHCI_PCI_DEVICE(O2, 8321, o2), 1943 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1944 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1945 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1946 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1947 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1948 SDHCI_PCI_DEVICE(O2, GG8_9860, o2), 1949 SDHCI_PCI_DEVICE(O2, GG8_9861, o2), 1950 SDHCI_PCI_DEVICE(O2, GG8_9862, o2), 1951 SDHCI_PCI_DEVICE(O2, GG8_9863, o2), 1952 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1953 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1954 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1955 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1956 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1957 SDHCI_PCI_DEVICE(GLI, 9767, gl9767), 1958 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1959 /* Generic SD host controller */ 1960 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1961 { /* end: all zeroes */ }, 1962 }; 1963 1964 MODULE_DEVICE_TABLE(pci, pci_ids); 1965 1966 /*****************************************************************************\ 1967 * * 1968 * SDHCI core callbacks * 1969 * * 1970 \*****************************************************************************/ 1971 1972 int sdhci_pci_enable_dma(struct sdhci_host *host) 1973 { 1974 struct sdhci_pci_slot *slot; 1975 struct pci_dev *pdev; 1976 1977 slot = sdhci_priv(host); 1978 pdev = slot->chip->pdev; 1979 1980 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1981 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1982 (host->flags & SDHCI_USE_SDMA)) { 1983 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1984 "doesn't fully claim to support it.\n"); 1985 } 1986 1987 pci_set_master(pdev); 1988 1989 return 0; 1990 } 1991 1992 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1993 { 1994 struct sdhci_pci_slot *slot = sdhci_priv(host); 1995 1996 if (slot->hw_reset) 1997 slot->hw_reset(host); 1998 } 1999 2000 static const struct sdhci_ops sdhci_pci_ops = { 2001 .set_clock = sdhci_set_clock, 2002 .enable_dma = sdhci_pci_enable_dma, 2003 .set_bus_width = sdhci_set_bus_width, 2004 .reset = sdhci_reset, 2005 .set_uhs_signaling = sdhci_set_uhs_signaling, 2006 .hw_reset = sdhci_pci_hw_reset, 2007 }; 2008 2009 /*****************************************************************************\ 2010 * * 2011 * Suspend/resume * 2012 * * 2013 \*****************************************************************************/ 2014 2015 #ifdef CONFIG_PM_SLEEP 2016 static int sdhci_pci_suspend(struct device *dev) 2017 { 2018 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2019 2020 if (!chip) 2021 return 0; 2022 2023 if (chip->fixes && chip->fixes->suspend) 2024 return chip->fixes->suspend(chip); 2025 2026 return sdhci_pci_suspend_host(chip); 2027 } 2028 2029 static int sdhci_pci_resume(struct device *dev) 2030 { 2031 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2032 2033 if (!chip) 2034 return 0; 2035 2036 if (chip->fixes && chip->fixes->resume) 2037 return chip->fixes->resume(chip); 2038 2039 return sdhci_pci_resume_host(chip); 2040 } 2041 #endif 2042 2043 #ifdef CONFIG_PM 2044 static int sdhci_pci_runtime_suspend(struct device *dev) 2045 { 2046 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2047 2048 if (!chip) 2049 return 0; 2050 2051 if (chip->fixes && chip->fixes->runtime_suspend) 2052 return chip->fixes->runtime_suspend(chip); 2053 2054 return sdhci_pci_runtime_suspend_host(chip); 2055 } 2056 2057 static int sdhci_pci_runtime_resume(struct device *dev) 2058 { 2059 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 2060 2061 if (!chip) 2062 return 0; 2063 2064 if (chip->fixes && chip->fixes->runtime_resume) 2065 return chip->fixes->runtime_resume(chip); 2066 2067 return sdhci_pci_runtime_resume_host(chip); 2068 } 2069 #endif 2070 2071 static const struct dev_pm_ops sdhci_pci_pm_ops = { 2072 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 2073 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 2074 sdhci_pci_runtime_resume, NULL) 2075 }; 2076 2077 /*****************************************************************************\ 2078 * * 2079 * Device probing/removal * 2080 * * 2081 \*****************************************************************************/ 2082 2083 static struct gpiod_lookup_table *sdhci_pci_add_gpio_lookup_table( 2084 struct sdhci_pci_chip *chip) 2085 { 2086 struct gpiod_lookup_table *cd_gpio_lookup_table; 2087 const struct dmi_system_id *dmi_id = NULL; 2088 size_t count; 2089 2090 if (chip->fixes && chip->fixes->cd_gpio_override) 2091 dmi_id = dmi_first_match(chip->fixes->cd_gpio_override); 2092 2093 if (!dmi_id) 2094 return NULL; 2095 2096 cd_gpio_lookup_table = dmi_id->driver_data; 2097 for (count = 0; cd_gpio_lookup_table->table[count].key; count++) 2098 ; 2099 2100 cd_gpio_lookup_table = kmemdup(dmi_id->driver_data, 2101 /* count + 1 terminating entry */ 2102 struct_size(cd_gpio_lookup_table, table, count + 1), 2103 GFP_KERNEL); 2104 if (!cd_gpio_lookup_table) 2105 return ERR_PTR(-ENOMEM); 2106 2107 gpiod_add_lookup_table(cd_gpio_lookup_table); 2108 return cd_gpio_lookup_table; 2109 } 2110 2111 static void sdhci_pci_remove_gpio_lookup_table(struct gpiod_lookup_table *lookup_table) 2112 { 2113 if (lookup_table) { 2114 gpiod_remove_lookup_table(lookup_table); 2115 kfree(lookup_table); 2116 } 2117 } 2118 2119 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 2120 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 2121 int slotno) 2122 { 2123 struct sdhci_pci_slot *slot; 2124 struct sdhci_host *host; 2125 int ret, bar = first_bar + slotno; 2126 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 2127 2128 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 2129 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 2130 return ERR_PTR(-ENODEV); 2131 } 2132 2133 if (pci_resource_len(pdev, bar) < 0x100) { 2134 dev_err(&pdev->dev, "Invalid iomem size. You may " 2135 "experience problems.\n"); 2136 } 2137 2138 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 2139 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 2140 return ERR_PTR(-ENODEV); 2141 } 2142 2143 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 2144 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 2145 return ERR_PTR(-ENODEV); 2146 } 2147 2148 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 2149 if (IS_ERR(host)) { 2150 dev_err(&pdev->dev, "cannot allocate host\n"); 2151 return ERR_CAST(host); 2152 } 2153 2154 slot = sdhci_priv(host); 2155 2156 slot->chip = chip; 2157 slot->host = host; 2158 slot->cd_idx = -1; 2159 2160 host->hw_name = "PCI"; 2161 host->ops = chip->fixes && chip->fixes->ops ? 2162 chip->fixes->ops : 2163 &sdhci_pci_ops; 2164 host->quirks = chip->quirks; 2165 host->quirks2 = chip->quirks2; 2166 2167 host->irq = pdev->irq; 2168 2169 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 2170 if (ret) { 2171 dev_err(&pdev->dev, "cannot request region\n"); 2172 goto cleanup; 2173 } 2174 2175 host->ioaddr = pcim_iomap_table(pdev)[bar]; 2176 2177 if (chip->fixes && chip->fixes->probe_slot) { 2178 ret = chip->fixes->probe_slot(slot); 2179 if (ret) 2180 goto cleanup; 2181 } 2182 2183 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 2184 host->mmc->slotno = slotno; 2185 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 2186 2187 if (device_can_wakeup(&pdev->dev)) 2188 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 2189 2190 if (host->mmc->caps & MMC_CAP_CD_WAKE) 2191 device_init_wakeup(&pdev->dev, true); 2192 2193 if (slot->cd_idx >= 0) { 2194 struct gpiod_lookup_table *cd_gpio_lookup_table; 2195 2196 cd_gpio_lookup_table = sdhci_pci_add_gpio_lookup_table(chip); 2197 if (IS_ERR(cd_gpio_lookup_table)) { 2198 ret = PTR_ERR(cd_gpio_lookup_table); 2199 goto remove; 2200 } 2201 2202 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 2203 slot->cd_override_level, 0); 2204 2205 sdhci_pci_remove_gpio_lookup_table(cd_gpio_lookup_table); 2206 2207 if (ret && ret != -EPROBE_DEFER) 2208 ret = mmc_gpiod_request_cd(host->mmc, NULL, 2209 slot->cd_idx, 2210 slot->cd_override_level, 2211 0); 2212 if (ret == -EPROBE_DEFER) 2213 goto remove; 2214 2215 if (ret) { 2216 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2217 slot->cd_idx = -1; 2218 } 2219 } 2220 2221 if (chip->fixes && chip->fixes->add_host) 2222 ret = chip->fixes->add_host(slot); 2223 else 2224 ret = sdhci_add_host(host); 2225 if (ret) 2226 goto remove; 2227 2228 /* 2229 * Check if the chip needs a separate GPIO for card detect to wake up 2230 * from runtime suspend. If it is not there, don't allow runtime PM. 2231 */ 2232 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && slot->cd_idx < 0) 2233 chip->allow_runtime_pm = false; 2234 2235 return slot; 2236 2237 remove: 2238 if (chip->fixes && chip->fixes->remove_slot) 2239 chip->fixes->remove_slot(slot, 0); 2240 2241 cleanup: 2242 sdhci_free_host(host); 2243 2244 return ERR_PTR(ret); 2245 } 2246 2247 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2248 { 2249 int dead; 2250 u32 scratch; 2251 2252 dead = 0; 2253 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2254 if (scratch == (u32)-1) 2255 dead = 1; 2256 2257 if (slot->chip->fixes && slot->chip->fixes->remove_host) 2258 slot->chip->fixes->remove_host(slot, dead); 2259 else 2260 sdhci_remove_host(slot->host, dead); 2261 2262 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2263 slot->chip->fixes->remove_slot(slot, dead); 2264 2265 sdhci_free_host(slot->host); 2266 } 2267 2268 int sdhci_pci_uhs2_add_host(struct sdhci_pci_slot *slot) 2269 { 2270 return sdhci_uhs2_add_host(slot->host); 2271 } 2272 2273 void sdhci_pci_uhs2_remove_host(struct sdhci_pci_slot *slot, int dead) 2274 { 2275 sdhci_uhs2_remove_host(slot->host, dead); 2276 } 2277 2278 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2279 { 2280 pm_suspend_ignore_children(dev, 1); 2281 pm_runtime_set_autosuspend_delay(dev, 50); 2282 pm_runtime_use_autosuspend(dev); 2283 pm_runtime_allow(dev); 2284 /* Stay active until mmc core scans for a card */ 2285 pm_runtime_put_noidle(dev); 2286 } 2287 2288 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2289 { 2290 pm_runtime_forbid(dev); 2291 pm_runtime_get_noresume(dev); 2292 } 2293 2294 static int sdhci_pci_probe(struct pci_dev *pdev, 2295 const struct pci_device_id *ent) 2296 { 2297 struct sdhci_pci_chip *chip; 2298 struct sdhci_pci_slot *slot; 2299 2300 u8 slots, first_bar; 2301 int ret, i; 2302 2303 BUG_ON(pdev == NULL); 2304 BUG_ON(ent == NULL); 2305 2306 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2307 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2308 2309 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2310 if (ret) 2311 return pcibios_err_to_errno(ret); 2312 2313 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2314 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2315 2316 BUG_ON(slots > MAX_SLOTS); 2317 2318 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2319 if (ret) 2320 return pcibios_err_to_errno(ret); 2321 2322 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2323 2324 if (first_bar > 5) { 2325 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2326 return -ENODEV; 2327 } 2328 2329 ret = pcim_enable_device(pdev); 2330 if (ret) 2331 return ret; 2332 2333 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2334 if (!chip) 2335 return -ENOMEM; 2336 2337 chip->pdev = pdev; 2338 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2339 if (chip->fixes) { 2340 chip->quirks = chip->fixes->quirks; 2341 chip->quirks2 = chip->fixes->quirks2; 2342 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2343 } 2344 chip->num_slots = slots; 2345 chip->pm_retune = true; 2346 chip->rpm_retune = true; 2347 2348 pci_set_drvdata(pdev, chip); 2349 2350 if (chip->fixes && chip->fixes->probe) { 2351 ret = chip->fixes->probe(chip); 2352 if (ret) 2353 return ret; 2354 } 2355 2356 slots = chip->num_slots; /* Quirk may have changed this */ 2357 2358 for (i = 0; i < slots; i++) { 2359 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2360 if (IS_ERR(slot)) { 2361 for (i--; i >= 0; i--) 2362 sdhci_pci_remove_slot(chip->slots[i]); 2363 return PTR_ERR(slot); 2364 } 2365 2366 chip->slots[i] = slot; 2367 } 2368 2369 if (chip->allow_runtime_pm) 2370 sdhci_pci_runtime_pm_allow(&pdev->dev); 2371 2372 return 0; 2373 } 2374 2375 static void sdhci_pci_remove(struct pci_dev *pdev) 2376 { 2377 int i; 2378 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2379 2380 if (chip->allow_runtime_pm) 2381 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2382 2383 for (i = 0; i < chip->num_slots; i++) 2384 sdhci_pci_remove_slot(chip->slots[i]); 2385 } 2386 2387 static struct pci_driver sdhci_driver = { 2388 .name = "sdhci-pci", 2389 .id_table = pci_ids, 2390 .probe = sdhci_pci_probe, 2391 .remove = sdhci_pci_remove, 2392 .driver = { 2393 .pm = &sdhci_pci_pm_ops, 2394 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2395 }, 2396 }; 2397 2398 module_pci_driver(sdhci_driver); 2399 2400 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2401 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2402 MODULE_LICENSE("GPL"); 2403