1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* linux/drivers/mmc/host/sdhci-pci.c - SDHCI on PCI bus interface 3 * 4 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. 5 * 6 * Thanks to the following companies for their support: 7 * 8 * - JMicron (hardware and technical support) 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/string.h> 13 #include <linux/delay.h> 14 #include <linux/highmem.h> 15 #include <linux/module.h> 16 #include <linux/pci.h> 17 #include <linux/dma-mapping.h> 18 #include <linux/slab.h> 19 #include <linux/device.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/scatterlist.h> 23 #include <linux/io.h> 24 #include <linux/iopoll.h> 25 #include <linux/gpio.h> 26 #include <linux/pm_runtime.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/mmc/sdhci-pci-data.h> 29 #include <linux/acpi.h> 30 #include <linux/dmi.h> 31 32 #ifdef CONFIG_X86 33 #include <asm/iosf_mbi.h> 34 #endif 35 36 #include "cqhci.h" 37 38 #include "sdhci.h" 39 #include "sdhci-pci.h" 40 41 static void sdhci_pci_hw_reset(struct sdhci_host *host); 42 43 #ifdef CONFIG_PM_SLEEP 44 static int sdhci_pci_init_wakeup(struct sdhci_pci_chip *chip) 45 { 46 mmc_pm_flag_t pm_flags = 0; 47 bool cap_cd_wake = false; 48 int i; 49 50 for (i = 0; i < chip->num_slots; i++) { 51 struct sdhci_pci_slot *slot = chip->slots[i]; 52 53 if (slot) { 54 pm_flags |= slot->host->mmc->pm_flags; 55 if (slot->host->mmc->caps & MMC_CAP_CD_WAKE) 56 cap_cd_wake = true; 57 } 58 } 59 60 if ((pm_flags & MMC_PM_KEEP_POWER) && (pm_flags & MMC_PM_WAKE_SDIO_IRQ)) 61 return device_wakeup_enable(&chip->pdev->dev); 62 else if (!cap_cd_wake) 63 return device_wakeup_disable(&chip->pdev->dev); 64 65 return 0; 66 } 67 68 static int sdhci_pci_suspend_host(struct sdhci_pci_chip *chip) 69 { 70 int i, ret; 71 72 sdhci_pci_init_wakeup(chip); 73 74 for (i = 0; i < chip->num_slots; i++) { 75 struct sdhci_pci_slot *slot = chip->slots[i]; 76 struct sdhci_host *host; 77 78 if (!slot) 79 continue; 80 81 host = slot->host; 82 83 if (chip->pm_retune && host->tuning_mode != SDHCI_TUNING_MODE_3) 84 mmc_retune_needed(host->mmc); 85 86 ret = sdhci_suspend_host(host); 87 if (ret) 88 goto err_pci_suspend; 89 90 if (device_may_wakeup(&chip->pdev->dev)) 91 mmc_gpio_set_cd_wake(host->mmc, true); 92 } 93 94 return 0; 95 96 err_pci_suspend: 97 while (--i >= 0) 98 sdhci_resume_host(chip->slots[i]->host); 99 return ret; 100 } 101 102 int sdhci_pci_resume_host(struct sdhci_pci_chip *chip) 103 { 104 struct sdhci_pci_slot *slot; 105 int i, ret; 106 107 for (i = 0; i < chip->num_slots; i++) { 108 slot = chip->slots[i]; 109 if (!slot) 110 continue; 111 112 ret = sdhci_resume_host(slot->host); 113 if (ret) 114 return ret; 115 116 mmc_gpio_set_cd_wake(slot->host->mmc, false); 117 } 118 119 return 0; 120 } 121 122 static int sdhci_cqhci_suspend(struct sdhci_pci_chip *chip) 123 { 124 int ret; 125 126 ret = cqhci_suspend(chip->slots[0]->host->mmc); 127 if (ret) 128 return ret; 129 130 return sdhci_pci_suspend_host(chip); 131 } 132 133 static int sdhci_cqhci_resume(struct sdhci_pci_chip *chip) 134 { 135 int ret; 136 137 ret = sdhci_pci_resume_host(chip); 138 if (ret) 139 return ret; 140 141 return cqhci_resume(chip->slots[0]->host->mmc); 142 } 143 #endif 144 145 #ifdef CONFIG_PM 146 static int sdhci_pci_runtime_suspend_host(struct sdhci_pci_chip *chip) 147 { 148 struct sdhci_pci_slot *slot; 149 struct sdhci_host *host; 150 int i, ret; 151 152 for (i = 0; i < chip->num_slots; i++) { 153 slot = chip->slots[i]; 154 if (!slot) 155 continue; 156 157 host = slot->host; 158 159 ret = sdhci_runtime_suspend_host(host); 160 if (ret) 161 goto err_pci_runtime_suspend; 162 163 if (chip->rpm_retune && 164 host->tuning_mode != SDHCI_TUNING_MODE_3) 165 mmc_retune_needed(host->mmc); 166 } 167 168 return 0; 169 170 err_pci_runtime_suspend: 171 while (--i >= 0) 172 sdhci_runtime_resume_host(chip->slots[i]->host, 0); 173 return ret; 174 } 175 176 static int sdhci_pci_runtime_resume_host(struct sdhci_pci_chip *chip) 177 { 178 struct sdhci_pci_slot *slot; 179 int i, ret; 180 181 for (i = 0; i < chip->num_slots; i++) { 182 slot = chip->slots[i]; 183 if (!slot) 184 continue; 185 186 ret = sdhci_runtime_resume_host(slot->host, 0); 187 if (ret) 188 return ret; 189 } 190 191 return 0; 192 } 193 194 static int sdhci_cqhci_runtime_suspend(struct sdhci_pci_chip *chip) 195 { 196 int ret; 197 198 ret = cqhci_suspend(chip->slots[0]->host->mmc); 199 if (ret) 200 return ret; 201 202 return sdhci_pci_runtime_suspend_host(chip); 203 } 204 205 static int sdhci_cqhci_runtime_resume(struct sdhci_pci_chip *chip) 206 { 207 int ret; 208 209 ret = sdhci_pci_runtime_resume_host(chip); 210 if (ret) 211 return ret; 212 213 return cqhci_resume(chip->slots[0]->host->mmc); 214 } 215 #endif 216 217 static u32 sdhci_cqhci_irq(struct sdhci_host *host, u32 intmask) 218 { 219 int cmd_error = 0; 220 int data_error = 0; 221 222 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 223 return intmask; 224 225 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 226 227 return 0; 228 } 229 230 static void sdhci_pci_dumpregs(struct mmc_host *mmc) 231 { 232 sdhci_dumpregs(mmc_priv(mmc)); 233 } 234 235 /*****************************************************************************\ 236 * * 237 * Hardware specific quirk handling * 238 * * 239 \*****************************************************************************/ 240 241 static int ricoh_probe(struct sdhci_pci_chip *chip) 242 { 243 if (chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG || 244 chip->pdev->subsystem_vendor == PCI_VENDOR_ID_SONY) 245 chip->quirks |= SDHCI_QUIRK_NO_CARD_NO_RESET; 246 return 0; 247 } 248 249 static int ricoh_mmc_probe_slot(struct sdhci_pci_slot *slot) 250 { 251 slot->host->caps = 252 FIELD_PREP(SDHCI_TIMEOUT_CLK_MASK, 0x21) | 253 FIELD_PREP(SDHCI_CLOCK_BASE_MASK, 0x21) | 254 SDHCI_TIMEOUT_CLK_UNIT | 255 SDHCI_CAN_VDD_330 | 256 SDHCI_CAN_DO_HISPD | 257 SDHCI_CAN_DO_SDMA; 258 return 0; 259 } 260 261 #ifdef CONFIG_PM_SLEEP 262 static int ricoh_mmc_resume(struct sdhci_pci_chip *chip) 263 { 264 /* Apply a delay to allow controller to settle */ 265 /* Otherwise it becomes confused if card state changed 266 during suspend */ 267 msleep(500); 268 return sdhci_pci_resume_host(chip); 269 } 270 #endif 271 272 static const struct sdhci_pci_fixes sdhci_ricoh = { 273 .probe = ricoh_probe, 274 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 275 SDHCI_QUIRK_FORCE_DMA | 276 SDHCI_QUIRK_CLOCK_BEFORE_RESET, 277 }; 278 279 static const struct sdhci_pci_fixes sdhci_ricoh_mmc = { 280 .probe_slot = ricoh_mmc_probe_slot, 281 #ifdef CONFIG_PM_SLEEP 282 .resume = ricoh_mmc_resume, 283 #endif 284 .quirks = SDHCI_QUIRK_32BIT_DMA_ADDR | 285 SDHCI_QUIRK_CLOCK_BEFORE_RESET | 286 SDHCI_QUIRK_NO_CARD_NO_RESET | 287 SDHCI_QUIRK_MISSING_CAPS 288 }; 289 290 static const struct sdhci_pci_fixes sdhci_ene_712 = { 291 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 292 SDHCI_QUIRK_BROKEN_DMA, 293 }; 294 295 static const struct sdhci_pci_fixes sdhci_ene_714 = { 296 .quirks = SDHCI_QUIRK_SINGLE_POWER_WRITE | 297 SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS | 298 SDHCI_QUIRK_BROKEN_DMA, 299 }; 300 301 static const struct sdhci_pci_fixes sdhci_cafe = { 302 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER | 303 SDHCI_QUIRK_NO_BUSY_IRQ | 304 SDHCI_QUIRK_BROKEN_CARD_DETECTION | 305 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 306 }; 307 308 static const struct sdhci_pci_fixes sdhci_intel_qrk = { 309 .quirks = SDHCI_QUIRK_NO_HISPD_BIT, 310 }; 311 312 static int mrst_hc_probe_slot(struct sdhci_pci_slot *slot) 313 { 314 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 315 return 0; 316 } 317 318 /* 319 * ADMA operation is disabled for Moorestown platform due to 320 * hardware bugs. 321 */ 322 static int mrst_hc_probe(struct sdhci_pci_chip *chip) 323 { 324 /* 325 * slots number is fixed here for MRST as SDIO3/5 are never used and 326 * have hardware bugs. 327 */ 328 chip->num_slots = 1; 329 return 0; 330 } 331 332 static int pch_hc_probe_slot(struct sdhci_pci_slot *slot) 333 { 334 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA; 335 return 0; 336 } 337 338 #ifdef CONFIG_PM 339 340 static irqreturn_t sdhci_pci_sd_cd(int irq, void *dev_id) 341 { 342 struct sdhci_pci_slot *slot = dev_id; 343 struct sdhci_host *host = slot->host; 344 345 mmc_detect_change(host->mmc, msecs_to_jiffies(200)); 346 return IRQ_HANDLED; 347 } 348 349 static void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 350 { 351 int err, irq, gpio = slot->cd_gpio; 352 353 slot->cd_gpio = -EINVAL; 354 slot->cd_irq = -EINVAL; 355 356 if (!gpio_is_valid(gpio)) 357 return; 358 359 err = devm_gpio_request(&slot->chip->pdev->dev, gpio, "sd_cd"); 360 if (err < 0) 361 goto out; 362 363 err = gpio_direction_input(gpio); 364 if (err < 0) 365 goto out_free; 366 367 irq = gpio_to_irq(gpio); 368 if (irq < 0) 369 goto out_free; 370 371 err = request_irq(irq, sdhci_pci_sd_cd, IRQF_TRIGGER_RISING | 372 IRQF_TRIGGER_FALLING, "sd_cd", slot); 373 if (err) 374 goto out_free; 375 376 slot->cd_gpio = gpio; 377 slot->cd_irq = irq; 378 379 return; 380 381 out_free: 382 devm_gpio_free(&slot->chip->pdev->dev, gpio); 383 out: 384 dev_warn(&slot->chip->pdev->dev, "failed to setup card detect wake up\n"); 385 } 386 387 static void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 388 { 389 if (slot->cd_irq >= 0) 390 free_irq(slot->cd_irq, slot); 391 } 392 393 #else 394 395 static inline void sdhci_pci_add_own_cd(struct sdhci_pci_slot *slot) 396 { 397 } 398 399 static inline void sdhci_pci_remove_own_cd(struct sdhci_pci_slot *slot) 400 { 401 } 402 403 #endif 404 405 static int mfd_emmc_probe_slot(struct sdhci_pci_slot *slot) 406 { 407 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE; 408 slot->host->mmc->caps2 |= MMC_CAP2_BOOTPART_NOACC; 409 return 0; 410 } 411 412 static int mfd_sdio_probe_slot(struct sdhci_pci_slot *slot) 413 { 414 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE; 415 return 0; 416 } 417 418 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc0 = { 419 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 420 .probe_slot = mrst_hc_probe_slot, 421 }; 422 423 static const struct sdhci_pci_fixes sdhci_intel_mrst_hc1_hc2 = { 424 .quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_NO_HISPD_BIT, 425 .probe = mrst_hc_probe, 426 }; 427 428 static const struct sdhci_pci_fixes sdhci_intel_mfd_sd = { 429 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 430 .allow_runtime_pm = true, 431 .own_cd_for_runtime_pm = true, 432 }; 433 434 static const struct sdhci_pci_fixes sdhci_intel_mfd_sdio = { 435 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 436 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON, 437 .allow_runtime_pm = true, 438 .probe_slot = mfd_sdio_probe_slot, 439 }; 440 441 static const struct sdhci_pci_fixes sdhci_intel_mfd_emmc = { 442 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 443 .allow_runtime_pm = true, 444 .probe_slot = mfd_emmc_probe_slot, 445 }; 446 447 static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = { 448 .quirks = SDHCI_QUIRK_BROKEN_ADMA, 449 .probe_slot = pch_hc_probe_slot, 450 }; 451 452 #ifdef CONFIG_X86 453 454 #define BYT_IOSF_SCCEP 0x63 455 #define BYT_IOSF_OCP_NETCTRL0 0x1078 456 #define BYT_IOSF_OCP_TIMEOUT_BASE GENMASK(10, 8) 457 458 static void byt_ocp_setting(struct pci_dev *pdev) 459 { 460 u32 val = 0; 461 462 if (pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC && 463 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SDIO && 464 pdev->device != PCI_DEVICE_ID_INTEL_BYT_SD && 465 pdev->device != PCI_DEVICE_ID_INTEL_BYT_EMMC2) 466 return; 467 468 if (iosf_mbi_read(BYT_IOSF_SCCEP, MBI_CR_READ, BYT_IOSF_OCP_NETCTRL0, 469 &val)) { 470 dev_err(&pdev->dev, "%s read error\n", __func__); 471 return; 472 } 473 474 if (!(val & BYT_IOSF_OCP_TIMEOUT_BASE)) 475 return; 476 477 val &= ~BYT_IOSF_OCP_TIMEOUT_BASE; 478 479 if (iosf_mbi_write(BYT_IOSF_SCCEP, MBI_CR_WRITE, BYT_IOSF_OCP_NETCTRL0, 480 val)) { 481 dev_err(&pdev->dev, "%s write error\n", __func__); 482 return; 483 } 484 485 dev_dbg(&pdev->dev, "%s completed\n", __func__); 486 } 487 488 #else 489 490 static inline void byt_ocp_setting(struct pci_dev *pdev) 491 { 492 } 493 494 #endif 495 496 enum { 497 INTEL_DSM_FNS = 0, 498 INTEL_DSM_V18_SWITCH = 3, 499 INTEL_DSM_V33_SWITCH = 4, 500 INTEL_DSM_DRV_STRENGTH = 9, 501 INTEL_DSM_D3_RETUNE = 10, 502 }; 503 504 struct intel_host { 505 u32 dsm_fns; 506 int drv_strength; 507 bool d3_retune; 508 bool rpm_retune_ok; 509 u32 glk_rx_ctrl1; 510 u32 glk_tun_val; 511 }; 512 513 static const guid_t intel_dsm_guid = 514 GUID_INIT(0xF6C13EA5, 0x65CD, 0x461F, 515 0xAB, 0x7A, 0x29, 0xF7, 0xE8, 0xD5, 0xBD, 0x61); 516 517 static int __intel_dsm(struct intel_host *intel_host, struct device *dev, 518 unsigned int fn, u32 *result) 519 { 520 union acpi_object *obj; 521 int err = 0; 522 size_t len; 523 524 obj = acpi_evaluate_dsm(ACPI_HANDLE(dev), &intel_dsm_guid, 0, fn, NULL); 525 if (!obj) 526 return -EOPNOTSUPP; 527 528 if (obj->type != ACPI_TYPE_BUFFER || obj->buffer.length < 1) { 529 err = -EINVAL; 530 goto out; 531 } 532 533 len = min_t(size_t, obj->buffer.length, 4); 534 535 *result = 0; 536 memcpy(result, obj->buffer.pointer, len); 537 out: 538 ACPI_FREE(obj); 539 540 return err; 541 } 542 543 static int intel_dsm(struct intel_host *intel_host, struct device *dev, 544 unsigned int fn, u32 *result) 545 { 546 if (fn > 31 || !(intel_host->dsm_fns & (1 << fn))) 547 return -EOPNOTSUPP; 548 549 return __intel_dsm(intel_host, dev, fn, result); 550 } 551 552 static void intel_dsm_init(struct intel_host *intel_host, struct device *dev, 553 struct mmc_host *mmc) 554 { 555 int err; 556 u32 val; 557 558 intel_host->d3_retune = true; 559 560 err = __intel_dsm(intel_host, dev, INTEL_DSM_FNS, &intel_host->dsm_fns); 561 if (err) { 562 pr_debug("%s: DSM not supported, error %d\n", 563 mmc_hostname(mmc), err); 564 return; 565 } 566 567 pr_debug("%s: DSM function mask %#x\n", 568 mmc_hostname(mmc), intel_host->dsm_fns); 569 570 err = intel_dsm(intel_host, dev, INTEL_DSM_DRV_STRENGTH, &val); 571 intel_host->drv_strength = err ? 0 : val; 572 573 err = intel_dsm(intel_host, dev, INTEL_DSM_D3_RETUNE, &val); 574 intel_host->d3_retune = err ? true : !!val; 575 } 576 577 static void sdhci_pci_int_hw_reset(struct sdhci_host *host) 578 { 579 u8 reg; 580 581 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 582 reg |= 0x10; 583 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 584 /* For eMMC, minimum is 1us but give it 9us for good measure */ 585 udelay(9); 586 reg &= ~0x10; 587 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 588 /* For eMMC, minimum is 200us but give it 300us for good measure */ 589 usleep_range(300, 1000); 590 } 591 592 static int intel_select_drive_strength(struct mmc_card *card, 593 unsigned int max_dtr, int host_drv, 594 int card_drv, int *drv_type) 595 { 596 struct sdhci_host *host = mmc_priv(card->host); 597 struct sdhci_pci_slot *slot = sdhci_priv(host); 598 struct intel_host *intel_host = sdhci_pci_priv(slot); 599 600 if (!(mmc_driver_type_mask(intel_host->drv_strength) & card_drv)) 601 return 0; 602 603 return intel_host->drv_strength; 604 } 605 606 static int bxt_get_cd(struct mmc_host *mmc) 607 { 608 int gpio_cd = mmc_gpio_get_cd(mmc); 609 struct sdhci_host *host = mmc_priv(mmc); 610 unsigned long flags; 611 int ret = 0; 612 613 if (!gpio_cd) 614 return 0; 615 616 spin_lock_irqsave(&host->lock, flags); 617 618 if (host->flags & SDHCI_DEVICE_DEAD) 619 goto out; 620 621 ret = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); 622 out: 623 spin_unlock_irqrestore(&host->lock, flags); 624 625 return ret; 626 } 627 628 #define SDHCI_INTEL_PWR_TIMEOUT_CNT 20 629 #define SDHCI_INTEL_PWR_TIMEOUT_UDELAY 100 630 631 static void sdhci_intel_set_power(struct sdhci_host *host, unsigned char mode, 632 unsigned short vdd) 633 { 634 int cntr; 635 u8 reg; 636 637 sdhci_set_power(host, mode, vdd); 638 639 if (mode == MMC_POWER_OFF) 640 return; 641 642 /* 643 * Bus power might not enable after D3 -> D0 transition due to the 644 * present state not yet having propagated. Retry for up to 2ms. 645 */ 646 for (cntr = 0; cntr < SDHCI_INTEL_PWR_TIMEOUT_CNT; cntr++) { 647 reg = sdhci_readb(host, SDHCI_POWER_CONTROL); 648 if (reg & SDHCI_POWER_ON) 649 break; 650 udelay(SDHCI_INTEL_PWR_TIMEOUT_UDELAY); 651 reg |= SDHCI_POWER_ON; 652 sdhci_writeb(host, reg, SDHCI_POWER_CONTROL); 653 } 654 } 655 656 #define INTEL_HS400_ES_REG 0x78 657 #define INTEL_HS400_ES_BIT BIT(0) 658 659 static void intel_hs400_enhanced_strobe(struct mmc_host *mmc, 660 struct mmc_ios *ios) 661 { 662 struct sdhci_host *host = mmc_priv(mmc); 663 u32 val; 664 665 val = sdhci_readl(host, INTEL_HS400_ES_REG); 666 if (ios->enhanced_strobe) 667 val |= INTEL_HS400_ES_BIT; 668 else 669 val &= ~INTEL_HS400_ES_BIT; 670 sdhci_writel(host, val, INTEL_HS400_ES_REG); 671 } 672 673 static int intel_start_signal_voltage_switch(struct mmc_host *mmc, 674 struct mmc_ios *ios) 675 { 676 struct device *dev = mmc_dev(mmc); 677 struct sdhci_host *host = mmc_priv(mmc); 678 struct sdhci_pci_slot *slot = sdhci_priv(host); 679 struct intel_host *intel_host = sdhci_pci_priv(slot); 680 unsigned int fn; 681 u32 result = 0; 682 int err; 683 684 err = sdhci_start_signal_voltage_switch(mmc, ios); 685 if (err) 686 return err; 687 688 switch (ios->signal_voltage) { 689 case MMC_SIGNAL_VOLTAGE_330: 690 fn = INTEL_DSM_V33_SWITCH; 691 break; 692 case MMC_SIGNAL_VOLTAGE_180: 693 fn = INTEL_DSM_V18_SWITCH; 694 break; 695 default: 696 return 0; 697 } 698 699 err = intel_dsm(intel_host, dev, fn, &result); 700 pr_debug("%s: %s DSM fn %u error %d result %u\n", 701 mmc_hostname(mmc), __func__, fn, err, result); 702 703 return 0; 704 } 705 706 static const struct sdhci_ops sdhci_intel_byt_ops = { 707 .set_clock = sdhci_set_clock, 708 .set_power = sdhci_intel_set_power, 709 .enable_dma = sdhci_pci_enable_dma, 710 .set_bus_width = sdhci_set_bus_width, 711 .reset = sdhci_reset, 712 .set_uhs_signaling = sdhci_set_uhs_signaling, 713 .hw_reset = sdhci_pci_hw_reset, 714 }; 715 716 static const struct sdhci_ops sdhci_intel_glk_ops = { 717 .set_clock = sdhci_set_clock, 718 .set_power = sdhci_intel_set_power, 719 .enable_dma = sdhci_pci_enable_dma, 720 .set_bus_width = sdhci_set_bus_width, 721 .reset = sdhci_reset, 722 .set_uhs_signaling = sdhci_set_uhs_signaling, 723 .hw_reset = sdhci_pci_hw_reset, 724 .irq = sdhci_cqhci_irq, 725 }; 726 727 static void byt_read_dsm(struct sdhci_pci_slot *slot) 728 { 729 struct intel_host *intel_host = sdhci_pci_priv(slot); 730 struct device *dev = &slot->chip->pdev->dev; 731 struct mmc_host *mmc = slot->host->mmc; 732 733 intel_dsm_init(intel_host, dev, mmc); 734 slot->chip->rpm_retune = intel_host->d3_retune; 735 } 736 737 static int intel_execute_tuning(struct mmc_host *mmc, u32 opcode) 738 { 739 int err = sdhci_execute_tuning(mmc, opcode); 740 struct sdhci_host *host = mmc_priv(mmc); 741 742 if (err) 743 return err; 744 745 /* 746 * Tuning can leave the IP in an active state (Buffer Read Enable bit 747 * set) which prevents the entry to low power states (i.e. S0i3). Data 748 * reset will clear it. 749 */ 750 sdhci_reset(host, SDHCI_RESET_DATA); 751 752 return 0; 753 } 754 755 static void byt_probe_slot(struct sdhci_pci_slot *slot) 756 { 757 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 758 struct device *dev = &slot->chip->pdev->dev; 759 struct mmc_host *mmc = slot->host->mmc; 760 761 byt_read_dsm(slot); 762 763 byt_ocp_setting(slot->chip->pdev); 764 765 ops->execute_tuning = intel_execute_tuning; 766 ops->start_signal_voltage_switch = intel_start_signal_voltage_switch; 767 768 device_property_read_u32(dev, "max-frequency", &mmc->f_max); 769 } 770 771 static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot) 772 { 773 byt_probe_slot(slot); 774 slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE | 775 MMC_CAP_HW_RESET | MMC_CAP_1_8V_DDR | 776 MMC_CAP_CMD_DURING_TFR | 777 MMC_CAP_WAIT_WHILE_BUSY; 778 slot->hw_reset = sdhci_pci_int_hw_reset; 779 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BSW_EMMC) 780 slot->host->timeout_clk = 1000; /* 1000 kHz i.e. 1 MHz */ 781 slot->host->mmc_host_ops.select_drive_strength = 782 intel_select_drive_strength; 783 return 0; 784 } 785 786 static bool glk_broken_cqhci(struct sdhci_pci_slot *slot) 787 { 788 return slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 789 dmi_match(DMI_BIOS_VENDOR, "LENOVO"); 790 } 791 792 static int glk_emmc_probe_slot(struct sdhci_pci_slot *slot) 793 { 794 int ret = byt_emmc_probe_slot(slot); 795 796 if (!glk_broken_cqhci(slot)) 797 slot->host->mmc->caps2 |= MMC_CAP2_CQE; 798 799 if (slot->chip->pdev->device != PCI_DEVICE_ID_INTEL_GLK_EMMC) { 800 slot->host->mmc->caps2 |= MMC_CAP2_HS400_ES, 801 slot->host->mmc_host_ops.hs400_enhanced_strobe = 802 intel_hs400_enhanced_strobe; 803 slot->host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; 804 } 805 806 return ret; 807 } 808 809 static const struct cqhci_host_ops glk_cqhci_ops = { 810 .enable = sdhci_cqe_enable, 811 .disable = sdhci_cqe_disable, 812 .dumpregs = sdhci_pci_dumpregs, 813 }; 814 815 static int glk_emmc_add_host(struct sdhci_pci_slot *slot) 816 { 817 struct device *dev = &slot->chip->pdev->dev; 818 struct sdhci_host *host = slot->host; 819 struct cqhci_host *cq_host; 820 bool dma64; 821 int ret; 822 823 ret = sdhci_setup_host(host); 824 if (ret) 825 return ret; 826 827 cq_host = devm_kzalloc(dev, sizeof(*cq_host), GFP_KERNEL); 828 if (!cq_host) { 829 ret = -ENOMEM; 830 goto cleanup; 831 } 832 833 cq_host->mmio = host->ioaddr + 0x200; 834 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 835 cq_host->ops = &glk_cqhci_ops; 836 837 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 838 if (dma64) 839 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 840 841 ret = cqhci_init(cq_host, host->mmc, dma64); 842 if (ret) 843 goto cleanup; 844 845 ret = __sdhci_add_host(host); 846 if (ret) 847 goto cleanup; 848 849 return 0; 850 851 cleanup: 852 sdhci_cleanup_host(host); 853 return ret; 854 } 855 856 #ifdef CONFIG_PM 857 #define GLK_RX_CTRL1 0x834 858 #define GLK_TUN_VAL 0x840 859 #define GLK_PATH_PLL GENMASK(13, 8) 860 #define GLK_DLY GENMASK(6, 0) 861 /* Workaround firmware failing to restore the tuning value */ 862 static void glk_rpm_retune_wa(struct sdhci_pci_chip *chip, bool susp) 863 { 864 struct sdhci_pci_slot *slot = chip->slots[0]; 865 struct intel_host *intel_host = sdhci_pci_priv(slot); 866 struct sdhci_host *host = slot->host; 867 u32 glk_rx_ctrl1; 868 u32 glk_tun_val; 869 u32 dly; 870 871 if (intel_host->rpm_retune_ok || !mmc_can_retune(host->mmc)) 872 return; 873 874 glk_rx_ctrl1 = sdhci_readl(host, GLK_RX_CTRL1); 875 glk_tun_val = sdhci_readl(host, GLK_TUN_VAL); 876 877 if (susp) { 878 intel_host->glk_rx_ctrl1 = glk_rx_ctrl1; 879 intel_host->glk_tun_val = glk_tun_val; 880 return; 881 } 882 883 if (!intel_host->glk_tun_val) 884 return; 885 886 if (glk_rx_ctrl1 != intel_host->glk_rx_ctrl1) { 887 intel_host->rpm_retune_ok = true; 888 return; 889 } 890 891 dly = FIELD_PREP(GLK_DLY, FIELD_GET(GLK_PATH_PLL, glk_rx_ctrl1) + 892 (intel_host->glk_tun_val << 1)); 893 if (dly == FIELD_GET(GLK_DLY, glk_rx_ctrl1)) 894 return; 895 896 glk_rx_ctrl1 = (glk_rx_ctrl1 & ~GLK_DLY) | dly; 897 sdhci_writel(host, glk_rx_ctrl1, GLK_RX_CTRL1); 898 899 intel_host->rpm_retune_ok = true; 900 chip->rpm_retune = true; 901 mmc_retune_needed(host->mmc); 902 pr_info("%s: Requiring re-tune after rpm resume", mmc_hostname(host->mmc)); 903 } 904 905 static void glk_rpm_retune_chk(struct sdhci_pci_chip *chip, bool susp) 906 { 907 if (chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_EMMC && 908 !chip->rpm_retune) 909 glk_rpm_retune_wa(chip, susp); 910 } 911 912 static int glk_runtime_suspend(struct sdhci_pci_chip *chip) 913 { 914 glk_rpm_retune_chk(chip, true); 915 916 return sdhci_cqhci_runtime_suspend(chip); 917 } 918 919 static int glk_runtime_resume(struct sdhci_pci_chip *chip) 920 { 921 glk_rpm_retune_chk(chip, false); 922 923 return sdhci_cqhci_runtime_resume(chip); 924 } 925 #endif 926 927 #ifdef CONFIG_ACPI 928 static int ni_set_max_freq(struct sdhci_pci_slot *slot) 929 { 930 acpi_status status; 931 unsigned long long max_freq; 932 933 status = acpi_evaluate_integer(ACPI_HANDLE(&slot->chip->pdev->dev), 934 "MXFQ", NULL, &max_freq); 935 if (ACPI_FAILURE(status)) { 936 dev_err(&slot->chip->pdev->dev, 937 "MXFQ not found in acpi table\n"); 938 return -EINVAL; 939 } 940 941 slot->host->mmc->f_max = max_freq * 1000000; 942 943 return 0; 944 } 945 #else 946 static inline int ni_set_max_freq(struct sdhci_pci_slot *slot) 947 { 948 return 0; 949 } 950 #endif 951 952 static int ni_byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 953 { 954 int err; 955 956 byt_probe_slot(slot); 957 958 err = ni_set_max_freq(slot); 959 if (err) 960 return err; 961 962 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 963 MMC_CAP_WAIT_WHILE_BUSY; 964 return 0; 965 } 966 967 static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot) 968 { 969 byt_probe_slot(slot); 970 slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE | 971 MMC_CAP_WAIT_WHILE_BUSY; 972 return 0; 973 } 974 975 static int byt_sd_probe_slot(struct sdhci_pci_slot *slot) 976 { 977 byt_probe_slot(slot); 978 slot->host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY | 979 MMC_CAP_AGGRESSIVE_PM | MMC_CAP_CD_WAKE; 980 slot->cd_idx = 0; 981 slot->cd_override_level = true; 982 if (slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXT_SD || 983 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_BXTM_SD || 984 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_APL_SD || 985 slot->chip->pdev->device == PCI_DEVICE_ID_INTEL_GLK_SD) 986 slot->host->mmc_host_ops.get_cd = bxt_get_cd; 987 988 if (slot->chip->pdev->subsystem_vendor == PCI_VENDOR_ID_NI && 989 slot->chip->pdev->subsystem_device == PCI_SUBDEVICE_ID_NI_78E3) 990 slot->host->mmc->caps2 |= MMC_CAP2_AVOID_3_3V; 991 992 return 0; 993 } 994 995 #ifdef CONFIG_PM_SLEEP 996 997 static int byt_resume(struct sdhci_pci_chip *chip) 998 { 999 byt_ocp_setting(chip->pdev); 1000 1001 return sdhci_pci_resume_host(chip); 1002 } 1003 1004 #endif 1005 1006 #ifdef CONFIG_PM 1007 1008 static int byt_runtime_resume(struct sdhci_pci_chip *chip) 1009 { 1010 byt_ocp_setting(chip->pdev); 1011 1012 return sdhci_pci_runtime_resume_host(chip); 1013 } 1014 1015 #endif 1016 1017 static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = { 1018 #ifdef CONFIG_PM_SLEEP 1019 .resume = byt_resume, 1020 #endif 1021 #ifdef CONFIG_PM 1022 .runtime_resume = byt_runtime_resume, 1023 #endif 1024 .allow_runtime_pm = true, 1025 .probe_slot = byt_emmc_probe_slot, 1026 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1027 SDHCI_QUIRK_NO_LED, 1028 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1029 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1030 SDHCI_QUIRK2_STOP_WITH_TC, 1031 .ops = &sdhci_intel_byt_ops, 1032 .priv_size = sizeof(struct intel_host), 1033 }; 1034 1035 static const struct sdhci_pci_fixes sdhci_intel_glk_emmc = { 1036 .allow_runtime_pm = true, 1037 .probe_slot = glk_emmc_probe_slot, 1038 .add_host = glk_emmc_add_host, 1039 #ifdef CONFIG_PM_SLEEP 1040 .suspend = sdhci_cqhci_suspend, 1041 .resume = sdhci_cqhci_resume, 1042 #endif 1043 #ifdef CONFIG_PM 1044 .runtime_suspend = glk_runtime_suspend, 1045 .runtime_resume = glk_runtime_resume, 1046 #endif 1047 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1048 SDHCI_QUIRK_NO_LED, 1049 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1050 SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 | 1051 SDHCI_QUIRK2_STOP_WITH_TC, 1052 .ops = &sdhci_intel_glk_ops, 1053 .priv_size = sizeof(struct intel_host), 1054 }; 1055 1056 static const struct sdhci_pci_fixes sdhci_ni_byt_sdio = { 1057 #ifdef CONFIG_PM_SLEEP 1058 .resume = byt_resume, 1059 #endif 1060 #ifdef CONFIG_PM 1061 .runtime_resume = byt_runtime_resume, 1062 #endif 1063 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1064 SDHCI_QUIRK_NO_LED, 1065 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1066 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1067 .allow_runtime_pm = true, 1068 .probe_slot = ni_byt_sdio_probe_slot, 1069 .ops = &sdhci_intel_byt_ops, 1070 .priv_size = sizeof(struct intel_host), 1071 }; 1072 1073 static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = { 1074 #ifdef CONFIG_PM_SLEEP 1075 .resume = byt_resume, 1076 #endif 1077 #ifdef CONFIG_PM 1078 .runtime_resume = byt_runtime_resume, 1079 #endif 1080 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1081 SDHCI_QUIRK_NO_LED, 1082 .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON | 1083 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1084 .allow_runtime_pm = true, 1085 .probe_slot = byt_sdio_probe_slot, 1086 .ops = &sdhci_intel_byt_ops, 1087 .priv_size = sizeof(struct intel_host), 1088 }; 1089 1090 static const struct sdhci_pci_fixes sdhci_intel_byt_sd = { 1091 #ifdef CONFIG_PM_SLEEP 1092 .resume = byt_resume, 1093 #endif 1094 #ifdef CONFIG_PM 1095 .runtime_resume = byt_runtime_resume, 1096 #endif 1097 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC | 1098 SDHCI_QUIRK_NO_LED, 1099 .quirks2 = SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON | 1100 SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1101 SDHCI_QUIRK2_STOP_WITH_TC, 1102 .allow_runtime_pm = true, 1103 .own_cd_for_runtime_pm = true, 1104 .probe_slot = byt_sd_probe_slot, 1105 .ops = &sdhci_intel_byt_ops, 1106 .priv_size = sizeof(struct intel_host), 1107 }; 1108 1109 /* Define Host controllers for Intel Merrifield platform */ 1110 #define INTEL_MRFLD_EMMC_0 0 1111 #define INTEL_MRFLD_EMMC_1 1 1112 #define INTEL_MRFLD_SD 2 1113 #define INTEL_MRFLD_SDIO 3 1114 1115 #ifdef CONFIG_ACPI 1116 static void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) 1117 { 1118 struct acpi_device *device, *child; 1119 1120 device = ACPI_COMPANION(&slot->chip->pdev->dev); 1121 if (!device) 1122 return; 1123 1124 acpi_device_fix_up_power(device); 1125 list_for_each_entry(child, &device->children, node) 1126 if (child->status.present && child->status.enabled) 1127 acpi_device_fix_up_power(child); 1128 } 1129 #else 1130 static inline void intel_mrfld_mmc_fix_up_power_slot(struct sdhci_pci_slot *slot) {} 1131 #endif 1132 1133 static int intel_mrfld_mmc_probe_slot(struct sdhci_pci_slot *slot) 1134 { 1135 unsigned int func = PCI_FUNC(slot->chip->pdev->devfn); 1136 1137 switch (func) { 1138 case INTEL_MRFLD_EMMC_0: 1139 case INTEL_MRFLD_EMMC_1: 1140 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1141 MMC_CAP_8_BIT_DATA | 1142 MMC_CAP_1_8V_DDR; 1143 break; 1144 case INTEL_MRFLD_SD: 1145 slot->host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1146 break; 1147 case INTEL_MRFLD_SDIO: 1148 /* Advertise 2.0v for compatibility with the SDIO card's OCR */ 1149 slot->host->ocr_mask = MMC_VDD_20_21 | MMC_VDD_165_195; 1150 slot->host->mmc->caps |= MMC_CAP_NONREMOVABLE | 1151 MMC_CAP_POWER_OFF_CARD; 1152 break; 1153 default: 1154 return -ENODEV; 1155 } 1156 1157 intel_mrfld_mmc_fix_up_power_slot(slot); 1158 return 0; 1159 } 1160 1161 static const struct sdhci_pci_fixes sdhci_intel_mrfld_mmc = { 1162 .quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 1163 .quirks2 = SDHCI_QUIRK2_BROKEN_HS200 | 1164 SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1165 .allow_runtime_pm = true, 1166 .probe_slot = intel_mrfld_mmc_probe_slot, 1167 }; 1168 1169 static int jmicron_pmos(struct sdhci_pci_chip *chip, int on) 1170 { 1171 u8 scratch; 1172 int ret; 1173 1174 ret = pci_read_config_byte(chip->pdev, 0xAE, &scratch); 1175 if (ret) 1176 return ret; 1177 1178 /* 1179 * Turn PMOS on [bit 0], set over current detection to 2.4 V 1180 * [bit 1:2] and enable over current debouncing [bit 6]. 1181 */ 1182 if (on) 1183 scratch |= 0x47; 1184 else 1185 scratch &= ~0x47; 1186 1187 return pci_write_config_byte(chip->pdev, 0xAE, scratch); 1188 } 1189 1190 static int jmicron_probe(struct sdhci_pci_chip *chip) 1191 { 1192 int ret; 1193 u16 mmcdev = 0; 1194 1195 if (chip->pdev->revision == 0) { 1196 chip->quirks |= SDHCI_QUIRK_32BIT_DMA_ADDR | 1197 SDHCI_QUIRK_32BIT_DMA_SIZE | 1198 SDHCI_QUIRK_32BIT_ADMA_SIZE | 1199 SDHCI_QUIRK_RESET_AFTER_REQUEST | 1200 SDHCI_QUIRK_BROKEN_SMALL_PIO; 1201 } 1202 1203 /* 1204 * JMicron chips can have two interfaces to the same hardware 1205 * in order to work around limitations in Microsoft's driver. 1206 * We need to make sure we only bind to one of them. 1207 * 1208 * This code assumes two things: 1209 * 1210 * 1. The PCI code adds subfunctions in order. 1211 * 1212 * 2. The MMC interface has a lower subfunction number 1213 * than the SD interface. 1214 */ 1215 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_SD) 1216 mmcdev = PCI_DEVICE_ID_JMICRON_JMB38X_MMC; 1217 else if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD) 1218 mmcdev = PCI_DEVICE_ID_JMICRON_JMB388_ESD; 1219 1220 if (mmcdev) { 1221 struct pci_dev *sd_dev; 1222 1223 sd_dev = NULL; 1224 while ((sd_dev = pci_get_device(PCI_VENDOR_ID_JMICRON, 1225 mmcdev, sd_dev)) != NULL) { 1226 if ((PCI_SLOT(chip->pdev->devfn) == 1227 PCI_SLOT(sd_dev->devfn)) && 1228 (chip->pdev->bus == sd_dev->bus)) 1229 break; 1230 } 1231 1232 if (sd_dev) { 1233 pci_dev_put(sd_dev); 1234 dev_info(&chip->pdev->dev, "Refusing to bind to " 1235 "secondary interface.\n"); 1236 return -ENODEV; 1237 } 1238 } 1239 1240 /* 1241 * JMicron chips need a bit of a nudge to enable the power 1242 * output pins. 1243 */ 1244 ret = jmicron_pmos(chip, 1); 1245 if (ret) { 1246 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1247 return ret; 1248 } 1249 1250 /* quirk for unsable RO-detection on JM388 chips */ 1251 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD || 1252 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1253 chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT; 1254 1255 return 0; 1256 } 1257 1258 static void jmicron_enable_mmc(struct sdhci_host *host, int on) 1259 { 1260 u8 scratch; 1261 1262 scratch = readb(host->ioaddr + 0xC0); 1263 1264 if (on) 1265 scratch |= 0x01; 1266 else 1267 scratch &= ~0x01; 1268 1269 writeb(scratch, host->ioaddr + 0xC0); 1270 } 1271 1272 static int jmicron_probe_slot(struct sdhci_pci_slot *slot) 1273 { 1274 if (slot->chip->pdev->revision == 0) { 1275 u16 version; 1276 1277 version = readl(slot->host->ioaddr + SDHCI_HOST_VERSION); 1278 version = (version & SDHCI_VENDOR_VER_MASK) >> 1279 SDHCI_VENDOR_VER_SHIFT; 1280 1281 /* 1282 * Older versions of the chip have lots of nasty glitches 1283 * in the ADMA engine. It's best just to avoid it 1284 * completely. 1285 */ 1286 if (version < 0xAC) 1287 slot->host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1288 } 1289 1290 /* JM388 MMC doesn't support 1.8V while SD supports it */ 1291 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1292 slot->host->ocr_avail_sd = MMC_VDD_32_33 | MMC_VDD_33_34 | 1293 MMC_VDD_29_30 | MMC_VDD_30_31 | 1294 MMC_VDD_165_195; /* allow 1.8V */ 1295 slot->host->ocr_avail_mmc = MMC_VDD_32_33 | MMC_VDD_33_34 | 1296 MMC_VDD_29_30 | MMC_VDD_30_31; /* no 1.8V for MMC */ 1297 } 1298 1299 /* 1300 * The secondary interface requires a bit set to get the 1301 * interrupts. 1302 */ 1303 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1304 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1305 jmicron_enable_mmc(slot->host, 1); 1306 1307 slot->host->mmc->caps |= MMC_CAP_BUS_WIDTH_TEST; 1308 1309 return 0; 1310 } 1311 1312 static void jmicron_remove_slot(struct sdhci_pci_slot *slot, int dead) 1313 { 1314 if (dead) 1315 return; 1316 1317 if (slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1318 slot->chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) 1319 jmicron_enable_mmc(slot->host, 0); 1320 } 1321 1322 #ifdef CONFIG_PM_SLEEP 1323 static int jmicron_suspend(struct sdhci_pci_chip *chip) 1324 { 1325 int i, ret; 1326 1327 ret = sdhci_pci_suspend_host(chip); 1328 if (ret) 1329 return ret; 1330 1331 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1332 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1333 for (i = 0; i < chip->num_slots; i++) 1334 jmicron_enable_mmc(chip->slots[i]->host, 0); 1335 } 1336 1337 return 0; 1338 } 1339 1340 static int jmicron_resume(struct sdhci_pci_chip *chip) 1341 { 1342 int ret, i; 1343 1344 if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC || 1345 chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) { 1346 for (i = 0; i < chip->num_slots; i++) 1347 jmicron_enable_mmc(chip->slots[i]->host, 1); 1348 } 1349 1350 ret = jmicron_pmos(chip, 1); 1351 if (ret) { 1352 dev_err(&chip->pdev->dev, "Failure enabling card power\n"); 1353 return ret; 1354 } 1355 1356 return sdhci_pci_resume_host(chip); 1357 } 1358 #endif 1359 1360 static const struct sdhci_pci_fixes sdhci_jmicron = { 1361 .probe = jmicron_probe, 1362 1363 .probe_slot = jmicron_probe_slot, 1364 .remove_slot = jmicron_remove_slot, 1365 1366 #ifdef CONFIG_PM_SLEEP 1367 .suspend = jmicron_suspend, 1368 .resume = jmicron_resume, 1369 #endif 1370 }; 1371 1372 /* SysKonnect CardBus2SDIO extra registers */ 1373 #define SYSKT_CTRL 0x200 1374 #define SYSKT_RDFIFO_STAT 0x204 1375 #define SYSKT_WRFIFO_STAT 0x208 1376 #define SYSKT_POWER_DATA 0x20c 1377 #define SYSKT_POWER_330 0xef 1378 #define SYSKT_POWER_300 0xf8 1379 #define SYSKT_POWER_184 0xcc 1380 #define SYSKT_POWER_CMD 0x20d 1381 #define SYSKT_POWER_START (1 << 7) 1382 #define SYSKT_POWER_STATUS 0x20e 1383 #define SYSKT_POWER_STATUS_OK (1 << 0) 1384 #define SYSKT_BOARD_REV 0x210 1385 #define SYSKT_CHIP_REV 0x211 1386 #define SYSKT_CONF_DATA 0x212 1387 #define SYSKT_CONF_DATA_1V8 (1 << 2) 1388 #define SYSKT_CONF_DATA_2V5 (1 << 1) 1389 #define SYSKT_CONF_DATA_3V3 (1 << 0) 1390 1391 static int syskt_probe(struct sdhci_pci_chip *chip) 1392 { 1393 if ((chip->pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1394 chip->pdev->class &= ~0x0000FF; 1395 chip->pdev->class |= PCI_SDHCI_IFDMA; 1396 } 1397 return 0; 1398 } 1399 1400 static int syskt_probe_slot(struct sdhci_pci_slot *slot) 1401 { 1402 int tm, ps; 1403 1404 u8 board_rev = readb(slot->host->ioaddr + SYSKT_BOARD_REV); 1405 u8 chip_rev = readb(slot->host->ioaddr + SYSKT_CHIP_REV); 1406 dev_info(&slot->chip->pdev->dev, "SysKonnect CardBus2SDIO, " 1407 "board rev %d.%d, chip rev %d.%d\n", 1408 board_rev >> 4, board_rev & 0xf, 1409 chip_rev >> 4, chip_rev & 0xf); 1410 if (chip_rev >= 0x20) 1411 slot->host->quirks |= SDHCI_QUIRK_FORCE_DMA; 1412 1413 writeb(SYSKT_POWER_330, slot->host->ioaddr + SYSKT_POWER_DATA); 1414 writeb(SYSKT_POWER_START, slot->host->ioaddr + SYSKT_POWER_CMD); 1415 udelay(50); 1416 tm = 10; /* Wait max 1 ms */ 1417 do { 1418 ps = readw(slot->host->ioaddr + SYSKT_POWER_STATUS); 1419 if (ps & SYSKT_POWER_STATUS_OK) 1420 break; 1421 udelay(100); 1422 } while (--tm); 1423 if (!tm) { 1424 dev_err(&slot->chip->pdev->dev, 1425 "power regulator never stabilized"); 1426 writeb(0, slot->host->ioaddr + SYSKT_POWER_CMD); 1427 return -ENODEV; 1428 } 1429 1430 return 0; 1431 } 1432 1433 static const struct sdhci_pci_fixes sdhci_syskt = { 1434 .quirks = SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER, 1435 .probe = syskt_probe, 1436 .probe_slot = syskt_probe_slot, 1437 }; 1438 1439 static int via_probe(struct sdhci_pci_chip *chip) 1440 { 1441 if (chip->pdev->revision == 0x10) 1442 chip->quirks |= SDHCI_QUIRK_DELAY_AFTER_POWER; 1443 1444 return 0; 1445 } 1446 1447 static const struct sdhci_pci_fixes sdhci_via = { 1448 .probe = via_probe, 1449 }; 1450 1451 static int rtsx_probe_slot(struct sdhci_pci_slot *slot) 1452 { 1453 slot->host->mmc->caps2 |= MMC_CAP2_HS200; 1454 return 0; 1455 } 1456 1457 static const struct sdhci_pci_fixes sdhci_rtsx = { 1458 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1459 SDHCI_QUIRK2_BROKEN_64_BIT_DMA | 1460 SDHCI_QUIRK2_BROKEN_DDR50, 1461 .probe_slot = rtsx_probe_slot, 1462 }; 1463 1464 /*AMD chipset generation*/ 1465 enum amd_chipset_gen { 1466 AMD_CHIPSET_BEFORE_ML, 1467 AMD_CHIPSET_CZ, 1468 AMD_CHIPSET_NL, 1469 AMD_CHIPSET_UNKNOWN, 1470 }; 1471 1472 /* AMD registers */ 1473 #define AMD_SD_AUTO_PATTERN 0xB8 1474 #define AMD_MSLEEP_DURATION 4 1475 #define AMD_SD_MISC_CONTROL 0xD0 1476 #define AMD_MAX_TUNE_VALUE 0x0B 1477 #define AMD_AUTO_TUNE_SEL 0x10800 1478 #define AMD_FIFO_PTR 0x30 1479 #define AMD_BIT_MASK 0x1F 1480 1481 static void amd_tuning_reset(struct sdhci_host *host) 1482 { 1483 unsigned int val; 1484 1485 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1486 val |= SDHCI_CTRL_PRESET_VAL_ENABLE | SDHCI_CTRL_EXEC_TUNING; 1487 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1488 1489 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1490 val &= ~SDHCI_CTRL_EXEC_TUNING; 1491 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); 1492 } 1493 1494 static void amd_config_tuning_phase(struct pci_dev *pdev, u8 phase) 1495 { 1496 unsigned int val; 1497 1498 pci_read_config_dword(pdev, AMD_SD_AUTO_PATTERN, &val); 1499 val &= ~AMD_BIT_MASK; 1500 val |= (AMD_AUTO_TUNE_SEL | (phase << 1)); 1501 pci_write_config_dword(pdev, AMD_SD_AUTO_PATTERN, val); 1502 } 1503 1504 static void amd_enable_manual_tuning(struct pci_dev *pdev) 1505 { 1506 unsigned int val; 1507 1508 pci_read_config_dword(pdev, AMD_SD_MISC_CONTROL, &val); 1509 val |= AMD_FIFO_PTR; 1510 pci_write_config_dword(pdev, AMD_SD_MISC_CONTROL, val); 1511 } 1512 1513 static int amd_execute_tuning_hs200(struct sdhci_host *host, u32 opcode) 1514 { 1515 struct sdhci_pci_slot *slot = sdhci_priv(host); 1516 struct pci_dev *pdev = slot->chip->pdev; 1517 u8 valid_win = 0; 1518 u8 valid_win_max = 0; 1519 u8 valid_win_end = 0; 1520 u8 ctrl, tune_around; 1521 1522 amd_tuning_reset(host); 1523 1524 for (tune_around = 0; tune_around < 12; tune_around++) { 1525 amd_config_tuning_phase(pdev, tune_around); 1526 1527 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1528 valid_win = 0; 1529 msleep(AMD_MSLEEP_DURATION); 1530 ctrl = SDHCI_RESET_CMD | SDHCI_RESET_DATA; 1531 sdhci_writeb(host, ctrl, SDHCI_SOFTWARE_RESET); 1532 } else if (++valid_win > valid_win_max) { 1533 valid_win_max = valid_win; 1534 valid_win_end = tune_around; 1535 } 1536 } 1537 1538 if (!valid_win_max) { 1539 dev_err(&pdev->dev, "no tuning point found\n"); 1540 return -EIO; 1541 } 1542 1543 amd_config_tuning_phase(pdev, valid_win_end - valid_win_max / 2); 1544 1545 amd_enable_manual_tuning(pdev); 1546 1547 host->mmc->retune_period = 0; 1548 1549 return 0; 1550 } 1551 1552 static int amd_execute_tuning(struct mmc_host *mmc, u32 opcode) 1553 { 1554 struct sdhci_host *host = mmc_priv(mmc); 1555 1556 /* AMD requires custom HS200 tuning */ 1557 if (host->timing == MMC_TIMING_MMC_HS200) 1558 return amd_execute_tuning_hs200(host, opcode); 1559 1560 /* Otherwise perform standard SDHCI tuning */ 1561 return sdhci_execute_tuning(mmc, opcode); 1562 } 1563 1564 static int amd_probe_slot(struct sdhci_pci_slot *slot) 1565 { 1566 struct mmc_host_ops *ops = &slot->host->mmc_host_ops; 1567 1568 ops->execute_tuning = amd_execute_tuning; 1569 1570 return 0; 1571 } 1572 1573 static int amd_probe(struct sdhci_pci_chip *chip) 1574 { 1575 struct pci_dev *smbus_dev; 1576 enum amd_chipset_gen gen; 1577 1578 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1579 PCI_DEVICE_ID_AMD_HUDSON2_SMBUS, NULL); 1580 if (smbus_dev) { 1581 gen = AMD_CHIPSET_BEFORE_ML; 1582 } else { 1583 smbus_dev = pci_get_device(PCI_VENDOR_ID_AMD, 1584 PCI_DEVICE_ID_AMD_KERNCZ_SMBUS, NULL); 1585 if (smbus_dev) { 1586 if (smbus_dev->revision < 0x51) 1587 gen = AMD_CHIPSET_CZ; 1588 else 1589 gen = AMD_CHIPSET_NL; 1590 } else { 1591 gen = AMD_CHIPSET_UNKNOWN; 1592 } 1593 } 1594 1595 if (gen == AMD_CHIPSET_BEFORE_ML || gen == AMD_CHIPSET_CZ) 1596 chip->quirks2 |= SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD; 1597 1598 return 0; 1599 } 1600 1601 static u32 sdhci_read_present_state(struct sdhci_host *host) 1602 { 1603 return sdhci_readl(host, SDHCI_PRESENT_STATE); 1604 } 1605 1606 static void amd_sdhci_reset(struct sdhci_host *host, u8 mask) 1607 { 1608 struct sdhci_pci_slot *slot = sdhci_priv(host); 1609 struct pci_dev *pdev = slot->chip->pdev; 1610 u32 present_state; 1611 1612 /* 1613 * SDHC 0x7906 requires a hard reset to clear all internal state. 1614 * Otherwise it can get into a bad state where the DATA lines are always 1615 * read as zeros. 1616 */ 1617 if (pdev->device == 0x7906 && (mask & SDHCI_RESET_ALL)) { 1618 pci_clear_master(pdev); 1619 1620 pci_save_state(pdev); 1621 1622 pci_set_power_state(pdev, PCI_D3cold); 1623 pr_debug("%s: power_state=%u\n", mmc_hostname(host->mmc), 1624 pdev->current_state); 1625 pci_set_power_state(pdev, PCI_D0); 1626 1627 pci_restore_state(pdev); 1628 1629 /* 1630 * SDHCI_RESET_ALL says the card detect logic should not be 1631 * reset, but since we need to reset the entire controller 1632 * we should wait until the card detect logic has stabilized. 1633 * 1634 * This normally takes about 40ms. 1635 */ 1636 readx_poll_timeout( 1637 sdhci_read_present_state, 1638 host, 1639 present_state, 1640 present_state & SDHCI_CD_STABLE, 1641 10000, 1642 100000 1643 ); 1644 } 1645 1646 return sdhci_reset(host, mask); 1647 } 1648 1649 static const struct sdhci_ops amd_sdhci_pci_ops = { 1650 .set_clock = sdhci_set_clock, 1651 .enable_dma = sdhci_pci_enable_dma, 1652 .set_bus_width = sdhci_set_bus_width, 1653 .reset = amd_sdhci_reset, 1654 .set_uhs_signaling = sdhci_set_uhs_signaling, 1655 }; 1656 1657 static const struct sdhci_pci_fixes sdhci_amd = { 1658 .probe = amd_probe, 1659 .ops = &amd_sdhci_pci_ops, 1660 .probe_slot = amd_probe_slot, 1661 }; 1662 1663 static const struct pci_device_id pci_ids[] = { 1664 SDHCI_PCI_DEVICE(RICOH, R5C822, ricoh), 1665 SDHCI_PCI_DEVICE(RICOH, R5C843, ricoh_mmc), 1666 SDHCI_PCI_DEVICE(RICOH, R5CE822, ricoh_mmc), 1667 SDHCI_PCI_DEVICE(RICOH, R5CE823, ricoh_mmc), 1668 SDHCI_PCI_DEVICE(ENE, CB712_SD, ene_712), 1669 SDHCI_PCI_DEVICE(ENE, CB712_SD_2, ene_712), 1670 SDHCI_PCI_DEVICE(ENE, CB714_SD, ene_714), 1671 SDHCI_PCI_DEVICE(ENE, CB714_SD_2, ene_714), 1672 SDHCI_PCI_DEVICE(MARVELL, 88ALP01_SD, cafe), 1673 SDHCI_PCI_DEVICE(JMICRON, JMB38X_SD, jmicron), 1674 SDHCI_PCI_DEVICE(JMICRON, JMB38X_MMC, jmicron), 1675 SDHCI_PCI_DEVICE(JMICRON, JMB388_SD, jmicron), 1676 SDHCI_PCI_DEVICE(JMICRON, JMB388_ESD, jmicron), 1677 SDHCI_PCI_DEVICE(SYSKONNECT, 8000, syskt), 1678 SDHCI_PCI_DEVICE(VIA, 95D0, via), 1679 SDHCI_PCI_DEVICE(REALTEK, 5250, rtsx), 1680 SDHCI_PCI_DEVICE(INTEL, QRK_SD, intel_qrk), 1681 SDHCI_PCI_DEVICE(INTEL, MRST_SD0, intel_mrst_hc0), 1682 SDHCI_PCI_DEVICE(INTEL, MRST_SD1, intel_mrst_hc1_hc2), 1683 SDHCI_PCI_DEVICE(INTEL, MRST_SD2, intel_mrst_hc1_hc2), 1684 SDHCI_PCI_DEVICE(INTEL, MFD_SD, intel_mfd_sd), 1685 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO1, intel_mfd_sdio), 1686 SDHCI_PCI_DEVICE(INTEL, MFD_SDIO2, intel_mfd_sdio), 1687 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC0, intel_mfd_emmc), 1688 SDHCI_PCI_DEVICE(INTEL, MFD_EMMC1, intel_mfd_emmc), 1689 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO0, intel_pch_sdio), 1690 SDHCI_PCI_DEVICE(INTEL, PCH_SDIO1, intel_pch_sdio), 1691 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC, intel_byt_emmc), 1692 SDHCI_PCI_SUBDEVICE(INTEL, BYT_SDIO, NI, 7884, ni_byt_sdio), 1693 SDHCI_PCI_DEVICE(INTEL, BYT_SDIO, intel_byt_sdio), 1694 SDHCI_PCI_DEVICE(INTEL, BYT_SD, intel_byt_sd), 1695 SDHCI_PCI_DEVICE(INTEL, BYT_EMMC2, intel_byt_emmc), 1696 SDHCI_PCI_DEVICE(INTEL, BSW_EMMC, intel_byt_emmc), 1697 SDHCI_PCI_DEVICE(INTEL, BSW_SDIO, intel_byt_sdio), 1698 SDHCI_PCI_DEVICE(INTEL, BSW_SD, intel_byt_sd), 1699 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO0, intel_mfd_sd), 1700 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO1, intel_mfd_sdio), 1701 SDHCI_PCI_DEVICE(INTEL, CLV_SDIO2, intel_mfd_sdio), 1702 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC0, intel_mfd_emmc), 1703 SDHCI_PCI_DEVICE(INTEL, CLV_EMMC1, intel_mfd_emmc), 1704 SDHCI_PCI_DEVICE(INTEL, MRFLD_MMC, intel_mrfld_mmc), 1705 SDHCI_PCI_DEVICE(INTEL, SPT_EMMC, intel_byt_emmc), 1706 SDHCI_PCI_DEVICE(INTEL, SPT_SDIO, intel_byt_sdio), 1707 SDHCI_PCI_DEVICE(INTEL, SPT_SD, intel_byt_sd), 1708 SDHCI_PCI_DEVICE(INTEL, DNV_EMMC, intel_byt_emmc), 1709 SDHCI_PCI_DEVICE(INTEL, CDF_EMMC, intel_glk_emmc), 1710 SDHCI_PCI_DEVICE(INTEL, BXT_EMMC, intel_byt_emmc), 1711 SDHCI_PCI_DEVICE(INTEL, BXT_SDIO, intel_byt_sdio), 1712 SDHCI_PCI_DEVICE(INTEL, BXT_SD, intel_byt_sd), 1713 SDHCI_PCI_DEVICE(INTEL, BXTM_EMMC, intel_byt_emmc), 1714 SDHCI_PCI_DEVICE(INTEL, BXTM_SDIO, intel_byt_sdio), 1715 SDHCI_PCI_DEVICE(INTEL, BXTM_SD, intel_byt_sd), 1716 SDHCI_PCI_DEVICE(INTEL, APL_EMMC, intel_byt_emmc), 1717 SDHCI_PCI_DEVICE(INTEL, APL_SDIO, intel_byt_sdio), 1718 SDHCI_PCI_DEVICE(INTEL, APL_SD, intel_byt_sd), 1719 SDHCI_PCI_DEVICE(INTEL, GLK_EMMC, intel_glk_emmc), 1720 SDHCI_PCI_DEVICE(INTEL, GLK_SDIO, intel_byt_sdio), 1721 SDHCI_PCI_DEVICE(INTEL, GLK_SD, intel_byt_sd), 1722 SDHCI_PCI_DEVICE(INTEL, CNP_EMMC, intel_glk_emmc), 1723 SDHCI_PCI_DEVICE(INTEL, CNP_SD, intel_byt_sd), 1724 SDHCI_PCI_DEVICE(INTEL, CNPH_SD, intel_byt_sd), 1725 SDHCI_PCI_DEVICE(INTEL, ICP_EMMC, intel_glk_emmc), 1726 SDHCI_PCI_DEVICE(INTEL, ICP_SD, intel_byt_sd), 1727 SDHCI_PCI_DEVICE(INTEL, EHL_EMMC, intel_glk_emmc), 1728 SDHCI_PCI_DEVICE(INTEL, EHL_SD, intel_byt_sd), 1729 SDHCI_PCI_DEVICE(INTEL, CML_EMMC, intel_glk_emmc), 1730 SDHCI_PCI_DEVICE(INTEL, CML_SD, intel_byt_sd), 1731 SDHCI_PCI_DEVICE(INTEL, CMLH_SD, intel_byt_sd), 1732 SDHCI_PCI_DEVICE(INTEL, JSL_EMMC, intel_glk_emmc), 1733 SDHCI_PCI_DEVICE(INTEL, JSL_SD, intel_byt_sd), 1734 SDHCI_PCI_DEVICE(O2, 8120, o2), 1735 SDHCI_PCI_DEVICE(O2, 8220, o2), 1736 SDHCI_PCI_DEVICE(O2, 8221, o2), 1737 SDHCI_PCI_DEVICE(O2, 8320, o2), 1738 SDHCI_PCI_DEVICE(O2, 8321, o2), 1739 SDHCI_PCI_DEVICE(O2, FUJIN2, o2), 1740 SDHCI_PCI_DEVICE(O2, SDS0, o2), 1741 SDHCI_PCI_DEVICE(O2, SDS1, o2), 1742 SDHCI_PCI_DEVICE(O2, SEABIRD0, o2), 1743 SDHCI_PCI_DEVICE(O2, SEABIRD1, o2), 1744 SDHCI_PCI_DEVICE(ARASAN, PHY_EMMC, arasan), 1745 SDHCI_PCI_DEVICE(SYNOPSYS, DWC_MSHC, snps), 1746 SDHCI_PCI_DEVICE(GLI, 9750, gl9750), 1747 SDHCI_PCI_DEVICE(GLI, 9755, gl9755), 1748 SDHCI_PCI_DEVICE(GLI, 9763E, gl9763e), 1749 SDHCI_PCI_DEVICE_CLASS(AMD, SYSTEM_SDHCI, PCI_CLASS_MASK, amd), 1750 /* Generic SD host controller */ 1751 {PCI_DEVICE_CLASS(SYSTEM_SDHCI, PCI_CLASS_MASK)}, 1752 { /* end: all zeroes */ }, 1753 }; 1754 1755 MODULE_DEVICE_TABLE(pci, pci_ids); 1756 1757 /*****************************************************************************\ 1758 * * 1759 * SDHCI core callbacks * 1760 * * 1761 \*****************************************************************************/ 1762 1763 int sdhci_pci_enable_dma(struct sdhci_host *host) 1764 { 1765 struct sdhci_pci_slot *slot; 1766 struct pci_dev *pdev; 1767 1768 slot = sdhci_priv(host); 1769 pdev = slot->chip->pdev; 1770 1771 if (((pdev->class & 0xFFFF00) == (PCI_CLASS_SYSTEM_SDHCI << 8)) && 1772 ((pdev->class & 0x0000FF) != PCI_SDHCI_IFDMA) && 1773 (host->flags & SDHCI_USE_SDMA)) { 1774 dev_warn(&pdev->dev, "Will use DMA mode even though HW " 1775 "doesn't fully claim to support it.\n"); 1776 } 1777 1778 pci_set_master(pdev); 1779 1780 return 0; 1781 } 1782 1783 static void sdhci_pci_gpio_hw_reset(struct sdhci_host *host) 1784 { 1785 struct sdhci_pci_slot *slot = sdhci_priv(host); 1786 int rst_n_gpio = slot->rst_n_gpio; 1787 1788 if (!gpio_is_valid(rst_n_gpio)) 1789 return; 1790 gpio_set_value_cansleep(rst_n_gpio, 0); 1791 /* For eMMC, minimum is 1us but give it 10us for good measure */ 1792 udelay(10); 1793 gpio_set_value_cansleep(rst_n_gpio, 1); 1794 /* For eMMC, minimum is 200us but give it 300us for good measure */ 1795 usleep_range(300, 1000); 1796 } 1797 1798 static void sdhci_pci_hw_reset(struct sdhci_host *host) 1799 { 1800 struct sdhci_pci_slot *slot = sdhci_priv(host); 1801 1802 if (slot->hw_reset) 1803 slot->hw_reset(host); 1804 } 1805 1806 static const struct sdhci_ops sdhci_pci_ops = { 1807 .set_clock = sdhci_set_clock, 1808 .enable_dma = sdhci_pci_enable_dma, 1809 .set_bus_width = sdhci_set_bus_width, 1810 .reset = sdhci_reset, 1811 .set_uhs_signaling = sdhci_set_uhs_signaling, 1812 .hw_reset = sdhci_pci_hw_reset, 1813 }; 1814 1815 /*****************************************************************************\ 1816 * * 1817 * Suspend/resume * 1818 * * 1819 \*****************************************************************************/ 1820 1821 #ifdef CONFIG_PM_SLEEP 1822 static int sdhci_pci_suspend(struct device *dev) 1823 { 1824 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1825 1826 if (!chip) 1827 return 0; 1828 1829 if (chip->fixes && chip->fixes->suspend) 1830 return chip->fixes->suspend(chip); 1831 1832 return sdhci_pci_suspend_host(chip); 1833 } 1834 1835 static int sdhci_pci_resume(struct device *dev) 1836 { 1837 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1838 1839 if (!chip) 1840 return 0; 1841 1842 if (chip->fixes && chip->fixes->resume) 1843 return chip->fixes->resume(chip); 1844 1845 return sdhci_pci_resume_host(chip); 1846 } 1847 #endif 1848 1849 #ifdef CONFIG_PM 1850 static int sdhci_pci_runtime_suspend(struct device *dev) 1851 { 1852 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1853 1854 if (!chip) 1855 return 0; 1856 1857 if (chip->fixes && chip->fixes->runtime_suspend) 1858 return chip->fixes->runtime_suspend(chip); 1859 1860 return sdhci_pci_runtime_suspend_host(chip); 1861 } 1862 1863 static int sdhci_pci_runtime_resume(struct device *dev) 1864 { 1865 struct sdhci_pci_chip *chip = dev_get_drvdata(dev); 1866 1867 if (!chip) 1868 return 0; 1869 1870 if (chip->fixes && chip->fixes->runtime_resume) 1871 return chip->fixes->runtime_resume(chip); 1872 1873 return sdhci_pci_runtime_resume_host(chip); 1874 } 1875 #endif 1876 1877 static const struct dev_pm_ops sdhci_pci_pm_ops = { 1878 SET_SYSTEM_SLEEP_PM_OPS(sdhci_pci_suspend, sdhci_pci_resume) 1879 SET_RUNTIME_PM_OPS(sdhci_pci_runtime_suspend, 1880 sdhci_pci_runtime_resume, NULL) 1881 }; 1882 1883 /*****************************************************************************\ 1884 * * 1885 * Device probing/removal * 1886 * * 1887 \*****************************************************************************/ 1888 1889 static struct sdhci_pci_slot *sdhci_pci_probe_slot( 1890 struct pci_dev *pdev, struct sdhci_pci_chip *chip, int first_bar, 1891 int slotno) 1892 { 1893 struct sdhci_pci_slot *slot; 1894 struct sdhci_host *host; 1895 int ret, bar = first_bar + slotno; 1896 size_t priv_size = chip->fixes ? chip->fixes->priv_size : 0; 1897 1898 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) { 1899 dev_err(&pdev->dev, "BAR %d is not iomem. Aborting.\n", bar); 1900 return ERR_PTR(-ENODEV); 1901 } 1902 1903 if (pci_resource_len(pdev, bar) < 0x100) { 1904 dev_err(&pdev->dev, "Invalid iomem size. You may " 1905 "experience problems.\n"); 1906 } 1907 1908 if ((pdev->class & 0x0000FF) == PCI_SDHCI_IFVENDOR) { 1909 dev_err(&pdev->dev, "Vendor specific interface. Aborting.\n"); 1910 return ERR_PTR(-ENODEV); 1911 } 1912 1913 if ((pdev->class & 0x0000FF) > PCI_SDHCI_IFVENDOR) { 1914 dev_err(&pdev->dev, "Unknown interface. Aborting.\n"); 1915 return ERR_PTR(-ENODEV); 1916 } 1917 1918 host = sdhci_alloc_host(&pdev->dev, sizeof(*slot) + priv_size); 1919 if (IS_ERR(host)) { 1920 dev_err(&pdev->dev, "cannot allocate host\n"); 1921 return ERR_CAST(host); 1922 } 1923 1924 slot = sdhci_priv(host); 1925 1926 slot->chip = chip; 1927 slot->host = host; 1928 slot->rst_n_gpio = -EINVAL; 1929 slot->cd_gpio = -EINVAL; 1930 slot->cd_idx = -1; 1931 1932 /* Retrieve platform data if there is any */ 1933 if (*sdhci_pci_get_data) 1934 slot->data = sdhci_pci_get_data(pdev, slotno); 1935 1936 if (slot->data) { 1937 if (slot->data->setup) { 1938 ret = slot->data->setup(slot->data); 1939 if (ret) { 1940 dev_err(&pdev->dev, "platform setup failed\n"); 1941 goto free; 1942 } 1943 } 1944 slot->rst_n_gpio = slot->data->rst_n_gpio; 1945 slot->cd_gpio = slot->data->cd_gpio; 1946 } 1947 1948 host->hw_name = "PCI"; 1949 host->ops = chip->fixes && chip->fixes->ops ? 1950 chip->fixes->ops : 1951 &sdhci_pci_ops; 1952 host->quirks = chip->quirks; 1953 host->quirks2 = chip->quirks2; 1954 1955 host->irq = pdev->irq; 1956 1957 ret = pcim_iomap_regions(pdev, BIT(bar), mmc_hostname(host->mmc)); 1958 if (ret) { 1959 dev_err(&pdev->dev, "cannot request region\n"); 1960 goto cleanup; 1961 } 1962 1963 host->ioaddr = pcim_iomap_table(pdev)[bar]; 1964 1965 if (chip->fixes && chip->fixes->probe_slot) { 1966 ret = chip->fixes->probe_slot(slot); 1967 if (ret) 1968 goto cleanup; 1969 } 1970 1971 if (gpio_is_valid(slot->rst_n_gpio)) { 1972 if (!devm_gpio_request(&pdev->dev, slot->rst_n_gpio, "eMMC_reset")) { 1973 gpio_direction_output(slot->rst_n_gpio, 1); 1974 slot->host->mmc->caps |= MMC_CAP_HW_RESET; 1975 slot->hw_reset = sdhci_pci_gpio_hw_reset; 1976 } else { 1977 dev_warn(&pdev->dev, "failed to request rst_n_gpio\n"); 1978 slot->rst_n_gpio = -EINVAL; 1979 } 1980 } 1981 1982 host->mmc->pm_caps = MMC_PM_KEEP_POWER; 1983 host->mmc->slotno = slotno; 1984 host->mmc->caps2 |= MMC_CAP2_NO_PRESCAN_POWERUP; 1985 1986 if (device_can_wakeup(&pdev->dev)) 1987 host->mmc->pm_caps |= MMC_PM_WAKE_SDIO_IRQ; 1988 1989 if (host->mmc->caps & MMC_CAP_CD_WAKE) 1990 device_init_wakeup(&pdev->dev, true); 1991 1992 if (slot->cd_idx >= 0) { 1993 ret = mmc_gpiod_request_cd(host->mmc, "cd", slot->cd_idx, 1994 slot->cd_override_level, 0); 1995 if (ret && ret != -EPROBE_DEFER) 1996 ret = mmc_gpiod_request_cd(host->mmc, NULL, 1997 slot->cd_idx, 1998 slot->cd_override_level, 1999 0); 2000 if (ret == -EPROBE_DEFER) 2001 goto remove; 2002 2003 if (ret) { 2004 dev_warn(&pdev->dev, "failed to setup card detect gpio\n"); 2005 slot->cd_idx = -1; 2006 } 2007 } 2008 2009 if (chip->fixes && chip->fixes->add_host) 2010 ret = chip->fixes->add_host(slot); 2011 else 2012 ret = sdhci_add_host(host); 2013 if (ret) 2014 goto remove; 2015 2016 sdhci_pci_add_own_cd(slot); 2017 2018 /* 2019 * Check if the chip needs a separate GPIO for card detect to wake up 2020 * from runtime suspend. If it is not there, don't allow runtime PM. 2021 * Note sdhci_pci_add_own_cd() sets slot->cd_gpio to -EINVAL on failure. 2022 */ 2023 if (chip->fixes && chip->fixes->own_cd_for_runtime_pm && 2024 !gpio_is_valid(slot->cd_gpio) && slot->cd_idx < 0) 2025 chip->allow_runtime_pm = false; 2026 2027 return slot; 2028 2029 remove: 2030 if (chip->fixes && chip->fixes->remove_slot) 2031 chip->fixes->remove_slot(slot, 0); 2032 2033 cleanup: 2034 if (slot->data && slot->data->cleanup) 2035 slot->data->cleanup(slot->data); 2036 2037 free: 2038 sdhci_free_host(host); 2039 2040 return ERR_PTR(ret); 2041 } 2042 2043 static void sdhci_pci_remove_slot(struct sdhci_pci_slot *slot) 2044 { 2045 int dead; 2046 u32 scratch; 2047 2048 sdhci_pci_remove_own_cd(slot); 2049 2050 dead = 0; 2051 scratch = readl(slot->host->ioaddr + SDHCI_INT_STATUS); 2052 if (scratch == (u32)-1) 2053 dead = 1; 2054 2055 sdhci_remove_host(slot->host, dead); 2056 2057 if (slot->chip->fixes && slot->chip->fixes->remove_slot) 2058 slot->chip->fixes->remove_slot(slot, dead); 2059 2060 if (slot->data && slot->data->cleanup) 2061 slot->data->cleanup(slot->data); 2062 2063 sdhci_free_host(slot->host); 2064 } 2065 2066 static void sdhci_pci_runtime_pm_allow(struct device *dev) 2067 { 2068 pm_suspend_ignore_children(dev, 1); 2069 pm_runtime_set_autosuspend_delay(dev, 50); 2070 pm_runtime_use_autosuspend(dev); 2071 pm_runtime_allow(dev); 2072 /* Stay active until mmc core scans for a card */ 2073 pm_runtime_put_noidle(dev); 2074 } 2075 2076 static void sdhci_pci_runtime_pm_forbid(struct device *dev) 2077 { 2078 pm_runtime_forbid(dev); 2079 pm_runtime_get_noresume(dev); 2080 } 2081 2082 static int sdhci_pci_probe(struct pci_dev *pdev, 2083 const struct pci_device_id *ent) 2084 { 2085 struct sdhci_pci_chip *chip; 2086 struct sdhci_pci_slot *slot; 2087 2088 u8 slots, first_bar; 2089 int ret, i; 2090 2091 BUG_ON(pdev == NULL); 2092 BUG_ON(ent == NULL); 2093 2094 dev_info(&pdev->dev, "SDHCI controller found [%04x:%04x] (rev %x)\n", 2095 (int)pdev->vendor, (int)pdev->device, (int)pdev->revision); 2096 2097 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &slots); 2098 if (ret) 2099 return ret; 2100 2101 slots = PCI_SLOT_INFO_SLOTS(slots) + 1; 2102 dev_dbg(&pdev->dev, "found %d slot(s)\n", slots); 2103 2104 BUG_ON(slots > MAX_SLOTS); 2105 2106 ret = pci_read_config_byte(pdev, PCI_SLOT_INFO, &first_bar); 2107 if (ret) 2108 return ret; 2109 2110 first_bar &= PCI_SLOT_INFO_FIRST_BAR_MASK; 2111 2112 if (first_bar > 5) { 2113 dev_err(&pdev->dev, "Invalid first BAR. Aborting.\n"); 2114 return -ENODEV; 2115 } 2116 2117 ret = pcim_enable_device(pdev); 2118 if (ret) 2119 return ret; 2120 2121 chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL); 2122 if (!chip) 2123 return -ENOMEM; 2124 2125 chip->pdev = pdev; 2126 chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data; 2127 if (chip->fixes) { 2128 chip->quirks = chip->fixes->quirks; 2129 chip->quirks2 = chip->fixes->quirks2; 2130 chip->allow_runtime_pm = chip->fixes->allow_runtime_pm; 2131 } 2132 chip->num_slots = slots; 2133 chip->pm_retune = true; 2134 chip->rpm_retune = true; 2135 2136 pci_set_drvdata(pdev, chip); 2137 2138 if (chip->fixes && chip->fixes->probe) { 2139 ret = chip->fixes->probe(chip); 2140 if (ret) 2141 return ret; 2142 } 2143 2144 slots = chip->num_slots; /* Quirk may have changed this */ 2145 2146 for (i = 0; i < slots; i++) { 2147 slot = sdhci_pci_probe_slot(pdev, chip, first_bar, i); 2148 if (IS_ERR(slot)) { 2149 for (i--; i >= 0; i--) 2150 sdhci_pci_remove_slot(chip->slots[i]); 2151 return PTR_ERR(slot); 2152 } 2153 2154 chip->slots[i] = slot; 2155 } 2156 2157 if (chip->allow_runtime_pm) 2158 sdhci_pci_runtime_pm_allow(&pdev->dev); 2159 2160 return 0; 2161 } 2162 2163 static void sdhci_pci_remove(struct pci_dev *pdev) 2164 { 2165 int i; 2166 struct sdhci_pci_chip *chip = pci_get_drvdata(pdev); 2167 2168 if (chip->allow_runtime_pm) 2169 sdhci_pci_runtime_pm_forbid(&pdev->dev); 2170 2171 for (i = 0; i < chip->num_slots; i++) 2172 sdhci_pci_remove_slot(chip->slots[i]); 2173 } 2174 2175 static struct pci_driver sdhci_driver = { 2176 .name = "sdhci-pci", 2177 .id_table = pci_ids, 2178 .probe = sdhci_pci_probe, 2179 .remove = sdhci_pci_remove, 2180 .driver = { 2181 .pm = &sdhci_pci_pm_ops 2182 }, 2183 }; 2184 2185 module_pci_driver(sdhci_driver); 2186 2187 MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); 2188 MODULE_DESCRIPTION("Secure Digital Host Controller Interface PCI driver"); 2189 MODULE_LICENSE("GPL"); 2190