17657c3a7SAlbert Herranz /* 27657c3a7SAlbert Herranz * Freescale eSDHC controller driver. 37657c3a7SAlbert Herranz * 4f060bc9cSJerry Huang * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 57657c3a7SAlbert Herranz * Copyright (c) 2009 MontaVista Software, Inc. 67657c3a7SAlbert Herranz * 77657c3a7SAlbert Herranz * Authors: Xiaobo Xie <X.Xie@freescale.com> 87657c3a7SAlbert Herranz * Anton Vorontsov <avorontsov@ru.mvista.com> 97657c3a7SAlbert Herranz * 107657c3a7SAlbert Herranz * This program is free software; you can redistribute it and/or modify 117657c3a7SAlbert Herranz * it under the terms of the GNU General Public License as published by 127657c3a7SAlbert Herranz * the Free Software Foundation; either version 2 of the License, or (at 137657c3a7SAlbert Herranz * your option) any later version. 147657c3a7SAlbert Herranz */ 157657c3a7SAlbert Herranz 1666b50a00SOded Gabbay #include <linux/err.h> 177657c3a7SAlbert Herranz #include <linux/io.h> 18f060bc9cSJerry Huang #include <linux/of.h> 197657c3a7SAlbert Herranz #include <linux/delay.h> 2088b47679SPaul Gortmaker #include <linux/module.h> 217657c3a7SAlbert Herranz #include <linux/mmc/host.h> 2238576af1SShawn Guo #include "sdhci-pltfm.h" 2380872e21SWolfram Sang #include "sdhci-esdhc.h" 247657c3a7SAlbert Herranz 25137ccd46SJerry Huang #define VENDOR_V_22 0x12 26a4071fbbSHaijun Zhang #define VENDOR_V_23 0x13 27*f4932cfdSyangbo lu 28*f4932cfdSyangbo lu struct sdhci_esdhc { 29*f4932cfdSyangbo lu u8 vendor_ver; 30*f4932cfdSyangbo lu u8 spec_ver; 31*f4932cfdSyangbo lu }; 32*f4932cfdSyangbo lu 33*f4932cfdSyangbo lu /** 34*f4932cfdSyangbo lu * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 35*f4932cfdSyangbo lu * to make it compatible with SD spec. 36*f4932cfdSyangbo lu * 37*f4932cfdSyangbo lu * @host: pointer to sdhci_host 38*f4932cfdSyangbo lu * @spec_reg: SD spec register address 39*f4932cfdSyangbo lu * @value: 32bit eSDHC register value on spec_reg address 40*f4932cfdSyangbo lu * 41*f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 42*f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 43*f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 44*f4932cfdSyangbo lu * and SD spec. 45*f4932cfdSyangbo lu * 46*f4932cfdSyangbo lu * Return a fixed up register value 47*f4932cfdSyangbo lu */ 48*f4932cfdSyangbo lu static u32 esdhc_readl_fixup(struct sdhci_host *host, 49*f4932cfdSyangbo lu int spec_reg, u32 value) 50137ccd46SJerry Huang { 51*f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 52*f4932cfdSyangbo lu struct sdhci_esdhc *esdhc = pltfm_host->priv; 53137ccd46SJerry Huang u32 ret; 54137ccd46SJerry Huang 55137ccd46SJerry Huang /* 56137ccd46SJerry Huang * The bit of ADMA flag in eSDHC is not compatible with standard 57137ccd46SJerry Huang * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 58137ccd46SJerry Huang * supported by eSDHC. 59137ccd46SJerry Huang * And for many FSL eSDHC controller, the reset value of field 60*f4932cfdSyangbo lu * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 61137ccd46SJerry Huang * only these vendor version is greater than 2.2/0x12 support ADMA. 62137ccd46SJerry Huang */ 63*f4932cfdSyangbo lu if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 64*f4932cfdSyangbo lu if (esdhc->vendor_ver > VENDOR_V_22) { 65*f4932cfdSyangbo lu ret = value | SDHCI_CAN_DO_ADMA2; 66*f4932cfdSyangbo lu return ret; 67137ccd46SJerry Huang } 68*f4932cfdSyangbo lu } 69*f4932cfdSyangbo lu ret = value; 70137ccd46SJerry Huang return ret; 71137ccd46SJerry Huang } 72137ccd46SJerry Huang 73*f4932cfdSyangbo lu static u16 esdhc_readw_fixup(struct sdhci_host *host, 74*f4932cfdSyangbo lu int spec_reg, u32 value) 757657c3a7SAlbert Herranz { 767657c3a7SAlbert Herranz u16 ret; 77*f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 787657c3a7SAlbert Herranz 79*f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_VERSION) 80*f4932cfdSyangbo lu ret = value & 0xffff; 817657c3a7SAlbert Herranz else 82*f4932cfdSyangbo lu ret = (value >> shift) & 0xffff; 83e51cbc9eSXu lei return ret; 84e51cbc9eSXu lei } 85e51cbc9eSXu lei 86*f4932cfdSyangbo lu static u8 esdhc_readb_fixup(struct sdhci_host *host, 87*f4932cfdSyangbo lu int spec_reg, u32 value) 88e51cbc9eSXu lei { 89*f4932cfdSyangbo lu u8 ret; 90*f4932cfdSyangbo lu u8 dma_bits; 91*f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 92*f4932cfdSyangbo lu 93*f4932cfdSyangbo lu ret = (value >> shift) & 0xff; 94ba8c4dc9SRoy Zang 95ba8c4dc9SRoy Zang /* 96ba8c4dc9SRoy Zang * "DMA select" locates at offset 0x28 in SD specification, but on 97ba8c4dc9SRoy Zang * P5020 or P3041, it locates at 0x29. 98ba8c4dc9SRoy Zang */ 99*f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 100ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 101*f4932cfdSyangbo lu dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 102ba8c4dc9SRoy Zang /* fixup the result */ 103ba8c4dc9SRoy Zang ret &= ~SDHCI_CTRL_DMA_MASK; 104ba8c4dc9SRoy Zang ret |= dma_bits; 105ba8c4dc9SRoy Zang } 106*f4932cfdSyangbo lu return ret; 107*f4932cfdSyangbo lu } 108*f4932cfdSyangbo lu 109*f4932cfdSyangbo lu /** 110*f4932cfdSyangbo lu * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 111*f4932cfdSyangbo lu * written into eSDHC register. 112*f4932cfdSyangbo lu * 113*f4932cfdSyangbo lu * @host: pointer to sdhci_host 114*f4932cfdSyangbo lu * @spec_reg: SD spec register address 115*f4932cfdSyangbo lu * @value: 8/16/32bit SD spec register value that would be written 116*f4932cfdSyangbo lu * @old_value: 32bit eSDHC register value on spec_reg address 117*f4932cfdSyangbo lu * 118*f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 119*f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 120*f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 121*f4932cfdSyangbo lu * and SD spec. 122*f4932cfdSyangbo lu * 123*f4932cfdSyangbo lu * Return a fixed up register value 124*f4932cfdSyangbo lu */ 125*f4932cfdSyangbo lu static u32 esdhc_writel_fixup(struct sdhci_host *host, 126*f4932cfdSyangbo lu int spec_reg, u32 value, u32 old_value) 127*f4932cfdSyangbo lu { 128*f4932cfdSyangbo lu u32 ret; 129*f4932cfdSyangbo lu 130*f4932cfdSyangbo lu /* 131*f4932cfdSyangbo lu * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 132*f4932cfdSyangbo lu * when SYSCTL[RSTD] is set for some special operations. 133*f4932cfdSyangbo lu * No any impact on other operation. 134*f4932cfdSyangbo lu */ 135*f4932cfdSyangbo lu if (spec_reg == SDHCI_INT_ENABLE) 136*f4932cfdSyangbo lu ret = value | SDHCI_INT_BLK_GAP; 137*f4932cfdSyangbo lu else 138*f4932cfdSyangbo lu ret = value; 139ba8c4dc9SRoy Zang 1407657c3a7SAlbert Herranz return ret; 1417657c3a7SAlbert Herranz } 1427657c3a7SAlbert Herranz 143*f4932cfdSyangbo lu static u32 esdhc_writew_fixup(struct sdhci_host *host, 144*f4932cfdSyangbo lu int spec_reg, u16 value, u32 old_value) 145a4071fbbSHaijun Zhang { 146*f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 147*f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 148*f4932cfdSyangbo lu u32 ret; 149*f4932cfdSyangbo lu 150*f4932cfdSyangbo lu switch (spec_reg) { 151*f4932cfdSyangbo lu case SDHCI_TRANSFER_MODE: 152a4071fbbSHaijun Zhang /* 153*f4932cfdSyangbo lu * Postpone this write, we must do it together with a 154*f4932cfdSyangbo lu * command write that is down below. Return old value. 155a4071fbbSHaijun Zhang */ 156*f4932cfdSyangbo lu pltfm_host->xfer_mode_shadow = value; 157*f4932cfdSyangbo lu return old_value; 158*f4932cfdSyangbo lu case SDHCI_COMMAND: 159*f4932cfdSyangbo lu ret = (value << 16) | pltfm_host->xfer_mode_shadow; 160*f4932cfdSyangbo lu return ret; 161a4071fbbSHaijun Zhang } 162a4071fbbSHaijun Zhang 163*f4932cfdSyangbo lu ret = old_value & (~(0xffff << shift)); 164*f4932cfdSyangbo lu ret |= (value << shift); 165*f4932cfdSyangbo lu 166*f4932cfdSyangbo lu if (spec_reg == SDHCI_BLOCK_SIZE) { 1677657c3a7SAlbert Herranz /* 1687657c3a7SAlbert Herranz * Two last DMA bits are reserved, and first one is used for 1697657c3a7SAlbert Herranz * non-standard blksz of 4096 bytes that we don't support 1707657c3a7SAlbert Herranz * yet. So clear the DMA boundary bits. 1717657c3a7SAlbert Herranz */ 172*f4932cfdSyangbo lu ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 1737657c3a7SAlbert Herranz } 174*f4932cfdSyangbo lu return ret; 1757657c3a7SAlbert Herranz } 1767657c3a7SAlbert Herranz 177*f4932cfdSyangbo lu static u32 esdhc_writeb_fixup(struct sdhci_host *host, 178*f4932cfdSyangbo lu int spec_reg, u8 value, u32 old_value) 1797657c3a7SAlbert Herranz { 180*f4932cfdSyangbo lu u32 ret; 181*f4932cfdSyangbo lu u32 dma_bits; 182*f4932cfdSyangbo lu u8 tmp; 183*f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 184*f4932cfdSyangbo lu 185ba8c4dc9SRoy Zang /* 186ba8c4dc9SRoy Zang * "DMA select" location is offset 0x28 in SD specification, but on 187ba8c4dc9SRoy Zang * P5020 or P3041, it's located at 0x29. 188ba8c4dc9SRoy Zang */ 189*f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 190dcaff04dSOded Gabbay /* 191dcaff04dSOded Gabbay * If host control register is not standard, exit 192dcaff04dSOded Gabbay * this function 193dcaff04dSOded Gabbay */ 194dcaff04dSOded Gabbay if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 195*f4932cfdSyangbo lu return old_value; 196dcaff04dSOded Gabbay 197ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 198*f4932cfdSyangbo lu dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 199*f4932cfdSyangbo lu ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 200*f4932cfdSyangbo lu tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 201*f4932cfdSyangbo lu (old_value & SDHCI_CTRL_DMA_MASK); 202*f4932cfdSyangbo lu ret = (ret & (~0xff)) | tmp; 203*f4932cfdSyangbo lu 204*f4932cfdSyangbo lu /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 205*f4932cfdSyangbo lu ret &= ~ESDHC_HOST_CONTROL_RES; 206*f4932cfdSyangbo lu return ret; 207ba8c4dc9SRoy Zang } 208ba8c4dc9SRoy Zang 209*f4932cfdSyangbo lu ret = (old_value & (~(0xff << shift))) | (value << shift); 210*f4932cfdSyangbo lu return ret; 211*f4932cfdSyangbo lu } 212*f4932cfdSyangbo lu 213*f4932cfdSyangbo lu static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 214*f4932cfdSyangbo lu { 215*f4932cfdSyangbo lu u32 ret; 216*f4932cfdSyangbo lu u32 value; 217*f4932cfdSyangbo lu 218*f4932cfdSyangbo lu value = ioread32be(host->ioaddr + reg); 219*f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 220*f4932cfdSyangbo lu 221*f4932cfdSyangbo lu return ret; 222*f4932cfdSyangbo lu } 223*f4932cfdSyangbo lu 224*f4932cfdSyangbo lu static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 225*f4932cfdSyangbo lu { 226*f4932cfdSyangbo lu u32 ret; 227*f4932cfdSyangbo lu u32 value; 228*f4932cfdSyangbo lu 229*f4932cfdSyangbo lu value = ioread32(host->ioaddr + reg); 230*f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 231*f4932cfdSyangbo lu 232*f4932cfdSyangbo lu return ret; 233*f4932cfdSyangbo lu } 234*f4932cfdSyangbo lu 235*f4932cfdSyangbo lu static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 236*f4932cfdSyangbo lu { 237*f4932cfdSyangbo lu u16 ret; 238*f4932cfdSyangbo lu u32 value; 239*f4932cfdSyangbo lu int base = reg & ~0x3; 240*f4932cfdSyangbo lu 241*f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 242*f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 243*f4932cfdSyangbo lu return ret; 244*f4932cfdSyangbo lu } 245*f4932cfdSyangbo lu 246*f4932cfdSyangbo lu static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 247*f4932cfdSyangbo lu { 248*f4932cfdSyangbo lu u16 ret; 249*f4932cfdSyangbo lu u32 value; 250*f4932cfdSyangbo lu int base = reg & ~0x3; 251*f4932cfdSyangbo lu 252*f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 253*f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 254*f4932cfdSyangbo lu return ret; 255*f4932cfdSyangbo lu } 256*f4932cfdSyangbo lu 257*f4932cfdSyangbo lu static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 258*f4932cfdSyangbo lu { 259*f4932cfdSyangbo lu u8 ret; 260*f4932cfdSyangbo lu u32 value; 261*f4932cfdSyangbo lu int base = reg & ~0x3; 262*f4932cfdSyangbo lu 263*f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 264*f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 265*f4932cfdSyangbo lu return ret; 266*f4932cfdSyangbo lu } 267*f4932cfdSyangbo lu 268*f4932cfdSyangbo lu static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 269*f4932cfdSyangbo lu { 270*f4932cfdSyangbo lu u8 ret; 271*f4932cfdSyangbo lu u32 value; 272*f4932cfdSyangbo lu int base = reg & ~0x3; 273*f4932cfdSyangbo lu 274*f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 275*f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 276*f4932cfdSyangbo lu return ret; 277*f4932cfdSyangbo lu } 278*f4932cfdSyangbo lu 279*f4932cfdSyangbo lu static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 280*f4932cfdSyangbo lu { 281*f4932cfdSyangbo lu u32 value; 282*f4932cfdSyangbo lu 283*f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 284*f4932cfdSyangbo lu iowrite32be(value, host->ioaddr + reg); 285*f4932cfdSyangbo lu } 286*f4932cfdSyangbo lu 287*f4932cfdSyangbo lu static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 288*f4932cfdSyangbo lu { 289*f4932cfdSyangbo lu u32 value; 290*f4932cfdSyangbo lu 291*f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 292*f4932cfdSyangbo lu iowrite32(value, host->ioaddr + reg); 293*f4932cfdSyangbo lu } 294*f4932cfdSyangbo lu 295*f4932cfdSyangbo lu static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 296*f4932cfdSyangbo lu { 297*f4932cfdSyangbo lu int base = reg & ~0x3; 298*f4932cfdSyangbo lu u32 value; 299*f4932cfdSyangbo lu u32 ret; 300*f4932cfdSyangbo lu 301*f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 302*f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 303*f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 304*f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 305*f4932cfdSyangbo lu } 306*f4932cfdSyangbo lu 307*f4932cfdSyangbo lu static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 308*f4932cfdSyangbo lu { 309*f4932cfdSyangbo lu int base = reg & ~0x3; 310*f4932cfdSyangbo lu u32 value; 311*f4932cfdSyangbo lu u32 ret; 312*f4932cfdSyangbo lu 313*f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 314*f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 315*f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 316*f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 317*f4932cfdSyangbo lu } 318*f4932cfdSyangbo lu 319*f4932cfdSyangbo lu static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 320*f4932cfdSyangbo lu { 321*f4932cfdSyangbo lu int base = reg & ~0x3; 322*f4932cfdSyangbo lu u32 value; 323*f4932cfdSyangbo lu u32 ret; 324*f4932cfdSyangbo lu 325*f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 326*f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 327*f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 328*f4932cfdSyangbo lu } 329*f4932cfdSyangbo lu 330*f4932cfdSyangbo lu static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 331*f4932cfdSyangbo lu { 332*f4932cfdSyangbo lu int base = reg & ~0x3; 333*f4932cfdSyangbo lu u32 value; 334*f4932cfdSyangbo lu u32 ret; 335*f4932cfdSyangbo lu 336*f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 337*f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 338*f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 3397657c3a7SAlbert Herranz } 3407657c3a7SAlbert Herranz 341a4071fbbSHaijun Zhang /* 342a4071fbbSHaijun Zhang * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 343a4071fbbSHaijun Zhang * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 344a4071fbbSHaijun Zhang * and Block Gap Event(IRQSTAT[BGE]) are also set. 345a4071fbbSHaijun Zhang * For Continue, apply soft reset for data(SYSCTL[RSTD]); 346a4071fbbSHaijun Zhang * and re-issue the entire read transaction from beginning. 347a4071fbbSHaijun Zhang */ 348*f4932cfdSyangbo lu static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 349a4071fbbSHaijun Zhang { 350*f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 351*f4932cfdSyangbo lu struct sdhci_esdhc *esdhc = pltfm_host->priv; 352a4071fbbSHaijun Zhang bool applicable; 353a4071fbbSHaijun Zhang dma_addr_t dmastart; 354a4071fbbSHaijun Zhang dma_addr_t dmanow; 355a4071fbbSHaijun Zhang 356a4071fbbSHaijun Zhang applicable = (intmask & SDHCI_INT_DATA_END) && 357a4071fbbSHaijun Zhang (intmask & SDHCI_INT_BLK_GAP) && 358*f4932cfdSyangbo lu (esdhc->vendor_ver == VENDOR_V_23); 359a4071fbbSHaijun Zhang if (!applicable) 360a4071fbbSHaijun Zhang return; 361a4071fbbSHaijun Zhang 362a4071fbbSHaijun Zhang host->data->error = 0; 363a4071fbbSHaijun Zhang dmastart = sg_dma_address(host->data->sg); 364a4071fbbSHaijun Zhang dmanow = dmastart + host->data->bytes_xfered; 365a4071fbbSHaijun Zhang /* 366a4071fbbSHaijun Zhang * Force update to the next DMA block boundary. 367a4071fbbSHaijun Zhang */ 368a4071fbbSHaijun Zhang dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 369a4071fbbSHaijun Zhang SDHCI_DEFAULT_BOUNDARY_SIZE; 370a4071fbbSHaijun Zhang host->data->bytes_xfered = dmanow - dmastart; 371a4071fbbSHaijun Zhang sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 372a4071fbbSHaijun Zhang } 373a4071fbbSHaijun Zhang 37480872e21SWolfram Sang static int esdhc_of_enable_dma(struct sdhci_host *host) 3757657c3a7SAlbert Herranz { 376*f4932cfdSyangbo lu u32 value; 377*f4932cfdSyangbo lu 378*f4932cfdSyangbo lu value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 379*f4932cfdSyangbo lu value |= ESDHC_DMA_SNOOP; 380*f4932cfdSyangbo lu sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 3817657c3a7SAlbert Herranz return 0; 3827657c3a7SAlbert Herranz } 3837657c3a7SAlbert Herranz 38480872e21SWolfram Sang static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 3857657c3a7SAlbert Herranz { 386e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3877657c3a7SAlbert Herranz 388e307148fSShawn Guo return pltfm_host->clock; 3897657c3a7SAlbert Herranz } 3907657c3a7SAlbert Herranz 39180872e21SWolfram Sang static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 3927657c3a7SAlbert Herranz { 393e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3947657c3a7SAlbert Herranz 395e307148fSShawn Guo return pltfm_host->clock / 256 / 16; 3967657c3a7SAlbert Herranz } 3977657c3a7SAlbert Herranz 398f060bc9cSJerry Huang static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 399f060bc9cSJerry Huang { 400*f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 401*f4932cfdSyangbo lu struct sdhci_esdhc *esdhc = pltfm_host->priv; 402bd455029SJoakim Tjernlund int pre_div = 1; 403d31fc00aSDong Aisheng int div = 1; 404d31fc00aSDong Aisheng u32 temp; 405d31fc00aSDong Aisheng 4061650d0c7SRussell King host->mmc->actual_clock = 0; 4071650d0c7SRussell King 408d31fc00aSDong Aisheng if (clock == 0) 409373073efSRussell King return; 410d31fc00aSDong Aisheng 41177bd2f6fSYangbo Lu /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 412*f4932cfdSyangbo lu if (esdhc->vendor_ver < VENDOR_V_23) 41377bd2f6fSYangbo Lu pre_div = 2; 41477bd2f6fSYangbo Lu 415f060bc9cSJerry Huang /* Workaround to reduce the clock frequency for p1010 esdhc */ 416f060bc9cSJerry Huang if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { 417f060bc9cSJerry Huang if (clock > 20000000) 418f060bc9cSJerry Huang clock -= 5000000; 419f060bc9cSJerry Huang if (clock > 40000000) 420f060bc9cSJerry Huang clock -= 5000000; 421f060bc9cSJerry Huang } 422f060bc9cSJerry Huang 423d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 424d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 425d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 426d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 427d31fc00aSDong Aisheng 428d31fc00aSDong Aisheng while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 429d31fc00aSDong Aisheng pre_div *= 2; 430d31fc00aSDong Aisheng 431d31fc00aSDong Aisheng while (host->max_clk / pre_div / div > clock && div < 16) 432d31fc00aSDong Aisheng div++; 433d31fc00aSDong Aisheng 434d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 435e76b8559SDong Aisheng clock, host->max_clk / pre_div / div); 436bd455029SJoakim Tjernlund host->mmc->actual_clock = host->max_clk / pre_div / div; 437d31fc00aSDong Aisheng pre_div >>= 1; 438d31fc00aSDong Aisheng div--; 439d31fc00aSDong Aisheng 440d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 441d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 442d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 443d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 444d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 445d31fc00aSDong Aisheng mdelay(1); 446f060bc9cSJerry Huang } 447f060bc9cSJerry Huang 4482317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 44966b50a00SOded Gabbay { 45066b50a00SOded Gabbay u32 ctrl; 45166b50a00SOded Gabbay 452*f4932cfdSyangbo lu ctrl = sdhci_readl(host, ESDHC_PROCTL); 453*f4932cfdSyangbo lu ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 45466b50a00SOded Gabbay switch (width) { 45566b50a00SOded Gabbay case MMC_BUS_WIDTH_8: 456*f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_8BITBUS; 45766b50a00SOded Gabbay break; 45866b50a00SOded Gabbay 45966b50a00SOded Gabbay case MMC_BUS_WIDTH_4: 460*f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_4BITBUS; 46166b50a00SOded Gabbay break; 46266b50a00SOded Gabbay 46366b50a00SOded Gabbay default: 46466b50a00SOded Gabbay break; 46566b50a00SOded Gabbay } 46666b50a00SOded Gabbay 467*f4932cfdSyangbo lu sdhci_writel(host, ctrl, ESDHC_PROCTL); 46866b50a00SOded Gabbay } 46966b50a00SOded Gabbay 470304f0a98SAlessio Igor Bogani static void esdhc_reset(struct sdhci_host *host, u8 mask) 471304f0a98SAlessio Igor Bogani { 472304f0a98SAlessio Igor Bogani sdhci_reset(host, mask); 473304f0a98SAlessio Igor Bogani 474304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 475304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 476304f0a98SAlessio Igor Bogani } 477304f0a98SAlessio Igor Bogani 478723f7924SRussell King #ifdef CONFIG_PM 479723f7924SRussell King static u32 esdhc_proctl; 480723f7924SRussell King static int esdhc_of_suspend(struct device *dev) 481723f7924SRussell King { 482723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 483723f7924SRussell King 484*f4932cfdSyangbo lu esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 485723f7924SRussell King 486723f7924SRussell King return sdhci_suspend_host(host); 487723f7924SRussell King } 488723f7924SRussell King 48906732b84SUlf Hansson static int esdhc_of_resume(struct device *dev) 490723f7924SRussell King { 491723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 492723f7924SRussell King int ret = sdhci_resume_host(host); 493723f7924SRussell King 494723f7924SRussell King if (ret == 0) { 495723f7924SRussell King /* Isn't this already done by sdhci_resume_host() ? --rmk */ 496723f7924SRussell King esdhc_of_enable_dma(host); 497*f4932cfdSyangbo lu sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 498723f7924SRussell King } 499723f7924SRussell King return ret; 500723f7924SRussell King } 501723f7924SRussell King 502723f7924SRussell King static const struct dev_pm_ops esdhc_pmops = { 50306732b84SUlf Hansson .suspend = esdhc_of_suspend, 50406732b84SUlf Hansson .resume = esdhc_of_resume, 505723f7924SRussell King }; 506723f7924SRussell King #define ESDHC_PMOPS (&esdhc_pmops) 507723f7924SRussell King #else 508723f7924SRussell King #define ESDHC_PMOPS NULL 509723f7924SRussell King #endif 510723f7924SRussell King 511*f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_be_ops = { 512*f4932cfdSyangbo lu .read_l = esdhc_be_readl, 513*f4932cfdSyangbo lu .read_w = esdhc_be_readw, 514*f4932cfdSyangbo lu .read_b = esdhc_be_readb, 515*f4932cfdSyangbo lu .write_l = esdhc_be_writel, 516*f4932cfdSyangbo lu .write_w = esdhc_be_writew, 517*f4932cfdSyangbo lu .write_b = esdhc_be_writeb, 518*f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 519*f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 520*f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 521*f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 522*f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 523*f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 524*f4932cfdSyangbo lu .reset = esdhc_reset, 525*f4932cfdSyangbo lu .set_uhs_signaling = sdhci_set_uhs_signaling, 526*f4932cfdSyangbo lu }; 527*f4932cfdSyangbo lu 528*f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_le_ops = { 529*f4932cfdSyangbo lu .read_l = esdhc_le_readl, 530*f4932cfdSyangbo lu .read_w = esdhc_le_readw, 531*f4932cfdSyangbo lu .read_b = esdhc_le_readb, 532*f4932cfdSyangbo lu .write_l = esdhc_le_writel, 533*f4932cfdSyangbo lu .write_w = esdhc_le_writew, 534*f4932cfdSyangbo lu .write_b = esdhc_le_writeb, 535*f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 536*f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 537*f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 538*f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 539*f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 540*f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 541*f4932cfdSyangbo lu .reset = esdhc_reset, 542*f4932cfdSyangbo lu .set_uhs_signaling = sdhci_set_uhs_signaling, 543*f4932cfdSyangbo lu }; 544*f4932cfdSyangbo lu 545*f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 546e307148fSShawn Guo .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION 547137ccd46SJerry Huang | SDHCI_QUIRK_NO_CARD_NO_RESET 548137ccd46SJerry Huang | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 549*f4932cfdSyangbo lu .ops = &sdhci_esdhc_be_ops, 5507657c3a7SAlbert Herranz }; 55138576af1SShawn Guo 552*f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 553*f4932cfdSyangbo lu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION 554*f4932cfdSyangbo lu | SDHCI_QUIRK_NO_CARD_NO_RESET 555*f4932cfdSyangbo lu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 556*f4932cfdSyangbo lu .ops = &sdhci_esdhc_le_ops, 557*f4932cfdSyangbo lu }; 558*f4932cfdSyangbo lu 559*f4932cfdSyangbo lu static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 560*f4932cfdSyangbo lu { 561*f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host; 562*f4932cfdSyangbo lu struct sdhci_esdhc *esdhc; 563*f4932cfdSyangbo lu u16 host_ver; 564*f4932cfdSyangbo lu 565*f4932cfdSyangbo lu pltfm_host = sdhci_priv(host); 566*f4932cfdSyangbo lu esdhc = devm_kzalloc(&pdev->dev, sizeof(struct sdhci_esdhc), 567*f4932cfdSyangbo lu GFP_KERNEL); 568*f4932cfdSyangbo lu 569*f4932cfdSyangbo lu host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 570*f4932cfdSyangbo lu esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 571*f4932cfdSyangbo lu SDHCI_VENDOR_VER_SHIFT; 572*f4932cfdSyangbo lu esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 573*f4932cfdSyangbo lu 574*f4932cfdSyangbo lu pltfm_host->priv = esdhc; 575*f4932cfdSyangbo lu } 576*f4932cfdSyangbo lu 577c3be1efdSBill Pemberton static int sdhci_esdhc_probe(struct platform_device *pdev) 57838576af1SShawn Guo { 57966b50a00SOded Gabbay struct sdhci_host *host; 580dcaff04dSOded Gabbay struct device_node *np; 58166b50a00SOded Gabbay int ret; 58266b50a00SOded Gabbay 583*f4932cfdSyangbo lu np = pdev->dev.of_node; 584*f4932cfdSyangbo lu 585*f4932cfdSyangbo lu if (of_get_property(np, "little-endian", NULL)) 586*f4932cfdSyangbo lu host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 0); 587*f4932cfdSyangbo lu else 588*f4932cfdSyangbo lu host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 0); 589*f4932cfdSyangbo lu 59066b50a00SOded Gabbay if (IS_ERR(host)) 59166b50a00SOded Gabbay return PTR_ERR(host); 59266b50a00SOded Gabbay 593*f4932cfdSyangbo lu esdhc_init(pdev, host); 594*f4932cfdSyangbo lu 59566b50a00SOded Gabbay sdhci_get_of_property(pdev); 59666b50a00SOded Gabbay 59774fd5e30SYangbo Lu if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 59874fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p5020-esdhc") || 59974fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p4080-esdhc") || 60074fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p1020-esdhc") || 601aaa58d0eSYangbo Lu of_device_is_compatible(np, "fsl,t1040-esdhc") || 602aaa58d0eSYangbo Lu of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 60374fd5e30SYangbo Lu host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 60474fd5e30SYangbo Lu 605dcaff04dSOded Gabbay if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 606dcaff04dSOded Gabbay /* 607dcaff04dSOded Gabbay * Freescale messed up with P2020 as it has a non-standard 608dcaff04dSOded Gabbay * host control register 609dcaff04dSOded Gabbay */ 610dcaff04dSOded Gabbay host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 611dcaff04dSOded Gabbay } 612dcaff04dSOded Gabbay 61366b50a00SOded Gabbay /* call to generic mmc_of_parse to support additional capabilities */ 614f0991408SUlf Hansson ret = mmc_of_parse(host->mmc); 615f0991408SUlf Hansson if (ret) 616f0991408SUlf Hansson goto err; 617f0991408SUlf Hansson 618490104acSHaijun Zhang mmc_of_parse_voltage(np, &host->ocr_mask); 61966b50a00SOded Gabbay 62066b50a00SOded Gabbay ret = sdhci_add_host(host); 62166b50a00SOded Gabbay if (ret) 622f0991408SUlf Hansson goto err; 62366b50a00SOded Gabbay 624f0991408SUlf Hansson return 0; 625f0991408SUlf Hansson err: 626f0991408SUlf Hansson sdhci_pltfm_free(pdev); 62766b50a00SOded Gabbay return ret; 62838576af1SShawn Guo } 62938576af1SShawn Guo 63038576af1SShawn Guo static const struct of_device_id sdhci_esdhc_of_match[] = { 63138576af1SShawn Guo { .compatible = "fsl,mpc8379-esdhc" }, 63238576af1SShawn Guo { .compatible = "fsl,mpc8536-esdhc" }, 63338576af1SShawn Guo { .compatible = "fsl,esdhc" }, 63438576af1SShawn Guo { } 63538576af1SShawn Guo }; 63638576af1SShawn Guo MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 63738576af1SShawn Guo 63838576af1SShawn Guo static struct platform_driver sdhci_esdhc_driver = { 63938576af1SShawn Guo .driver = { 64038576af1SShawn Guo .name = "sdhci-esdhc", 64138576af1SShawn Guo .of_match_table = sdhci_esdhc_of_match, 642723f7924SRussell King .pm = ESDHC_PMOPS, 64338576af1SShawn Guo }, 64438576af1SShawn Guo .probe = sdhci_esdhc_probe, 645caebcae9SKevin Hao .remove = sdhci_pltfm_unregister, 64638576af1SShawn Guo }; 64738576af1SShawn Guo 648d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_driver); 64938576af1SShawn Guo 65038576af1SShawn Guo MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 65138576af1SShawn Guo MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 65238576af1SShawn Guo "Anton Vorontsov <avorontsov@ru.mvista.com>"); 65338576af1SShawn Guo MODULE_LICENSE("GPL v2"); 654