17657c3a7SAlbert Herranz /* 27657c3a7SAlbert Herranz * Freescale eSDHC controller driver. 37657c3a7SAlbert Herranz * 4*f060bc9cSJerry Huang * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 57657c3a7SAlbert Herranz * Copyright (c) 2009 MontaVista Software, Inc. 67657c3a7SAlbert Herranz * 77657c3a7SAlbert Herranz * Authors: Xiaobo Xie <X.Xie@freescale.com> 87657c3a7SAlbert Herranz * Anton Vorontsov <avorontsov@ru.mvista.com> 97657c3a7SAlbert Herranz * 107657c3a7SAlbert Herranz * This program is free software; you can redistribute it and/or modify 117657c3a7SAlbert Herranz * it under the terms of the GNU General Public License as published by 127657c3a7SAlbert Herranz * the Free Software Foundation; either version 2 of the License, or (at 137657c3a7SAlbert Herranz * your option) any later version. 147657c3a7SAlbert Herranz */ 157657c3a7SAlbert Herranz 167657c3a7SAlbert Herranz #include <linux/io.h> 17*f060bc9cSJerry Huang #include <linux/of.h> 187657c3a7SAlbert Herranz #include <linux/delay.h> 1988b47679SPaul Gortmaker #include <linux/module.h> 207657c3a7SAlbert Herranz #include <linux/mmc/host.h> 2138576af1SShawn Guo #include "sdhci-pltfm.h" 2280872e21SWolfram Sang #include "sdhci-esdhc.h" 237657c3a7SAlbert Herranz 247657c3a7SAlbert Herranz static u16 esdhc_readw(struct sdhci_host *host, int reg) 257657c3a7SAlbert Herranz { 267657c3a7SAlbert Herranz u16 ret; 27e51cbc9eSXu lei int base = reg & ~0x3; 28e51cbc9eSXu lei int shift = (reg & 0x2) * 8; 297657c3a7SAlbert Herranz 307657c3a7SAlbert Herranz if (unlikely(reg == SDHCI_HOST_VERSION)) 31e51cbc9eSXu lei ret = in_be32(host->ioaddr + base) & 0xffff; 327657c3a7SAlbert Herranz else 33e51cbc9eSXu lei ret = (in_be32(host->ioaddr + base) >> shift) & 0xffff; 34e51cbc9eSXu lei return ret; 35e51cbc9eSXu lei } 36e51cbc9eSXu lei 37e51cbc9eSXu lei static u8 esdhc_readb(struct sdhci_host *host, int reg) 38e51cbc9eSXu lei { 39e51cbc9eSXu lei int base = reg & ~0x3; 40e51cbc9eSXu lei int shift = (reg & 0x3) * 8; 41e51cbc9eSXu lei u8 ret = (in_be32(host->ioaddr + base) >> shift) & 0xff; 42ba8c4dc9SRoy Zang 43ba8c4dc9SRoy Zang /* 44ba8c4dc9SRoy Zang * "DMA select" locates at offset 0x28 in SD specification, but on 45ba8c4dc9SRoy Zang * P5020 or P3041, it locates at 0x29. 46ba8c4dc9SRoy Zang */ 47ba8c4dc9SRoy Zang if (reg == SDHCI_HOST_CONTROL) { 48ba8c4dc9SRoy Zang u32 dma_bits; 49ba8c4dc9SRoy Zang 50ba8c4dc9SRoy Zang dma_bits = in_be32(host->ioaddr + reg); 51ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 52ba8c4dc9SRoy Zang dma_bits = (dma_bits >> 5) & SDHCI_CTRL_DMA_MASK; 53ba8c4dc9SRoy Zang 54ba8c4dc9SRoy Zang /* fixup the result */ 55ba8c4dc9SRoy Zang ret &= ~SDHCI_CTRL_DMA_MASK; 56ba8c4dc9SRoy Zang ret |= dma_bits; 57ba8c4dc9SRoy Zang } 58ba8c4dc9SRoy Zang 597657c3a7SAlbert Herranz return ret; 607657c3a7SAlbert Herranz } 617657c3a7SAlbert Herranz 627657c3a7SAlbert Herranz static void esdhc_writew(struct sdhci_host *host, u16 val, int reg) 637657c3a7SAlbert Herranz { 647657c3a7SAlbert Herranz if (reg == SDHCI_BLOCK_SIZE) { 657657c3a7SAlbert Herranz /* 667657c3a7SAlbert Herranz * Two last DMA bits are reserved, and first one is used for 677657c3a7SAlbert Herranz * non-standard blksz of 4096 bytes that we don't support 687657c3a7SAlbert Herranz * yet. So clear the DMA boundary bits. 697657c3a7SAlbert Herranz */ 707657c3a7SAlbert Herranz val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 717657c3a7SAlbert Herranz } 727657c3a7SAlbert Herranz sdhci_be32bs_writew(host, val, reg); 737657c3a7SAlbert Herranz } 747657c3a7SAlbert Herranz 757657c3a7SAlbert Herranz static void esdhc_writeb(struct sdhci_host *host, u8 val, int reg) 767657c3a7SAlbert Herranz { 77ba8c4dc9SRoy Zang /* 78ba8c4dc9SRoy Zang * "DMA select" location is offset 0x28 in SD specification, but on 79ba8c4dc9SRoy Zang * P5020 or P3041, it's located at 0x29. 80ba8c4dc9SRoy Zang */ 81ba8c4dc9SRoy Zang if (reg == SDHCI_HOST_CONTROL) { 82ba8c4dc9SRoy Zang u32 dma_bits; 83ba8c4dc9SRoy Zang 84ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 85ba8c4dc9SRoy Zang dma_bits = (val & SDHCI_CTRL_DMA_MASK) << 5; 86ba8c4dc9SRoy Zang clrsetbits_be32(host->ioaddr + reg , SDHCI_CTRL_DMA_MASK << 5, 87ba8c4dc9SRoy Zang dma_bits); 88ba8c4dc9SRoy Zang val &= ~SDHCI_CTRL_DMA_MASK; 89ba8c4dc9SRoy Zang val |= in_be32(host->ioaddr + reg) & SDHCI_CTRL_DMA_MASK; 90ba8c4dc9SRoy Zang } 91ba8c4dc9SRoy Zang 927657c3a7SAlbert Herranz /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */ 937657c3a7SAlbert Herranz if (reg == SDHCI_HOST_CONTROL) 947657c3a7SAlbert Herranz val &= ~ESDHC_HOST_CONTROL_RES; 957657c3a7SAlbert Herranz sdhci_be32bs_writeb(host, val, reg); 967657c3a7SAlbert Herranz } 977657c3a7SAlbert Herranz 9880872e21SWolfram Sang static int esdhc_of_enable_dma(struct sdhci_host *host) 997657c3a7SAlbert Herranz { 1007657c3a7SAlbert Herranz setbits32(host->ioaddr + ESDHC_DMA_SYSCTL, ESDHC_DMA_SNOOP); 1017657c3a7SAlbert Herranz return 0; 1027657c3a7SAlbert Herranz } 1037657c3a7SAlbert Herranz 10480872e21SWolfram Sang static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 1057657c3a7SAlbert Herranz { 106e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1077657c3a7SAlbert Herranz 108e307148fSShawn Guo return pltfm_host->clock; 1097657c3a7SAlbert Herranz } 1107657c3a7SAlbert Herranz 11180872e21SWolfram Sang static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 1127657c3a7SAlbert Herranz { 113e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1147657c3a7SAlbert Herranz 115e307148fSShawn Guo return pltfm_host->clock / 256 / 16; 1167657c3a7SAlbert Herranz } 1177657c3a7SAlbert Herranz 118*f060bc9cSJerry Huang static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 119*f060bc9cSJerry Huang { 120*f060bc9cSJerry Huang /* Workaround to reduce the clock frequency for p1010 esdhc */ 121*f060bc9cSJerry Huang if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { 122*f060bc9cSJerry Huang if (clock > 20000000) 123*f060bc9cSJerry Huang clock -= 5000000; 124*f060bc9cSJerry Huang if (clock > 40000000) 125*f060bc9cSJerry Huang clock -= 5000000; 126*f060bc9cSJerry Huang } 127*f060bc9cSJerry Huang 128*f060bc9cSJerry Huang /* Set the clock */ 129*f060bc9cSJerry Huang esdhc_set_clock(host, clock); 130*f060bc9cSJerry Huang } 131*f060bc9cSJerry Huang 132192b5372SJerry Huang #ifdef CONFIG_PM 133192b5372SJerry Huang static u32 esdhc_proctl; 134192b5372SJerry Huang static void esdhc_of_suspend(struct sdhci_host *host) 135192b5372SJerry Huang { 136192b5372SJerry Huang esdhc_proctl = sdhci_be32bs_readl(host, SDHCI_HOST_CONTROL); 137192b5372SJerry Huang } 138192b5372SJerry Huang 139192b5372SJerry Huang static void esdhc_of_resume(struct sdhci_host *host) 140192b5372SJerry Huang { 141192b5372SJerry Huang esdhc_of_enable_dma(host); 142192b5372SJerry Huang sdhci_be32bs_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 143192b5372SJerry Huang } 144192b5372SJerry Huang #endif 145192b5372SJerry Huang 146e307148fSShawn Guo static struct sdhci_ops sdhci_esdhc_ops = { 147dc297c92SMatt Fleming .read_l = sdhci_be32bs_readl, 148dc297c92SMatt Fleming .read_w = esdhc_readw, 149e51cbc9eSXu lei .read_b = esdhc_readb, 150dc297c92SMatt Fleming .write_l = sdhci_be32bs_writel, 151dc297c92SMatt Fleming .write_w = esdhc_writew, 152dc297c92SMatt Fleming .write_b = esdhc_writeb, 153*f060bc9cSJerry Huang .set_clock = esdhc_of_set_clock, 15480872e21SWolfram Sang .enable_dma = esdhc_of_enable_dma, 15580872e21SWolfram Sang .get_max_clock = esdhc_of_get_max_clock, 15680872e21SWolfram Sang .get_min_clock = esdhc_of_get_min_clock, 157192b5372SJerry Huang #ifdef CONFIG_PM 158192b5372SJerry Huang .platform_suspend = esdhc_of_suspend, 159192b5372SJerry Huang .platform_resume = esdhc_of_resume, 160192b5372SJerry Huang #endif 161e307148fSShawn Guo }; 162e307148fSShawn Guo 16338576af1SShawn Guo static struct sdhci_pltfm_data sdhci_esdhc_pdata = { 164e307148fSShawn Guo /* card detection could be handled via GPIO */ 165e307148fSShawn Guo .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_BROKEN_CARD_DETECTION 166e307148fSShawn Guo | SDHCI_QUIRK_NO_CARD_NO_RESET, 167e307148fSShawn Guo .ops = &sdhci_esdhc_ops, 1687657c3a7SAlbert Herranz }; 16938576af1SShawn Guo 17038576af1SShawn Guo static int __devinit sdhci_esdhc_probe(struct platform_device *pdev) 17138576af1SShawn Guo { 17238576af1SShawn Guo return sdhci_pltfm_register(pdev, &sdhci_esdhc_pdata); 17338576af1SShawn Guo } 17438576af1SShawn Guo 17538576af1SShawn Guo static int __devexit sdhci_esdhc_remove(struct platform_device *pdev) 17638576af1SShawn Guo { 17738576af1SShawn Guo return sdhci_pltfm_unregister(pdev); 17838576af1SShawn Guo } 17938576af1SShawn Guo 18038576af1SShawn Guo static const struct of_device_id sdhci_esdhc_of_match[] = { 18138576af1SShawn Guo { .compatible = "fsl,mpc8379-esdhc" }, 18238576af1SShawn Guo { .compatible = "fsl,mpc8536-esdhc" }, 18338576af1SShawn Guo { .compatible = "fsl,esdhc" }, 18438576af1SShawn Guo { } 18538576af1SShawn Guo }; 18638576af1SShawn Guo MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 18738576af1SShawn Guo 18838576af1SShawn Guo static struct platform_driver sdhci_esdhc_driver = { 18938576af1SShawn Guo .driver = { 19038576af1SShawn Guo .name = "sdhci-esdhc", 19138576af1SShawn Guo .owner = THIS_MODULE, 19238576af1SShawn Guo .of_match_table = sdhci_esdhc_of_match, 19329495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 19438576af1SShawn Guo }, 19538576af1SShawn Guo .probe = sdhci_esdhc_probe, 19638576af1SShawn Guo .remove = __devexit_p(sdhci_esdhc_remove), 19738576af1SShawn Guo }; 19838576af1SShawn Guo 199d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_driver); 20038576af1SShawn Guo 20138576af1SShawn Guo MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 20238576af1SShawn Guo MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 20338576af1SShawn Guo "Anton Vorontsov <avorontsov@ru.mvista.com>"); 20438576af1SShawn Guo MODULE_LICENSE("GPL v2"); 205