17657c3a7SAlbert Herranz /* 27657c3a7SAlbert Herranz * Freescale eSDHC controller driver. 37657c3a7SAlbert Herranz * 4f060bc9cSJerry Huang * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc. 57657c3a7SAlbert Herranz * Copyright (c) 2009 MontaVista Software, Inc. 67657c3a7SAlbert Herranz * 77657c3a7SAlbert Herranz * Authors: Xiaobo Xie <X.Xie@freescale.com> 87657c3a7SAlbert Herranz * Anton Vorontsov <avorontsov@ru.mvista.com> 97657c3a7SAlbert Herranz * 107657c3a7SAlbert Herranz * This program is free software; you can redistribute it and/or modify 117657c3a7SAlbert Herranz * it under the terms of the GNU General Public License as published by 127657c3a7SAlbert Herranz * the Free Software Foundation; either version 2 of the License, or (at 137657c3a7SAlbert Herranz * your option) any later version. 147657c3a7SAlbert Herranz */ 157657c3a7SAlbert Herranz 1666b50a00SOded Gabbay #include <linux/err.h> 177657c3a7SAlbert Herranz #include <linux/io.h> 18f060bc9cSJerry Huang #include <linux/of.h> 197657c3a7SAlbert Herranz #include <linux/delay.h> 2088b47679SPaul Gortmaker #include <linux/module.h> 21151ede40Syangbo lu #include <linux/sys_soc.h> 22*19c3a0efSyangbo lu #include <linux/clk.h> 23*19c3a0efSyangbo lu #include <linux/ktime.h> 247657c3a7SAlbert Herranz #include <linux/mmc/host.h> 2538576af1SShawn Guo #include "sdhci-pltfm.h" 2680872e21SWolfram Sang #include "sdhci-esdhc.h" 277657c3a7SAlbert Herranz 28137ccd46SJerry Huang #define VENDOR_V_22 0x12 29a4071fbbSHaijun Zhang #define VENDOR_V_23 0x13 30f4932cfdSyangbo lu 31f4932cfdSyangbo lu struct sdhci_esdhc { 32f4932cfdSyangbo lu u8 vendor_ver; 33f4932cfdSyangbo lu u8 spec_ver; 34151ede40Syangbo lu bool quirk_incorrect_hostver; 35*19c3a0efSyangbo lu unsigned int peripheral_clock; 36f4932cfdSyangbo lu }; 37f4932cfdSyangbo lu 38f4932cfdSyangbo lu /** 39f4932cfdSyangbo lu * esdhc_read*_fixup - Fixup the value read from incompatible eSDHC register 40f4932cfdSyangbo lu * to make it compatible with SD spec. 41f4932cfdSyangbo lu * 42f4932cfdSyangbo lu * @host: pointer to sdhci_host 43f4932cfdSyangbo lu * @spec_reg: SD spec register address 44f4932cfdSyangbo lu * @value: 32bit eSDHC register value on spec_reg address 45f4932cfdSyangbo lu * 46f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 47f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 48f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 49f4932cfdSyangbo lu * and SD spec. 50f4932cfdSyangbo lu * 51f4932cfdSyangbo lu * Return a fixed up register value 52f4932cfdSyangbo lu */ 53f4932cfdSyangbo lu static u32 esdhc_readl_fixup(struct sdhci_host *host, 54f4932cfdSyangbo lu int spec_reg, u32 value) 55137ccd46SJerry Huang { 56f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 578605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 58137ccd46SJerry Huang u32 ret; 59137ccd46SJerry Huang 60137ccd46SJerry Huang /* 61137ccd46SJerry Huang * The bit of ADMA flag in eSDHC is not compatible with standard 62137ccd46SJerry Huang * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is 63137ccd46SJerry Huang * supported by eSDHC. 64137ccd46SJerry Huang * And for many FSL eSDHC controller, the reset value of field 65f4932cfdSyangbo lu * SDHCI_CAN_DO_ADMA1 is 1, but some of them can't support ADMA, 66137ccd46SJerry Huang * only these vendor version is greater than 2.2/0x12 support ADMA. 67137ccd46SJerry Huang */ 68f4932cfdSyangbo lu if ((spec_reg == SDHCI_CAPABILITIES) && (value & SDHCI_CAN_DO_ADMA1)) { 69f4932cfdSyangbo lu if (esdhc->vendor_ver > VENDOR_V_22) { 70f4932cfdSyangbo lu ret = value | SDHCI_CAN_DO_ADMA2; 71f4932cfdSyangbo lu return ret; 72137ccd46SJerry Huang } 73f4932cfdSyangbo lu } 74b0921d5cSMichael Walle /* 75b0921d5cSMichael Walle * The DAT[3:0] line signal levels and the CMD line signal level are 76b0921d5cSMichael Walle * not compatible with standard SDHC register. The line signal levels 77b0921d5cSMichael Walle * DAT[7:0] are at bits 31:24 and the command line signal level is at 78b0921d5cSMichael Walle * bit 23. All other bits are the same as in the standard SDHC 79b0921d5cSMichael Walle * register. 80b0921d5cSMichael Walle */ 81b0921d5cSMichael Walle if (spec_reg == SDHCI_PRESENT_STATE) { 82b0921d5cSMichael Walle ret = value & 0x000fffff; 83b0921d5cSMichael Walle ret |= (value >> 4) & SDHCI_DATA_LVL_MASK; 84b0921d5cSMichael Walle ret |= (value << 1) & SDHCI_CMD_LVL; 85b0921d5cSMichael Walle return ret; 86b0921d5cSMichael Walle } 87b0921d5cSMichael Walle 88f4932cfdSyangbo lu ret = value; 89137ccd46SJerry Huang return ret; 90137ccd46SJerry Huang } 91137ccd46SJerry Huang 92f4932cfdSyangbo lu static u16 esdhc_readw_fixup(struct sdhci_host *host, 93f4932cfdSyangbo lu int spec_reg, u32 value) 947657c3a7SAlbert Herranz { 95151ede40Syangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 96151ede40Syangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 977657c3a7SAlbert Herranz u16 ret; 98f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 997657c3a7SAlbert Herranz 100f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_VERSION) 101f4932cfdSyangbo lu ret = value & 0xffff; 1027657c3a7SAlbert Herranz else 103f4932cfdSyangbo lu ret = (value >> shift) & 0xffff; 104151ede40Syangbo lu /* Workaround for T4240-R1.0-R2.0 eSDHC which has incorrect 105151ede40Syangbo lu * vendor version and spec version information. 106151ede40Syangbo lu */ 107151ede40Syangbo lu if ((spec_reg == SDHCI_HOST_VERSION) && 108151ede40Syangbo lu (esdhc->quirk_incorrect_hostver)) 109151ede40Syangbo lu ret = (VENDOR_V_23 << SDHCI_VENDOR_VER_SHIFT) | SDHCI_SPEC_200; 110e51cbc9eSXu lei return ret; 111e51cbc9eSXu lei } 112e51cbc9eSXu lei 113f4932cfdSyangbo lu static u8 esdhc_readb_fixup(struct sdhci_host *host, 114f4932cfdSyangbo lu int spec_reg, u32 value) 115e51cbc9eSXu lei { 116f4932cfdSyangbo lu u8 ret; 117f4932cfdSyangbo lu u8 dma_bits; 118f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 119f4932cfdSyangbo lu 120f4932cfdSyangbo lu ret = (value >> shift) & 0xff; 121ba8c4dc9SRoy Zang 122ba8c4dc9SRoy Zang /* 123ba8c4dc9SRoy Zang * "DMA select" locates at offset 0x28 in SD specification, but on 124ba8c4dc9SRoy Zang * P5020 or P3041, it locates at 0x29. 125ba8c4dc9SRoy Zang */ 126f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 127ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 128f4932cfdSyangbo lu dma_bits = (value >> 5) & SDHCI_CTRL_DMA_MASK; 129ba8c4dc9SRoy Zang /* fixup the result */ 130ba8c4dc9SRoy Zang ret &= ~SDHCI_CTRL_DMA_MASK; 131ba8c4dc9SRoy Zang ret |= dma_bits; 132ba8c4dc9SRoy Zang } 133f4932cfdSyangbo lu return ret; 134f4932cfdSyangbo lu } 135f4932cfdSyangbo lu 136f4932cfdSyangbo lu /** 137f4932cfdSyangbo lu * esdhc_write*_fixup - Fixup the SD spec register value so that it could be 138f4932cfdSyangbo lu * written into eSDHC register. 139f4932cfdSyangbo lu * 140f4932cfdSyangbo lu * @host: pointer to sdhci_host 141f4932cfdSyangbo lu * @spec_reg: SD spec register address 142f4932cfdSyangbo lu * @value: 8/16/32bit SD spec register value that would be written 143f4932cfdSyangbo lu * @old_value: 32bit eSDHC register value on spec_reg address 144f4932cfdSyangbo lu * 145f4932cfdSyangbo lu * In SD spec, there are 8/16/32/64 bits registers, while all of eSDHC 146f4932cfdSyangbo lu * registers are 32 bits. There are differences in register size, register 147f4932cfdSyangbo lu * address, register function, bit position and function between eSDHC spec 148f4932cfdSyangbo lu * and SD spec. 149f4932cfdSyangbo lu * 150f4932cfdSyangbo lu * Return a fixed up register value 151f4932cfdSyangbo lu */ 152f4932cfdSyangbo lu static u32 esdhc_writel_fixup(struct sdhci_host *host, 153f4932cfdSyangbo lu int spec_reg, u32 value, u32 old_value) 154f4932cfdSyangbo lu { 155f4932cfdSyangbo lu u32 ret; 156f4932cfdSyangbo lu 157f4932cfdSyangbo lu /* 158f4932cfdSyangbo lu * Enabling IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE] 159f4932cfdSyangbo lu * when SYSCTL[RSTD] is set for some special operations. 160f4932cfdSyangbo lu * No any impact on other operation. 161f4932cfdSyangbo lu */ 162f4932cfdSyangbo lu if (spec_reg == SDHCI_INT_ENABLE) 163f4932cfdSyangbo lu ret = value | SDHCI_INT_BLK_GAP; 164f4932cfdSyangbo lu else 165f4932cfdSyangbo lu ret = value; 166ba8c4dc9SRoy Zang 1677657c3a7SAlbert Herranz return ret; 1687657c3a7SAlbert Herranz } 1697657c3a7SAlbert Herranz 170f4932cfdSyangbo lu static u32 esdhc_writew_fixup(struct sdhci_host *host, 171f4932cfdSyangbo lu int spec_reg, u16 value, u32 old_value) 172a4071fbbSHaijun Zhang { 173f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 174f4932cfdSyangbo lu int shift = (spec_reg & 0x2) * 8; 175f4932cfdSyangbo lu u32 ret; 176f4932cfdSyangbo lu 177f4932cfdSyangbo lu switch (spec_reg) { 178f4932cfdSyangbo lu case SDHCI_TRANSFER_MODE: 179a4071fbbSHaijun Zhang /* 180f4932cfdSyangbo lu * Postpone this write, we must do it together with a 181f4932cfdSyangbo lu * command write that is down below. Return old value. 182a4071fbbSHaijun Zhang */ 183f4932cfdSyangbo lu pltfm_host->xfer_mode_shadow = value; 184f4932cfdSyangbo lu return old_value; 185f4932cfdSyangbo lu case SDHCI_COMMAND: 186f4932cfdSyangbo lu ret = (value << 16) | pltfm_host->xfer_mode_shadow; 187f4932cfdSyangbo lu return ret; 188a4071fbbSHaijun Zhang } 189a4071fbbSHaijun Zhang 190f4932cfdSyangbo lu ret = old_value & (~(0xffff << shift)); 191f4932cfdSyangbo lu ret |= (value << shift); 192f4932cfdSyangbo lu 193f4932cfdSyangbo lu if (spec_reg == SDHCI_BLOCK_SIZE) { 1947657c3a7SAlbert Herranz /* 1957657c3a7SAlbert Herranz * Two last DMA bits are reserved, and first one is used for 1967657c3a7SAlbert Herranz * non-standard blksz of 4096 bytes that we don't support 1977657c3a7SAlbert Herranz * yet. So clear the DMA boundary bits. 1987657c3a7SAlbert Herranz */ 199f4932cfdSyangbo lu ret &= (~SDHCI_MAKE_BLKSZ(0x7, 0)); 2007657c3a7SAlbert Herranz } 201f4932cfdSyangbo lu return ret; 2027657c3a7SAlbert Herranz } 2037657c3a7SAlbert Herranz 204f4932cfdSyangbo lu static u32 esdhc_writeb_fixup(struct sdhci_host *host, 205f4932cfdSyangbo lu int spec_reg, u8 value, u32 old_value) 2067657c3a7SAlbert Herranz { 207f4932cfdSyangbo lu u32 ret; 208f4932cfdSyangbo lu u32 dma_bits; 209f4932cfdSyangbo lu u8 tmp; 210f4932cfdSyangbo lu int shift = (spec_reg & 0x3) * 8; 211f4932cfdSyangbo lu 212ba8c4dc9SRoy Zang /* 2139e4703dfSyangbo lu * eSDHC doesn't have a standard power control register, so we do 2149e4703dfSyangbo lu * nothing here to avoid incorrect operation. 2159e4703dfSyangbo lu */ 2169e4703dfSyangbo lu if (spec_reg == SDHCI_POWER_CONTROL) 2179e4703dfSyangbo lu return old_value; 2189e4703dfSyangbo lu /* 219ba8c4dc9SRoy Zang * "DMA select" location is offset 0x28 in SD specification, but on 220ba8c4dc9SRoy Zang * P5020 or P3041, it's located at 0x29. 221ba8c4dc9SRoy Zang */ 222f4932cfdSyangbo lu if (spec_reg == SDHCI_HOST_CONTROL) { 223dcaff04dSOded Gabbay /* 224dcaff04dSOded Gabbay * If host control register is not standard, exit 225dcaff04dSOded Gabbay * this function 226dcaff04dSOded Gabbay */ 227dcaff04dSOded Gabbay if (host->quirks2 & SDHCI_QUIRK2_BROKEN_HOST_CONTROL) 228f4932cfdSyangbo lu return old_value; 229dcaff04dSOded Gabbay 230ba8c4dc9SRoy Zang /* DMA select is 22,23 bits in Protocol Control Register */ 231f4932cfdSyangbo lu dma_bits = (value & SDHCI_CTRL_DMA_MASK) << 5; 232f4932cfdSyangbo lu ret = (old_value & (~(SDHCI_CTRL_DMA_MASK << 5))) | dma_bits; 233f4932cfdSyangbo lu tmp = (value & (~SDHCI_CTRL_DMA_MASK)) | 234f4932cfdSyangbo lu (old_value & SDHCI_CTRL_DMA_MASK); 235f4932cfdSyangbo lu ret = (ret & (~0xff)) | tmp; 236f4932cfdSyangbo lu 237f4932cfdSyangbo lu /* Prevent SDHCI core from writing reserved bits (e.g. HISPD) */ 238f4932cfdSyangbo lu ret &= ~ESDHC_HOST_CONTROL_RES; 239f4932cfdSyangbo lu return ret; 240ba8c4dc9SRoy Zang } 241ba8c4dc9SRoy Zang 242f4932cfdSyangbo lu ret = (old_value & (~(0xff << shift))) | (value << shift); 243f4932cfdSyangbo lu return ret; 244f4932cfdSyangbo lu } 245f4932cfdSyangbo lu 246f4932cfdSyangbo lu static u32 esdhc_be_readl(struct sdhci_host *host, int reg) 247f4932cfdSyangbo lu { 248f4932cfdSyangbo lu u32 ret; 249f4932cfdSyangbo lu u32 value; 250f4932cfdSyangbo lu 251f4932cfdSyangbo lu value = ioread32be(host->ioaddr + reg); 252f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 253f4932cfdSyangbo lu 254f4932cfdSyangbo lu return ret; 255f4932cfdSyangbo lu } 256f4932cfdSyangbo lu 257f4932cfdSyangbo lu static u32 esdhc_le_readl(struct sdhci_host *host, int reg) 258f4932cfdSyangbo lu { 259f4932cfdSyangbo lu u32 ret; 260f4932cfdSyangbo lu u32 value; 261f4932cfdSyangbo lu 262f4932cfdSyangbo lu value = ioread32(host->ioaddr + reg); 263f4932cfdSyangbo lu ret = esdhc_readl_fixup(host, reg, value); 264f4932cfdSyangbo lu 265f4932cfdSyangbo lu return ret; 266f4932cfdSyangbo lu } 267f4932cfdSyangbo lu 268f4932cfdSyangbo lu static u16 esdhc_be_readw(struct sdhci_host *host, int reg) 269f4932cfdSyangbo lu { 270f4932cfdSyangbo lu u16 ret; 271f4932cfdSyangbo lu u32 value; 272f4932cfdSyangbo lu int base = reg & ~0x3; 273f4932cfdSyangbo lu 274f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 275f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 276f4932cfdSyangbo lu return ret; 277f4932cfdSyangbo lu } 278f4932cfdSyangbo lu 279f4932cfdSyangbo lu static u16 esdhc_le_readw(struct sdhci_host *host, int reg) 280f4932cfdSyangbo lu { 281f4932cfdSyangbo lu u16 ret; 282f4932cfdSyangbo lu u32 value; 283f4932cfdSyangbo lu int base = reg & ~0x3; 284f4932cfdSyangbo lu 285f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 286f4932cfdSyangbo lu ret = esdhc_readw_fixup(host, reg, value); 287f4932cfdSyangbo lu return ret; 288f4932cfdSyangbo lu } 289f4932cfdSyangbo lu 290f4932cfdSyangbo lu static u8 esdhc_be_readb(struct sdhci_host *host, int reg) 291f4932cfdSyangbo lu { 292f4932cfdSyangbo lu u8 ret; 293f4932cfdSyangbo lu u32 value; 294f4932cfdSyangbo lu int base = reg & ~0x3; 295f4932cfdSyangbo lu 296f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 297f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 298f4932cfdSyangbo lu return ret; 299f4932cfdSyangbo lu } 300f4932cfdSyangbo lu 301f4932cfdSyangbo lu static u8 esdhc_le_readb(struct sdhci_host *host, int reg) 302f4932cfdSyangbo lu { 303f4932cfdSyangbo lu u8 ret; 304f4932cfdSyangbo lu u32 value; 305f4932cfdSyangbo lu int base = reg & ~0x3; 306f4932cfdSyangbo lu 307f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 308f4932cfdSyangbo lu ret = esdhc_readb_fixup(host, reg, value); 309f4932cfdSyangbo lu return ret; 310f4932cfdSyangbo lu } 311f4932cfdSyangbo lu 312f4932cfdSyangbo lu static void esdhc_be_writel(struct sdhci_host *host, u32 val, int reg) 313f4932cfdSyangbo lu { 314f4932cfdSyangbo lu u32 value; 315f4932cfdSyangbo lu 316f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 317f4932cfdSyangbo lu iowrite32be(value, host->ioaddr + reg); 318f4932cfdSyangbo lu } 319f4932cfdSyangbo lu 320f4932cfdSyangbo lu static void esdhc_le_writel(struct sdhci_host *host, u32 val, int reg) 321f4932cfdSyangbo lu { 322f4932cfdSyangbo lu u32 value; 323f4932cfdSyangbo lu 324f4932cfdSyangbo lu value = esdhc_writel_fixup(host, reg, val, 0); 325f4932cfdSyangbo lu iowrite32(value, host->ioaddr + reg); 326f4932cfdSyangbo lu } 327f4932cfdSyangbo lu 328f4932cfdSyangbo lu static void esdhc_be_writew(struct sdhci_host *host, u16 val, int reg) 329f4932cfdSyangbo lu { 330f4932cfdSyangbo lu int base = reg & ~0x3; 331f4932cfdSyangbo lu u32 value; 332f4932cfdSyangbo lu u32 ret; 333f4932cfdSyangbo lu 334f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 335f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 336f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 337f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 338f4932cfdSyangbo lu } 339f4932cfdSyangbo lu 340f4932cfdSyangbo lu static void esdhc_le_writew(struct sdhci_host *host, u16 val, int reg) 341f4932cfdSyangbo lu { 342f4932cfdSyangbo lu int base = reg & ~0x3; 343f4932cfdSyangbo lu u32 value; 344f4932cfdSyangbo lu u32 ret; 345f4932cfdSyangbo lu 346f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 347f4932cfdSyangbo lu ret = esdhc_writew_fixup(host, reg, val, value); 348f4932cfdSyangbo lu if (reg != SDHCI_TRANSFER_MODE) 349f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 350f4932cfdSyangbo lu } 351f4932cfdSyangbo lu 352f4932cfdSyangbo lu static void esdhc_be_writeb(struct sdhci_host *host, u8 val, int reg) 353f4932cfdSyangbo lu { 354f4932cfdSyangbo lu int base = reg & ~0x3; 355f4932cfdSyangbo lu u32 value; 356f4932cfdSyangbo lu u32 ret; 357f4932cfdSyangbo lu 358f4932cfdSyangbo lu value = ioread32be(host->ioaddr + base); 359f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 360f4932cfdSyangbo lu iowrite32be(ret, host->ioaddr + base); 361f4932cfdSyangbo lu } 362f4932cfdSyangbo lu 363f4932cfdSyangbo lu static void esdhc_le_writeb(struct sdhci_host *host, u8 val, int reg) 364f4932cfdSyangbo lu { 365f4932cfdSyangbo lu int base = reg & ~0x3; 366f4932cfdSyangbo lu u32 value; 367f4932cfdSyangbo lu u32 ret; 368f4932cfdSyangbo lu 369f4932cfdSyangbo lu value = ioread32(host->ioaddr + base); 370f4932cfdSyangbo lu ret = esdhc_writeb_fixup(host, reg, val, value); 371f4932cfdSyangbo lu iowrite32(ret, host->ioaddr + base); 3727657c3a7SAlbert Herranz } 3737657c3a7SAlbert Herranz 374a4071fbbSHaijun Zhang /* 375a4071fbbSHaijun Zhang * For Abort or Suspend after Stop at Block Gap, ignore the ADMA 376a4071fbbSHaijun Zhang * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC]) 377a4071fbbSHaijun Zhang * and Block Gap Event(IRQSTAT[BGE]) are also set. 378a4071fbbSHaijun Zhang * For Continue, apply soft reset for data(SYSCTL[RSTD]); 379a4071fbbSHaijun Zhang * and re-issue the entire read transaction from beginning. 380a4071fbbSHaijun Zhang */ 381f4932cfdSyangbo lu static void esdhc_of_adma_workaround(struct sdhci_host *host, u32 intmask) 382a4071fbbSHaijun Zhang { 383f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3848605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 385a4071fbbSHaijun Zhang bool applicable; 386a4071fbbSHaijun Zhang dma_addr_t dmastart; 387a4071fbbSHaijun Zhang dma_addr_t dmanow; 388a4071fbbSHaijun Zhang 389a4071fbbSHaijun Zhang applicable = (intmask & SDHCI_INT_DATA_END) && 390a4071fbbSHaijun Zhang (intmask & SDHCI_INT_BLK_GAP) && 391f4932cfdSyangbo lu (esdhc->vendor_ver == VENDOR_V_23); 392a4071fbbSHaijun Zhang if (!applicable) 393a4071fbbSHaijun Zhang return; 394a4071fbbSHaijun Zhang 395a4071fbbSHaijun Zhang host->data->error = 0; 396a4071fbbSHaijun Zhang dmastart = sg_dma_address(host->data->sg); 397a4071fbbSHaijun Zhang dmanow = dmastart + host->data->bytes_xfered; 398a4071fbbSHaijun Zhang /* 399a4071fbbSHaijun Zhang * Force update to the next DMA block boundary. 400a4071fbbSHaijun Zhang */ 401a4071fbbSHaijun Zhang dmanow = (dmanow & ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + 402a4071fbbSHaijun Zhang SDHCI_DEFAULT_BOUNDARY_SIZE; 403a4071fbbSHaijun Zhang host->data->bytes_xfered = dmanow - dmastart; 404a4071fbbSHaijun Zhang sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); 405a4071fbbSHaijun Zhang } 406a4071fbbSHaijun Zhang 40780872e21SWolfram Sang static int esdhc_of_enable_dma(struct sdhci_host *host) 4087657c3a7SAlbert Herranz { 409f4932cfdSyangbo lu u32 value; 410f4932cfdSyangbo lu 411f4932cfdSyangbo lu value = sdhci_readl(host, ESDHC_DMA_SYSCTL); 412f4932cfdSyangbo lu value |= ESDHC_DMA_SNOOP; 413f4932cfdSyangbo lu sdhci_writel(host, value, ESDHC_DMA_SYSCTL); 4147657c3a7SAlbert Herranz return 0; 4157657c3a7SAlbert Herranz } 4167657c3a7SAlbert Herranz 41780872e21SWolfram Sang static unsigned int esdhc_of_get_max_clock(struct sdhci_host *host) 4187657c3a7SAlbert Herranz { 419e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 420*19c3a0efSyangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 4217657c3a7SAlbert Herranz 422*19c3a0efSyangbo lu if (esdhc->peripheral_clock) 423*19c3a0efSyangbo lu return esdhc->peripheral_clock; 424*19c3a0efSyangbo lu else 425e307148fSShawn Guo return pltfm_host->clock; 4267657c3a7SAlbert Herranz } 4277657c3a7SAlbert Herranz 42880872e21SWolfram Sang static unsigned int esdhc_of_get_min_clock(struct sdhci_host *host) 4297657c3a7SAlbert Herranz { 430e307148fSShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 431*19c3a0efSyangbo lu struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 432*19c3a0efSyangbo lu unsigned int clock; 4337657c3a7SAlbert Herranz 434*19c3a0efSyangbo lu if (esdhc->peripheral_clock) 435*19c3a0efSyangbo lu clock = esdhc->peripheral_clock; 436*19c3a0efSyangbo lu else 437*19c3a0efSyangbo lu clock = pltfm_host->clock; 438*19c3a0efSyangbo lu return clock / 256 / 16; 4397657c3a7SAlbert Herranz } 4407657c3a7SAlbert Herranz 441f060bc9cSJerry Huang static void esdhc_of_set_clock(struct sdhci_host *host, unsigned int clock) 442f060bc9cSJerry Huang { 443f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 4448605e7aeSJisheng Zhang struct sdhci_esdhc *esdhc = sdhci_pltfm_priv(pltfm_host); 445bd455029SJoakim Tjernlund int pre_div = 1; 446d31fc00aSDong Aisheng int div = 1; 447e87d2db2Syangbo lu u32 timeout; 448d31fc00aSDong Aisheng u32 temp; 449d31fc00aSDong Aisheng 4501650d0c7SRussell King host->mmc->actual_clock = 0; 4511650d0c7SRussell King 452d31fc00aSDong Aisheng if (clock == 0) 453373073efSRussell King return; 454d31fc00aSDong Aisheng 45577bd2f6fSYangbo Lu /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */ 456f4932cfdSyangbo lu if (esdhc->vendor_ver < VENDOR_V_23) 45777bd2f6fSYangbo Lu pre_div = 2; 45877bd2f6fSYangbo Lu 459f060bc9cSJerry Huang /* Workaround to reduce the clock frequency for p1010 esdhc */ 460f060bc9cSJerry Huang if (of_find_compatible_node(NULL, NULL, "fsl,p1010-esdhc")) { 461f060bc9cSJerry Huang if (clock > 20000000) 462f060bc9cSJerry Huang clock -= 5000000; 463f060bc9cSJerry Huang if (clock > 40000000) 464f060bc9cSJerry Huang clock -= 5000000; 465f060bc9cSJerry Huang } 466f060bc9cSJerry Huang 467d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 468e87d2db2Syangbo lu temp &= ~(ESDHC_CLOCK_SDCLKEN | ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | 469e87d2db2Syangbo lu ESDHC_CLOCK_PEREN | ESDHC_CLOCK_MASK); 470d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 471d31fc00aSDong Aisheng 472d31fc00aSDong Aisheng while (host->max_clk / pre_div / 16 > clock && pre_div < 256) 473d31fc00aSDong Aisheng pre_div *= 2; 474d31fc00aSDong Aisheng 475d31fc00aSDong Aisheng while (host->max_clk / pre_div / div > clock && div < 16) 476d31fc00aSDong Aisheng div++; 477d31fc00aSDong Aisheng 478d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 479e76b8559SDong Aisheng clock, host->max_clk / pre_div / div); 480bd455029SJoakim Tjernlund host->mmc->actual_clock = host->max_clk / pre_div / div; 481d31fc00aSDong Aisheng pre_div >>= 1; 482d31fc00aSDong Aisheng div--; 483d31fc00aSDong Aisheng 484d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 485d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 486d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 487d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 488d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 489e87d2db2Syangbo lu 490e87d2db2Syangbo lu /* Wait max 20 ms */ 491e87d2db2Syangbo lu timeout = 20; 492e87d2db2Syangbo lu while (!(sdhci_readl(host, ESDHC_PRSSTAT) & ESDHC_CLOCK_STABLE)) { 493e87d2db2Syangbo lu if (timeout == 0) { 494e87d2db2Syangbo lu pr_err("%s: Internal clock never stabilised.\n", 495e87d2db2Syangbo lu mmc_hostname(host->mmc)); 496e87d2db2Syangbo lu return; 497e87d2db2Syangbo lu } 498e87d2db2Syangbo lu timeout--; 499d31fc00aSDong Aisheng mdelay(1); 500f060bc9cSJerry Huang } 501f060bc9cSJerry Huang 502e87d2db2Syangbo lu temp |= ESDHC_CLOCK_SDCLKEN; 503e87d2db2Syangbo lu sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 504e87d2db2Syangbo lu } 505e87d2db2Syangbo lu 5062317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 50766b50a00SOded Gabbay { 50866b50a00SOded Gabbay u32 ctrl; 50966b50a00SOded Gabbay 510f4932cfdSyangbo lu ctrl = sdhci_readl(host, ESDHC_PROCTL); 511f4932cfdSyangbo lu ctrl &= (~ESDHC_CTRL_BUSWIDTH_MASK); 51266b50a00SOded Gabbay switch (width) { 51366b50a00SOded Gabbay case MMC_BUS_WIDTH_8: 514f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_8BITBUS; 51566b50a00SOded Gabbay break; 51666b50a00SOded Gabbay 51766b50a00SOded Gabbay case MMC_BUS_WIDTH_4: 518f4932cfdSyangbo lu ctrl |= ESDHC_CTRL_4BITBUS; 51966b50a00SOded Gabbay break; 52066b50a00SOded Gabbay 52166b50a00SOded Gabbay default: 52266b50a00SOded Gabbay break; 52366b50a00SOded Gabbay } 52466b50a00SOded Gabbay 525f4932cfdSyangbo lu sdhci_writel(host, ctrl, ESDHC_PROCTL); 52666b50a00SOded Gabbay } 52766b50a00SOded Gabbay 528*19c3a0efSyangbo lu static void esdhc_clock_enable(struct sdhci_host *host, bool enable) 529*19c3a0efSyangbo lu { 530*19c3a0efSyangbo lu u32 val; 531*19c3a0efSyangbo lu ktime_t timeout; 532*19c3a0efSyangbo lu 533*19c3a0efSyangbo lu val = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 534*19c3a0efSyangbo lu 535*19c3a0efSyangbo lu if (enable) 536*19c3a0efSyangbo lu val |= ESDHC_CLOCK_SDCLKEN; 537*19c3a0efSyangbo lu else 538*19c3a0efSyangbo lu val &= ~ESDHC_CLOCK_SDCLKEN; 539*19c3a0efSyangbo lu 540*19c3a0efSyangbo lu sdhci_writel(host, val, ESDHC_SYSTEM_CONTROL); 541*19c3a0efSyangbo lu 542*19c3a0efSyangbo lu /* Wait max 20 ms */ 543*19c3a0efSyangbo lu timeout = ktime_add_ms(ktime_get(), 20); 544*19c3a0efSyangbo lu val = ESDHC_CLOCK_STABLE; 545*19c3a0efSyangbo lu while (!(sdhci_readl(host, ESDHC_PRSSTAT) & val)) { 546*19c3a0efSyangbo lu if (ktime_after(ktime_get(), timeout)) { 547*19c3a0efSyangbo lu pr_err("%s: Internal clock never stabilised.\n", 548*19c3a0efSyangbo lu mmc_hostname(host->mmc)); 549*19c3a0efSyangbo lu break; 550*19c3a0efSyangbo lu } 551*19c3a0efSyangbo lu udelay(10); 552*19c3a0efSyangbo lu } 553*19c3a0efSyangbo lu } 554*19c3a0efSyangbo lu 555304f0a98SAlessio Igor Bogani static void esdhc_reset(struct sdhci_host *host, u8 mask) 556304f0a98SAlessio Igor Bogani { 557304f0a98SAlessio Igor Bogani sdhci_reset(host, mask); 558304f0a98SAlessio Igor Bogani 559304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 560304f0a98SAlessio Igor Bogani sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 561304f0a98SAlessio Igor Bogani } 562304f0a98SAlessio Igor Bogani 5639e48b336SUlf Hansson #ifdef CONFIG_PM_SLEEP 564723f7924SRussell King static u32 esdhc_proctl; 565723f7924SRussell King static int esdhc_of_suspend(struct device *dev) 566723f7924SRussell King { 567723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 568723f7924SRussell King 569f4932cfdSyangbo lu esdhc_proctl = sdhci_readl(host, SDHCI_HOST_CONTROL); 570723f7924SRussell King 571d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 572d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 573d38dcad4SAdrian Hunter 574723f7924SRussell King return sdhci_suspend_host(host); 575723f7924SRussell King } 576723f7924SRussell King 57706732b84SUlf Hansson static int esdhc_of_resume(struct device *dev) 578723f7924SRussell King { 579723f7924SRussell King struct sdhci_host *host = dev_get_drvdata(dev); 580723f7924SRussell King int ret = sdhci_resume_host(host); 581723f7924SRussell King 582723f7924SRussell King if (ret == 0) { 583723f7924SRussell King /* Isn't this already done by sdhci_resume_host() ? --rmk */ 584723f7924SRussell King esdhc_of_enable_dma(host); 585f4932cfdSyangbo lu sdhci_writel(host, esdhc_proctl, SDHCI_HOST_CONTROL); 586723f7924SRussell King } 587723f7924SRussell King return ret; 588723f7924SRussell King } 589723f7924SRussell King #endif 590723f7924SRussell King 5919e48b336SUlf Hansson static SIMPLE_DEV_PM_OPS(esdhc_of_dev_pm_ops, 5929e48b336SUlf Hansson esdhc_of_suspend, 5939e48b336SUlf Hansson esdhc_of_resume); 5949e48b336SUlf Hansson 595f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_be_ops = { 596f4932cfdSyangbo lu .read_l = esdhc_be_readl, 597f4932cfdSyangbo lu .read_w = esdhc_be_readw, 598f4932cfdSyangbo lu .read_b = esdhc_be_readb, 599f4932cfdSyangbo lu .write_l = esdhc_be_writel, 600f4932cfdSyangbo lu .write_w = esdhc_be_writew, 601f4932cfdSyangbo lu .write_b = esdhc_be_writeb, 602f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 603f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 604f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 605f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 606f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 607f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 608f4932cfdSyangbo lu .reset = esdhc_reset, 609f4932cfdSyangbo lu .set_uhs_signaling = sdhci_set_uhs_signaling, 610f4932cfdSyangbo lu }; 611f4932cfdSyangbo lu 612f4932cfdSyangbo lu static const struct sdhci_ops sdhci_esdhc_le_ops = { 613f4932cfdSyangbo lu .read_l = esdhc_le_readl, 614f4932cfdSyangbo lu .read_w = esdhc_le_readw, 615f4932cfdSyangbo lu .read_b = esdhc_le_readb, 616f4932cfdSyangbo lu .write_l = esdhc_le_writel, 617f4932cfdSyangbo lu .write_w = esdhc_le_writew, 618f4932cfdSyangbo lu .write_b = esdhc_le_writeb, 619f4932cfdSyangbo lu .set_clock = esdhc_of_set_clock, 620f4932cfdSyangbo lu .enable_dma = esdhc_of_enable_dma, 621f4932cfdSyangbo lu .get_max_clock = esdhc_of_get_max_clock, 622f4932cfdSyangbo lu .get_min_clock = esdhc_of_get_min_clock, 623f4932cfdSyangbo lu .adma_workaround = esdhc_of_adma_workaround, 624f4932cfdSyangbo lu .set_bus_width = esdhc_pltfm_set_bus_width, 625f4932cfdSyangbo lu .reset = esdhc_reset, 626f4932cfdSyangbo lu .set_uhs_signaling = sdhci_set_uhs_signaling, 627f4932cfdSyangbo lu }; 628f4932cfdSyangbo lu 629f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_be_pdata = { 630e9acc77dSyangbo lu .quirks = ESDHC_DEFAULT_QUIRKS | 631e9acc77dSyangbo lu #ifdef CONFIG_PPC 632e9acc77dSyangbo lu SDHCI_QUIRK_BROKEN_CARD_DETECTION | 633e9acc77dSyangbo lu #endif 634e9acc77dSyangbo lu SDHCI_QUIRK_NO_CARD_NO_RESET | 635e9acc77dSyangbo lu SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 636f4932cfdSyangbo lu .ops = &sdhci_esdhc_be_ops, 6377657c3a7SAlbert Herranz }; 63838576af1SShawn Guo 639f4932cfdSyangbo lu static const struct sdhci_pltfm_data sdhci_esdhc_le_pdata = { 640e9acc77dSyangbo lu .quirks = ESDHC_DEFAULT_QUIRKS | 641e9acc77dSyangbo lu SDHCI_QUIRK_NO_CARD_NO_RESET | 642e9acc77dSyangbo lu SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC, 643f4932cfdSyangbo lu .ops = &sdhci_esdhc_le_ops, 644f4932cfdSyangbo lu }; 645f4932cfdSyangbo lu 646151ede40Syangbo lu static struct soc_device_attribute soc_incorrect_hostver[] = { 647151ede40Syangbo lu { .family = "QorIQ T4240", .revision = "1.0", }, 648151ede40Syangbo lu { .family = "QorIQ T4240", .revision = "2.0", }, 649151ede40Syangbo lu { }, 650151ede40Syangbo lu }; 651151ede40Syangbo lu 652f4932cfdSyangbo lu static void esdhc_init(struct platform_device *pdev, struct sdhci_host *host) 653f4932cfdSyangbo lu { 654f4932cfdSyangbo lu struct sdhci_pltfm_host *pltfm_host; 655f4932cfdSyangbo lu struct sdhci_esdhc *esdhc; 656*19c3a0efSyangbo lu struct device_node *np; 657*19c3a0efSyangbo lu struct clk *clk; 658*19c3a0efSyangbo lu u32 val; 659f4932cfdSyangbo lu u16 host_ver; 660f4932cfdSyangbo lu 661f4932cfdSyangbo lu pltfm_host = sdhci_priv(host); 6628605e7aeSJisheng Zhang esdhc = sdhci_pltfm_priv(pltfm_host); 663f4932cfdSyangbo lu 664f4932cfdSyangbo lu host_ver = sdhci_readw(host, SDHCI_HOST_VERSION); 665f4932cfdSyangbo lu esdhc->vendor_ver = (host_ver & SDHCI_VENDOR_VER_MASK) >> 666f4932cfdSyangbo lu SDHCI_VENDOR_VER_SHIFT; 667f4932cfdSyangbo lu esdhc->spec_ver = host_ver & SDHCI_SPEC_VER_MASK; 668151ede40Syangbo lu if (soc_device_match(soc_incorrect_hostver)) 669151ede40Syangbo lu esdhc->quirk_incorrect_hostver = true; 670151ede40Syangbo lu else 671151ede40Syangbo lu esdhc->quirk_incorrect_hostver = false; 672*19c3a0efSyangbo lu 673*19c3a0efSyangbo lu np = pdev->dev.of_node; 674*19c3a0efSyangbo lu clk = of_clk_get(np, 0); 675*19c3a0efSyangbo lu if (!IS_ERR(clk)) { 676*19c3a0efSyangbo lu /* 677*19c3a0efSyangbo lu * esdhc->peripheral_clock would be assigned with a value 678*19c3a0efSyangbo lu * which is eSDHC base clock when use periperal clock. 679*19c3a0efSyangbo lu * For ls1046a, the clock value got by common clk API is 680*19c3a0efSyangbo lu * peripheral clock while the eSDHC base clock is 1/2 681*19c3a0efSyangbo lu * peripheral clock. 682*19c3a0efSyangbo lu */ 683*19c3a0efSyangbo lu if (of_device_is_compatible(np, "fsl,ls1046a-esdhc")) 684*19c3a0efSyangbo lu esdhc->peripheral_clock = clk_get_rate(clk) / 2; 685*19c3a0efSyangbo lu else 686*19c3a0efSyangbo lu esdhc->peripheral_clock = clk_get_rate(clk); 687*19c3a0efSyangbo lu 688*19c3a0efSyangbo lu clk_put(clk); 689*19c3a0efSyangbo lu } 690*19c3a0efSyangbo lu 691*19c3a0efSyangbo lu if (esdhc->peripheral_clock) { 692*19c3a0efSyangbo lu esdhc_clock_enable(host, false); 693*19c3a0efSyangbo lu val = sdhci_readl(host, ESDHC_DMA_SYSCTL); 694*19c3a0efSyangbo lu val |= ESDHC_PERIPHERAL_CLK_SEL; 695*19c3a0efSyangbo lu sdhci_writel(host, val, ESDHC_DMA_SYSCTL); 696*19c3a0efSyangbo lu esdhc_clock_enable(host, true); 697*19c3a0efSyangbo lu } 698f4932cfdSyangbo lu } 699f4932cfdSyangbo lu 700c3be1efdSBill Pemberton static int sdhci_esdhc_probe(struct platform_device *pdev) 70138576af1SShawn Guo { 70266b50a00SOded Gabbay struct sdhci_host *host; 703dcaff04dSOded Gabbay struct device_node *np; 7041ef5e49eSyangbo lu struct sdhci_pltfm_host *pltfm_host; 7051ef5e49eSyangbo lu struct sdhci_esdhc *esdhc; 70666b50a00SOded Gabbay int ret; 70766b50a00SOded Gabbay 708f4932cfdSyangbo lu np = pdev->dev.of_node; 709f4932cfdSyangbo lu 710150d4240SJulia Lawall if (of_property_read_bool(np, "little-endian")) 7118605e7aeSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_le_pdata, 7128605e7aeSJisheng Zhang sizeof(struct sdhci_esdhc)); 713f4932cfdSyangbo lu else 7148605e7aeSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_be_pdata, 7158605e7aeSJisheng Zhang sizeof(struct sdhci_esdhc)); 716f4932cfdSyangbo lu 71766b50a00SOded Gabbay if (IS_ERR(host)) 71866b50a00SOded Gabbay return PTR_ERR(host); 71966b50a00SOded Gabbay 720f4932cfdSyangbo lu esdhc_init(pdev, host); 721f4932cfdSyangbo lu 72266b50a00SOded Gabbay sdhci_get_of_property(pdev); 72366b50a00SOded Gabbay 7241ef5e49eSyangbo lu pltfm_host = sdhci_priv(host); 7258605e7aeSJisheng Zhang esdhc = sdhci_pltfm_priv(pltfm_host); 7261ef5e49eSyangbo lu if (esdhc->vendor_ver == VENDOR_V_22) 7271ef5e49eSyangbo lu host->quirks2 |= SDHCI_QUIRK2_HOST_NO_CMD23; 7281ef5e49eSyangbo lu 7291ef5e49eSyangbo lu if (esdhc->vendor_ver > VENDOR_V_22) 7301ef5e49eSyangbo lu host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 7311ef5e49eSyangbo lu 73274fd5e30SYangbo Lu if (of_device_is_compatible(np, "fsl,p5040-esdhc") || 73374fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p5020-esdhc") || 73474fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p4080-esdhc") || 73574fd5e30SYangbo Lu of_device_is_compatible(np, "fsl,p1020-esdhc") || 736e9acc77dSyangbo lu of_device_is_compatible(np, "fsl,t1040-esdhc")) 73774fd5e30SYangbo Lu host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 73874fd5e30SYangbo Lu 739a22950c8Syangbo lu if (of_device_is_compatible(np, "fsl,ls1021a-esdhc")) 740a22950c8Syangbo lu host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 741a22950c8Syangbo lu 742dcaff04dSOded Gabbay if (of_device_is_compatible(np, "fsl,p2020-esdhc")) { 743dcaff04dSOded Gabbay /* 744dcaff04dSOded Gabbay * Freescale messed up with P2020 as it has a non-standard 745dcaff04dSOded Gabbay * host control register 746dcaff04dSOded Gabbay */ 747dcaff04dSOded Gabbay host->quirks2 |= SDHCI_QUIRK2_BROKEN_HOST_CONTROL; 748dcaff04dSOded Gabbay } 749dcaff04dSOded Gabbay 75066b50a00SOded Gabbay /* call to generic mmc_of_parse to support additional capabilities */ 751f0991408SUlf Hansson ret = mmc_of_parse(host->mmc); 752f0991408SUlf Hansson if (ret) 753f0991408SUlf Hansson goto err; 754f0991408SUlf Hansson 755490104acSHaijun Zhang mmc_of_parse_voltage(np, &host->ocr_mask); 75666b50a00SOded Gabbay 75766b50a00SOded Gabbay ret = sdhci_add_host(host); 75866b50a00SOded Gabbay if (ret) 759f0991408SUlf Hansson goto err; 76066b50a00SOded Gabbay 761f0991408SUlf Hansson return 0; 762f0991408SUlf Hansson err: 763f0991408SUlf Hansson sdhci_pltfm_free(pdev); 76466b50a00SOded Gabbay return ret; 76538576af1SShawn Guo } 76638576af1SShawn Guo 76738576af1SShawn Guo static const struct of_device_id sdhci_esdhc_of_match[] = { 76838576af1SShawn Guo { .compatible = "fsl,mpc8379-esdhc" }, 76938576af1SShawn Guo { .compatible = "fsl,mpc8536-esdhc" }, 77038576af1SShawn Guo { .compatible = "fsl,esdhc" }, 77138576af1SShawn Guo { } 77238576af1SShawn Guo }; 77338576af1SShawn Guo MODULE_DEVICE_TABLE(of, sdhci_esdhc_of_match); 77438576af1SShawn Guo 77538576af1SShawn Guo static struct platform_driver sdhci_esdhc_driver = { 77638576af1SShawn Guo .driver = { 77738576af1SShawn Guo .name = "sdhci-esdhc", 77838576af1SShawn Guo .of_match_table = sdhci_esdhc_of_match, 7799e48b336SUlf Hansson .pm = &esdhc_of_dev_pm_ops, 78038576af1SShawn Guo }, 78138576af1SShawn Guo .probe = sdhci_esdhc_probe, 782caebcae9SKevin Hao .remove = sdhci_pltfm_unregister, 78338576af1SShawn Guo }; 78438576af1SShawn Guo 785d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_driver); 78638576af1SShawn Guo 78738576af1SShawn Guo MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC"); 78838576af1SShawn Guo MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, " 78938576af1SShawn Guo "Anton Vorontsov <avorontsov@ru.mvista.com>"); 79038576af1SShawn Guo MODULE_LICENSE("GPL v2"); 791