1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller 4 * 5 * Copyright (C) 2018 Synaptics Incorporated 6 * 7 * Author: Jisheng Zhang <jszhang@kernel.org> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/arm-smccc.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/iopoll.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_domain.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reset.h> 23 #include <linux/sizes.h> 24 25 #include "sdhci-pltfm.h" 26 #include "cqhci.h" 27 28 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 29 30 /* DWCMSHC specific Mode Select value */ 31 #define DWCMSHC_CTRL_HS400 0x7 32 33 /* DWC IP vendor area 1 pointer */ 34 #define DWCMSHC_P_VENDOR_AREA1 0xe8 35 #define DWCMSHC_AREA1_MASK GENMASK(11, 0) 36 /* Offset inside the vendor area 1 */ 37 #define DWCMSHC_HOST_CTRL3 0x8 38 #define DWCMSHC_EMMC_CONTROL 0x2c 39 #define DWCMSHC_CARD_IS_EMMC BIT(0) 40 #define DWCMSHC_ENHANCED_STROBE BIT(8) 41 #define DWCMSHC_EMMC_ATCTRL 0x40 42 /* Tuning and auto-tuning fields in AT_CTRL_R control register */ 43 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ 44 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ 45 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ 46 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ 47 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ 48 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ 49 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ 50 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */ 51 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ 52 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ 53 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ 54 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ 55 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ 56 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ 57 58 /* DWC IP vendor area 2 pointer */ 59 #define DWCMSHC_P_VENDOR_AREA2 0xea 60 61 /* Sophgo CV18XX specific Registers */ 62 #define CV18XX_SDHCI_MSHC_CTRL 0x00 63 #define CV18XX_EMMC_FUNC_EN BIT(0) 64 #define CV18XX_LATANCY_1T BIT(1) 65 #define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40 66 #define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0) 67 #define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8) 68 #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1 69 #define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16) 70 #define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24) 71 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1 72 #define CV18XX_SDHCI_PHY_CONFIG 0x4c 73 #define CV18XX_PHY_TX_BPS BIT(0) 74 75 #define CV18XX_TUNE_MAX 128 76 #define CV18XX_TUNE_STEP 1 77 #define CV18XX_RETRY_TUNING_MAX 50 78 79 /* Rockchip specific Registers */ 80 #define DWCMSHC_EMMC_DLL_CTRL 0x800 81 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 82 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 83 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 84 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 85 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 86 #define DWCMSHC_EMMC_DLL_START BIT(0) 87 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 88 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 89 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 90 #define DWCMSHC_EMMC_DLL_START_POINT 16 91 #define DWCMSHC_EMMC_DLL_INC 8 92 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 93 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 94 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 95 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA 96 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 97 #define DLL_STRBIN_TAPNUM_DEFAULT 0x4 98 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 99 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 100 #define DLL_STRBIN_DELAY_NUM_OFFSET 16 101 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 102 #define DLL_RXCLK_NO_INVERTER 1 103 #define DLL_RXCLK_INVERTER 0 104 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 105 #define DLL_RXCLK_ORI_GATE BIT(31) 106 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 107 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 108 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 109 110 #define DLL_LOCK_WO_TMOUT(x) \ 111 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 112 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 113 114 /* PHY register area pointer */ 115 #define DWC_MSHC_PTR_PHY_R 0x300 116 117 /* PHY general configuration */ 118 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) 119 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ 120 #define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */ 121 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ 122 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ 123 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */ 124 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ 125 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ 126 #define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */ 127 128 /* PHY command/response pad settings */ 129 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) 130 131 /* PHY data pad settings */ 132 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) 133 134 /* PHY clock pad settings */ 135 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) 136 137 /* PHY strobe pad settings */ 138 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) 139 140 /* PHY reset pad settings */ 141 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) 142 143 /* Bitfields are common for all pad settings */ 144 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ 145 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ 146 147 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ 148 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ 149 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ 150 151 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ 152 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ 153 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ 154 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ 155 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */ 156 157 /* PHY CLK delay line settings */ 158 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) 159 #define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0) 160 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ 161 162 /* PHY CLK delay line delay code */ 163 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) 164 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ 165 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ 166 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ 167 168 #define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20) 169 #define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1) 170 171 /* PHY drift_cclk_rx delay line configuration setting */ 172 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) 173 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ 174 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ 175 #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */ 176 177 /* PHY DLL control settings */ 178 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) 179 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ 180 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ 181 182 /* PHY DLL configuration register 1 */ 183 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) 184 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ 185 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ 186 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ 187 188 /* PHY DLL configuration register 2 */ 189 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) 190 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ 191 192 /* PHY DLL master and slave delay line configuration settings */ 193 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) 194 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ 195 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ 196 197 #define FLAG_IO_FIXED_1V8 BIT(0) 198 199 #define BOUNDARY_OK(addr, len) \ 200 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) 201 202 #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 203 SDHCI_TRNS_BLK_CNT_EN | \ 204 SDHCI_TRNS_DMA) 205 206 /* SMC call for BlueField-3 eMMC RST_N */ 207 #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 208 209 enum dwcmshc_rk_type { 210 DWCMSHC_RK3568, 211 DWCMSHC_RK3588, 212 }; 213 214 struct rk35xx_priv { 215 struct reset_control *reset; 216 enum dwcmshc_rk_type devtype; 217 u8 txclk_tapnum; 218 }; 219 220 #define DWCMSHC_MAX_OTHER_CLKS 3 221 222 struct dwcmshc_priv { 223 struct clk *bus_clk; 224 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ 225 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */ 226 227 int num_other_clks; 228 struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS]; 229 230 void *priv; /* pointer to SoC private stuff */ 231 u16 delay_line; 232 u16 flags; 233 }; 234 235 struct dwcmshc_pltfm_data { 236 const struct sdhci_pltfm_data pdata; 237 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 238 void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 239 }; 240 241 static int dwcmshc_get_enable_other_clks(struct device *dev, 242 struct dwcmshc_priv *priv, 243 int num_clks, 244 const char * const clk_ids[]) 245 { 246 int err; 247 248 if (num_clks > DWCMSHC_MAX_OTHER_CLKS) 249 return -EINVAL; 250 251 for (int i = 0; i < num_clks; i++) 252 priv->other_clks[i].id = clk_ids[i]; 253 254 err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks); 255 if (err) { 256 dev_err(dev, "failed to get clocks %d\n", err); 257 return err; 258 } 259 260 err = clk_bulk_prepare_enable(num_clks, priv->other_clks); 261 if (err) 262 dev_err(dev, "failed to enable clocks %d\n", err); 263 264 priv->num_other_clks = num_clks; 265 266 return err; 267 } 268 269 /* 270 * If DMA addr spans 128MB boundary, we split the DMA transfer into two 271 * so that each DMA transfer doesn't exceed the boundary. 272 */ 273 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, 274 dma_addr_t addr, int len, unsigned int cmd) 275 { 276 int tmplen, offset; 277 278 if (likely(!len || BOUNDARY_OK(addr, len))) { 279 sdhci_adma_write_desc(host, desc, addr, len, cmd); 280 return; 281 } 282 283 offset = addr & (SZ_128M - 1); 284 tmplen = SZ_128M - offset; 285 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); 286 287 addr += tmplen; 288 len -= tmplen; 289 sdhci_adma_write_desc(host, desc, addr, len, cmd); 290 } 291 292 static void dwcmshc_reset(struct sdhci_host *host, u8 mask) 293 { 294 sdhci_reset(host, mask); 295 296 /* The dwcmshc does not comply with the SDHCI specification 297 * regarding the "Software Reset for CMD line should clear 'Command 298 * Complete' in the Normal Interrupt Status Register." Clear the bit 299 * here to compensate for this quirk. 300 */ 301 if (mask & SDHCI_RESET_CMD) 302 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); 303 } 304 305 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) 306 { 307 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 308 309 if (pltfm_host->clk) 310 return sdhci_pltfm_clk_get_max_clock(host); 311 else 312 return pltfm_host->clock; 313 } 314 315 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) 316 { 317 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 318 319 return clk_round_rate(pltfm_host->clk, ULONG_MAX); 320 } 321 322 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, 323 struct mmc_request *mrq) 324 { 325 struct sdhci_host *host = mmc_priv(mmc); 326 327 /* 328 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit 329 * block count register which doesn't support stuff bits of 330 * CMD23 argument on dwcmsch host controller. 331 */ 332 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) 333 host->flags &= ~SDHCI_AUTO_CMD23; 334 else 335 host->flags |= SDHCI_AUTO_CMD23; 336 } 337 338 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) 339 { 340 dwcmshc_check_auto_cmd23(mmc, mrq); 341 342 sdhci_request(mmc, mrq); 343 } 344 345 static void dwcmshc_phy_init(struct sdhci_host *host) 346 { 347 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 348 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 349 u32 rxsel = PHY_PAD_RXSEL_3V3; 350 u32 val; 351 352 if (priv->flags & FLAG_IO_FIXED_1V8 || 353 host->mmc->ios.timing & MMC_SIGNAL_VOLTAGE_180) 354 rxsel = PHY_PAD_RXSEL_1V8; 355 356 /* deassert phy reset & set tx drive strength */ 357 val = PHY_CNFG_RSTN_DEASSERT; 358 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); 359 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); 360 sdhci_writel(host, val, PHY_CNFG_R); 361 362 /* disable delay line */ 363 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); 364 365 /* set delay line */ 366 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); 367 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); 368 369 /* enable delay lane */ 370 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 371 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 372 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 373 374 /* configure phy pads */ 375 val = rxsel; 376 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 377 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 378 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 379 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 380 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 381 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 382 383 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 384 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 385 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 386 387 val = rxsel; 388 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 389 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 390 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 391 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 392 393 /* enable data strobe mode */ 394 if (rxsel == PHY_PAD_RXSEL_1V8) { 395 u8 sel = FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL); 396 397 sdhci_writeb(host, sel, PHY_DLLDL_CNFG_R); 398 } 399 400 /* enable phy dll */ 401 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); 402 403 } 404 405 static void th1520_sdhci_set_phy(struct sdhci_host *host) 406 { 407 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 408 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 409 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 410 u16 emmc_ctrl; 411 412 dwcmshc_phy_init(host); 413 414 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 415 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 416 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC; 417 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 418 } 419 420 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | 421 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); 422 } 423 424 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, 425 unsigned int timing) 426 { 427 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 428 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 429 u16 ctrl, ctrl_2; 430 431 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 432 /* Select Bus Speed Mode for host */ 433 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 434 if ((timing == MMC_TIMING_MMC_HS200) || 435 (timing == MMC_TIMING_UHS_SDR104)) 436 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 437 else if (timing == MMC_TIMING_UHS_SDR12) 438 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 439 else if ((timing == MMC_TIMING_UHS_SDR25) || 440 (timing == MMC_TIMING_MMC_HS)) 441 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 442 else if (timing == MMC_TIMING_UHS_SDR50) 443 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 444 else if ((timing == MMC_TIMING_UHS_DDR50) || 445 (timing == MMC_TIMING_MMC_DDR52)) 446 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 447 else if (timing == MMC_TIMING_MMC_HS400) { 448 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ 449 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 450 ctrl |= DWCMSHC_CARD_IS_EMMC; 451 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 452 453 ctrl_2 |= DWCMSHC_CTRL_HS400; 454 } 455 456 if (priv->flags & FLAG_IO_FIXED_1V8) 457 ctrl_2 |= SDHCI_CTRL_VDD_180; 458 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 459 } 460 461 static void th1520_set_uhs_signaling(struct sdhci_host *host, 462 unsigned int timing) 463 { 464 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 465 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 466 467 dwcmshc_set_uhs_signaling(host, timing); 468 if (timing == MMC_TIMING_MMC_HS400) 469 priv->delay_line = PHY_SDCLKDL_DC_HS400; 470 else 471 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); 472 th1520_sdhci_set_phy(host); 473 } 474 475 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, 476 struct mmc_ios *ios) 477 { 478 u32 vendor; 479 struct sdhci_host *host = mmc_priv(mmc); 480 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 481 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 482 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; 483 484 vendor = sdhci_readl(host, reg); 485 if (ios->enhanced_strobe) 486 vendor |= DWCMSHC_ENHANCED_STROBE; 487 else 488 vendor &= ~DWCMSHC_ENHANCED_STROBE; 489 490 sdhci_writel(host, vendor, reg); 491 } 492 493 static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode) 494 { 495 int err = sdhci_execute_tuning(mmc, opcode); 496 struct sdhci_host *host = mmc_priv(mmc); 497 498 if (err) 499 return err; 500 501 /* 502 * Tuning can leave the IP in an active state (Buffer Read Enable bit 503 * set) which prevents the entry to low power states (i.e. S0i3). Data 504 * reset will clear it. 505 */ 506 sdhci_reset(host, SDHCI_RESET_DATA); 507 508 return 0; 509 } 510 511 static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask) 512 { 513 int cmd_error = 0; 514 int data_error = 0; 515 516 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 517 return intmask; 518 519 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 520 521 return 0; 522 } 523 524 static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc) 525 { 526 struct sdhci_host *host = mmc_priv(mmc); 527 u8 ctrl; 528 529 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 530 531 sdhci_cqe_enable(mmc); 532 533 /* 534 * The "DesignWare Cores Mobile Storage Host Controller 535 * DWC_mshc / DWC_mshc_lite Databook" says: 536 * when Host Version 4 Enable" is 1 in Host Control 2 register, 537 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected. 538 * Selection of 32-bit/64-bit System Addressing: 539 * either 32-bit or 64-bit system addressing is selected by 540 * 64-bit Addressing bit in Host Control 2 register. 541 * 542 * On the other hand the "DesignWare Cores Mobile Storage Host 543 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to 544 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register. 545 */ 546 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 547 ctrl &= ~SDHCI_CTRL_DMA_MASK; 548 ctrl |= SDHCI_CTRL_ADMA32; 549 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 550 } 551 552 static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, 553 dma_addr_t addr, int len, bool end, bool dma64) 554 { 555 int tmplen, offset; 556 557 if (likely(!len || BOUNDARY_OK(addr, len))) { 558 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 559 return; 560 } 561 562 offset = addr & (SZ_128M - 1); 563 tmplen = SZ_128M - offset; 564 cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64); 565 566 addr += tmplen; 567 len -= tmplen; 568 *desc += cq_host->trans_desc_len; 569 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 570 } 571 572 static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc) 573 { 574 sdhci_dumpregs(mmc_priv(mmc)); 575 } 576 577 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 578 { 579 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 580 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 581 struct rk35xx_priv *priv = dwc_priv->priv; 582 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 583 u32 extra, reg; 584 int err; 585 586 host->mmc->actual_clock = 0; 587 588 if (clock == 0) { 589 /* Disable interface clock at initial state. */ 590 sdhci_set_clock(host, clock); 591 return; 592 } 593 594 /* Rockchip platform only support 375KHz for identify mode */ 595 if (clock <= 400000) 596 clock = 375000; 597 598 err = clk_set_rate(pltfm_host->clk, clock); 599 if (err) 600 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); 601 602 sdhci_set_clock(host, clock); 603 604 /* Disable cmd conflict check */ 605 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; 606 extra = sdhci_readl(host, reg); 607 extra &= ~BIT(0); 608 sdhci_writel(host, extra, reg); 609 610 if (clock <= 52000000) { 611 /* 612 * Disable DLL and reset both of sample and drive clock. 613 * The bypass bit and start bit need to be set if DLL is not locked. 614 */ 615 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); 616 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); 617 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 618 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 619 /* 620 * Before switching to hs400es mode, the driver will enable 621 * enhanced strobe first. PHY needs to configure the parameters 622 * of enhanced strobe first. 623 */ 624 extra = DWCMSHC_EMMC_DLL_DLYENA | 625 DLL_STRBIN_DELAY_NUM_SEL | 626 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; 627 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 628 return; 629 } 630 631 /* Reset DLL */ 632 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 633 udelay(1); 634 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); 635 636 /* 637 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but 638 * we must set it in higher speed mode. 639 */ 640 extra = DWCMSHC_EMMC_DLL_DLYENA; 641 if (priv->devtype == DWCMSHC_RK3568) 642 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 643 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 644 645 /* Init DLL settings */ 646 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 647 0x2 << DWCMSHC_EMMC_DLL_INC | 648 DWCMSHC_EMMC_DLL_START; 649 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 650 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, 651 extra, DLL_LOCK_WO_TMOUT(extra), 1, 652 500 * USEC_PER_MSEC); 653 if (err) { 654 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); 655 return; 656 } 657 658 extra = 0x1 << 16 | /* tune clock stop en */ 659 0x3 << 17 | /* pre-change delay */ 660 0x3 << 19; /* post-change delay */ 661 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 662 663 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || 664 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) 665 txclk_tapnum = priv->txclk_tapnum; 666 667 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 668 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; 669 670 extra = DLL_CMDOUT_SRC_CLK_NEG | 671 DLL_CMDOUT_EN_SRC_CLK_NEG | 672 DWCMSHC_EMMC_DLL_DLYENA | 673 DLL_CMDOUT_TAPNUM_90_DEGREES | 674 DLL_CMDOUT_TAPNUM_FROM_SW; 675 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 676 } 677 678 extra = DWCMSHC_EMMC_DLL_DLYENA | 679 DLL_TXCLK_TAPNUM_FROM_SW | 680 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | 681 txclk_tapnum; 682 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 683 684 extra = DWCMSHC_EMMC_DLL_DLYENA | 685 DLL_STRBIN_TAPNUM_DEFAULT | 686 DLL_STRBIN_TAPNUM_FROM_SW; 687 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 688 } 689 690 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) 691 { 692 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 693 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 694 struct rk35xx_priv *priv = dwc_priv->priv; 695 696 if (mask & SDHCI_RESET_ALL && priv->reset) { 697 reset_control_assert(priv->reset); 698 udelay(1); 699 reset_control_deassert(priv->reset); 700 } 701 702 sdhci_reset(host, mask); 703 } 704 705 static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host, 706 struct dwcmshc_priv *dwc_priv) 707 { 708 static const char * const clk_ids[] = {"axi", "block", "timer"}; 709 struct rk35xx_priv *priv; 710 int err; 711 712 priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 713 if (!priv) 714 return -ENOMEM; 715 716 if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc")) 717 priv->devtype = DWCMSHC_RK3588; 718 else 719 priv->devtype = DWCMSHC_RK3568; 720 721 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 722 if (IS_ERR(priv->reset)) { 723 err = PTR_ERR(priv->reset); 724 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 725 return err; 726 } 727 728 err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 729 ARRAY_SIZE(clk_ids), clk_ids); 730 if (err) 731 return err; 732 733 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 734 &priv->txclk_tapnum)) 735 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 736 737 /* Disable cmd conflict check */ 738 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 739 /* Reset previous settings */ 740 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 741 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 742 743 dwc_priv->priv = priv; 744 745 return 0; 746 } 747 748 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 749 { 750 /* 751 * Don't support highspeed bus mode with low clk speed as we 752 * cannot use DLL for this condition. 753 */ 754 if (host->mmc->f_max <= 52000000) { 755 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 756 host->mmc->f_max); 757 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 758 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 759 } 760 } 761 762 static void dwcmshc_rk3576_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 763 { 764 struct device *dev = mmc_dev(host->mmc); 765 int ret; 766 767 /* 768 * This works around the design of the RK3576's power domains, which 769 * makes the PD_NVM power domain, which the sdhci controller on the 770 * RK3576 is in, never come back the same way once it's run-time 771 * suspended once. This can happen during early kernel boot if no driver 772 * is using either PD_NVM or its child power domain PD_SDGMAC for a 773 * short moment, leading to it being turned off to save power. By 774 * keeping it on, sdhci suspending won't lead to PD_NVM becoming a 775 * candidate for getting turned off. 776 */ 777 ret = dev_pm_genpd_rpm_always_on(dev, true); 778 if (ret && ret != -EOPNOTSUPP) 779 dev_warn(dev, "failed to set PD rpm always on, SoC may hang later: %pe\n", 780 ERR_PTR(ret)); 781 782 dwcmshc_rk35xx_postinit(host, dwc_priv); 783 } 784 785 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) 786 { 787 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 788 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 789 u32 val = 0; 790 791 if (host->flags & SDHCI_HS400_TUNING) 792 return 0; 793 794 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL), 795 PHY_ATDL_CNFG_R); 796 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 797 798 /* 799 * configure tuning settings: 800 * - center phase select code driven in block gap interval 801 * - disable reporting of framing errors 802 * - disable software managed tuning 803 * - disable user selection of sampling window edges, 804 * instead tuning calculated edges are used 805 */ 806 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | 807 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); 808 809 /* 810 * configure tuning settings: 811 * - enable auto-tuning 812 * - enable sampling window threshold 813 * - stop clocks during phase code change 814 * - set max latency in cycles between tx and rx clocks 815 * - set max latency in cycles to switch output phase 816 * - set max sampling window threshold value 817 */ 818 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; 819 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); 820 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); 821 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); 822 823 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 824 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 825 826 /* perform tuning */ 827 sdhci_start_tuning(host); 828 host->tuning_loop_count = 128; 829 host->tuning_err = __sdhci_execute_tuning(host, opcode); 830 if (host->tuning_err) { 831 /* disable auto-tuning upon tuning error */ 832 val &= ~AT_CTRL_AT_EN; 833 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 834 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); 835 return -EIO; 836 } 837 sdhci_end_tuning(host); 838 839 return 0; 840 } 841 842 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) 843 { 844 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 845 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 846 u16 ctrl_2; 847 848 dwcmshc_reset(host, mask); 849 850 if (priv->flags & FLAG_IO_FIXED_1V8) { 851 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 852 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) { 853 ctrl_2 |= SDHCI_CTRL_VDD_180; 854 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 855 } 856 } 857 } 858 859 static int th1520_init(struct device *dev, 860 struct sdhci_host *host, 861 struct dwcmshc_priv *dwc_priv) 862 { 863 dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; 864 865 if (device_property_read_bool(dev, "mmc-ddr-1_8v") || 866 device_property_read_bool(dev, "mmc-hs200-1_8v") || 867 device_property_read_bool(dev, "mmc-hs400-1_8v")) 868 dwc_priv->flags |= FLAG_IO_FIXED_1V8; 869 else 870 dwc_priv->flags &= ~FLAG_IO_FIXED_1V8; 871 872 /* 873 * start_signal_voltage_switch() will try 3.3V first 874 * then 1.8V. Use SDHCI_SIGNALING_180 rather than 875 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V 876 * in sdhci_start_signal_voltage_switch(). 877 */ 878 if (dwc_priv->flags & FLAG_IO_FIXED_1V8) { 879 host->flags &= ~SDHCI_SIGNALING_330; 880 host->flags |= SDHCI_SIGNALING_180; 881 } 882 883 sdhci_enable_v4_mode(host); 884 885 return 0; 886 } 887 888 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) 889 { 890 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 891 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 892 u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 893 894 dwcmshc_reset(host, mask); 895 896 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 897 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 898 val |= CV18XX_EMMC_FUNC_EN; 899 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 900 } 901 902 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 903 val |= CV18XX_LATANCY_1T; 904 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 905 906 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 907 val |= CV18XX_PHY_TX_BPS; 908 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 909 910 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 911 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 912 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) | 913 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK)); 914 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 915 } 916 917 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap) 918 { 919 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 920 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 921 u16 clk; 922 u32 val; 923 924 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 925 clk &= ~SDHCI_CLOCK_CARD_EN; 926 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 927 928 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 929 val &= ~CV18XX_LATANCY_1T; 930 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 931 932 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 933 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 934 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap)); 935 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 936 937 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 938 939 clk |= SDHCI_CLOCK_CARD_EN; 940 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 941 usleep_range(1000, 2000); 942 } 943 944 static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error) 945 { 946 int ret, retry = 0; 947 948 while (retry < CV18XX_RETRY_TUNING_MAX) { 949 ret = mmc_send_tuning(mmc, opcode, NULL); 950 if (ret) 951 return ret; 952 retry++; 953 } 954 955 return 0; 956 } 957 958 static void cv18xx_sdhci_post_tuning(struct sdhci_host *host) 959 { 960 u32 val; 961 962 val = sdhci_readl(host, SDHCI_INT_STATUS); 963 val |= SDHCI_INT_DATA_AVAIL; 964 sdhci_writel(host, val, SDHCI_INT_STATUS); 965 966 dwcmshc_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 967 } 968 969 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 970 { 971 int min, max, avg, ret; 972 int win_length, target_min, target_max, target_win_length; 973 974 min = max = 0; 975 target_win_length = 0; 976 977 sdhci_reset_tuning(host); 978 979 while (max < CV18XX_TUNE_MAX) { 980 /* find the mininum delay first which can pass tuning */ 981 while (min < CV18XX_TUNE_MAX) { 982 cv18xx_sdhci_set_tap(host, min); 983 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL)) 984 break; 985 min += CV18XX_TUNE_STEP; 986 } 987 988 /* find the maxinum delay which can not pass tuning */ 989 max = min + CV18XX_TUNE_STEP; 990 while (max < CV18XX_TUNE_MAX) { 991 cv18xx_sdhci_set_tap(host, max); 992 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) { 993 max -= CV18XX_TUNE_STEP; 994 break; 995 } 996 max += CV18XX_TUNE_STEP; 997 } 998 999 win_length = max - min + 1; 1000 /* get the largest pass window */ 1001 if (win_length > target_win_length) { 1002 target_win_length = win_length; 1003 target_min = min; 1004 target_max = max; 1005 } 1006 1007 /* continue to find the next pass window */ 1008 min = max + CV18XX_TUNE_STEP; 1009 } 1010 1011 cv18xx_sdhci_post_tuning(host); 1012 1013 /* use average delay to get the best timing */ 1014 avg = (target_min + target_max) / 2; 1015 cv18xx_sdhci_set_tap(host, avg); 1016 ret = mmc_send_tuning(host->mmc, opcode, NULL); 1017 1018 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 1019 ret ? "failed" : "passed", avg, ret); 1020 1021 return ret; 1022 } 1023 1024 static inline void sg2042_sdhci_phy_init(struct sdhci_host *host) 1025 { 1026 u32 val; 1027 1028 /* Asset phy reset & set tx drive strength */ 1029 val = sdhci_readl(host, PHY_CNFG_R); 1030 val &= ~PHY_CNFG_RSTN_DEASSERT; 1031 val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1); 1032 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042); 1033 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042); 1034 sdhci_writel(host, val, PHY_CNFG_R); 1035 1036 /* Configure phy pads */ 1037 val = PHY_PAD_RXSEL_3V3; 1038 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 1039 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1040 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1041 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 1042 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 1043 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 1044 1045 val = PHY_PAD_RXSEL_3V3; 1046 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1047 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1048 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 1049 1050 val = PHY_PAD_RXSEL_3V3; 1051 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 1052 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1053 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1054 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 1055 1056 /* Configure delay line */ 1057 /* Enable fixed delay */ 1058 sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R); 1059 /* 1060 * Set delay line. 1061 * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written. 1062 * Ensure UPDATE_DC[4] is '0' when not updating code. 1063 */ 1064 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 1065 val |= PHY_SDCLKDL_CNFG_UPDATE; 1066 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 1067 /* Add 10 * 70ps = 0.7ns for output delay */ 1068 sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R); 1069 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 1070 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 1071 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 1072 1073 /* Set SMPLDL_CNFG, Bypass */ 1074 sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R); 1075 1076 /* Set ATDL_CNFG, tuning clk not use for init */ 1077 val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042); 1078 sdhci_writeb(host, val, PHY_ATDL_CNFG_R); 1079 1080 /* Deasset phy reset */ 1081 val = sdhci_readl(host, PHY_CNFG_R); 1082 val |= PHY_CNFG_RSTN_DEASSERT; 1083 sdhci_writel(host, val, PHY_CNFG_R); 1084 } 1085 1086 static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask) 1087 { 1088 sdhci_reset(host, mask); 1089 1090 if (mask & SDHCI_RESET_ALL) 1091 sg2042_sdhci_phy_init(host); 1092 } 1093 1094 static int sg2042_init(struct device *dev, struct sdhci_host *host, 1095 struct dwcmshc_priv *dwc_priv) 1096 { 1097 static const char * const clk_ids[] = {"timer"}; 1098 1099 return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 1100 ARRAY_SIZE(clk_ids), clk_ids); 1101 } 1102 1103 static const struct sdhci_ops sdhci_dwcmshc_ops = { 1104 .set_clock = sdhci_set_clock, 1105 .set_bus_width = sdhci_set_bus_width, 1106 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1107 .get_max_clock = dwcmshc_get_max_clock, 1108 .reset = dwcmshc_reset, 1109 .adma_write_desc = dwcmshc_adma_write_desc, 1110 .irq = dwcmshc_cqe_irq_handler, 1111 }; 1112 1113 #ifdef CONFIG_ACPI 1114 static void dwcmshc_bf3_hw_reset(struct sdhci_host *host) 1115 { 1116 struct arm_smccc_res res = { 0 }; 1117 1118 arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res); 1119 1120 if (res.a0) 1121 pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc)); 1122 } 1123 1124 static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = { 1125 .set_clock = sdhci_set_clock, 1126 .set_bus_width = sdhci_set_bus_width, 1127 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1128 .get_max_clock = dwcmshc_get_max_clock, 1129 .reset = sdhci_reset, 1130 .adma_write_desc = dwcmshc_adma_write_desc, 1131 .irq = dwcmshc_cqe_irq_handler, 1132 .hw_reset = dwcmshc_bf3_hw_reset, 1133 }; 1134 #endif 1135 1136 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { 1137 .set_clock = dwcmshc_rk3568_set_clock, 1138 .set_bus_width = sdhci_set_bus_width, 1139 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1140 .get_max_clock = rk35xx_get_max_clock, 1141 .reset = rk35xx_sdhci_reset, 1142 .adma_write_desc = dwcmshc_adma_write_desc, 1143 .irq = dwcmshc_cqe_irq_handler, 1144 }; 1145 1146 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { 1147 .set_clock = sdhci_set_clock, 1148 .set_bus_width = sdhci_set_bus_width, 1149 .set_uhs_signaling = th1520_set_uhs_signaling, 1150 .get_max_clock = dwcmshc_get_max_clock, 1151 .reset = th1520_sdhci_reset, 1152 .adma_write_desc = dwcmshc_adma_write_desc, 1153 .voltage_switch = dwcmshc_phy_init, 1154 .platform_execute_tuning = th1520_execute_tuning, 1155 }; 1156 1157 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { 1158 .set_clock = sdhci_set_clock, 1159 .set_bus_width = sdhci_set_bus_width, 1160 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1161 .get_max_clock = dwcmshc_get_max_clock, 1162 .reset = cv18xx_sdhci_reset, 1163 .adma_write_desc = dwcmshc_adma_write_desc, 1164 .platform_execute_tuning = cv18xx_sdhci_execute_tuning, 1165 }; 1166 1167 static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { 1168 .set_clock = sdhci_set_clock, 1169 .set_bus_width = sdhci_set_bus_width, 1170 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1171 .get_max_clock = dwcmshc_get_max_clock, 1172 .reset = sg2042_sdhci_reset, 1173 .adma_write_desc = dwcmshc_adma_write_desc, 1174 .platform_execute_tuning = th1520_execute_tuning, 1175 }; 1176 1177 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { 1178 .pdata = { 1179 .ops = &sdhci_dwcmshc_ops, 1180 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1181 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1182 }, 1183 }; 1184 1185 #ifdef CONFIG_ACPI 1186 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = { 1187 .pdata = { 1188 .ops = &sdhci_dwcmshc_bf3_ops, 1189 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1190 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1191 SDHCI_QUIRK2_ACMD23_BROKEN, 1192 }, 1193 }; 1194 #endif 1195 1196 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 1197 .pdata = { 1198 .ops = &sdhci_dwcmshc_rk35xx_ops, 1199 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1200 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 1201 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1202 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 1203 }, 1204 .init = dwcmshc_rk35xx_init, 1205 .postinit = dwcmshc_rk35xx_postinit, 1206 }; 1207 1208 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk3576_pdata = { 1209 .pdata = { 1210 .ops = &sdhci_dwcmshc_rk35xx_ops, 1211 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1212 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 1213 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1214 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 1215 }, 1216 .init = dwcmshc_rk35xx_init, 1217 .postinit = dwcmshc_rk3576_postinit, 1218 }; 1219 1220 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { 1221 .pdata = { 1222 .ops = &sdhci_dwcmshc_th1520_ops, 1223 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1224 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1225 }, 1226 .init = th1520_init, 1227 }; 1228 1229 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { 1230 .pdata = { 1231 .ops = &sdhci_dwcmshc_cv18xx_ops, 1232 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1233 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1234 }, 1235 }; 1236 1237 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { 1238 .pdata = { 1239 .ops = &sdhci_dwcmshc_sg2042_ops, 1240 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1241 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1242 }, 1243 .init = sg2042_init, 1244 }; 1245 1246 static const struct cqhci_host_ops dwcmshc_cqhci_ops = { 1247 .enable = dwcmshc_sdhci_cqe_enable, 1248 .disable = sdhci_cqe_disable, 1249 .dumpregs = dwcmshc_cqhci_dumpregs, 1250 .set_tran_desc = dwcmshc_set_tran_desc, 1251 }; 1252 1253 static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev) 1254 { 1255 struct cqhci_host *cq_host; 1256 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1257 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1258 bool dma64 = false; 1259 u16 clk; 1260 int err; 1261 1262 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1263 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1264 if (!cq_host) { 1265 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n"); 1266 goto dsbl_cqe_caps; 1267 } 1268 1269 /* 1270 * For dwcmshc host controller we have to enable internal clock 1271 * before access to some registers from Vendor Specific Area 2. 1272 */ 1273 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1274 clk |= SDHCI_CLOCK_INT_EN; 1275 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1276 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1277 if (!(clk & SDHCI_CLOCK_INT_EN)) { 1278 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n"); 1279 goto free_cq_host; 1280 } 1281 1282 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; 1283 cq_host->ops = &dwcmshc_cqhci_ops; 1284 1285 /* Enable using of 128-bit task descriptors */ 1286 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1287 if (dma64) { 1288 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n"); 1289 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1290 } 1291 err = cqhci_init(cq_host, host->mmc, dma64); 1292 if (err) { 1293 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err); 1294 goto int_clock_disable; 1295 } 1296 1297 dev_dbg(mmc_dev(host->mmc), "CQE init done\n"); 1298 1299 return; 1300 1301 int_clock_disable: 1302 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1303 clk &= ~SDHCI_CLOCK_INT_EN; 1304 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1305 1306 free_cq_host: 1307 devm_kfree(&pdev->dev, cq_host); 1308 1309 dsbl_cqe_caps: 1310 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); 1311 } 1312 1313 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { 1314 { 1315 .compatible = "rockchip,rk3588-dwcmshc", 1316 .data = &sdhci_dwcmshc_rk35xx_pdata, 1317 }, 1318 { 1319 .compatible = "rockchip,rk3576-dwcmshc", 1320 .data = &sdhci_dwcmshc_rk3576_pdata, 1321 }, 1322 { 1323 .compatible = "rockchip,rk3568-dwcmshc", 1324 .data = &sdhci_dwcmshc_rk35xx_pdata, 1325 }, 1326 { 1327 .compatible = "snps,dwcmshc-sdhci", 1328 .data = &sdhci_dwcmshc_pdata, 1329 }, 1330 { 1331 .compatible = "sophgo,cv1800b-dwcmshc", 1332 .data = &sdhci_dwcmshc_cv18xx_pdata, 1333 }, 1334 { 1335 .compatible = "sophgo,sg2002-dwcmshc", 1336 .data = &sdhci_dwcmshc_cv18xx_pdata, 1337 }, 1338 { 1339 .compatible = "thead,th1520-dwcmshc", 1340 .data = &sdhci_dwcmshc_th1520_pdata, 1341 }, 1342 { 1343 .compatible = "sophgo,sg2042-dwcmshc", 1344 .data = &sdhci_dwcmshc_sg2042_pdata, 1345 }, 1346 {}, 1347 }; 1348 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); 1349 1350 #ifdef CONFIG_ACPI 1351 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { 1352 { 1353 .id = "MLNXBF30", 1354 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata, 1355 }, 1356 {} 1357 }; 1358 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids); 1359 #endif 1360 1361 static int dwcmshc_probe(struct platform_device *pdev) 1362 { 1363 struct device *dev = &pdev->dev; 1364 struct sdhci_pltfm_host *pltfm_host; 1365 struct sdhci_host *host; 1366 struct dwcmshc_priv *priv; 1367 const struct dwcmshc_pltfm_data *pltfm_data; 1368 int err; 1369 u32 extra, caps; 1370 1371 pltfm_data = device_get_match_data(&pdev->dev); 1372 if (!pltfm_data) { 1373 dev_err(&pdev->dev, "Error: No device match data found\n"); 1374 return -ENODEV; 1375 } 1376 1377 host = sdhci_pltfm_init(pdev, &pltfm_data->pdata, 1378 sizeof(struct dwcmshc_priv)); 1379 if (IS_ERR(host)) 1380 return PTR_ERR(host); 1381 1382 /* 1383 * extra adma table cnt for cross 128M boundary handling. 1384 */ 1385 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); 1386 if (extra > SDHCI_MAX_SEGS) 1387 extra = SDHCI_MAX_SEGS; 1388 host->adma_table_cnt += extra; 1389 1390 pltfm_host = sdhci_priv(host); 1391 priv = sdhci_pltfm_priv(pltfm_host); 1392 1393 if (dev->of_node) { 1394 pltfm_host->clk = devm_clk_get(dev, "core"); 1395 if (IS_ERR(pltfm_host->clk)) 1396 return dev_err_probe(dev, PTR_ERR(pltfm_host->clk), 1397 "failed to get core clk\n"); 1398 1399 err = clk_prepare_enable(pltfm_host->clk); 1400 if (err) 1401 return err; 1402 1403 priv->bus_clk = devm_clk_get(dev, "bus"); 1404 if (!IS_ERR(priv->bus_clk)) 1405 clk_prepare_enable(priv->bus_clk); 1406 } 1407 1408 err = mmc_of_parse(host->mmc); 1409 if (err) 1410 goto err_clk; 1411 1412 sdhci_get_of_property(pdev); 1413 1414 priv->vendor_specific_area1 = 1415 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; 1416 1417 host->mmc_host_ops.request = dwcmshc_request; 1418 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 1419 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; 1420 1421 if (pltfm_data->init) { 1422 err = pltfm_data->init(&pdev->dev, host, priv); 1423 if (err) 1424 goto err_clk; 1425 } 1426 1427 #ifdef CONFIG_ACPI 1428 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) 1429 sdhci_enable_v4_mode(host); 1430 #endif 1431 1432 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 1433 if (caps & SDHCI_CAN_64BIT_V4) 1434 sdhci_enable_v4_mode(host); 1435 1436 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1437 1438 pm_runtime_get_noresume(dev); 1439 pm_runtime_set_active(dev); 1440 pm_runtime_enable(dev); 1441 1442 err = sdhci_setup_host(host); 1443 if (err) 1444 goto err_rpm; 1445 1446 /* Setup Command Queue Engine if enabled */ 1447 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 1448 priv->vendor_specific_area2 = 1449 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2); 1450 1451 dwcmshc_cqhci_init(host, pdev); 1452 } 1453 1454 if (pltfm_data->postinit) 1455 pltfm_data->postinit(host, priv); 1456 1457 err = __sdhci_add_host(host); 1458 if (err) 1459 goto err_setup_host; 1460 1461 pm_runtime_put(dev); 1462 1463 return 0; 1464 1465 err_setup_host: 1466 sdhci_cleanup_host(host); 1467 err_rpm: 1468 pm_runtime_disable(dev); 1469 pm_runtime_put_noidle(dev); 1470 err_clk: 1471 clk_disable_unprepare(pltfm_host->clk); 1472 clk_disable_unprepare(priv->bus_clk); 1473 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1474 return err; 1475 } 1476 1477 static void dwcmshc_disable_card_clk(struct sdhci_host *host) 1478 { 1479 u16 ctrl; 1480 1481 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1482 if (ctrl & SDHCI_CLOCK_CARD_EN) { 1483 ctrl &= ~SDHCI_CLOCK_CARD_EN; 1484 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1485 } 1486 } 1487 1488 static void dwcmshc_remove(struct platform_device *pdev) 1489 { 1490 struct sdhci_host *host = platform_get_drvdata(pdev); 1491 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1492 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1493 1494 pm_runtime_get_sync(&pdev->dev); 1495 pm_runtime_disable(&pdev->dev); 1496 pm_runtime_put_noidle(&pdev->dev); 1497 1498 sdhci_remove_host(host, 0); 1499 1500 dwcmshc_disable_card_clk(host); 1501 1502 clk_disable_unprepare(pltfm_host->clk); 1503 clk_disable_unprepare(priv->bus_clk); 1504 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1505 } 1506 1507 static int dwcmshc_suspend(struct device *dev) 1508 { 1509 struct sdhci_host *host = dev_get_drvdata(dev); 1510 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1511 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1512 int ret; 1513 1514 pm_runtime_resume(dev); 1515 1516 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1517 ret = cqhci_suspend(host->mmc); 1518 if (ret) 1519 return ret; 1520 } 1521 1522 ret = sdhci_suspend_host(host); 1523 if (ret) 1524 return ret; 1525 1526 clk_disable_unprepare(pltfm_host->clk); 1527 if (!IS_ERR(priv->bus_clk)) 1528 clk_disable_unprepare(priv->bus_clk); 1529 1530 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1531 1532 return ret; 1533 } 1534 1535 static int dwcmshc_resume(struct device *dev) 1536 { 1537 struct sdhci_host *host = dev_get_drvdata(dev); 1538 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1539 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1540 int ret; 1541 1542 ret = clk_prepare_enable(pltfm_host->clk); 1543 if (ret) 1544 return ret; 1545 1546 if (!IS_ERR(priv->bus_clk)) { 1547 ret = clk_prepare_enable(priv->bus_clk); 1548 if (ret) 1549 goto disable_clk; 1550 } 1551 1552 ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks); 1553 if (ret) 1554 goto disable_bus_clk; 1555 1556 ret = sdhci_resume_host(host); 1557 if (ret) 1558 goto disable_other_clks; 1559 1560 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1561 ret = cqhci_resume(host->mmc); 1562 if (ret) 1563 goto disable_other_clks; 1564 } 1565 1566 return 0; 1567 1568 disable_other_clks: 1569 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1570 disable_bus_clk: 1571 if (!IS_ERR(priv->bus_clk)) 1572 clk_disable_unprepare(priv->bus_clk); 1573 disable_clk: 1574 clk_disable_unprepare(pltfm_host->clk); 1575 return ret; 1576 } 1577 1578 static void dwcmshc_enable_card_clk(struct sdhci_host *host) 1579 { 1580 u16 ctrl; 1581 1582 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1583 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { 1584 ctrl |= SDHCI_CLOCK_CARD_EN; 1585 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1586 } 1587 } 1588 1589 static int dwcmshc_runtime_suspend(struct device *dev) 1590 { 1591 struct sdhci_host *host = dev_get_drvdata(dev); 1592 1593 dwcmshc_disable_card_clk(host); 1594 1595 return 0; 1596 } 1597 1598 static int dwcmshc_runtime_resume(struct device *dev) 1599 { 1600 struct sdhci_host *host = dev_get_drvdata(dev); 1601 1602 dwcmshc_enable_card_clk(host); 1603 1604 return 0; 1605 } 1606 1607 static const struct dev_pm_ops dwcmshc_pmops = { 1608 SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume) 1609 RUNTIME_PM_OPS(dwcmshc_runtime_suspend, dwcmshc_runtime_resume, NULL) 1610 }; 1611 1612 static struct platform_driver sdhci_dwcmshc_driver = { 1613 .driver = { 1614 .name = "sdhci-dwcmshc", 1615 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1616 .of_match_table = sdhci_dwcmshc_dt_ids, 1617 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), 1618 .pm = pm_ptr(&dwcmshc_pmops), 1619 }, 1620 .probe = dwcmshc_probe, 1621 .remove = dwcmshc_remove, 1622 }; 1623 module_platform_driver(sdhci_dwcmshc_driver); 1624 1625 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC"); 1626 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); 1627 MODULE_LICENSE("GPL v2"); 1628