1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller 4 * 5 * Copyright (C) 2018 Synaptics Incorporated 6 * 7 * Author: Jisheng Zhang <jszhang@kernel.org> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/arm-smccc.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/iopoll.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <linux/sizes.h> 23 24 #include "sdhci-pltfm.h" 25 #include "cqhci.h" 26 27 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 28 29 /* DWCMSHC specific Mode Select value */ 30 #define DWCMSHC_CTRL_HS400 0x7 31 32 /* DWC IP vendor area 1 pointer */ 33 #define DWCMSHC_P_VENDOR_AREA1 0xe8 34 #define DWCMSHC_AREA1_MASK GENMASK(11, 0) 35 /* Offset inside the vendor area 1 */ 36 #define DWCMSHC_HOST_CTRL3 0x8 37 #define DWCMSHC_EMMC_CONTROL 0x2c 38 #define DWCMSHC_CARD_IS_EMMC BIT(0) 39 #define DWCMSHC_ENHANCED_STROBE BIT(8) 40 #define DWCMSHC_EMMC_ATCTRL 0x40 41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */ 42 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ 43 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ 44 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ 45 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ 46 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ 47 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ 48 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ 49 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */ 50 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ 51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ 52 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ 53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ 54 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ 55 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ 56 57 /* DWC IP vendor area 2 pointer */ 58 #define DWCMSHC_P_VENDOR_AREA2 0xea 59 60 /* Sophgo CV18XX specific Registers */ 61 #define CV18XX_SDHCI_MSHC_CTRL 0x00 62 #define CV18XX_EMMC_FUNC_EN BIT(0) 63 #define CV18XX_LATANCY_1T BIT(1) 64 #define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40 65 #define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0) 66 #define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8) 67 #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1 68 #define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16) 69 #define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24) 70 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1 71 #define CV18XX_SDHCI_PHY_CONFIG 0x4c 72 #define CV18XX_PHY_TX_BPS BIT(0) 73 74 #define CV18XX_TUNE_MAX 128 75 #define CV18XX_TUNE_STEP 1 76 #define CV18XX_RETRY_TUNING_MAX 50 77 78 /* Rockchip specific Registers */ 79 #define DWCMSHC_EMMC_DLL_CTRL 0x800 80 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 81 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 82 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 83 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 84 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 85 #define DWCMSHC_EMMC_DLL_START BIT(0) 86 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 87 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 88 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 89 #define DWCMSHC_EMMC_DLL_START_POINT 16 90 #define DWCMSHC_EMMC_DLL_INC 8 91 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 92 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 93 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 94 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA 95 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 96 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8 97 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 98 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 99 #define DLL_STRBIN_DELAY_NUM_OFFSET 16 100 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 101 #define DLL_RXCLK_NO_INVERTER 1 102 #define DLL_RXCLK_INVERTER 0 103 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 104 #define DLL_RXCLK_ORI_GATE BIT(31) 105 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 106 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 107 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 108 109 #define DLL_LOCK_WO_TMOUT(x) \ 110 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 111 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 112 113 /* PHY register area pointer */ 114 #define DWC_MSHC_PTR_PHY_R 0x300 115 116 /* PHY general configuration */ 117 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) 118 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ 119 #define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */ 120 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ 121 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ 122 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */ 123 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ 124 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ 125 #define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */ 126 127 /* PHY command/response pad settings */ 128 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) 129 130 /* PHY data pad settings */ 131 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) 132 133 /* PHY clock pad settings */ 134 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) 135 136 /* PHY strobe pad settings */ 137 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) 138 139 /* PHY reset pad settings */ 140 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) 141 142 /* Bitfields are common for all pad settings */ 143 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ 144 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ 145 146 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ 147 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ 148 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ 149 150 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ 151 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ 152 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ 153 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ 154 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */ 155 156 /* PHY CLK delay line settings */ 157 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) 158 #define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0) 159 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ 160 161 /* PHY CLK delay line delay code */ 162 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) 163 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ 164 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ 165 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ 166 167 #define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20) 168 #define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1) 169 170 /* PHY drift_cclk_rx delay line configuration setting */ 171 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) 172 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ 173 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ 174 #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */ 175 176 /* PHY DLL control settings */ 177 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) 178 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ 179 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ 180 181 /* PHY DLL configuration register 1 */ 182 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) 183 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ 184 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ 185 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ 186 187 /* PHY DLL configuration register 2 */ 188 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) 189 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ 190 191 /* PHY DLL master and slave delay line configuration settings */ 192 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) 193 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ 194 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ 195 196 #define FLAG_IO_FIXED_1V8 BIT(0) 197 198 #define BOUNDARY_OK(addr, len) \ 199 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) 200 201 #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 202 SDHCI_TRNS_BLK_CNT_EN | \ 203 SDHCI_TRNS_DMA) 204 205 /* SMC call for BlueField-3 eMMC RST_N */ 206 #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 207 208 enum dwcmshc_rk_type { 209 DWCMSHC_RK3568, 210 DWCMSHC_RK3588, 211 }; 212 213 struct rk35xx_priv { 214 struct reset_control *reset; 215 enum dwcmshc_rk_type devtype; 216 u8 txclk_tapnum; 217 }; 218 219 #define DWCMSHC_MAX_OTHER_CLKS 3 220 221 struct dwcmshc_priv { 222 struct clk *bus_clk; 223 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ 224 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */ 225 226 int num_other_clks; 227 struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS]; 228 229 void *priv; /* pointer to SoC private stuff */ 230 u16 delay_line; 231 u16 flags; 232 }; 233 234 struct dwcmshc_pltfm_data { 235 const struct sdhci_pltfm_data pdata; 236 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 237 void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 238 }; 239 240 static int dwcmshc_get_enable_other_clks(struct device *dev, 241 struct dwcmshc_priv *priv, 242 int num_clks, 243 const char * const clk_ids[]) 244 { 245 int err; 246 247 if (num_clks > DWCMSHC_MAX_OTHER_CLKS) 248 return -EINVAL; 249 250 for (int i = 0; i < num_clks; i++) 251 priv->other_clks[i].id = clk_ids[i]; 252 253 err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks); 254 if (err) { 255 dev_err(dev, "failed to get clocks %d\n", err); 256 return err; 257 } 258 259 err = clk_bulk_prepare_enable(num_clks, priv->other_clks); 260 if (err) 261 dev_err(dev, "failed to enable clocks %d\n", err); 262 263 priv->num_other_clks = num_clks; 264 265 return err; 266 } 267 268 /* 269 * If DMA addr spans 128MB boundary, we split the DMA transfer into two 270 * so that each DMA transfer doesn't exceed the boundary. 271 */ 272 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, 273 dma_addr_t addr, int len, unsigned int cmd) 274 { 275 int tmplen, offset; 276 277 if (likely(!len || BOUNDARY_OK(addr, len))) { 278 sdhci_adma_write_desc(host, desc, addr, len, cmd); 279 return; 280 } 281 282 offset = addr & (SZ_128M - 1); 283 tmplen = SZ_128M - offset; 284 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); 285 286 addr += tmplen; 287 len -= tmplen; 288 sdhci_adma_write_desc(host, desc, addr, len, cmd); 289 } 290 291 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) 292 { 293 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 294 295 if (pltfm_host->clk) 296 return sdhci_pltfm_clk_get_max_clock(host); 297 else 298 return pltfm_host->clock; 299 } 300 301 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) 302 { 303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 304 305 return clk_round_rate(pltfm_host->clk, ULONG_MAX); 306 } 307 308 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, 309 struct mmc_request *mrq) 310 { 311 struct sdhci_host *host = mmc_priv(mmc); 312 313 /* 314 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit 315 * block count register which doesn't support stuff bits of 316 * CMD23 argument on dwcmsch host controller. 317 */ 318 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) 319 host->flags &= ~SDHCI_AUTO_CMD23; 320 else 321 host->flags |= SDHCI_AUTO_CMD23; 322 } 323 324 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) 325 { 326 dwcmshc_check_auto_cmd23(mmc, mrq); 327 328 sdhci_request(mmc, mrq); 329 } 330 331 static void dwcmshc_phy_init(struct sdhci_host *host) 332 { 333 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 334 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 335 u32 rxsel = PHY_PAD_RXSEL_3V3; 336 u32 val; 337 338 if (priv->flags & FLAG_IO_FIXED_1V8 || 339 host->mmc->ios.timing & MMC_SIGNAL_VOLTAGE_180) 340 rxsel = PHY_PAD_RXSEL_1V8; 341 342 /* deassert phy reset & set tx drive strength */ 343 val = PHY_CNFG_RSTN_DEASSERT; 344 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); 345 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); 346 sdhci_writel(host, val, PHY_CNFG_R); 347 348 /* disable delay line */ 349 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); 350 351 /* set delay line */ 352 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); 353 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); 354 355 /* enable delay lane */ 356 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 357 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 358 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 359 360 /* configure phy pads */ 361 val = rxsel; 362 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 363 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 364 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 365 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 366 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 367 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 368 369 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 370 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 371 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 372 373 val = rxsel; 374 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 375 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 376 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 377 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 378 379 /* enable data strobe mode */ 380 if (rxsel == PHY_PAD_RXSEL_1V8) { 381 u8 sel = FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL); 382 383 sdhci_writeb(host, sel, PHY_DLLDL_CNFG_R); 384 } 385 386 /* enable phy dll */ 387 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); 388 389 } 390 391 static void th1520_sdhci_set_phy(struct sdhci_host *host) 392 { 393 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 394 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 395 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 396 u16 emmc_ctrl; 397 398 dwcmshc_phy_init(host); 399 400 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 401 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 402 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC; 403 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 404 } 405 406 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | 407 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); 408 } 409 410 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, 411 unsigned int timing) 412 { 413 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 414 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 415 u16 ctrl, ctrl_2; 416 417 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 418 /* Select Bus Speed Mode for host */ 419 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 420 if ((timing == MMC_TIMING_MMC_HS200) || 421 (timing == MMC_TIMING_UHS_SDR104)) 422 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 423 else if (timing == MMC_TIMING_UHS_SDR12) 424 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 425 else if ((timing == MMC_TIMING_UHS_SDR25) || 426 (timing == MMC_TIMING_MMC_HS)) 427 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 428 else if (timing == MMC_TIMING_UHS_SDR50) 429 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 430 else if ((timing == MMC_TIMING_UHS_DDR50) || 431 (timing == MMC_TIMING_MMC_DDR52)) 432 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 433 else if (timing == MMC_TIMING_MMC_HS400) { 434 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ 435 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 436 ctrl |= DWCMSHC_CARD_IS_EMMC; 437 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 438 439 ctrl_2 |= DWCMSHC_CTRL_HS400; 440 } 441 442 if (priv->flags & FLAG_IO_FIXED_1V8) 443 ctrl_2 |= SDHCI_CTRL_VDD_180; 444 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 445 } 446 447 static void th1520_set_uhs_signaling(struct sdhci_host *host, 448 unsigned int timing) 449 { 450 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 451 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 452 453 dwcmshc_set_uhs_signaling(host, timing); 454 if (timing == MMC_TIMING_MMC_HS400) 455 priv->delay_line = PHY_SDCLKDL_DC_HS400; 456 else 457 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); 458 th1520_sdhci_set_phy(host); 459 } 460 461 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, 462 struct mmc_ios *ios) 463 { 464 u32 vendor; 465 struct sdhci_host *host = mmc_priv(mmc); 466 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 467 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 468 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; 469 470 vendor = sdhci_readl(host, reg); 471 if (ios->enhanced_strobe) 472 vendor |= DWCMSHC_ENHANCED_STROBE; 473 else 474 vendor &= ~DWCMSHC_ENHANCED_STROBE; 475 476 sdhci_writel(host, vendor, reg); 477 } 478 479 static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode) 480 { 481 int err = sdhci_execute_tuning(mmc, opcode); 482 struct sdhci_host *host = mmc_priv(mmc); 483 484 if (err) 485 return err; 486 487 /* 488 * Tuning can leave the IP in an active state (Buffer Read Enable bit 489 * set) which prevents the entry to low power states (i.e. S0i3). Data 490 * reset will clear it. 491 */ 492 sdhci_reset(host, SDHCI_RESET_DATA); 493 494 return 0; 495 } 496 497 static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask) 498 { 499 int cmd_error = 0; 500 int data_error = 0; 501 502 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 503 return intmask; 504 505 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 506 507 return 0; 508 } 509 510 static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc) 511 { 512 struct sdhci_host *host = mmc_priv(mmc); 513 u8 ctrl; 514 515 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 516 517 sdhci_cqe_enable(mmc); 518 519 /* 520 * The "DesignWare Cores Mobile Storage Host Controller 521 * DWC_mshc / DWC_mshc_lite Databook" says: 522 * when Host Version 4 Enable" is 1 in Host Control 2 register, 523 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected. 524 * Selection of 32-bit/64-bit System Addressing: 525 * either 32-bit or 64-bit system addressing is selected by 526 * 64-bit Addressing bit in Host Control 2 register. 527 * 528 * On the other hand the "DesignWare Cores Mobile Storage Host 529 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to 530 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register. 531 */ 532 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 533 ctrl &= ~SDHCI_CTRL_DMA_MASK; 534 ctrl |= SDHCI_CTRL_ADMA32; 535 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 536 } 537 538 static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, 539 dma_addr_t addr, int len, bool end, bool dma64) 540 { 541 int tmplen, offset; 542 543 if (likely(!len || BOUNDARY_OK(addr, len))) { 544 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 545 return; 546 } 547 548 offset = addr & (SZ_128M - 1); 549 tmplen = SZ_128M - offset; 550 cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64); 551 552 addr += tmplen; 553 len -= tmplen; 554 *desc += cq_host->trans_desc_len; 555 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 556 } 557 558 static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc) 559 { 560 sdhci_dumpregs(mmc_priv(mmc)); 561 } 562 563 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 564 { 565 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 566 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 567 struct rk35xx_priv *priv = dwc_priv->priv; 568 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 569 u32 extra, reg; 570 int err; 571 572 host->mmc->actual_clock = 0; 573 574 if (clock == 0) { 575 /* Disable interface clock at initial state. */ 576 sdhci_set_clock(host, clock); 577 return; 578 } 579 580 /* Rockchip platform only support 375KHz for identify mode */ 581 if (clock <= 400000) 582 clock = 375000; 583 584 err = clk_set_rate(pltfm_host->clk, clock); 585 if (err) 586 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); 587 588 sdhci_set_clock(host, clock); 589 590 /* Disable cmd conflict check */ 591 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; 592 extra = sdhci_readl(host, reg); 593 extra &= ~BIT(0); 594 sdhci_writel(host, extra, reg); 595 596 if (clock <= 52000000) { 597 /* 598 * Disable DLL and reset both of sample and drive clock. 599 * The bypass bit and start bit need to be set if DLL is not locked. 600 */ 601 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); 602 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); 603 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 604 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 605 /* 606 * Before switching to hs400es mode, the driver will enable 607 * enhanced strobe first. PHY needs to configure the parameters 608 * of enhanced strobe first. 609 */ 610 extra = DWCMSHC_EMMC_DLL_DLYENA | 611 DLL_STRBIN_DELAY_NUM_SEL | 612 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; 613 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 614 return; 615 } 616 617 /* Reset DLL */ 618 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 619 udelay(1); 620 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); 621 622 /* 623 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but 624 * we must set it in higher speed mode. 625 */ 626 extra = DWCMSHC_EMMC_DLL_DLYENA; 627 if (priv->devtype == DWCMSHC_RK3568) 628 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 629 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 630 631 /* Init DLL settings */ 632 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 633 0x2 << DWCMSHC_EMMC_DLL_INC | 634 DWCMSHC_EMMC_DLL_START; 635 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 636 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, 637 extra, DLL_LOCK_WO_TMOUT(extra), 1, 638 500 * USEC_PER_MSEC); 639 if (err) { 640 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); 641 return; 642 } 643 644 extra = 0x1 << 16 | /* tune clock stop en */ 645 0x3 << 17 | /* pre-change delay */ 646 0x3 << 19; /* post-change delay */ 647 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 648 649 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || 650 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) 651 txclk_tapnum = priv->txclk_tapnum; 652 653 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 654 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; 655 656 extra = DLL_CMDOUT_SRC_CLK_NEG | 657 DLL_CMDOUT_EN_SRC_CLK_NEG | 658 DWCMSHC_EMMC_DLL_DLYENA | 659 DLL_CMDOUT_TAPNUM_90_DEGREES | 660 DLL_CMDOUT_TAPNUM_FROM_SW; 661 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 662 } 663 664 extra = DWCMSHC_EMMC_DLL_DLYENA | 665 DLL_TXCLK_TAPNUM_FROM_SW | 666 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | 667 txclk_tapnum; 668 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 669 670 extra = DWCMSHC_EMMC_DLL_DLYENA | 671 DLL_STRBIN_TAPNUM_DEFAULT | 672 DLL_STRBIN_TAPNUM_FROM_SW; 673 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 674 } 675 676 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) 677 { 678 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 679 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 680 struct rk35xx_priv *priv = dwc_priv->priv; 681 682 if (mask & SDHCI_RESET_ALL && priv->reset) { 683 reset_control_assert(priv->reset); 684 udelay(1); 685 reset_control_deassert(priv->reset); 686 } 687 688 sdhci_reset(host, mask); 689 } 690 691 static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host, 692 struct dwcmshc_priv *dwc_priv) 693 { 694 static const char * const clk_ids[] = {"axi", "block", "timer"}; 695 struct rk35xx_priv *priv; 696 int err; 697 698 priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 699 if (!priv) 700 return -ENOMEM; 701 702 if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc")) 703 priv->devtype = DWCMSHC_RK3588; 704 else 705 priv->devtype = DWCMSHC_RK3568; 706 707 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 708 if (IS_ERR(priv->reset)) { 709 err = PTR_ERR(priv->reset); 710 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 711 return err; 712 } 713 714 err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 715 ARRAY_SIZE(clk_ids), clk_ids); 716 if (err) 717 return err; 718 719 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 720 &priv->txclk_tapnum)) 721 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 722 723 /* Disable cmd conflict check */ 724 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 725 /* Reset previous settings */ 726 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 727 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 728 729 dwc_priv->priv = priv; 730 731 return 0; 732 } 733 734 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 735 { 736 /* 737 * Don't support highspeed bus mode with low clk speed as we 738 * cannot use DLL for this condition. 739 */ 740 if (host->mmc->f_max <= 52000000) { 741 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 742 host->mmc->f_max); 743 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 744 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 745 } 746 } 747 748 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) 749 { 750 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 751 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 752 u32 val = 0; 753 754 if (host->flags & SDHCI_HS400_TUNING) 755 return 0; 756 757 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL), 758 PHY_ATDL_CNFG_R); 759 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 760 761 /* 762 * configure tuning settings: 763 * - center phase select code driven in block gap interval 764 * - disable reporting of framing errors 765 * - disable software managed tuning 766 * - disable user selection of sampling window edges, 767 * instead tuning calculated edges are used 768 */ 769 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | 770 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); 771 772 /* 773 * configure tuning settings: 774 * - enable auto-tuning 775 * - enable sampling window threshold 776 * - stop clocks during phase code change 777 * - set max latency in cycles between tx and rx clocks 778 * - set max latency in cycles to switch output phase 779 * - set max sampling window threshold value 780 */ 781 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; 782 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); 783 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); 784 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); 785 786 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 787 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 788 789 /* perform tuning */ 790 sdhci_start_tuning(host); 791 host->tuning_loop_count = 128; 792 host->tuning_err = __sdhci_execute_tuning(host, opcode); 793 if (host->tuning_err) { 794 /* disable auto-tuning upon tuning error */ 795 val &= ~AT_CTRL_AT_EN; 796 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 797 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); 798 return -EIO; 799 } 800 sdhci_end_tuning(host); 801 802 return 0; 803 } 804 805 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) 806 { 807 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 808 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 809 u16 ctrl_2; 810 811 sdhci_reset(host, mask); 812 813 /* The T-Head 1520 SoC does not comply with the SDHCI specification 814 * regarding the "Software Reset for CMD line should clear 'Command 815 * Complete' in the Normal Interrupt Status Register." Clear the bit 816 * here to compensate for this quirk. 817 */ 818 if (mask & SDHCI_RESET_CMD) 819 sdhci_writel(host, SDHCI_INT_RESPONSE, SDHCI_INT_STATUS); 820 821 if (priv->flags & FLAG_IO_FIXED_1V8) { 822 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 823 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) { 824 ctrl_2 |= SDHCI_CTRL_VDD_180; 825 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 826 } 827 } 828 } 829 830 static int th1520_init(struct device *dev, 831 struct sdhci_host *host, 832 struct dwcmshc_priv *dwc_priv) 833 { 834 dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; 835 836 if (device_property_read_bool(dev, "mmc-ddr-1_8v") || 837 device_property_read_bool(dev, "mmc-hs200-1_8v") || 838 device_property_read_bool(dev, "mmc-hs400-1_8v")) 839 dwc_priv->flags |= FLAG_IO_FIXED_1V8; 840 else 841 dwc_priv->flags &= ~FLAG_IO_FIXED_1V8; 842 843 /* 844 * start_signal_voltage_switch() will try 3.3V first 845 * then 1.8V. Use SDHCI_SIGNALING_180 rather than 846 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V 847 * in sdhci_start_signal_voltage_switch(). 848 */ 849 if (dwc_priv->flags & FLAG_IO_FIXED_1V8) { 850 host->flags &= ~SDHCI_SIGNALING_330; 851 host->flags |= SDHCI_SIGNALING_180; 852 } 853 854 sdhci_enable_v4_mode(host); 855 856 return 0; 857 } 858 859 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) 860 { 861 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 862 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 863 u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 864 865 sdhci_reset(host, mask); 866 867 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 868 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 869 val |= CV18XX_EMMC_FUNC_EN; 870 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 871 } 872 873 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 874 val |= CV18XX_LATANCY_1T; 875 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 876 877 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 878 val |= CV18XX_PHY_TX_BPS; 879 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 880 881 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 882 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 883 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) | 884 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK)); 885 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 886 } 887 888 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap) 889 { 890 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 891 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 892 u16 clk; 893 u32 val; 894 895 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 896 clk &= ~SDHCI_CLOCK_CARD_EN; 897 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 898 899 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 900 val &= ~CV18XX_LATANCY_1T; 901 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 902 903 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 904 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 905 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap)); 906 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 907 908 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 909 910 clk |= SDHCI_CLOCK_CARD_EN; 911 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 912 usleep_range(1000, 2000); 913 } 914 915 static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error) 916 { 917 int ret, retry = 0; 918 919 while (retry < CV18XX_RETRY_TUNING_MAX) { 920 ret = mmc_send_tuning(mmc, opcode, NULL); 921 if (ret) 922 return ret; 923 retry++; 924 } 925 926 return 0; 927 } 928 929 static void cv18xx_sdhci_post_tuning(struct sdhci_host *host) 930 { 931 u32 val; 932 933 val = sdhci_readl(host, SDHCI_INT_STATUS); 934 val |= SDHCI_INT_DATA_AVAIL; 935 sdhci_writel(host, val, SDHCI_INT_STATUS); 936 937 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 938 } 939 940 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 941 { 942 int min, max, avg, ret; 943 int win_length, target_min, target_max, target_win_length; 944 945 min = max = 0; 946 target_win_length = 0; 947 948 sdhci_reset_tuning(host); 949 950 while (max < CV18XX_TUNE_MAX) { 951 /* find the mininum delay first which can pass tuning */ 952 while (min < CV18XX_TUNE_MAX) { 953 cv18xx_sdhci_set_tap(host, min); 954 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL)) 955 break; 956 min += CV18XX_TUNE_STEP; 957 } 958 959 /* find the maxinum delay which can not pass tuning */ 960 max = min + CV18XX_TUNE_STEP; 961 while (max < CV18XX_TUNE_MAX) { 962 cv18xx_sdhci_set_tap(host, max); 963 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) { 964 max -= CV18XX_TUNE_STEP; 965 break; 966 } 967 max += CV18XX_TUNE_STEP; 968 } 969 970 win_length = max - min + 1; 971 /* get the largest pass window */ 972 if (win_length > target_win_length) { 973 target_win_length = win_length; 974 target_min = min; 975 target_max = max; 976 } 977 978 /* continue to find the next pass window */ 979 min = max + CV18XX_TUNE_STEP; 980 } 981 982 cv18xx_sdhci_post_tuning(host); 983 984 /* use average delay to get the best timing */ 985 avg = (target_min + target_max) / 2; 986 cv18xx_sdhci_set_tap(host, avg); 987 ret = mmc_send_tuning(host->mmc, opcode, NULL); 988 989 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 990 ret ? "failed" : "passed", avg, ret); 991 992 return ret; 993 } 994 995 static inline void sg2042_sdhci_phy_init(struct sdhci_host *host) 996 { 997 u32 val; 998 999 /* Asset phy reset & set tx drive strength */ 1000 val = sdhci_readl(host, PHY_CNFG_R); 1001 val &= ~PHY_CNFG_RSTN_DEASSERT; 1002 val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1); 1003 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042); 1004 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042); 1005 sdhci_writel(host, val, PHY_CNFG_R); 1006 1007 /* Configure phy pads */ 1008 val = PHY_PAD_RXSEL_3V3; 1009 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 1010 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1011 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1012 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 1013 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 1014 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 1015 1016 val = PHY_PAD_RXSEL_3V3; 1017 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1018 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1019 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 1020 1021 val = PHY_PAD_RXSEL_3V3; 1022 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 1023 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1024 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1025 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 1026 1027 /* Configure delay line */ 1028 /* Enable fixed delay */ 1029 sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R); 1030 /* 1031 * Set delay line. 1032 * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written. 1033 * Ensure UPDATE_DC[4] is '0' when not updating code. 1034 */ 1035 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 1036 val |= PHY_SDCLKDL_CNFG_UPDATE; 1037 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 1038 /* Add 10 * 70ps = 0.7ns for output delay */ 1039 sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R); 1040 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 1041 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 1042 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 1043 1044 /* Set SMPLDL_CNFG, Bypass */ 1045 sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R); 1046 1047 /* Set ATDL_CNFG, tuning clk not use for init */ 1048 val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042); 1049 sdhci_writeb(host, val, PHY_ATDL_CNFG_R); 1050 1051 /* Deasset phy reset */ 1052 val = sdhci_readl(host, PHY_CNFG_R); 1053 val |= PHY_CNFG_RSTN_DEASSERT; 1054 sdhci_writel(host, val, PHY_CNFG_R); 1055 } 1056 1057 static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask) 1058 { 1059 sdhci_reset(host, mask); 1060 1061 if (mask & SDHCI_RESET_ALL) 1062 sg2042_sdhci_phy_init(host); 1063 } 1064 1065 static int sg2042_init(struct device *dev, struct sdhci_host *host, 1066 struct dwcmshc_priv *dwc_priv) 1067 { 1068 static const char * const clk_ids[] = {"timer"}; 1069 1070 return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 1071 ARRAY_SIZE(clk_ids), clk_ids); 1072 } 1073 1074 static const struct sdhci_ops sdhci_dwcmshc_ops = { 1075 .set_clock = sdhci_set_clock, 1076 .set_bus_width = sdhci_set_bus_width, 1077 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1078 .get_max_clock = dwcmshc_get_max_clock, 1079 .reset = sdhci_reset, 1080 .adma_write_desc = dwcmshc_adma_write_desc, 1081 .irq = dwcmshc_cqe_irq_handler, 1082 }; 1083 1084 #ifdef CONFIG_ACPI 1085 static void dwcmshc_bf3_hw_reset(struct sdhci_host *host) 1086 { 1087 struct arm_smccc_res res = { 0 }; 1088 1089 arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res); 1090 1091 if (res.a0) 1092 pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc)); 1093 } 1094 1095 static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = { 1096 .set_clock = sdhci_set_clock, 1097 .set_bus_width = sdhci_set_bus_width, 1098 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1099 .get_max_clock = dwcmshc_get_max_clock, 1100 .reset = sdhci_reset, 1101 .adma_write_desc = dwcmshc_adma_write_desc, 1102 .irq = dwcmshc_cqe_irq_handler, 1103 .hw_reset = dwcmshc_bf3_hw_reset, 1104 }; 1105 #endif 1106 1107 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { 1108 .set_clock = dwcmshc_rk3568_set_clock, 1109 .set_bus_width = sdhci_set_bus_width, 1110 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1111 .get_max_clock = rk35xx_get_max_clock, 1112 .reset = rk35xx_sdhci_reset, 1113 .adma_write_desc = dwcmshc_adma_write_desc, 1114 .irq = dwcmshc_cqe_irq_handler, 1115 }; 1116 1117 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { 1118 .set_clock = sdhci_set_clock, 1119 .set_bus_width = sdhci_set_bus_width, 1120 .set_uhs_signaling = th1520_set_uhs_signaling, 1121 .get_max_clock = dwcmshc_get_max_clock, 1122 .reset = th1520_sdhci_reset, 1123 .adma_write_desc = dwcmshc_adma_write_desc, 1124 .voltage_switch = dwcmshc_phy_init, 1125 .platform_execute_tuning = th1520_execute_tuning, 1126 }; 1127 1128 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { 1129 .set_clock = sdhci_set_clock, 1130 .set_bus_width = sdhci_set_bus_width, 1131 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1132 .get_max_clock = dwcmshc_get_max_clock, 1133 .reset = cv18xx_sdhci_reset, 1134 .adma_write_desc = dwcmshc_adma_write_desc, 1135 .platform_execute_tuning = cv18xx_sdhci_execute_tuning, 1136 }; 1137 1138 static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { 1139 .set_clock = sdhci_set_clock, 1140 .set_bus_width = sdhci_set_bus_width, 1141 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1142 .get_max_clock = dwcmshc_get_max_clock, 1143 .reset = sg2042_sdhci_reset, 1144 .adma_write_desc = dwcmshc_adma_write_desc, 1145 .platform_execute_tuning = th1520_execute_tuning, 1146 }; 1147 1148 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { 1149 .pdata = { 1150 .ops = &sdhci_dwcmshc_ops, 1151 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1152 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1153 }, 1154 }; 1155 1156 #ifdef CONFIG_ACPI 1157 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = { 1158 .pdata = { 1159 .ops = &sdhci_dwcmshc_bf3_ops, 1160 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1161 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1162 SDHCI_QUIRK2_ACMD23_BROKEN, 1163 }, 1164 }; 1165 #endif 1166 1167 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 1168 .pdata = { 1169 .ops = &sdhci_dwcmshc_rk35xx_ops, 1170 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1171 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 1172 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1173 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 1174 }, 1175 .init = dwcmshc_rk35xx_init, 1176 .postinit = dwcmshc_rk35xx_postinit, 1177 }; 1178 1179 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { 1180 .pdata = { 1181 .ops = &sdhci_dwcmshc_th1520_ops, 1182 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1183 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1184 }, 1185 .init = th1520_init, 1186 }; 1187 1188 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { 1189 .pdata = { 1190 .ops = &sdhci_dwcmshc_cv18xx_ops, 1191 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1192 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1193 }, 1194 }; 1195 1196 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { 1197 .pdata = { 1198 .ops = &sdhci_dwcmshc_sg2042_ops, 1199 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1200 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1201 }, 1202 .init = sg2042_init, 1203 }; 1204 1205 static const struct cqhci_host_ops dwcmshc_cqhci_ops = { 1206 .enable = dwcmshc_sdhci_cqe_enable, 1207 .disable = sdhci_cqe_disable, 1208 .dumpregs = dwcmshc_cqhci_dumpregs, 1209 .set_tran_desc = dwcmshc_set_tran_desc, 1210 }; 1211 1212 static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev) 1213 { 1214 struct cqhci_host *cq_host; 1215 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1216 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1217 bool dma64 = false; 1218 u16 clk; 1219 int err; 1220 1221 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1222 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1223 if (!cq_host) { 1224 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n"); 1225 goto dsbl_cqe_caps; 1226 } 1227 1228 /* 1229 * For dwcmshc host controller we have to enable internal clock 1230 * before access to some registers from Vendor Specific Area 2. 1231 */ 1232 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1233 clk |= SDHCI_CLOCK_INT_EN; 1234 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1235 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1236 if (!(clk & SDHCI_CLOCK_INT_EN)) { 1237 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n"); 1238 goto free_cq_host; 1239 } 1240 1241 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; 1242 cq_host->ops = &dwcmshc_cqhci_ops; 1243 1244 /* Enable using of 128-bit task descriptors */ 1245 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1246 if (dma64) { 1247 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n"); 1248 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1249 } 1250 err = cqhci_init(cq_host, host->mmc, dma64); 1251 if (err) { 1252 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err); 1253 goto int_clock_disable; 1254 } 1255 1256 dev_dbg(mmc_dev(host->mmc), "CQE init done\n"); 1257 1258 return; 1259 1260 int_clock_disable: 1261 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1262 clk &= ~SDHCI_CLOCK_INT_EN; 1263 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1264 1265 free_cq_host: 1266 devm_kfree(&pdev->dev, cq_host); 1267 1268 dsbl_cqe_caps: 1269 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); 1270 } 1271 1272 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { 1273 { 1274 .compatible = "rockchip,rk3588-dwcmshc", 1275 .data = &sdhci_dwcmshc_rk35xx_pdata, 1276 }, 1277 { 1278 .compatible = "rockchip,rk3568-dwcmshc", 1279 .data = &sdhci_dwcmshc_rk35xx_pdata, 1280 }, 1281 { 1282 .compatible = "snps,dwcmshc-sdhci", 1283 .data = &sdhci_dwcmshc_pdata, 1284 }, 1285 { 1286 .compatible = "sophgo,cv1800b-dwcmshc", 1287 .data = &sdhci_dwcmshc_cv18xx_pdata, 1288 }, 1289 { 1290 .compatible = "sophgo,sg2002-dwcmshc", 1291 .data = &sdhci_dwcmshc_cv18xx_pdata, 1292 }, 1293 { 1294 .compatible = "thead,th1520-dwcmshc", 1295 .data = &sdhci_dwcmshc_th1520_pdata, 1296 }, 1297 { 1298 .compatible = "sophgo,sg2042-dwcmshc", 1299 .data = &sdhci_dwcmshc_sg2042_pdata, 1300 }, 1301 {}, 1302 }; 1303 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); 1304 1305 #ifdef CONFIG_ACPI 1306 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { 1307 { 1308 .id = "MLNXBF30", 1309 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata, 1310 }, 1311 {} 1312 }; 1313 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids); 1314 #endif 1315 1316 static int dwcmshc_probe(struct platform_device *pdev) 1317 { 1318 struct device *dev = &pdev->dev; 1319 struct sdhci_pltfm_host *pltfm_host; 1320 struct sdhci_host *host; 1321 struct dwcmshc_priv *priv; 1322 const struct dwcmshc_pltfm_data *pltfm_data; 1323 int err; 1324 u32 extra, caps; 1325 1326 pltfm_data = device_get_match_data(&pdev->dev); 1327 if (!pltfm_data) { 1328 dev_err(&pdev->dev, "Error: No device match data found\n"); 1329 return -ENODEV; 1330 } 1331 1332 host = sdhci_pltfm_init(pdev, &pltfm_data->pdata, 1333 sizeof(struct dwcmshc_priv)); 1334 if (IS_ERR(host)) 1335 return PTR_ERR(host); 1336 1337 /* 1338 * extra adma table cnt for cross 128M boundary handling. 1339 */ 1340 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); 1341 if (extra > SDHCI_MAX_SEGS) 1342 extra = SDHCI_MAX_SEGS; 1343 host->adma_table_cnt += extra; 1344 1345 pltfm_host = sdhci_priv(host); 1346 priv = sdhci_pltfm_priv(pltfm_host); 1347 1348 if (dev->of_node) { 1349 pltfm_host->clk = devm_clk_get(dev, "core"); 1350 if (IS_ERR(pltfm_host->clk)) { 1351 err = PTR_ERR(pltfm_host->clk); 1352 dev_err(dev, "failed to get core clk: %d\n", err); 1353 goto free_pltfm; 1354 } 1355 err = clk_prepare_enable(pltfm_host->clk); 1356 if (err) 1357 goto free_pltfm; 1358 1359 priv->bus_clk = devm_clk_get(dev, "bus"); 1360 if (!IS_ERR(priv->bus_clk)) 1361 clk_prepare_enable(priv->bus_clk); 1362 } 1363 1364 err = mmc_of_parse(host->mmc); 1365 if (err) 1366 goto err_clk; 1367 1368 sdhci_get_of_property(pdev); 1369 1370 priv->vendor_specific_area1 = 1371 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; 1372 1373 host->mmc_host_ops.request = dwcmshc_request; 1374 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 1375 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; 1376 1377 if (pltfm_data->init) { 1378 err = pltfm_data->init(&pdev->dev, host, priv); 1379 if (err) 1380 goto err_clk; 1381 } 1382 1383 #ifdef CONFIG_ACPI 1384 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) 1385 sdhci_enable_v4_mode(host); 1386 #endif 1387 1388 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 1389 if (caps & SDHCI_CAN_64BIT_V4) 1390 sdhci_enable_v4_mode(host); 1391 1392 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1393 1394 pm_runtime_get_noresume(dev); 1395 pm_runtime_set_active(dev); 1396 pm_runtime_enable(dev); 1397 1398 err = sdhci_setup_host(host); 1399 if (err) 1400 goto err_rpm; 1401 1402 /* Setup Command Queue Engine if enabled */ 1403 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 1404 priv->vendor_specific_area2 = 1405 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2); 1406 1407 dwcmshc_cqhci_init(host, pdev); 1408 } 1409 1410 if (pltfm_data->postinit) 1411 pltfm_data->postinit(host, priv); 1412 1413 err = __sdhci_add_host(host); 1414 if (err) 1415 goto err_setup_host; 1416 1417 pm_runtime_put(dev); 1418 1419 return 0; 1420 1421 err_setup_host: 1422 sdhci_cleanup_host(host); 1423 err_rpm: 1424 pm_runtime_disable(dev); 1425 pm_runtime_put_noidle(dev); 1426 err_clk: 1427 clk_disable_unprepare(pltfm_host->clk); 1428 clk_disable_unprepare(priv->bus_clk); 1429 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1430 free_pltfm: 1431 sdhci_pltfm_free(pdev); 1432 return err; 1433 } 1434 1435 static void dwcmshc_disable_card_clk(struct sdhci_host *host) 1436 { 1437 u16 ctrl; 1438 1439 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1440 if (ctrl & SDHCI_CLOCK_CARD_EN) { 1441 ctrl &= ~SDHCI_CLOCK_CARD_EN; 1442 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1443 } 1444 } 1445 1446 static void dwcmshc_remove(struct platform_device *pdev) 1447 { 1448 struct sdhci_host *host = platform_get_drvdata(pdev); 1449 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1450 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1451 1452 pm_runtime_get_sync(&pdev->dev); 1453 pm_runtime_disable(&pdev->dev); 1454 pm_runtime_put_noidle(&pdev->dev); 1455 1456 sdhci_remove_host(host, 0); 1457 1458 dwcmshc_disable_card_clk(host); 1459 1460 clk_disable_unprepare(pltfm_host->clk); 1461 clk_disable_unprepare(priv->bus_clk); 1462 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1463 sdhci_pltfm_free(pdev); 1464 } 1465 1466 #ifdef CONFIG_PM_SLEEP 1467 static int dwcmshc_suspend(struct device *dev) 1468 { 1469 struct sdhci_host *host = dev_get_drvdata(dev); 1470 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1471 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1472 int ret; 1473 1474 pm_runtime_resume(dev); 1475 1476 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1477 ret = cqhci_suspend(host->mmc); 1478 if (ret) 1479 return ret; 1480 } 1481 1482 ret = sdhci_suspend_host(host); 1483 if (ret) 1484 return ret; 1485 1486 clk_disable_unprepare(pltfm_host->clk); 1487 if (!IS_ERR(priv->bus_clk)) 1488 clk_disable_unprepare(priv->bus_clk); 1489 1490 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1491 1492 return ret; 1493 } 1494 1495 static int dwcmshc_resume(struct device *dev) 1496 { 1497 struct sdhci_host *host = dev_get_drvdata(dev); 1498 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1499 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1500 int ret; 1501 1502 ret = clk_prepare_enable(pltfm_host->clk); 1503 if (ret) 1504 return ret; 1505 1506 if (!IS_ERR(priv->bus_clk)) { 1507 ret = clk_prepare_enable(priv->bus_clk); 1508 if (ret) 1509 goto disable_clk; 1510 } 1511 1512 ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks); 1513 if (ret) 1514 goto disable_bus_clk; 1515 1516 ret = sdhci_resume_host(host); 1517 if (ret) 1518 goto disable_other_clks; 1519 1520 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1521 ret = cqhci_resume(host->mmc); 1522 if (ret) 1523 goto disable_other_clks; 1524 } 1525 1526 return 0; 1527 1528 disable_other_clks: 1529 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1530 disable_bus_clk: 1531 if (!IS_ERR(priv->bus_clk)) 1532 clk_disable_unprepare(priv->bus_clk); 1533 disable_clk: 1534 clk_disable_unprepare(pltfm_host->clk); 1535 return ret; 1536 } 1537 #endif 1538 1539 #ifdef CONFIG_PM 1540 1541 static void dwcmshc_enable_card_clk(struct sdhci_host *host) 1542 { 1543 u16 ctrl; 1544 1545 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1546 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { 1547 ctrl |= SDHCI_CLOCK_CARD_EN; 1548 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1549 } 1550 } 1551 1552 static int dwcmshc_runtime_suspend(struct device *dev) 1553 { 1554 struct sdhci_host *host = dev_get_drvdata(dev); 1555 1556 dwcmshc_disable_card_clk(host); 1557 1558 return 0; 1559 } 1560 1561 static int dwcmshc_runtime_resume(struct device *dev) 1562 { 1563 struct sdhci_host *host = dev_get_drvdata(dev); 1564 1565 dwcmshc_enable_card_clk(host); 1566 1567 return 0; 1568 } 1569 1570 #endif 1571 1572 static const struct dev_pm_ops dwcmshc_pmops = { 1573 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume) 1574 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, 1575 dwcmshc_runtime_resume, NULL) 1576 }; 1577 1578 static struct platform_driver sdhci_dwcmshc_driver = { 1579 .driver = { 1580 .name = "sdhci-dwcmshc", 1581 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1582 .of_match_table = sdhci_dwcmshc_dt_ids, 1583 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), 1584 .pm = &dwcmshc_pmops, 1585 }, 1586 .probe = dwcmshc_probe, 1587 .remove = dwcmshc_remove, 1588 }; 1589 module_platform_driver(sdhci_dwcmshc_driver); 1590 1591 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC"); 1592 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); 1593 MODULE_LICENSE("GPL v2"); 1594