1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller 4 * 5 * Copyright (C) 2018 Synaptics Incorporated 6 * 7 * Author: Jisheng Zhang <jszhang@kernel.org> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/bitfield.h> 12 #include <linux/clk.h> 13 #include <linux/dma-mapping.h> 14 #include <linux/iopoll.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 #include <linux/sizes.h> 22 23 #include "sdhci-pltfm.h" 24 #include "cqhci.h" 25 26 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 27 28 /* DWCMSHC specific Mode Select value */ 29 #define DWCMSHC_CTRL_HS400 0x7 30 31 /* DWC IP vendor area 1 pointer */ 32 #define DWCMSHC_P_VENDOR_AREA1 0xe8 33 #define DWCMSHC_AREA1_MASK GENMASK(11, 0) 34 /* Offset inside the vendor area 1 */ 35 #define DWCMSHC_HOST_CTRL3 0x8 36 #define DWCMSHC_EMMC_CONTROL 0x2c 37 #define DWCMSHC_CARD_IS_EMMC BIT(0) 38 #define DWCMSHC_ENHANCED_STROBE BIT(8) 39 #define DWCMSHC_EMMC_ATCTRL 0x40 40 /* Tuning and auto-tuning fields in AT_CTRL_R control register */ 41 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ 42 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ 43 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ 44 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ 45 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ 46 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ 47 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ 48 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */ 49 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ 50 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ 51 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ 52 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ 53 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ 54 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ 55 56 /* DWC IP vendor area 2 pointer */ 57 #define DWCMSHC_P_VENDOR_AREA2 0xea 58 59 /* Sophgo CV18XX specific Registers */ 60 #define CV18XX_SDHCI_MSHC_CTRL 0x00 61 #define CV18XX_EMMC_FUNC_EN BIT(0) 62 #define CV18XX_LATANCY_1T BIT(1) 63 #define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40 64 #define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0) 65 #define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8) 66 #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1 67 #define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16) 68 #define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24) 69 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1 70 #define CV18XX_SDHCI_PHY_CONFIG 0x4c 71 #define CV18XX_PHY_TX_BPS BIT(0) 72 73 #define CV18XX_TUNE_MAX 128 74 #define CV18XX_TUNE_STEP 1 75 #define CV18XX_RETRY_TUNING_MAX 50 76 77 /* Rockchip specific Registers */ 78 #define DWCMSHC_EMMC_DLL_CTRL 0x800 79 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 80 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 81 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 82 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 83 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 84 #define DWCMSHC_EMMC_DLL_START BIT(0) 85 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 86 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 87 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 88 #define DWCMSHC_EMMC_DLL_START_POINT 16 89 #define DWCMSHC_EMMC_DLL_INC 8 90 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 91 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 92 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 93 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA 94 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 95 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8 96 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 97 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 98 #define DLL_STRBIN_DELAY_NUM_OFFSET 16 99 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 100 #define DLL_RXCLK_NO_INVERTER 1 101 #define DLL_RXCLK_INVERTER 0 102 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 103 #define DLL_RXCLK_ORI_GATE BIT(31) 104 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 105 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 106 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 107 108 #define DLL_LOCK_WO_TMOUT(x) \ 109 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 110 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 111 #define RK35xx_MAX_CLKS 3 112 113 /* PHY register area pointer */ 114 #define DWC_MSHC_PTR_PHY_R 0x300 115 116 /* PHY general configuration */ 117 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) 118 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ 119 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ 120 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ 121 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ 122 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ 123 124 /* PHY command/response pad settings */ 125 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) 126 127 /* PHY data pad settings */ 128 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) 129 130 /* PHY clock pad settings */ 131 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) 132 133 /* PHY strobe pad settings */ 134 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) 135 136 /* PHY reset pad settings */ 137 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) 138 139 /* Bitfields are common for all pad settings */ 140 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ 141 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ 142 143 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ 144 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ 145 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ 146 147 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ 148 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ 149 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ 150 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ 151 152 /* PHY CLK delay line settings */ 153 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) 154 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ 155 156 /* PHY CLK delay line delay code */ 157 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) 158 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ 159 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ 160 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ 161 162 /* PHY drift_cclk_rx delay line configuration setting */ 163 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) 164 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ 165 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ 166 167 /* PHY DLL control settings */ 168 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) 169 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ 170 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ 171 172 /* PHY DLL configuration register 1 */ 173 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) 174 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ 175 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ 176 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ 177 178 /* PHY DLL configuration register 2 */ 179 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) 180 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ 181 182 /* PHY DLL master and slave delay line configuration settings */ 183 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) 184 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ 185 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ 186 187 #define FLAG_IO_FIXED_1V8 BIT(0) 188 189 #define BOUNDARY_OK(addr, len) \ 190 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) 191 192 #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 193 SDHCI_TRNS_BLK_CNT_EN | \ 194 SDHCI_TRNS_DMA) 195 196 enum dwcmshc_rk_type { 197 DWCMSHC_RK3568, 198 DWCMSHC_RK3588, 199 }; 200 201 struct rk35xx_priv { 202 /* Rockchip specified optional clocks */ 203 struct clk_bulk_data rockchip_clks[RK35xx_MAX_CLKS]; 204 struct reset_control *reset; 205 enum dwcmshc_rk_type devtype; 206 u8 txclk_tapnum; 207 }; 208 209 struct dwcmshc_priv { 210 struct clk *bus_clk; 211 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ 212 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */ 213 214 void *priv; /* pointer to SoC private stuff */ 215 u16 delay_line; 216 u16 flags; 217 }; 218 219 /* 220 * If DMA addr spans 128MB boundary, we split the DMA transfer into two 221 * so that each DMA transfer doesn't exceed the boundary. 222 */ 223 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, 224 dma_addr_t addr, int len, unsigned int cmd) 225 { 226 int tmplen, offset; 227 228 if (likely(!len || BOUNDARY_OK(addr, len))) { 229 sdhci_adma_write_desc(host, desc, addr, len, cmd); 230 return; 231 } 232 233 offset = addr & (SZ_128M - 1); 234 tmplen = SZ_128M - offset; 235 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); 236 237 addr += tmplen; 238 len -= tmplen; 239 sdhci_adma_write_desc(host, desc, addr, len, cmd); 240 } 241 242 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) 243 { 244 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 245 246 if (pltfm_host->clk) 247 return sdhci_pltfm_clk_get_max_clock(host); 248 else 249 return pltfm_host->clock; 250 } 251 252 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) 253 { 254 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 255 256 return clk_round_rate(pltfm_host->clk, ULONG_MAX); 257 } 258 259 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, 260 struct mmc_request *mrq) 261 { 262 struct sdhci_host *host = mmc_priv(mmc); 263 264 /* 265 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit 266 * block count register which doesn't support stuff bits of 267 * CMD23 argument on dwcmsch host controller. 268 */ 269 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) 270 host->flags &= ~SDHCI_AUTO_CMD23; 271 else 272 host->flags |= SDHCI_AUTO_CMD23; 273 } 274 275 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) 276 { 277 dwcmshc_check_auto_cmd23(mmc, mrq); 278 279 sdhci_request(mmc, mrq); 280 } 281 282 static void dwcmshc_phy_1_8v_init(struct sdhci_host *host) 283 { 284 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 285 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 286 u32 val; 287 288 /* deassert phy reset & set tx drive strength */ 289 val = PHY_CNFG_RSTN_DEASSERT; 290 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); 291 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); 292 sdhci_writel(host, val, PHY_CNFG_R); 293 294 /* disable delay line */ 295 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); 296 297 /* set delay line */ 298 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); 299 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); 300 301 /* enable delay lane */ 302 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 303 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 304 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 305 306 /* configure phy pads */ 307 val = PHY_PAD_RXSEL_1V8; 308 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 309 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 310 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 311 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 312 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 313 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 314 315 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 316 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 317 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 318 319 val = PHY_PAD_RXSEL_1V8; 320 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 321 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 322 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 323 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 324 325 /* enable data strobe mode */ 326 sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL), 327 PHY_DLLDL_CNFG_R); 328 329 /* enable phy dll */ 330 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); 331 } 332 333 static void dwcmshc_phy_3_3v_init(struct sdhci_host *host) 334 { 335 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 336 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 337 u32 val; 338 339 /* deassert phy reset & set tx drive strength */ 340 val = PHY_CNFG_RSTN_DEASSERT; 341 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); 342 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); 343 sdhci_writel(host, val, PHY_CNFG_R); 344 345 /* disable delay line */ 346 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); 347 348 /* set delay line */ 349 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); 350 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); 351 352 /* enable delay lane */ 353 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 354 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 355 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 356 357 /* configure phy pads */ 358 val = PHY_PAD_RXSEL_3V3; 359 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 360 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 361 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 362 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 363 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 364 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 365 366 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 367 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 368 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 369 370 val = PHY_PAD_RXSEL_3V3; 371 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 372 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 373 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 374 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 375 376 /* enable phy dll */ 377 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); 378 } 379 380 static void th1520_sdhci_set_phy(struct sdhci_host *host) 381 { 382 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 383 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 384 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 385 u16 emmc_ctrl; 386 387 /* Before power on, set PHY configs */ 388 if (priv->flags & FLAG_IO_FIXED_1V8) 389 dwcmshc_phy_1_8v_init(host); 390 else 391 dwcmshc_phy_3_3v_init(host); 392 393 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 394 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 395 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC; 396 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 397 } 398 399 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | 400 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); 401 } 402 403 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, 404 unsigned int timing) 405 { 406 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 407 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 408 u16 ctrl, ctrl_2; 409 410 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 411 /* Select Bus Speed Mode for host */ 412 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 413 if ((timing == MMC_TIMING_MMC_HS200) || 414 (timing == MMC_TIMING_UHS_SDR104)) 415 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 416 else if (timing == MMC_TIMING_UHS_SDR12) 417 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 418 else if ((timing == MMC_TIMING_UHS_SDR25) || 419 (timing == MMC_TIMING_MMC_HS)) 420 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 421 else if (timing == MMC_TIMING_UHS_SDR50) 422 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 423 else if ((timing == MMC_TIMING_UHS_DDR50) || 424 (timing == MMC_TIMING_MMC_DDR52)) 425 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 426 else if (timing == MMC_TIMING_MMC_HS400) { 427 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ 428 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 429 ctrl |= DWCMSHC_CARD_IS_EMMC; 430 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 431 432 ctrl_2 |= DWCMSHC_CTRL_HS400; 433 } 434 435 if (priv->flags & FLAG_IO_FIXED_1V8) 436 ctrl_2 |= SDHCI_CTRL_VDD_180; 437 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 438 } 439 440 static void th1520_set_uhs_signaling(struct sdhci_host *host, 441 unsigned int timing) 442 { 443 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 444 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 445 446 dwcmshc_set_uhs_signaling(host, timing); 447 if (timing == MMC_TIMING_MMC_HS400) 448 priv->delay_line = PHY_SDCLKDL_DC_HS400; 449 else 450 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); 451 th1520_sdhci_set_phy(host); 452 } 453 454 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, 455 struct mmc_ios *ios) 456 { 457 u32 vendor; 458 struct sdhci_host *host = mmc_priv(mmc); 459 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 460 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 461 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; 462 463 vendor = sdhci_readl(host, reg); 464 if (ios->enhanced_strobe) 465 vendor |= DWCMSHC_ENHANCED_STROBE; 466 else 467 vendor &= ~DWCMSHC_ENHANCED_STROBE; 468 469 sdhci_writel(host, vendor, reg); 470 } 471 472 static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode) 473 { 474 int err = sdhci_execute_tuning(mmc, opcode); 475 struct sdhci_host *host = mmc_priv(mmc); 476 477 if (err) 478 return err; 479 480 /* 481 * Tuning can leave the IP in an active state (Buffer Read Enable bit 482 * set) which prevents the entry to low power states (i.e. S0i3). Data 483 * reset will clear it. 484 */ 485 sdhci_reset(host, SDHCI_RESET_DATA); 486 487 return 0; 488 } 489 490 static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask) 491 { 492 int cmd_error = 0; 493 int data_error = 0; 494 495 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 496 return intmask; 497 498 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 499 500 return 0; 501 } 502 503 static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc) 504 { 505 struct sdhci_host *host = mmc_priv(mmc); 506 u8 ctrl; 507 508 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 509 510 sdhci_cqe_enable(mmc); 511 512 /* 513 * The "DesignWare Cores Mobile Storage Host Controller 514 * DWC_mshc / DWC_mshc_lite Databook" says: 515 * when Host Version 4 Enable" is 1 in Host Control 2 register, 516 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected. 517 * Selection of 32-bit/64-bit System Addressing: 518 * either 32-bit or 64-bit system addressing is selected by 519 * 64-bit Addressing bit in Host Control 2 register. 520 * 521 * On the other hand the "DesignWare Cores Mobile Storage Host 522 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to 523 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register. 524 */ 525 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 526 ctrl &= ~SDHCI_CTRL_DMA_MASK; 527 ctrl |= SDHCI_CTRL_ADMA32; 528 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 529 } 530 531 static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, 532 dma_addr_t addr, int len, bool end, bool dma64) 533 { 534 int tmplen, offset; 535 536 if (likely(!len || BOUNDARY_OK(addr, len))) { 537 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 538 return; 539 } 540 541 offset = addr & (SZ_128M - 1); 542 tmplen = SZ_128M - offset; 543 cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64); 544 545 addr += tmplen; 546 len -= tmplen; 547 *desc += cq_host->trans_desc_len; 548 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 549 } 550 551 static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc) 552 { 553 sdhci_dumpregs(mmc_priv(mmc)); 554 } 555 556 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 557 { 558 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 559 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 560 struct rk35xx_priv *priv = dwc_priv->priv; 561 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 562 u32 extra, reg; 563 int err; 564 565 host->mmc->actual_clock = 0; 566 567 if (clock == 0) { 568 /* Disable interface clock at initial state. */ 569 sdhci_set_clock(host, clock); 570 return; 571 } 572 573 /* Rockchip platform only support 375KHz for identify mode */ 574 if (clock <= 400000) 575 clock = 375000; 576 577 err = clk_set_rate(pltfm_host->clk, clock); 578 if (err) 579 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); 580 581 sdhci_set_clock(host, clock); 582 583 /* Disable cmd conflict check */ 584 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; 585 extra = sdhci_readl(host, reg); 586 extra &= ~BIT(0); 587 sdhci_writel(host, extra, reg); 588 589 if (clock <= 52000000) { 590 /* 591 * Disable DLL and reset both of sample and drive clock. 592 * The bypass bit and start bit need to be set if DLL is not locked. 593 */ 594 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); 595 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); 596 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 597 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 598 /* 599 * Before switching to hs400es mode, the driver will enable 600 * enhanced strobe first. PHY needs to configure the parameters 601 * of enhanced strobe first. 602 */ 603 extra = DWCMSHC_EMMC_DLL_DLYENA | 604 DLL_STRBIN_DELAY_NUM_SEL | 605 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; 606 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 607 return; 608 } 609 610 /* Reset DLL */ 611 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 612 udelay(1); 613 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); 614 615 /* 616 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but 617 * we must set it in higher speed mode. 618 */ 619 extra = DWCMSHC_EMMC_DLL_DLYENA; 620 if (priv->devtype == DWCMSHC_RK3568) 621 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 622 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 623 624 /* Init DLL settings */ 625 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 626 0x2 << DWCMSHC_EMMC_DLL_INC | 627 DWCMSHC_EMMC_DLL_START; 628 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 629 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, 630 extra, DLL_LOCK_WO_TMOUT(extra), 1, 631 500 * USEC_PER_MSEC); 632 if (err) { 633 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); 634 return; 635 } 636 637 extra = 0x1 << 16 | /* tune clock stop en */ 638 0x3 << 17 | /* pre-change delay */ 639 0x3 << 19; /* post-change delay */ 640 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 641 642 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || 643 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) 644 txclk_tapnum = priv->txclk_tapnum; 645 646 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 647 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; 648 649 extra = DLL_CMDOUT_SRC_CLK_NEG | 650 DLL_CMDOUT_EN_SRC_CLK_NEG | 651 DWCMSHC_EMMC_DLL_DLYENA | 652 DLL_CMDOUT_TAPNUM_90_DEGREES | 653 DLL_CMDOUT_TAPNUM_FROM_SW; 654 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 655 } 656 657 extra = DWCMSHC_EMMC_DLL_DLYENA | 658 DLL_TXCLK_TAPNUM_FROM_SW | 659 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | 660 txclk_tapnum; 661 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 662 663 extra = DWCMSHC_EMMC_DLL_DLYENA | 664 DLL_STRBIN_TAPNUM_DEFAULT | 665 DLL_STRBIN_TAPNUM_FROM_SW; 666 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 667 } 668 669 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) 670 { 671 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 672 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 673 struct rk35xx_priv *priv = dwc_priv->priv; 674 675 if (mask & SDHCI_RESET_ALL && priv->reset) { 676 reset_control_assert(priv->reset); 677 udelay(1); 678 reset_control_deassert(priv->reset); 679 } 680 681 sdhci_reset(host, mask); 682 } 683 684 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) 685 { 686 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 687 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 688 u32 val = 0; 689 690 if (host->flags & SDHCI_HS400_TUNING) 691 return 0; 692 693 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL), 694 PHY_ATDL_CNFG_R); 695 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 696 697 /* 698 * configure tuning settings: 699 * - center phase select code driven in block gap interval 700 * - disable reporting of framing errors 701 * - disable software managed tuning 702 * - disable user selection of sampling window edges, 703 * instead tuning calculated edges are used 704 */ 705 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | 706 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); 707 708 /* 709 * configure tuning settings: 710 * - enable auto-tuning 711 * - enable sampling window threshold 712 * - stop clocks during phase code change 713 * - set max latency in cycles between tx and rx clocks 714 * - set max latency in cycles to switch output phase 715 * - set max sampling window threshold value 716 */ 717 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; 718 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); 719 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); 720 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); 721 722 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 723 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 724 725 /* perform tuning */ 726 sdhci_start_tuning(host); 727 host->tuning_loop_count = 128; 728 host->tuning_err = __sdhci_execute_tuning(host, opcode); 729 if (host->tuning_err) { 730 /* disable auto-tuning upon tuning error */ 731 val &= ~AT_CTRL_AT_EN; 732 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 733 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); 734 return -EIO; 735 } 736 sdhci_end_tuning(host); 737 738 return 0; 739 } 740 741 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) 742 { 743 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 744 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 745 u16 ctrl_2; 746 747 sdhci_reset(host, mask); 748 749 if (priv->flags & FLAG_IO_FIXED_1V8) { 750 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 751 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) { 752 ctrl_2 |= SDHCI_CTRL_VDD_180; 753 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 754 } 755 } 756 } 757 758 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) 759 { 760 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 761 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 762 u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 763 764 sdhci_reset(host, mask); 765 766 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 767 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 768 val |= CV18XX_EMMC_FUNC_EN; 769 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 770 } 771 772 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 773 val |= CV18XX_LATANCY_1T; 774 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 775 776 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 777 val |= CV18XX_PHY_TX_BPS; 778 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 779 780 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 781 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 782 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) | 783 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK)); 784 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 785 } 786 787 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap) 788 { 789 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 790 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 791 u16 clk; 792 u32 val; 793 794 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 795 clk &= ~SDHCI_CLOCK_CARD_EN; 796 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 797 798 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 799 val &= ~CV18XX_LATANCY_1T; 800 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 801 802 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 803 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 804 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap)); 805 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 806 807 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 808 809 clk |= SDHCI_CLOCK_CARD_EN; 810 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 811 usleep_range(1000, 2000); 812 } 813 814 static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error) 815 { 816 int ret, retry = 0; 817 818 while (retry < CV18XX_RETRY_TUNING_MAX) { 819 ret = mmc_send_tuning(mmc, opcode, NULL); 820 if (ret) 821 return ret; 822 retry++; 823 } 824 825 return 0; 826 } 827 828 static void cv18xx_sdhci_post_tuning(struct sdhci_host *host) 829 { 830 u32 val; 831 832 val = sdhci_readl(host, SDHCI_INT_STATUS); 833 val |= SDHCI_INT_DATA_AVAIL; 834 sdhci_writel(host, val, SDHCI_INT_STATUS); 835 836 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 837 } 838 839 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 840 { 841 int min, max, avg, ret; 842 int win_length, target_min, target_max, target_win_length; 843 844 min = max = 0; 845 target_win_length = 0; 846 847 sdhci_reset_tuning(host); 848 849 while (max < CV18XX_TUNE_MAX) { 850 /* find the mininum delay first which can pass tuning */ 851 while (min < CV18XX_TUNE_MAX) { 852 cv18xx_sdhci_set_tap(host, min); 853 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL)) 854 break; 855 min += CV18XX_TUNE_STEP; 856 } 857 858 /* find the maxinum delay which can not pass tuning */ 859 max = min + CV18XX_TUNE_STEP; 860 while (max < CV18XX_TUNE_MAX) { 861 cv18xx_sdhci_set_tap(host, max); 862 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) { 863 max -= CV18XX_TUNE_STEP; 864 break; 865 } 866 max += CV18XX_TUNE_STEP; 867 } 868 869 win_length = max - min + 1; 870 /* get the largest pass window */ 871 if (win_length > target_win_length) { 872 target_win_length = win_length; 873 target_min = min; 874 target_max = max; 875 } 876 877 /* continue to find the next pass window */ 878 min = max + CV18XX_TUNE_STEP; 879 } 880 881 cv18xx_sdhci_post_tuning(host); 882 883 /* use average delay to get the best timing */ 884 avg = (target_min + target_max) / 2; 885 cv18xx_sdhci_set_tap(host, avg); 886 ret = mmc_send_tuning(host->mmc, opcode, NULL); 887 888 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 889 ret ? "failed" : "passed", avg, ret); 890 891 return ret; 892 } 893 894 static const struct sdhci_ops sdhci_dwcmshc_ops = { 895 .set_clock = sdhci_set_clock, 896 .set_bus_width = sdhci_set_bus_width, 897 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 898 .get_max_clock = dwcmshc_get_max_clock, 899 .reset = sdhci_reset, 900 .adma_write_desc = dwcmshc_adma_write_desc, 901 .irq = dwcmshc_cqe_irq_handler, 902 }; 903 904 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { 905 .set_clock = dwcmshc_rk3568_set_clock, 906 .set_bus_width = sdhci_set_bus_width, 907 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 908 .get_max_clock = rk35xx_get_max_clock, 909 .reset = rk35xx_sdhci_reset, 910 .adma_write_desc = dwcmshc_adma_write_desc, 911 .irq = dwcmshc_cqe_irq_handler, 912 }; 913 914 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { 915 .set_clock = sdhci_set_clock, 916 .set_bus_width = sdhci_set_bus_width, 917 .set_uhs_signaling = th1520_set_uhs_signaling, 918 .get_max_clock = dwcmshc_get_max_clock, 919 .reset = th1520_sdhci_reset, 920 .adma_write_desc = dwcmshc_adma_write_desc, 921 .voltage_switch = dwcmshc_phy_1_8v_init, 922 .platform_execute_tuning = th1520_execute_tuning, 923 }; 924 925 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { 926 .set_clock = sdhci_set_clock, 927 .set_bus_width = sdhci_set_bus_width, 928 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 929 .get_max_clock = dwcmshc_get_max_clock, 930 .reset = cv18xx_sdhci_reset, 931 .adma_write_desc = dwcmshc_adma_write_desc, 932 .platform_execute_tuning = cv18xx_sdhci_execute_tuning, 933 }; 934 935 static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { 936 .ops = &sdhci_dwcmshc_ops, 937 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 938 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 939 }; 940 941 #ifdef CONFIG_ACPI 942 static const struct sdhci_pltfm_data sdhci_dwcmshc_bf3_pdata = { 943 .ops = &sdhci_dwcmshc_ops, 944 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 945 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 946 SDHCI_QUIRK2_ACMD23_BROKEN, 947 }; 948 #endif 949 950 static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 951 .ops = &sdhci_dwcmshc_rk35xx_ops, 952 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 953 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 954 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 955 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 956 }; 957 958 static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = { 959 .ops = &sdhci_dwcmshc_th1520_ops, 960 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 961 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 962 }; 963 964 static const struct sdhci_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { 965 .ops = &sdhci_dwcmshc_cv18xx_ops, 966 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 967 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 968 }; 969 970 static const struct cqhci_host_ops dwcmshc_cqhci_ops = { 971 .enable = dwcmshc_sdhci_cqe_enable, 972 .disable = sdhci_cqe_disable, 973 .dumpregs = dwcmshc_cqhci_dumpregs, 974 .set_tran_desc = dwcmshc_set_tran_desc, 975 }; 976 977 static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev) 978 { 979 struct cqhci_host *cq_host; 980 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 981 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 982 bool dma64 = false; 983 u16 clk; 984 int err; 985 986 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 987 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 988 if (!cq_host) { 989 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n"); 990 goto dsbl_cqe_caps; 991 } 992 993 /* 994 * For dwcmshc host controller we have to enable internal clock 995 * before access to some registers from Vendor Specific Area 2. 996 */ 997 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 998 clk |= SDHCI_CLOCK_INT_EN; 999 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1000 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1001 if (!(clk & SDHCI_CLOCK_INT_EN)) { 1002 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n"); 1003 goto free_cq_host; 1004 } 1005 1006 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; 1007 cq_host->ops = &dwcmshc_cqhci_ops; 1008 1009 /* Enable using of 128-bit task descriptors */ 1010 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1011 if (dma64) { 1012 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n"); 1013 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1014 } 1015 err = cqhci_init(cq_host, host->mmc, dma64); 1016 if (err) { 1017 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err); 1018 goto int_clock_disable; 1019 } 1020 1021 dev_dbg(mmc_dev(host->mmc), "CQE init done\n"); 1022 1023 return; 1024 1025 int_clock_disable: 1026 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1027 clk &= ~SDHCI_CLOCK_INT_EN; 1028 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1029 1030 free_cq_host: 1031 devm_kfree(&pdev->dev, cq_host); 1032 1033 dsbl_cqe_caps: 1034 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); 1035 } 1036 1037 static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 1038 { 1039 int err; 1040 struct rk35xx_priv *priv = dwc_priv->priv; 1041 1042 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 1043 if (IS_ERR(priv->reset)) { 1044 err = PTR_ERR(priv->reset); 1045 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 1046 return err; 1047 } 1048 1049 priv->rockchip_clks[0].id = "axi"; 1050 priv->rockchip_clks[1].id = "block"; 1051 priv->rockchip_clks[2].id = "timer"; 1052 err = devm_clk_bulk_get_optional(mmc_dev(host->mmc), RK35xx_MAX_CLKS, 1053 priv->rockchip_clks); 1054 if (err) { 1055 dev_err(mmc_dev(host->mmc), "failed to get clocks %d\n", err); 1056 return err; 1057 } 1058 1059 err = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, priv->rockchip_clks); 1060 if (err) { 1061 dev_err(mmc_dev(host->mmc), "failed to enable clocks %d\n", err); 1062 return err; 1063 } 1064 1065 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 1066 &priv->txclk_tapnum)) 1067 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 1068 1069 /* Disable cmd conflict check */ 1070 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 1071 /* Reset previous settings */ 1072 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 1073 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 1074 1075 return 0; 1076 } 1077 1078 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 1079 { 1080 /* 1081 * Don't support highspeed bus mode with low clk speed as we 1082 * cannot use DLL for this condition. 1083 */ 1084 if (host->mmc->f_max <= 52000000) { 1085 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 1086 host->mmc->f_max); 1087 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 1088 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 1089 } 1090 } 1091 1092 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { 1093 { 1094 .compatible = "rockchip,rk3588-dwcmshc", 1095 .data = &sdhci_dwcmshc_rk35xx_pdata, 1096 }, 1097 { 1098 .compatible = "rockchip,rk3568-dwcmshc", 1099 .data = &sdhci_dwcmshc_rk35xx_pdata, 1100 }, 1101 { 1102 .compatible = "snps,dwcmshc-sdhci", 1103 .data = &sdhci_dwcmshc_pdata, 1104 }, 1105 { 1106 .compatible = "sophgo,cv1800b-dwcmshc", 1107 .data = &sdhci_dwcmshc_cv18xx_pdata, 1108 }, 1109 { 1110 .compatible = "sophgo,sg2002-dwcmshc", 1111 .data = &sdhci_dwcmshc_cv18xx_pdata, 1112 }, 1113 { 1114 .compatible = "thead,th1520-dwcmshc", 1115 .data = &sdhci_dwcmshc_th1520_pdata, 1116 }, 1117 {}, 1118 }; 1119 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); 1120 1121 #ifdef CONFIG_ACPI 1122 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { 1123 { 1124 .id = "MLNXBF30", 1125 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata, 1126 }, 1127 {} 1128 }; 1129 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids); 1130 #endif 1131 1132 static int dwcmshc_probe(struct platform_device *pdev) 1133 { 1134 struct device *dev = &pdev->dev; 1135 struct sdhci_pltfm_host *pltfm_host; 1136 struct sdhci_host *host; 1137 struct dwcmshc_priv *priv; 1138 struct rk35xx_priv *rk_priv = NULL; 1139 const struct sdhci_pltfm_data *pltfm_data; 1140 int err; 1141 u32 extra, caps; 1142 1143 pltfm_data = device_get_match_data(&pdev->dev); 1144 if (!pltfm_data) { 1145 dev_err(&pdev->dev, "Error: No device match data found\n"); 1146 return -ENODEV; 1147 } 1148 1149 host = sdhci_pltfm_init(pdev, pltfm_data, 1150 sizeof(struct dwcmshc_priv)); 1151 if (IS_ERR(host)) 1152 return PTR_ERR(host); 1153 1154 /* 1155 * extra adma table cnt for cross 128M boundary handling. 1156 */ 1157 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); 1158 if (extra > SDHCI_MAX_SEGS) 1159 extra = SDHCI_MAX_SEGS; 1160 host->adma_table_cnt += extra; 1161 1162 pltfm_host = sdhci_priv(host); 1163 priv = sdhci_pltfm_priv(pltfm_host); 1164 1165 if (dev->of_node) { 1166 pltfm_host->clk = devm_clk_get(dev, "core"); 1167 if (IS_ERR(pltfm_host->clk)) { 1168 err = PTR_ERR(pltfm_host->clk); 1169 dev_err(dev, "failed to get core clk: %d\n", err); 1170 goto free_pltfm; 1171 } 1172 err = clk_prepare_enable(pltfm_host->clk); 1173 if (err) 1174 goto free_pltfm; 1175 1176 priv->bus_clk = devm_clk_get(dev, "bus"); 1177 if (!IS_ERR(priv->bus_clk)) 1178 clk_prepare_enable(priv->bus_clk); 1179 } 1180 1181 err = mmc_of_parse(host->mmc); 1182 if (err) 1183 goto err_clk; 1184 1185 sdhci_get_of_property(pdev); 1186 1187 priv->vendor_specific_area1 = 1188 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; 1189 1190 host->mmc_host_ops.request = dwcmshc_request; 1191 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 1192 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; 1193 1194 if (pltfm_data == &sdhci_dwcmshc_rk35xx_pdata) { 1195 rk_priv = devm_kzalloc(&pdev->dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 1196 if (!rk_priv) { 1197 err = -ENOMEM; 1198 goto err_clk; 1199 } 1200 1201 if (of_device_is_compatible(pdev->dev.of_node, "rockchip,rk3588-dwcmshc")) 1202 rk_priv->devtype = DWCMSHC_RK3588; 1203 else 1204 rk_priv->devtype = DWCMSHC_RK3568; 1205 1206 priv->priv = rk_priv; 1207 1208 err = dwcmshc_rk35xx_init(host, priv); 1209 if (err) 1210 goto err_clk; 1211 } 1212 1213 if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { 1214 priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; 1215 1216 if (device_property_read_bool(dev, "mmc-ddr-1_8v") || 1217 device_property_read_bool(dev, "mmc-hs200-1_8v") || 1218 device_property_read_bool(dev, "mmc-hs400-1_8v")) 1219 priv->flags |= FLAG_IO_FIXED_1V8; 1220 else 1221 priv->flags &= ~FLAG_IO_FIXED_1V8; 1222 1223 /* 1224 * start_signal_voltage_switch() will try 3.3V first 1225 * then 1.8V. Use SDHCI_SIGNALING_180 rather than 1226 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V 1227 * in sdhci_start_signal_voltage_switch(). 1228 */ 1229 if (priv->flags & FLAG_IO_FIXED_1V8) { 1230 host->flags &= ~SDHCI_SIGNALING_330; 1231 host->flags |= SDHCI_SIGNALING_180; 1232 } 1233 1234 sdhci_enable_v4_mode(host); 1235 } 1236 1237 #ifdef CONFIG_ACPI 1238 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) 1239 sdhci_enable_v4_mode(host); 1240 #endif 1241 1242 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 1243 if (caps & SDHCI_CAN_64BIT_V4) 1244 sdhci_enable_v4_mode(host); 1245 1246 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1247 1248 pm_runtime_get_noresume(dev); 1249 pm_runtime_set_active(dev); 1250 pm_runtime_enable(dev); 1251 1252 err = sdhci_setup_host(host); 1253 if (err) 1254 goto err_rpm; 1255 1256 /* Setup Command Queue Engine if enabled */ 1257 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 1258 priv->vendor_specific_area2 = 1259 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2); 1260 1261 dwcmshc_cqhci_init(host, pdev); 1262 } 1263 1264 if (rk_priv) 1265 dwcmshc_rk35xx_postinit(host, priv); 1266 1267 err = __sdhci_add_host(host); 1268 if (err) 1269 goto err_setup_host; 1270 1271 pm_runtime_put(dev); 1272 1273 return 0; 1274 1275 err_setup_host: 1276 sdhci_cleanup_host(host); 1277 err_rpm: 1278 pm_runtime_disable(dev); 1279 pm_runtime_put_noidle(dev); 1280 err_clk: 1281 clk_disable_unprepare(pltfm_host->clk); 1282 clk_disable_unprepare(priv->bus_clk); 1283 if (rk_priv) 1284 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1285 rk_priv->rockchip_clks); 1286 free_pltfm: 1287 sdhci_pltfm_free(pdev); 1288 return err; 1289 } 1290 1291 static void dwcmshc_disable_card_clk(struct sdhci_host *host) 1292 { 1293 u16 ctrl; 1294 1295 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1296 if (ctrl & SDHCI_CLOCK_CARD_EN) { 1297 ctrl &= ~SDHCI_CLOCK_CARD_EN; 1298 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1299 } 1300 } 1301 1302 static void dwcmshc_remove(struct platform_device *pdev) 1303 { 1304 struct sdhci_host *host = platform_get_drvdata(pdev); 1305 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1306 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1307 struct rk35xx_priv *rk_priv = priv->priv; 1308 1309 pm_runtime_get_sync(&pdev->dev); 1310 pm_runtime_disable(&pdev->dev); 1311 pm_runtime_put_noidle(&pdev->dev); 1312 1313 sdhci_remove_host(host, 0); 1314 1315 dwcmshc_disable_card_clk(host); 1316 1317 clk_disable_unprepare(pltfm_host->clk); 1318 clk_disable_unprepare(priv->bus_clk); 1319 if (rk_priv) 1320 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1321 rk_priv->rockchip_clks); 1322 sdhci_pltfm_free(pdev); 1323 } 1324 1325 #ifdef CONFIG_PM_SLEEP 1326 static int dwcmshc_suspend(struct device *dev) 1327 { 1328 struct sdhci_host *host = dev_get_drvdata(dev); 1329 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1330 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1331 struct rk35xx_priv *rk_priv = priv->priv; 1332 int ret; 1333 1334 pm_runtime_resume(dev); 1335 1336 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1337 ret = cqhci_suspend(host->mmc); 1338 if (ret) 1339 return ret; 1340 } 1341 1342 ret = sdhci_suspend_host(host); 1343 if (ret) 1344 return ret; 1345 1346 clk_disable_unprepare(pltfm_host->clk); 1347 if (!IS_ERR(priv->bus_clk)) 1348 clk_disable_unprepare(priv->bus_clk); 1349 1350 if (rk_priv) 1351 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1352 rk_priv->rockchip_clks); 1353 1354 return ret; 1355 } 1356 1357 static int dwcmshc_resume(struct device *dev) 1358 { 1359 struct sdhci_host *host = dev_get_drvdata(dev); 1360 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1361 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1362 struct rk35xx_priv *rk_priv = priv->priv; 1363 int ret; 1364 1365 ret = clk_prepare_enable(pltfm_host->clk); 1366 if (ret) 1367 return ret; 1368 1369 if (!IS_ERR(priv->bus_clk)) { 1370 ret = clk_prepare_enable(priv->bus_clk); 1371 if (ret) 1372 goto disable_clk; 1373 } 1374 1375 if (rk_priv) { 1376 ret = clk_bulk_prepare_enable(RK35xx_MAX_CLKS, 1377 rk_priv->rockchip_clks); 1378 if (ret) 1379 goto disable_bus_clk; 1380 } 1381 1382 ret = sdhci_resume_host(host); 1383 if (ret) 1384 goto disable_rockchip_clks; 1385 1386 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1387 ret = cqhci_resume(host->mmc); 1388 if (ret) 1389 goto disable_rockchip_clks; 1390 } 1391 1392 return 0; 1393 1394 disable_rockchip_clks: 1395 if (rk_priv) 1396 clk_bulk_disable_unprepare(RK35xx_MAX_CLKS, 1397 rk_priv->rockchip_clks); 1398 disable_bus_clk: 1399 if (!IS_ERR(priv->bus_clk)) 1400 clk_disable_unprepare(priv->bus_clk); 1401 disable_clk: 1402 clk_disable_unprepare(pltfm_host->clk); 1403 return ret; 1404 } 1405 #endif 1406 1407 #ifdef CONFIG_PM 1408 1409 static void dwcmshc_enable_card_clk(struct sdhci_host *host) 1410 { 1411 u16 ctrl; 1412 1413 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1414 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { 1415 ctrl |= SDHCI_CLOCK_CARD_EN; 1416 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1417 } 1418 } 1419 1420 static int dwcmshc_runtime_suspend(struct device *dev) 1421 { 1422 struct sdhci_host *host = dev_get_drvdata(dev); 1423 1424 dwcmshc_disable_card_clk(host); 1425 1426 return 0; 1427 } 1428 1429 static int dwcmshc_runtime_resume(struct device *dev) 1430 { 1431 struct sdhci_host *host = dev_get_drvdata(dev); 1432 1433 dwcmshc_enable_card_clk(host); 1434 1435 return 0; 1436 } 1437 1438 #endif 1439 1440 static const struct dev_pm_ops dwcmshc_pmops = { 1441 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume) 1442 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, 1443 dwcmshc_runtime_resume, NULL) 1444 }; 1445 1446 static struct platform_driver sdhci_dwcmshc_driver = { 1447 .driver = { 1448 .name = "sdhci-dwcmshc", 1449 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1450 .of_match_table = sdhci_dwcmshc_dt_ids, 1451 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), 1452 .pm = &dwcmshc_pmops, 1453 }, 1454 .probe = dwcmshc_probe, 1455 .remove_new = dwcmshc_remove, 1456 }; 1457 module_platform_driver(sdhci_dwcmshc_driver); 1458 1459 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC"); 1460 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); 1461 MODULE_LICENSE("GPL v2"); 1462