1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Driver for Synopsys DesignWare Cores Mobile Storage Host Controller 4 * 5 * Copyright (C) 2018 Synaptics Incorporated 6 * 7 * Author: Jisheng Zhang <jszhang@kernel.org> 8 */ 9 10 #include <linux/acpi.h> 11 #include <linux/arm-smccc.h> 12 #include <linux/bitfield.h> 13 #include <linux/clk.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/iopoll.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 #include <linux/sizes.h> 23 24 #include "sdhci-pltfm.h" 25 #include "cqhci.h" 26 27 #define SDHCI_DWCMSHC_ARG2_STUFF GENMASK(31, 16) 28 29 /* DWCMSHC specific Mode Select value */ 30 #define DWCMSHC_CTRL_HS400 0x7 31 32 /* DWC IP vendor area 1 pointer */ 33 #define DWCMSHC_P_VENDOR_AREA1 0xe8 34 #define DWCMSHC_AREA1_MASK GENMASK(11, 0) 35 /* Offset inside the vendor area 1 */ 36 #define DWCMSHC_HOST_CTRL3 0x8 37 #define DWCMSHC_EMMC_CONTROL 0x2c 38 #define DWCMSHC_CARD_IS_EMMC BIT(0) 39 #define DWCMSHC_ENHANCED_STROBE BIT(8) 40 #define DWCMSHC_EMMC_ATCTRL 0x40 41 /* Tuning and auto-tuning fields in AT_CTRL_R control register */ 42 #define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ 43 #define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ 44 #define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ 45 #define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ 46 #define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ 47 #define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ 48 #define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ 49 #define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */ 50 #define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ 51 #define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ 52 #define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ 53 #define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ 54 #define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ 55 #define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ 56 57 /* DWC IP vendor area 2 pointer */ 58 #define DWCMSHC_P_VENDOR_AREA2 0xea 59 60 /* Sophgo CV18XX specific Registers */ 61 #define CV18XX_SDHCI_MSHC_CTRL 0x00 62 #define CV18XX_EMMC_FUNC_EN BIT(0) 63 #define CV18XX_LATANCY_1T BIT(1) 64 #define CV18XX_SDHCI_PHY_TX_RX_DLY 0x40 65 #define CV18XX_PHY_TX_DLY_MSK GENMASK(6, 0) 66 #define CV18XX_PHY_TX_SRC_MSK GENMASK(9, 8) 67 #define CV18XX_PHY_TX_SRC_INVERT_CLK_TX 0x1 68 #define CV18XX_PHY_RX_DLY_MSK GENMASK(22, 16) 69 #define CV18XX_PHY_RX_SRC_MSK GENMASK(25, 24) 70 #define CV18XX_PHY_RX_SRC_INVERT_RX_CLK 0x1 71 #define CV18XX_SDHCI_PHY_CONFIG 0x4c 72 #define CV18XX_PHY_TX_BPS BIT(0) 73 74 #define CV18XX_TUNE_MAX 128 75 #define CV18XX_TUNE_STEP 1 76 #define CV18XX_RETRY_TUNING_MAX 50 77 78 /* Rockchip specific Registers */ 79 #define DWCMSHC_EMMC_DLL_CTRL 0x800 80 #define DWCMSHC_EMMC_DLL_RXCLK 0x804 81 #define DWCMSHC_EMMC_DLL_TXCLK 0x808 82 #define DWCMSHC_EMMC_DLL_STRBIN 0x80c 83 #define DECMSHC_EMMC_DLL_CMDOUT 0x810 84 #define DWCMSHC_EMMC_DLL_STATUS0 0x840 85 #define DWCMSHC_EMMC_DLL_START BIT(0) 86 #define DWCMSHC_EMMC_DLL_LOCKED BIT(8) 87 #define DWCMSHC_EMMC_DLL_TIMEOUT BIT(9) 88 #define DWCMSHC_EMMC_DLL_RXCLK_SRCSEL 29 89 #define DWCMSHC_EMMC_DLL_START_POINT 16 90 #define DWCMSHC_EMMC_DLL_INC 8 91 #define DWCMSHC_EMMC_DLL_BYPASS BIT(24) 92 #define DWCMSHC_EMMC_DLL_DLYENA BIT(27) 93 #define DLL_TXCLK_TAPNUM_DEFAULT 0x10 94 #define DLL_TXCLK_TAPNUM_90_DEGREES 0xA 95 #define DLL_TXCLK_TAPNUM_FROM_SW BIT(24) 96 #define DLL_STRBIN_TAPNUM_DEFAULT 0x8 97 #define DLL_STRBIN_TAPNUM_FROM_SW BIT(24) 98 #define DLL_STRBIN_DELAY_NUM_SEL BIT(26) 99 #define DLL_STRBIN_DELAY_NUM_OFFSET 16 100 #define DLL_STRBIN_DELAY_NUM_DEFAULT 0x16 101 #define DLL_RXCLK_NO_INVERTER 1 102 #define DLL_RXCLK_INVERTER 0 103 #define DLL_CMDOUT_TAPNUM_90_DEGREES 0x8 104 #define DLL_RXCLK_ORI_GATE BIT(31) 105 #define DLL_CMDOUT_TAPNUM_FROM_SW BIT(24) 106 #define DLL_CMDOUT_SRC_CLK_NEG BIT(28) 107 #define DLL_CMDOUT_EN_SRC_CLK_NEG BIT(29) 108 109 #define DLL_LOCK_WO_TMOUT(x) \ 110 ((((x) & DWCMSHC_EMMC_DLL_LOCKED) == DWCMSHC_EMMC_DLL_LOCKED) && \ 111 (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) 112 113 /* PHY register area pointer */ 114 #define DWC_MSHC_PTR_PHY_R 0x300 115 116 /* PHY general configuration */ 117 #define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) 118 #define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ 119 #define PHY_CNFG_PHY_PWRGOOD_MASK BIT_MASK(1) /* bit [1] */ 120 #define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ 121 #define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ 122 #define PHY_CNFG_PAD_SP_SG2042 0x09 /* PMOS TX drive strength for SG2042 */ 123 #define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ 124 #define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ 125 #define PHY_CNFG_PAD_SN_SG2042 0x08 /* NMOS TX drive strength for SG2042 */ 126 127 /* PHY command/response pad settings */ 128 #define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) 129 130 /* PHY data pad settings */ 131 #define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) 132 133 /* PHY clock pad settings */ 134 #define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) 135 136 /* PHY strobe pad settings */ 137 #define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) 138 139 /* PHY reset pad settings */ 140 #define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) 141 142 /* Bitfields are common for all pad settings */ 143 #define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ 144 #define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ 145 146 #define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ 147 #define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ 148 #define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ 149 150 #define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ 151 #define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ 152 #define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ 153 #define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ 154 #define PHY_PAD_TXSLEW_CTRL_N_SG2042 0x2 /* Slew control for N-Type pad TX for SG2042 */ 155 156 /* PHY CLK delay line settings */ 157 #define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) 158 #define PHY_SDCLKDL_CNFG_EXTDLY_EN BIT(0) 159 #define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ 160 161 /* PHY CLK delay line delay code */ 162 #define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) 163 #define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ 164 #define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ 165 #define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ 166 167 #define PHY_SMPLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x20) 168 #define PHY_SMPLDL_CNFG_BYPASS_EN BIT(1) 169 170 /* PHY drift_cclk_rx delay line configuration setting */ 171 #define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) 172 #define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ 173 #define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ 174 #define PHY_ATDL_CNFG_INPSEL_SG2042 0x2 /* delay line input source for SG2042 */ 175 176 /* PHY DLL control settings */ 177 #define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) 178 #define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ 179 #define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ 180 181 /* PHY DLL configuration register 1 */ 182 #define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) 183 #define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ 184 #define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ 185 #define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ 186 187 /* PHY DLL configuration register 2 */ 188 #define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) 189 #define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ 190 191 /* PHY DLL master and slave delay line configuration settings */ 192 #define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) 193 #define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ 194 #define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ 195 196 #define FLAG_IO_FIXED_1V8 BIT(0) 197 198 #define BOUNDARY_OK(addr, len) \ 199 ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) 200 201 #define DWCMSHC_SDHCI_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ 202 SDHCI_TRNS_BLK_CNT_EN | \ 203 SDHCI_TRNS_DMA) 204 205 /* SMC call for BlueField-3 eMMC RST_N */ 206 #define BLUEFIELD_SMC_SET_EMMC_RST_N 0x82000007 207 208 enum dwcmshc_rk_type { 209 DWCMSHC_RK3568, 210 DWCMSHC_RK3588, 211 }; 212 213 struct rk35xx_priv { 214 struct reset_control *reset; 215 enum dwcmshc_rk_type devtype; 216 u8 txclk_tapnum; 217 }; 218 219 #define DWCMSHC_MAX_OTHER_CLKS 3 220 221 struct dwcmshc_priv { 222 struct clk *bus_clk; 223 int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA1 reg */ 224 int vendor_specific_area2; /* P_VENDOR_SPECIFIC_AREA2 reg */ 225 226 int num_other_clks; 227 struct clk_bulk_data other_clks[DWCMSHC_MAX_OTHER_CLKS]; 228 229 void *priv; /* pointer to SoC private stuff */ 230 u16 delay_line; 231 u16 flags; 232 }; 233 234 struct dwcmshc_pltfm_data { 235 const struct sdhci_pltfm_data pdata; 236 int (*init)(struct device *dev, struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 237 void (*postinit)(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv); 238 }; 239 240 static int dwcmshc_get_enable_other_clks(struct device *dev, 241 struct dwcmshc_priv *priv, 242 int num_clks, 243 const char * const clk_ids[]) 244 { 245 int err; 246 247 if (num_clks > DWCMSHC_MAX_OTHER_CLKS) 248 return -EINVAL; 249 250 for (int i = 0; i < num_clks; i++) 251 priv->other_clks[i].id = clk_ids[i]; 252 253 err = devm_clk_bulk_get_optional(dev, num_clks, priv->other_clks); 254 if (err) { 255 dev_err(dev, "failed to get clocks %d\n", err); 256 return err; 257 } 258 259 err = clk_bulk_prepare_enable(num_clks, priv->other_clks); 260 if (err) 261 dev_err(dev, "failed to enable clocks %d\n", err); 262 263 priv->num_other_clks = num_clks; 264 265 return err; 266 } 267 268 /* 269 * If DMA addr spans 128MB boundary, we split the DMA transfer into two 270 * so that each DMA transfer doesn't exceed the boundary. 271 */ 272 static void dwcmshc_adma_write_desc(struct sdhci_host *host, void **desc, 273 dma_addr_t addr, int len, unsigned int cmd) 274 { 275 int tmplen, offset; 276 277 if (likely(!len || BOUNDARY_OK(addr, len))) { 278 sdhci_adma_write_desc(host, desc, addr, len, cmd); 279 return; 280 } 281 282 offset = addr & (SZ_128M - 1); 283 tmplen = SZ_128M - offset; 284 sdhci_adma_write_desc(host, desc, addr, tmplen, cmd); 285 286 addr += tmplen; 287 len -= tmplen; 288 sdhci_adma_write_desc(host, desc, addr, len, cmd); 289 } 290 291 static unsigned int dwcmshc_get_max_clock(struct sdhci_host *host) 292 { 293 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 294 295 if (pltfm_host->clk) 296 return sdhci_pltfm_clk_get_max_clock(host); 297 else 298 return pltfm_host->clock; 299 } 300 301 static unsigned int rk35xx_get_max_clock(struct sdhci_host *host) 302 { 303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 304 305 return clk_round_rate(pltfm_host->clk, ULONG_MAX); 306 } 307 308 static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc, 309 struct mmc_request *mrq) 310 { 311 struct sdhci_host *host = mmc_priv(mmc); 312 313 /* 314 * No matter V4 is enabled or not, ARGUMENT2 register is 32-bit 315 * block count register which doesn't support stuff bits of 316 * CMD23 argument on dwcmsch host controller. 317 */ 318 if (mrq->sbc && (mrq->sbc->arg & SDHCI_DWCMSHC_ARG2_STUFF)) 319 host->flags &= ~SDHCI_AUTO_CMD23; 320 else 321 host->flags |= SDHCI_AUTO_CMD23; 322 } 323 324 static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) 325 { 326 dwcmshc_check_auto_cmd23(mmc, mrq); 327 328 sdhci_request(mmc, mrq); 329 } 330 331 static void dwcmshc_phy_1_8v_init(struct sdhci_host *host) 332 { 333 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 334 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 335 u32 val; 336 337 /* deassert phy reset & set tx drive strength */ 338 val = PHY_CNFG_RSTN_DEASSERT; 339 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); 340 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); 341 sdhci_writel(host, val, PHY_CNFG_R); 342 343 /* disable delay line */ 344 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); 345 346 /* set delay line */ 347 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); 348 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); 349 350 /* enable delay lane */ 351 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 352 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 353 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 354 355 /* configure phy pads */ 356 val = PHY_PAD_RXSEL_1V8; 357 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 358 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 359 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 360 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 361 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 362 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 363 364 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 365 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 366 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 367 368 val = PHY_PAD_RXSEL_1V8; 369 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 370 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 371 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 372 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 373 374 /* enable data strobe mode */ 375 sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL), 376 PHY_DLLDL_CNFG_R); 377 378 /* enable phy dll */ 379 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); 380 } 381 382 static void dwcmshc_phy_3_3v_init(struct sdhci_host *host) 383 { 384 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 385 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 386 u32 val; 387 388 /* deassert phy reset & set tx drive strength */ 389 val = PHY_CNFG_RSTN_DEASSERT; 390 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); 391 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); 392 sdhci_writel(host, val, PHY_CNFG_R); 393 394 /* disable delay line */ 395 sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); 396 397 /* set delay line */ 398 sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); 399 sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); 400 401 /* enable delay lane */ 402 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 403 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 404 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 405 406 /* configure phy pads */ 407 val = PHY_PAD_RXSEL_3V3; 408 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 409 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 410 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 411 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 412 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 413 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 414 415 val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 416 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 417 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 418 419 val = PHY_PAD_RXSEL_3V3; 420 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 421 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 422 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); 423 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 424 425 /* enable phy dll */ 426 sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); 427 } 428 429 static void th1520_sdhci_set_phy(struct sdhci_host *host) 430 { 431 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 432 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 433 u32 emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 434 u16 emmc_ctrl; 435 436 /* Before power on, set PHY configs */ 437 if (priv->flags & FLAG_IO_FIXED_1V8) 438 dwcmshc_phy_1_8v_init(host); 439 else 440 dwcmshc_phy_3_3v_init(host); 441 442 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 443 emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 444 emmc_ctrl |= DWCMSHC_CARD_IS_EMMC; 445 sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 446 } 447 448 sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | 449 PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); 450 } 451 452 static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, 453 unsigned int timing) 454 { 455 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 456 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 457 u16 ctrl, ctrl_2; 458 459 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 460 /* Select Bus Speed Mode for host */ 461 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 462 if ((timing == MMC_TIMING_MMC_HS200) || 463 (timing == MMC_TIMING_UHS_SDR104)) 464 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 465 else if (timing == MMC_TIMING_UHS_SDR12) 466 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 467 else if ((timing == MMC_TIMING_UHS_SDR25) || 468 (timing == MMC_TIMING_MMC_HS)) 469 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 470 else if (timing == MMC_TIMING_UHS_SDR50) 471 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 472 else if ((timing == MMC_TIMING_UHS_DDR50) || 473 (timing == MMC_TIMING_MMC_DDR52)) 474 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 475 else if (timing == MMC_TIMING_MMC_HS400) { 476 /* set CARD_IS_EMMC bit to enable Data Strobe for HS400 */ 477 ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 478 ctrl |= DWCMSHC_CARD_IS_EMMC; 479 sdhci_writew(host, ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); 480 481 ctrl_2 |= DWCMSHC_CTRL_HS400; 482 } 483 484 if (priv->flags & FLAG_IO_FIXED_1V8) 485 ctrl_2 |= SDHCI_CTRL_VDD_180; 486 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 487 } 488 489 static void th1520_set_uhs_signaling(struct sdhci_host *host, 490 unsigned int timing) 491 { 492 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 493 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 494 495 dwcmshc_set_uhs_signaling(host, timing); 496 if (timing == MMC_TIMING_MMC_HS400) 497 priv->delay_line = PHY_SDCLKDL_DC_HS400; 498 else 499 sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); 500 th1520_sdhci_set_phy(host); 501 } 502 503 static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, 504 struct mmc_ios *ios) 505 { 506 u32 vendor; 507 struct sdhci_host *host = mmc_priv(mmc); 508 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 509 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 510 int reg = priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL; 511 512 vendor = sdhci_readl(host, reg); 513 if (ios->enhanced_strobe) 514 vendor |= DWCMSHC_ENHANCED_STROBE; 515 else 516 vendor &= ~DWCMSHC_ENHANCED_STROBE; 517 518 sdhci_writel(host, vendor, reg); 519 } 520 521 static int dwcmshc_execute_tuning(struct mmc_host *mmc, u32 opcode) 522 { 523 int err = sdhci_execute_tuning(mmc, opcode); 524 struct sdhci_host *host = mmc_priv(mmc); 525 526 if (err) 527 return err; 528 529 /* 530 * Tuning can leave the IP in an active state (Buffer Read Enable bit 531 * set) which prevents the entry to low power states (i.e. S0i3). Data 532 * reset will clear it. 533 */ 534 sdhci_reset(host, SDHCI_RESET_DATA); 535 536 return 0; 537 } 538 539 static u32 dwcmshc_cqe_irq_handler(struct sdhci_host *host, u32 intmask) 540 { 541 int cmd_error = 0; 542 int data_error = 0; 543 544 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 545 return intmask; 546 547 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 548 549 return 0; 550 } 551 552 static void dwcmshc_sdhci_cqe_enable(struct mmc_host *mmc) 553 { 554 struct sdhci_host *host = mmc_priv(mmc); 555 u8 ctrl; 556 557 sdhci_writew(host, DWCMSHC_SDHCI_CQE_TRNS_MODE, SDHCI_TRANSFER_MODE); 558 559 sdhci_cqe_enable(mmc); 560 561 /* 562 * The "DesignWare Cores Mobile Storage Host Controller 563 * DWC_mshc / DWC_mshc_lite Databook" says: 564 * when Host Version 4 Enable" is 1 in Host Control 2 register, 565 * SDHCI_CTRL_ADMA32 bit means ADMA2 is selected. 566 * Selection of 32-bit/64-bit System Addressing: 567 * either 32-bit or 64-bit system addressing is selected by 568 * 64-bit Addressing bit in Host Control 2 register. 569 * 570 * On the other hand the "DesignWare Cores Mobile Storage Host 571 * Controller DWC_mshc / DWC_mshc_lite User Guide" says, that we have to 572 * set DMA_SEL to ADMA2 _only_ mode in the Host Control 2 register. 573 */ 574 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 575 ctrl &= ~SDHCI_CTRL_DMA_MASK; 576 ctrl |= SDHCI_CTRL_ADMA32; 577 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 578 } 579 580 static void dwcmshc_set_tran_desc(struct cqhci_host *cq_host, u8 **desc, 581 dma_addr_t addr, int len, bool end, bool dma64) 582 { 583 int tmplen, offset; 584 585 if (likely(!len || BOUNDARY_OK(addr, len))) { 586 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 587 return; 588 } 589 590 offset = addr & (SZ_128M - 1); 591 tmplen = SZ_128M - offset; 592 cqhci_set_tran_desc(*desc, addr, tmplen, false, dma64); 593 594 addr += tmplen; 595 len -= tmplen; 596 *desc += cq_host->trans_desc_len; 597 cqhci_set_tran_desc(*desc, addr, len, end, dma64); 598 } 599 600 static void dwcmshc_cqhci_dumpregs(struct mmc_host *mmc) 601 { 602 sdhci_dumpregs(mmc_priv(mmc)); 603 } 604 605 static void dwcmshc_rk3568_set_clock(struct sdhci_host *host, unsigned int clock) 606 { 607 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 608 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 609 struct rk35xx_priv *priv = dwc_priv->priv; 610 u8 txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 611 u32 extra, reg; 612 int err; 613 614 host->mmc->actual_clock = 0; 615 616 if (clock == 0) { 617 /* Disable interface clock at initial state. */ 618 sdhci_set_clock(host, clock); 619 return; 620 } 621 622 /* Rockchip platform only support 375KHz for identify mode */ 623 if (clock <= 400000) 624 clock = 375000; 625 626 err = clk_set_rate(pltfm_host->clk, clock); 627 if (err) 628 dev_err(mmc_dev(host->mmc), "fail to set clock %d", clock); 629 630 sdhci_set_clock(host, clock); 631 632 /* Disable cmd conflict check */ 633 reg = dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3; 634 extra = sdhci_readl(host, reg); 635 extra &= ~BIT(0); 636 sdhci_writel(host, extra, reg); 637 638 if (clock <= 52000000) { 639 /* 640 * Disable DLL and reset both of sample and drive clock. 641 * The bypass bit and start bit need to be set if DLL is not locked. 642 */ 643 sdhci_writel(host, DWCMSHC_EMMC_DLL_BYPASS | DWCMSHC_EMMC_DLL_START, DWCMSHC_EMMC_DLL_CTRL); 644 sdhci_writel(host, DLL_RXCLK_ORI_GATE, DWCMSHC_EMMC_DLL_RXCLK); 645 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 646 sdhci_writel(host, 0, DECMSHC_EMMC_DLL_CMDOUT); 647 /* 648 * Before switching to hs400es mode, the driver will enable 649 * enhanced strobe first. PHY needs to configure the parameters 650 * of enhanced strobe first. 651 */ 652 extra = DWCMSHC_EMMC_DLL_DLYENA | 653 DLL_STRBIN_DELAY_NUM_SEL | 654 DLL_STRBIN_DELAY_NUM_DEFAULT << DLL_STRBIN_DELAY_NUM_OFFSET; 655 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 656 return; 657 } 658 659 /* Reset DLL */ 660 sdhci_writel(host, BIT(1), DWCMSHC_EMMC_DLL_CTRL); 661 udelay(1); 662 sdhci_writel(host, 0x0, DWCMSHC_EMMC_DLL_CTRL); 663 664 /* 665 * We shouldn't set DLL_RXCLK_NO_INVERTER for identify mode but 666 * we must set it in higher speed mode. 667 */ 668 extra = DWCMSHC_EMMC_DLL_DLYENA; 669 if (priv->devtype == DWCMSHC_RK3568) 670 extra |= DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL; 671 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_RXCLK); 672 673 /* Init DLL settings */ 674 extra = 0x5 << DWCMSHC_EMMC_DLL_START_POINT | 675 0x2 << DWCMSHC_EMMC_DLL_INC | 676 DWCMSHC_EMMC_DLL_START; 677 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_CTRL); 678 err = readl_poll_timeout(host->ioaddr + DWCMSHC_EMMC_DLL_STATUS0, 679 extra, DLL_LOCK_WO_TMOUT(extra), 1, 680 500 * USEC_PER_MSEC); 681 if (err) { 682 dev_err(mmc_dev(host->mmc), "DLL lock timeout!\n"); 683 return; 684 } 685 686 extra = 0x1 << 16 | /* tune clock stop en */ 687 0x3 << 17 | /* pre-change delay */ 688 0x3 << 19; /* post-change delay */ 689 sdhci_writel(host, extra, dwc_priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 690 691 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200 || 692 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) 693 txclk_tapnum = priv->txclk_tapnum; 694 695 if ((priv->devtype == DWCMSHC_RK3588) && host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 696 txclk_tapnum = DLL_TXCLK_TAPNUM_90_DEGREES; 697 698 extra = DLL_CMDOUT_SRC_CLK_NEG | 699 DLL_CMDOUT_EN_SRC_CLK_NEG | 700 DWCMSHC_EMMC_DLL_DLYENA | 701 DLL_CMDOUT_TAPNUM_90_DEGREES | 702 DLL_CMDOUT_TAPNUM_FROM_SW; 703 sdhci_writel(host, extra, DECMSHC_EMMC_DLL_CMDOUT); 704 } 705 706 extra = DWCMSHC_EMMC_DLL_DLYENA | 707 DLL_TXCLK_TAPNUM_FROM_SW | 708 DLL_RXCLK_NO_INVERTER << DWCMSHC_EMMC_DLL_RXCLK_SRCSEL | 709 txclk_tapnum; 710 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_TXCLK); 711 712 extra = DWCMSHC_EMMC_DLL_DLYENA | 713 DLL_STRBIN_TAPNUM_DEFAULT | 714 DLL_STRBIN_TAPNUM_FROM_SW; 715 sdhci_writel(host, extra, DWCMSHC_EMMC_DLL_STRBIN); 716 } 717 718 static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) 719 { 720 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 721 struct dwcmshc_priv *dwc_priv = sdhci_pltfm_priv(pltfm_host); 722 struct rk35xx_priv *priv = dwc_priv->priv; 723 724 if (mask & SDHCI_RESET_ALL && priv->reset) { 725 reset_control_assert(priv->reset); 726 udelay(1); 727 reset_control_deassert(priv->reset); 728 } 729 730 sdhci_reset(host, mask); 731 } 732 733 static int dwcmshc_rk35xx_init(struct device *dev, struct sdhci_host *host, 734 struct dwcmshc_priv *dwc_priv) 735 { 736 static const char * const clk_ids[] = {"axi", "block", "timer"}; 737 struct rk35xx_priv *priv; 738 int err; 739 740 priv = devm_kzalloc(dev, sizeof(struct rk35xx_priv), GFP_KERNEL); 741 if (!priv) 742 return -ENOMEM; 743 744 if (of_device_is_compatible(dev->of_node, "rockchip,rk3588-dwcmshc")) 745 priv->devtype = DWCMSHC_RK3588; 746 else 747 priv->devtype = DWCMSHC_RK3568; 748 749 priv->reset = devm_reset_control_array_get_optional_exclusive(mmc_dev(host->mmc)); 750 if (IS_ERR(priv->reset)) { 751 err = PTR_ERR(priv->reset); 752 dev_err(mmc_dev(host->mmc), "failed to get reset control %d\n", err); 753 return err; 754 } 755 756 err = dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 757 ARRAY_SIZE(clk_ids), clk_ids); 758 if (err) 759 return err; 760 761 if (of_property_read_u8(mmc_dev(host->mmc)->of_node, "rockchip,txclk-tapnum", 762 &priv->txclk_tapnum)) 763 priv->txclk_tapnum = DLL_TXCLK_TAPNUM_DEFAULT; 764 765 /* Disable cmd conflict check */ 766 sdhci_writel(host, 0x0, dwc_priv->vendor_specific_area1 + DWCMSHC_HOST_CTRL3); 767 /* Reset previous settings */ 768 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_TXCLK); 769 sdhci_writel(host, 0, DWCMSHC_EMMC_DLL_STRBIN); 770 771 dwc_priv->priv = priv; 772 773 return 0; 774 } 775 776 static void dwcmshc_rk35xx_postinit(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) 777 { 778 /* 779 * Don't support highspeed bus mode with low clk speed as we 780 * cannot use DLL for this condition. 781 */ 782 if (host->mmc->f_max <= 52000000) { 783 dev_info(mmc_dev(host->mmc), "Disabling HS200/HS400, frequency too low (%d)\n", 784 host->mmc->f_max); 785 host->mmc->caps2 &= ~(MMC_CAP2_HS200 | MMC_CAP2_HS400); 786 host->mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR); 787 } 788 } 789 790 static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) 791 { 792 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 793 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 794 u32 val = 0; 795 796 if (host->flags & SDHCI_HS400_TUNING) 797 return 0; 798 799 sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL), 800 PHY_ATDL_CNFG_R); 801 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 802 803 /* 804 * configure tuning settings: 805 * - center phase select code driven in block gap interval 806 * - disable reporting of framing errors 807 * - disable software managed tuning 808 * - disable user selection of sampling window edges, 809 * instead tuning calculated edges are used 810 */ 811 val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | 812 FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); 813 814 /* 815 * configure tuning settings: 816 * - enable auto-tuning 817 * - enable sampling window threshold 818 * - stop clocks during phase code change 819 * - set max latency in cycles between tx and rx clocks 820 * - set max latency in cycles to switch output phase 821 * - set max sampling window threshold value 822 */ 823 val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; 824 val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); 825 val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); 826 val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); 827 828 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 829 val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 830 831 /* perform tuning */ 832 sdhci_start_tuning(host); 833 host->tuning_loop_count = 128; 834 host->tuning_err = __sdhci_execute_tuning(host, opcode); 835 if (host->tuning_err) { 836 /* disable auto-tuning upon tuning error */ 837 val &= ~AT_CTRL_AT_EN; 838 sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); 839 dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); 840 return -EIO; 841 } 842 sdhci_end_tuning(host); 843 844 return 0; 845 } 846 847 static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) 848 { 849 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 850 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 851 u16 ctrl_2; 852 853 sdhci_reset(host, mask); 854 855 if (priv->flags & FLAG_IO_FIXED_1V8) { 856 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 857 if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) { 858 ctrl_2 |= SDHCI_CTRL_VDD_180; 859 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 860 } 861 } 862 } 863 864 static int th1520_init(struct device *dev, 865 struct sdhci_host *host, 866 struct dwcmshc_priv *dwc_priv) 867 { 868 dwc_priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; 869 870 if (device_property_read_bool(dev, "mmc-ddr-1_8v") || 871 device_property_read_bool(dev, "mmc-hs200-1_8v") || 872 device_property_read_bool(dev, "mmc-hs400-1_8v")) 873 dwc_priv->flags |= FLAG_IO_FIXED_1V8; 874 else 875 dwc_priv->flags &= ~FLAG_IO_FIXED_1V8; 876 877 /* 878 * start_signal_voltage_switch() will try 3.3V first 879 * then 1.8V. Use SDHCI_SIGNALING_180 rather than 880 * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V 881 * in sdhci_start_signal_voltage_switch(). 882 */ 883 if (dwc_priv->flags & FLAG_IO_FIXED_1V8) { 884 host->flags &= ~SDHCI_SIGNALING_330; 885 host->flags |= SDHCI_SIGNALING_180; 886 } 887 888 sdhci_enable_v4_mode(host); 889 890 return 0; 891 } 892 893 static void cv18xx_sdhci_reset(struct sdhci_host *host, u8 mask) 894 { 895 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 896 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 897 u32 val, emmc_caps = MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 898 899 sdhci_reset(host, mask); 900 901 if ((host->mmc->caps2 & emmc_caps) == emmc_caps) { 902 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 903 val |= CV18XX_EMMC_FUNC_EN; 904 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 905 } 906 907 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 908 val |= CV18XX_LATANCY_1T; 909 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 910 911 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 912 val |= CV18XX_PHY_TX_BPS; 913 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 914 915 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 916 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 917 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, 0) | 918 FIELD_PREP(CV18XX_PHY_RX_SRC_MSK, CV18XX_PHY_RX_SRC_INVERT_RX_CLK)); 919 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 920 } 921 922 static void cv18xx_sdhci_set_tap(struct sdhci_host *host, int tap) 923 { 924 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 925 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 926 u16 clk; 927 u32 val; 928 929 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 930 clk &= ~SDHCI_CLOCK_CARD_EN; 931 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 932 933 val = sdhci_readl(host, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 934 val &= ~CV18XX_LATANCY_1T; 935 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_MSHC_CTRL); 936 937 val = (FIELD_PREP(CV18XX_PHY_TX_DLY_MSK, 0) | 938 FIELD_PREP(CV18XX_PHY_TX_SRC_MSK, CV18XX_PHY_TX_SRC_INVERT_CLK_TX) | 939 FIELD_PREP(CV18XX_PHY_RX_DLY_MSK, tap)); 940 sdhci_writel(host, val, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_TX_RX_DLY); 941 942 sdhci_writel(host, 0, priv->vendor_specific_area1 + CV18XX_SDHCI_PHY_CONFIG); 943 944 clk |= SDHCI_CLOCK_CARD_EN; 945 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 946 usleep_range(1000, 2000); 947 } 948 949 static int cv18xx_retry_tuning(struct mmc_host *mmc, u32 opcode, int *cmd_error) 950 { 951 int ret, retry = 0; 952 953 while (retry < CV18XX_RETRY_TUNING_MAX) { 954 ret = mmc_send_tuning(mmc, opcode, NULL); 955 if (ret) 956 return ret; 957 retry++; 958 } 959 960 return 0; 961 } 962 963 static void cv18xx_sdhci_post_tuning(struct sdhci_host *host) 964 { 965 u32 val; 966 967 val = sdhci_readl(host, SDHCI_INT_STATUS); 968 val |= SDHCI_INT_DATA_AVAIL; 969 sdhci_writel(host, val, SDHCI_INT_STATUS); 970 971 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 972 } 973 974 static int cv18xx_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) 975 { 976 int min, max, avg, ret; 977 int win_length, target_min, target_max, target_win_length; 978 979 min = max = 0; 980 target_win_length = 0; 981 982 sdhci_reset_tuning(host); 983 984 while (max < CV18XX_TUNE_MAX) { 985 /* find the mininum delay first which can pass tuning */ 986 while (min < CV18XX_TUNE_MAX) { 987 cv18xx_sdhci_set_tap(host, min); 988 if (!cv18xx_retry_tuning(host->mmc, opcode, NULL)) 989 break; 990 min += CV18XX_TUNE_STEP; 991 } 992 993 /* find the maxinum delay which can not pass tuning */ 994 max = min + CV18XX_TUNE_STEP; 995 while (max < CV18XX_TUNE_MAX) { 996 cv18xx_sdhci_set_tap(host, max); 997 if (cv18xx_retry_tuning(host->mmc, opcode, NULL)) { 998 max -= CV18XX_TUNE_STEP; 999 break; 1000 } 1001 max += CV18XX_TUNE_STEP; 1002 } 1003 1004 win_length = max - min + 1; 1005 /* get the largest pass window */ 1006 if (win_length > target_win_length) { 1007 target_win_length = win_length; 1008 target_min = min; 1009 target_max = max; 1010 } 1011 1012 /* continue to find the next pass window */ 1013 min = max + CV18XX_TUNE_STEP; 1014 } 1015 1016 cv18xx_sdhci_post_tuning(host); 1017 1018 /* use average delay to get the best timing */ 1019 avg = (target_min + target_max) / 2; 1020 cv18xx_sdhci_set_tap(host, avg); 1021 ret = mmc_send_tuning(host->mmc, opcode, NULL); 1022 1023 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 1024 ret ? "failed" : "passed", avg, ret); 1025 1026 return ret; 1027 } 1028 1029 static inline void sg2042_sdhci_phy_init(struct sdhci_host *host) 1030 { 1031 u32 val; 1032 1033 /* Asset phy reset & set tx drive strength */ 1034 val = sdhci_readl(host, PHY_CNFG_R); 1035 val &= ~PHY_CNFG_RSTN_DEASSERT; 1036 val |= FIELD_PREP(PHY_CNFG_PHY_PWRGOOD_MASK, 1); 1037 val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP_SG2042); 1038 val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN_SG2042); 1039 sdhci_writel(host, val, PHY_CNFG_R); 1040 1041 /* Configure phy pads */ 1042 val = PHY_PAD_RXSEL_3V3; 1043 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); 1044 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1045 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1046 sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); 1047 sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); 1048 sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); 1049 1050 val = PHY_PAD_RXSEL_3V3; 1051 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1052 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1053 sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); 1054 1055 val = PHY_PAD_RXSEL_3V3; 1056 val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); 1057 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); 1058 val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N_SG2042); 1059 sdhci_writew(host, val, PHY_STBPAD_CNFG_R); 1060 1061 /* Configure delay line */ 1062 /* Enable fixed delay */ 1063 sdhci_writeb(host, PHY_SDCLKDL_CNFG_EXTDLY_EN, PHY_SDCLKDL_CNFG_R); 1064 /* 1065 * Set delay line. 1066 * Its recommended that bit UPDATE_DC[4] is 1 when SDCLKDL_DC is being written. 1067 * Ensure UPDATE_DC[4] is '0' when not updating code. 1068 */ 1069 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 1070 val |= PHY_SDCLKDL_CNFG_UPDATE; 1071 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 1072 /* Add 10 * 70ps = 0.7ns for output delay */ 1073 sdhci_writeb(host, 10, PHY_SDCLKDL_DC_R); 1074 val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); 1075 val &= ~(PHY_SDCLKDL_CNFG_UPDATE); 1076 sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); 1077 1078 /* Set SMPLDL_CNFG, Bypass */ 1079 sdhci_writeb(host, PHY_SMPLDL_CNFG_BYPASS_EN, PHY_SMPLDL_CNFG_R); 1080 1081 /* Set ATDL_CNFG, tuning clk not use for init */ 1082 val = FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL_SG2042); 1083 sdhci_writeb(host, val, PHY_ATDL_CNFG_R); 1084 1085 /* Deasset phy reset */ 1086 val = sdhci_readl(host, PHY_CNFG_R); 1087 val |= PHY_CNFG_RSTN_DEASSERT; 1088 sdhci_writel(host, val, PHY_CNFG_R); 1089 } 1090 1091 static void sg2042_sdhci_reset(struct sdhci_host *host, u8 mask) 1092 { 1093 sdhci_reset(host, mask); 1094 1095 if (mask & SDHCI_RESET_ALL) 1096 sg2042_sdhci_phy_init(host); 1097 } 1098 1099 static int sg2042_init(struct device *dev, struct sdhci_host *host, 1100 struct dwcmshc_priv *dwc_priv) 1101 { 1102 static const char * const clk_ids[] = {"timer"}; 1103 1104 return dwcmshc_get_enable_other_clks(mmc_dev(host->mmc), dwc_priv, 1105 ARRAY_SIZE(clk_ids), clk_ids); 1106 } 1107 1108 static const struct sdhci_ops sdhci_dwcmshc_ops = { 1109 .set_clock = sdhci_set_clock, 1110 .set_bus_width = sdhci_set_bus_width, 1111 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1112 .get_max_clock = dwcmshc_get_max_clock, 1113 .reset = sdhci_reset, 1114 .adma_write_desc = dwcmshc_adma_write_desc, 1115 .irq = dwcmshc_cqe_irq_handler, 1116 }; 1117 1118 #ifdef CONFIG_ACPI 1119 static void dwcmshc_bf3_hw_reset(struct sdhci_host *host) 1120 { 1121 struct arm_smccc_res res = { 0 }; 1122 1123 arm_smccc_smc(BLUEFIELD_SMC_SET_EMMC_RST_N, 0, 0, 0, 0, 0, 0, 0, &res); 1124 1125 if (res.a0) 1126 pr_err("%s: RST_N failed.\n", mmc_hostname(host->mmc)); 1127 } 1128 1129 static const struct sdhci_ops sdhci_dwcmshc_bf3_ops = { 1130 .set_clock = sdhci_set_clock, 1131 .set_bus_width = sdhci_set_bus_width, 1132 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1133 .get_max_clock = dwcmshc_get_max_clock, 1134 .reset = sdhci_reset, 1135 .adma_write_desc = dwcmshc_adma_write_desc, 1136 .irq = dwcmshc_cqe_irq_handler, 1137 .hw_reset = dwcmshc_bf3_hw_reset, 1138 }; 1139 #endif 1140 1141 static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { 1142 .set_clock = dwcmshc_rk3568_set_clock, 1143 .set_bus_width = sdhci_set_bus_width, 1144 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1145 .get_max_clock = rk35xx_get_max_clock, 1146 .reset = rk35xx_sdhci_reset, 1147 .adma_write_desc = dwcmshc_adma_write_desc, 1148 .irq = dwcmshc_cqe_irq_handler, 1149 }; 1150 1151 static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { 1152 .set_clock = sdhci_set_clock, 1153 .set_bus_width = sdhci_set_bus_width, 1154 .set_uhs_signaling = th1520_set_uhs_signaling, 1155 .get_max_clock = dwcmshc_get_max_clock, 1156 .reset = th1520_sdhci_reset, 1157 .adma_write_desc = dwcmshc_adma_write_desc, 1158 .voltage_switch = dwcmshc_phy_1_8v_init, 1159 .platform_execute_tuning = th1520_execute_tuning, 1160 }; 1161 1162 static const struct sdhci_ops sdhci_dwcmshc_cv18xx_ops = { 1163 .set_clock = sdhci_set_clock, 1164 .set_bus_width = sdhci_set_bus_width, 1165 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1166 .get_max_clock = dwcmshc_get_max_clock, 1167 .reset = cv18xx_sdhci_reset, 1168 .adma_write_desc = dwcmshc_adma_write_desc, 1169 .platform_execute_tuning = cv18xx_sdhci_execute_tuning, 1170 }; 1171 1172 static const struct sdhci_ops sdhci_dwcmshc_sg2042_ops = { 1173 .set_clock = sdhci_set_clock, 1174 .set_bus_width = sdhci_set_bus_width, 1175 .set_uhs_signaling = dwcmshc_set_uhs_signaling, 1176 .get_max_clock = dwcmshc_get_max_clock, 1177 .reset = sg2042_sdhci_reset, 1178 .adma_write_desc = dwcmshc_adma_write_desc, 1179 .platform_execute_tuning = th1520_execute_tuning, 1180 }; 1181 1182 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_pdata = { 1183 .pdata = { 1184 .ops = &sdhci_dwcmshc_ops, 1185 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1186 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1187 }, 1188 }; 1189 1190 #ifdef CONFIG_ACPI 1191 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_bf3_pdata = { 1192 .pdata = { 1193 .ops = &sdhci_dwcmshc_bf3_ops, 1194 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1195 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1196 SDHCI_QUIRK2_ACMD23_BROKEN, 1197 }, 1198 }; 1199 #endif 1200 1201 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { 1202 .pdata = { 1203 .ops = &sdhci_dwcmshc_rk35xx_ops, 1204 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN | 1205 SDHCI_QUIRK_BROKEN_TIMEOUT_VAL, 1206 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | 1207 SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, 1208 }, 1209 .init = dwcmshc_rk35xx_init, 1210 .postinit = dwcmshc_rk35xx_postinit, 1211 }; 1212 1213 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_th1520_pdata = { 1214 .pdata = { 1215 .ops = &sdhci_dwcmshc_th1520_ops, 1216 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1217 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1218 }, 1219 .init = th1520_init, 1220 }; 1221 1222 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_cv18xx_pdata = { 1223 .pdata = { 1224 .ops = &sdhci_dwcmshc_cv18xx_ops, 1225 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1226 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1227 }, 1228 }; 1229 1230 static const struct dwcmshc_pltfm_data sdhci_dwcmshc_sg2042_pdata = { 1231 .pdata = { 1232 .ops = &sdhci_dwcmshc_sg2042_ops, 1233 .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, 1234 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 1235 }, 1236 .init = sg2042_init, 1237 }; 1238 1239 static const struct cqhci_host_ops dwcmshc_cqhci_ops = { 1240 .enable = dwcmshc_sdhci_cqe_enable, 1241 .disable = sdhci_cqe_disable, 1242 .dumpregs = dwcmshc_cqhci_dumpregs, 1243 .set_tran_desc = dwcmshc_set_tran_desc, 1244 }; 1245 1246 static void dwcmshc_cqhci_init(struct sdhci_host *host, struct platform_device *pdev) 1247 { 1248 struct cqhci_host *cq_host; 1249 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1250 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1251 bool dma64 = false; 1252 u16 clk; 1253 int err; 1254 1255 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1256 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1257 if (!cq_host) { 1258 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: not enough memory\n"); 1259 goto dsbl_cqe_caps; 1260 } 1261 1262 /* 1263 * For dwcmshc host controller we have to enable internal clock 1264 * before access to some registers from Vendor Specific Area 2. 1265 */ 1266 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1267 clk |= SDHCI_CLOCK_INT_EN; 1268 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1269 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1270 if (!(clk & SDHCI_CLOCK_INT_EN)) { 1271 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: internal clock enable error\n"); 1272 goto free_cq_host; 1273 } 1274 1275 cq_host->mmio = host->ioaddr + priv->vendor_specific_area2; 1276 cq_host->ops = &dwcmshc_cqhci_ops; 1277 1278 /* Enable using of 128-bit task descriptors */ 1279 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 1280 if (dma64) { 1281 dev_dbg(mmc_dev(host->mmc), "128-bit task descriptors\n"); 1282 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 1283 } 1284 err = cqhci_init(cq_host, host->mmc, dma64); 1285 if (err) { 1286 dev_err(mmc_dev(host->mmc), "Unable to setup CQE: error %d\n", err); 1287 goto int_clock_disable; 1288 } 1289 1290 dev_dbg(mmc_dev(host->mmc), "CQE init done\n"); 1291 1292 return; 1293 1294 int_clock_disable: 1295 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1296 clk &= ~SDHCI_CLOCK_INT_EN; 1297 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 1298 1299 free_cq_host: 1300 devm_kfree(&pdev->dev, cq_host); 1301 1302 dsbl_cqe_caps: 1303 host->mmc->caps2 &= ~(MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD); 1304 } 1305 1306 static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { 1307 { 1308 .compatible = "rockchip,rk3588-dwcmshc", 1309 .data = &sdhci_dwcmshc_rk35xx_pdata, 1310 }, 1311 { 1312 .compatible = "rockchip,rk3568-dwcmshc", 1313 .data = &sdhci_dwcmshc_rk35xx_pdata, 1314 }, 1315 { 1316 .compatible = "snps,dwcmshc-sdhci", 1317 .data = &sdhci_dwcmshc_pdata, 1318 }, 1319 { 1320 .compatible = "sophgo,cv1800b-dwcmshc", 1321 .data = &sdhci_dwcmshc_cv18xx_pdata, 1322 }, 1323 { 1324 .compatible = "sophgo,sg2002-dwcmshc", 1325 .data = &sdhci_dwcmshc_cv18xx_pdata, 1326 }, 1327 { 1328 .compatible = "thead,th1520-dwcmshc", 1329 .data = &sdhci_dwcmshc_th1520_pdata, 1330 }, 1331 { 1332 .compatible = "sophgo,sg2042-dwcmshc", 1333 .data = &sdhci_dwcmshc_sg2042_pdata, 1334 }, 1335 {}, 1336 }; 1337 MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); 1338 1339 #ifdef CONFIG_ACPI 1340 static const struct acpi_device_id sdhci_dwcmshc_acpi_ids[] = { 1341 { 1342 .id = "MLNXBF30", 1343 .driver_data = (kernel_ulong_t)&sdhci_dwcmshc_bf3_pdata, 1344 }, 1345 {} 1346 }; 1347 MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids); 1348 #endif 1349 1350 static int dwcmshc_probe(struct platform_device *pdev) 1351 { 1352 struct device *dev = &pdev->dev; 1353 struct sdhci_pltfm_host *pltfm_host; 1354 struct sdhci_host *host; 1355 struct dwcmshc_priv *priv; 1356 const struct dwcmshc_pltfm_data *pltfm_data; 1357 int err; 1358 u32 extra, caps; 1359 1360 pltfm_data = device_get_match_data(&pdev->dev); 1361 if (!pltfm_data) { 1362 dev_err(&pdev->dev, "Error: No device match data found\n"); 1363 return -ENODEV; 1364 } 1365 1366 host = sdhci_pltfm_init(pdev, &pltfm_data->pdata, 1367 sizeof(struct dwcmshc_priv)); 1368 if (IS_ERR(host)) 1369 return PTR_ERR(host); 1370 1371 /* 1372 * extra adma table cnt for cross 128M boundary handling. 1373 */ 1374 extra = DIV_ROUND_UP_ULL(dma_get_required_mask(dev), SZ_128M); 1375 if (extra > SDHCI_MAX_SEGS) 1376 extra = SDHCI_MAX_SEGS; 1377 host->adma_table_cnt += extra; 1378 1379 pltfm_host = sdhci_priv(host); 1380 priv = sdhci_pltfm_priv(pltfm_host); 1381 1382 if (dev->of_node) { 1383 pltfm_host->clk = devm_clk_get(dev, "core"); 1384 if (IS_ERR(pltfm_host->clk)) { 1385 err = PTR_ERR(pltfm_host->clk); 1386 dev_err(dev, "failed to get core clk: %d\n", err); 1387 goto free_pltfm; 1388 } 1389 err = clk_prepare_enable(pltfm_host->clk); 1390 if (err) 1391 goto free_pltfm; 1392 1393 priv->bus_clk = devm_clk_get(dev, "bus"); 1394 if (!IS_ERR(priv->bus_clk)) 1395 clk_prepare_enable(priv->bus_clk); 1396 } 1397 1398 err = mmc_of_parse(host->mmc); 1399 if (err) 1400 goto err_clk; 1401 1402 sdhci_get_of_property(pdev); 1403 1404 priv->vendor_specific_area1 = 1405 sdhci_readl(host, DWCMSHC_P_VENDOR_AREA1) & DWCMSHC_AREA1_MASK; 1406 1407 host->mmc_host_ops.request = dwcmshc_request; 1408 host->mmc_host_ops.hs400_enhanced_strobe = dwcmshc_hs400_enhanced_strobe; 1409 host->mmc_host_ops.execute_tuning = dwcmshc_execute_tuning; 1410 1411 if (pltfm_data->init) { 1412 err = pltfm_data->init(&pdev->dev, host, priv); 1413 if (err) 1414 goto err_clk; 1415 } 1416 1417 #ifdef CONFIG_ACPI 1418 if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) 1419 sdhci_enable_v4_mode(host); 1420 #endif 1421 1422 caps = sdhci_readl(host, SDHCI_CAPABILITIES); 1423 if (caps & SDHCI_CAN_64BIT_V4) 1424 sdhci_enable_v4_mode(host); 1425 1426 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; 1427 1428 pm_runtime_get_noresume(dev); 1429 pm_runtime_set_active(dev); 1430 pm_runtime_enable(dev); 1431 1432 err = sdhci_setup_host(host); 1433 if (err) 1434 goto err_rpm; 1435 1436 /* Setup Command Queue Engine if enabled */ 1437 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 1438 priv->vendor_specific_area2 = 1439 sdhci_readw(host, DWCMSHC_P_VENDOR_AREA2); 1440 1441 dwcmshc_cqhci_init(host, pdev); 1442 } 1443 1444 if (pltfm_data->postinit) 1445 pltfm_data->postinit(host, priv); 1446 1447 err = __sdhci_add_host(host); 1448 if (err) 1449 goto err_setup_host; 1450 1451 pm_runtime_put(dev); 1452 1453 return 0; 1454 1455 err_setup_host: 1456 sdhci_cleanup_host(host); 1457 err_rpm: 1458 pm_runtime_disable(dev); 1459 pm_runtime_put_noidle(dev); 1460 err_clk: 1461 clk_disable_unprepare(pltfm_host->clk); 1462 clk_disable_unprepare(priv->bus_clk); 1463 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1464 free_pltfm: 1465 sdhci_pltfm_free(pdev); 1466 return err; 1467 } 1468 1469 static void dwcmshc_disable_card_clk(struct sdhci_host *host) 1470 { 1471 u16 ctrl; 1472 1473 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1474 if (ctrl & SDHCI_CLOCK_CARD_EN) { 1475 ctrl &= ~SDHCI_CLOCK_CARD_EN; 1476 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1477 } 1478 } 1479 1480 static void dwcmshc_remove(struct platform_device *pdev) 1481 { 1482 struct sdhci_host *host = platform_get_drvdata(pdev); 1483 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1484 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1485 1486 pm_runtime_get_sync(&pdev->dev); 1487 pm_runtime_disable(&pdev->dev); 1488 pm_runtime_put_noidle(&pdev->dev); 1489 1490 sdhci_remove_host(host, 0); 1491 1492 dwcmshc_disable_card_clk(host); 1493 1494 clk_disable_unprepare(pltfm_host->clk); 1495 clk_disable_unprepare(priv->bus_clk); 1496 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1497 sdhci_pltfm_free(pdev); 1498 } 1499 1500 #ifdef CONFIG_PM_SLEEP 1501 static int dwcmshc_suspend(struct device *dev) 1502 { 1503 struct sdhci_host *host = dev_get_drvdata(dev); 1504 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1505 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1506 int ret; 1507 1508 pm_runtime_resume(dev); 1509 1510 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1511 ret = cqhci_suspend(host->mmc); 1512 if (ret) 1513 return ret; 1514 } 1515 1516 ret = sdhci_suspend_host(host); 1517 if (ret) 1518 return ret; 1519 1520 clk_disable_unprepare(pltfm_host->clk); 1521 if (!IS_ERR(priv->bus_clk)) 1522 clk_disable_unprepare(priv->bus_clk); 1523 1524 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1525 1526 return ret; 1527 } 1528 1529 static int dwcmshc_resume(struct device *dev) 1530 { 1531 struct sdhci_host *host = dev_get_drvdata(dev); 1532 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1533 struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); 1534 int ret; 1535 1536 ret = clk_prepare_enable(pltfm_host->clk); 1537 if (ret) 1538 return ret; 1539 1540 if (!IS_ERR(priv->bus_clk)) { 1541 ret = clk_prepare_enable(priv->bus_clk); 1542 if (ret) 1543 goto disable_clk; 1544 } 1545 1546 ret = clk_bulk_prepare_enable(priv->num_other_clks, priv->other_clks); 1547 if (ret) 1548 goto disable_bus_clk; 1549 1550 ret = sdhci_resume_host(host); 1551 if (ret) 1552 goto disable_other_clks; 1553 1554 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1555 ret = cqhci_resume(host->mmc); 1556 if (ret) 1557 goto disable_other_clks; 1558 } 1559 1560 return 0; 1561 1562 disable_other_clks: 1563 clk_bulk_disable_unprepare(priv->num_other_clks, priv->other_clks); 1564 disable_bus_clk: 1565 if (!IS_ERR(priv->bus_clk)) 1566 clk_disable_unprepare(priv->bus_clk); 1567 disable_clk: 1568 clk_disable_unprepare(pltfm_host->clk); 1569 return ret; 1570 } 1571 #endif 1572 1573 #ifdef CONFIG_PM 1574 1575 static void dwcmshc_enable_card_clk(struct sdhci_host *host) 1576 { 1577 u16 ctrl; 1578 1579 ctrl = sdhci_readw(host, SDHCI_CLOCK_CONTROL); 1580 if ((ctrl & SDHCI_CLOCK_INT_EN) && !(ctrl & SDHCI_CLOCK_CARD_EN)) { 1581 ctrl |= SDHCI_CLOCK_CARD_EN; 1582 sdhci_writew(host, ctrl, SDHCI_CLOCK_CONTROL); 1583 } 1584 } 1585 1586 static int dwcmshc_runtime_suspend(struct device *dev) 1587 { 1588 struct sdhci_host *host = dev_get_drvdata(dev); 1589 1590 dwcmshc_disable_card_clk(host); 1591 1592 return 0; 1593 } 1594 1595 static int dwcmshc_runtime_resume(struct device *dev) 1596 { 1597 struct sdhci_host *host = dev_get_drvdata(dev); 1598 1599 dwcmshc_enable_card_clk(host); 1600 1601 return 0; 1602 } 1603 1604 #endif 1605 1606 static const struct dev_pm_ops dwcmshc_pmops = { 1607 SET_SYSTEM_SLEEP_PM_OPS(dwcmshc_suspend, dwcmshc_resume) 1608 SET_RUNTIME_PM_OPS(dwcmshc_runtime_suspend, 1609 dwcmshc_runtime_resume, NULL) 1610 }; 1611 1612 static struct platform_driver sdhci_dwcmshc_driver = { 1613 .driver = { 1614 .name = "sdhci-dwcmshc", 1615 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1616 .of_match_table = sdhci_dwcmshc_dt_ids, 1617 .acpi_match_table = ACPI_PTR(sdhci_dwcmshc_acpi_ids), 1618 .pm = &dwcmshc_pmops, 1619 }, 1620 .probe = dwcmshc_probe, 1621 .remove_new = dwcmshc_remove, 1622 }; 1623 module_platform_driver(sdhci_dwcmshc_driver); 1624 1625 MODULE_DESCRIPTION("SDHCI platform driver for Synopsys DWC MSHC"); 1626 MODULE_AUTHOR("Jisheng Zhang <jszhang@kernel.org>"); 1627 MODULE_LICENSE("GPL v2"); 1628