1 /* 2 * Freescale eSDHC controller driver generics for OF and pltfm. 3 * 4 * Copyright (c) 2007 Freescale Semiconductor, Inc. 5 * Copyright (c) 2009 MontaVista Software, Inc. 6 * Copyright (c) 2010 Pengutronix e.K. 7 * Author: Wolfram Sang <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 */ 13 14 #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 15 #define _DRIVERS_MMC_SDHCI_ESDHC_H 16 17 /* 18 * Ops and quirks for the Freescale eSDHC controller. 19 */ 20 21 #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 22 SDHCI_QUIRK_NO_BUSY_IRQ | \ 23 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 24 SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 25 SDHCI_QUIRK_NO_HISPD_BIT) 26 27 #define ESDHC_PROCTL 0x28 28 29 #define ESDHC_SYSTEM_CONTROL 0x2c 30 #define ESDHC_CLOCK_MASK 0x0000fff0 31 #define ESDHC_PREDIV_SHIFT 8 32 #define ESDHC_DIVIDER_SHIFT 4 33 #define ESDHC_CLOCK_PEREN 0x00000004 34 #define ESDHC_CLOCK_HCKEN 0x00000002 35 #define ESDHC_CLOCK_IPGEN 0x00000001 36 37 /* pltfm-specific */ 38 #define ESDHC_HOST_CONTROL_LE 0x20 39 40 /* 41 * P2020 interpretation of the SDHCI_HOST_CONTROL register 42 */ 43 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 44 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 45 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 46 47 /* OF-specific */ 48 #define ESDHC_DMA_SYSCTL 0x40c 49 #define ESDHC_DMA_SNOOP 0x00000040 50 51 #define ESDHC_HOST_CONTROL_RES 0x01 52 53 #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 54