1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Freescale eSDHC controller driver generics for OF and pltfm. 4 * 5 * Copyright (c) 2007 Freescale Semiconductor, Inc. 6 * Copyright (c) 2009 MontaVista Software, Inc. 7 * Copyright (c) 2010 Pengutronix e.K. 8 * Author: Wolfram Sang <w.sang@pengutronix.de> 9 */ 10 11 #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 12 #define _DRIVERS_MMC_SDHCI_ESDHC_H 13 14 /* 15 * Ops and quirks for the Freescale eSDHC controller. 16 */ 17 18 #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 19 SDHCI_QUIRK_32BIT_DMA_ADDR | \ 20 SDHCI_QUIRK_NO_BUSY_IRQ | \ 21 SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 22 SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 23 SDHCI_QUIRK_NO_HISPD_BIT) 24 25 /* pltfm-specific */ 26 #define ESDHC_HOST_CONTROL_LE 0x20 27 28 /* 29 * eSDHC register definition 30 */ 31 32 /* Present State Register */ 33 #define ESDHC_PRSSTAT 0x24 34 #define ESDHC_CLOCK_STABLE 0x00000008 35 36 /* Protocol Control Register */ 37 #define ESDHC_PROCTL 0x28 38 #define ESDHC_VOLT_SEL 0x00000400 39 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 40 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 41 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 42 #define ESDHC_HOST_CONTROL_RES 0x01 43 44 /* System Control Register */ 45 #define ESDHC_SYSTEM_CONTROL 0x2c 46 #define ESDHC_CLOCK_MASK 0x0000fff0 47 #define ESDHC_PREDIV_SHIFT 8 48 #define ESDHC_DIVIDER_SHIFT 4 49 #define ESDHC_CLOCK_SDCLKEN 0x00000008 50 #define ESDHC_CLOCK_PEREN 0x00000004 51 #define ESDHC_CLOCK_HCKEN 0x00000002 52 #define ESDHC_CLOCK_IPGEN 0x00000001 53 54 /* System Control 2 Register */ 55 #define ESDHC_SYSTEM_CONTROL_2 0x3c 56 #define ESDHC_SMPCLKSEL 0x00800000 57 #define ESDHC_EXTN 0x00400000 58 59 /* Host Controller Capabilities Register 2 */ 60 #define ESDHC_CAPABILITIES_1 0x114 61 62 /* Tuning Block Control Register */ 63 #define ESDHC_TBCTL 0x120 64 #define ESDHC_HS400_WNDW_ADJUST 0x00000040 65 #define ESDHC_HS400_MODE 0x00000010 66 #define ESDHC_TB_EN 0x00000004 67 #define ESDHC_TB_MODE_MASK 0x00000003 68 #define ESDHC_TB_MODE_SW 0x00000003 69 #define ESDHC_TB_MODE_3 0x00000002 70 71 #define ESDHC_TBSTAT 0x124 72 73 #define ESDHC_TBPTR 0x128 74 #define ESDHC_WNDW_STRT_PTR_SHIFT 8 75 #define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8) 76 #define ESDHC_WNDW_END_PTR_MASK 0x7f 77 78 /* SD Clock Control Register */ 79 #define ESDHC_SDCLKCTL 0x144 80 #define ESDHC_LPBK_CLK_SEL 0x80000000 81 #define ESDHC_CMD_CLK_CTL 0x00008000 82 83 /* SD Timing Control Register */ 84 #define ESDHC_SDTIMNGCTL 0x148 85 #define ESDHC_FLW_CTL_BG 0x00008000 86 87 /* DLL Config 0 Register */ 88 #define ESDHC_DLLCFG0 0x160 89 #define ESDHC_DLL_ENABLE 0x80000000 90 #define ESDHC_DLL_FREQ_SEL 0x08000000 91 92 /* DLL Config 1 Register */ 93 #define ESDHC_DLLCFG1 0x164 94 #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000 95 96 /* DLL Status 0 Register */ 97 #define ESDHC_DLLSTAT0 0x170 98 #define ESDHC_DLL_STS_SLV_LOCK 0x08000000 99 100 /* Control Register for DMA transfer */ 101 #define ESDHC_DMA_SYSCTL 0x40c 102 #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 103 #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000 104 #define ESDHC_DMA_SNOOP 0x00000040 105 106 #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 107