180872e21SWolfram Sang /* 280872e21SWolfram Sang * Freescale eSDHC controller driver generics for OF and pltfm. 380872e21SWolfram Sang * 480872e21SWolfram Sang * Copyright (c) 2007 Freescale Semiconductor, Inc. 580872e21SWolfram Sang * Copyright (c) 2009 MontaVista Software, Inc. 680872e21SWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 780872e21SWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 880872e21SWolfram Sang * 980872e21SWolfram Sang * This program is free software; you can redistribute it and/or modify 1080872e21SWolfram Sang * it under the terms of the GNU General Public License as published by 1180872e21SWolfram Sang * the Free Software Foundation; either version 2 of the License. 1280872e21SWolfram Sang */ 1380872e21SWolfram Sang 1480872e21SWolfram Sang #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 1580872e21SWolfram Sang #define _DRIVERS_MMC_SDHCI_ESDHC_H 1680872e21SWolfram Sang 1780872e21SWolfram Sang /* 1880872e21SWolfram Sang * Ops and quirks for the Freescale eSDHC controller. 1980872e21SWolfram Sang */ 2080872e21SWolfram Sang 2180872e21SWolfram Sang #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 2280872e21SWolfram Sang SDHCI_QUIRK_NO_BUSY_IRQ | \ 2380872e21SWolfram Sang SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 2467b589a2SYangbo Lu SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 2567b589a2SYangbo Lu SDHCI_QUIRK_NO_HISPD_BIT) 2680872e21SWolfram Sang 27*a6b44888Syangbo lu /* pltfm-specific */ 28*a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_LE 0x20 29f4932cfdSyangbo lu 30*a6b44888Syangbo lu /* 31*a6b44888Syangbo lu * eSDHC register definition 32*a6b44888Syangbo lu */ 33*a6b44888Syangbo lu 34*a6b44888Syangbo lu /* Protocol Control Register */ 35*a6b44888Syangbo lu #define ESDHC_PROCTL 0x28 36*a6b44888Syangbo lu #define ESDHC_CTRL_4BITBUS (0x1 << 1) 37*a6b44888Syangbo lu #define ESDHC_CTRL_8BITBUS (0x2 << 1) 38*a6b44888Syangbo lu #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 39*a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_RES 0x01 40*a6b44888Syangbo lu 41*a6b44888Syangbo lu /* System Control Register */ 4280872e21SWolfram Sang #define ESDHC_SYSTEM_CONTROL 0x2c 4380872e21SWolfram Sang #define ESDHC_CLOCK_MASK 0x0000fff0 4480872e21SWolfram Sang #define ESDHC_PREDIV_SHIFT 8 4580872e21SWolfram Sang #define ESDHC_DIVIDER_SHIFT 4 4680872e21SWolfram Sang #define ESDHC_CLOCK_PEREN 0x00000004 4780872e21SWolfram Sang #define ESDHC_CLOCK_HCKEN 0x00000002 4880872e21SWolfram Sang #define ESDHC_CLOCK_IPGEN 0x00000001 4980872e21SWolfram Sang 50*a6b44888Syangbo lu /* Control Register for DMA transfer */ 5180872e21SWolfram Sang #define ESDHC_DMA_SYSCTL 0x40c 5280872e21SWolfram Sang #define ESDHC_DMA_SNOOP 0x00000040 5380872e21SWolfram Sang 5480872e21SWolfram Sang #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 55