1*84a14ae8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 280872e21SWolfram Sang /* 380872e21SWolfram Sang * Freescale eSDHC controller driver generics for OF and pltfm. 480872e21SWolfram Sang * 580872e21SWolfram Sang * Copyright (c) 2007 Freescale Semiconductor, Inc. 680872e21SWolfram Sang * Copyright (c) 2009 MontaVista Software, Inc. 780872e21SWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 880872e21SWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 980872e21SWolfram Sang */ 1080872e21SWolfram Sang 1180872e21SWolfram Sang #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 1280872e21SWolfram Sang #define _DRIVERS_MMC_SDHCI_ESDHC_H 1380872e21SWolfram Sang 1480872e21SWolfram Sang /* 1580872e21SWolfram Sang * Ops and quirks for the Freescale eSDHC controller. 1680872e21SWolfram Sang */ 1780872e21SWolfram Sang 1880872e21SWolfram Sang #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 19cbb45093SBenoît Thébaudeau SDHCI_QUIRK_32BIT_DMA_ADDR | \ 2080872e21SWolfram Sang SDHCI_QUIRK_NO_BUSY_IRQ | \ 2180872e21SWolfram Sang SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 2267b589a2SYangbo Lu SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 2367b589a2SYangbo Lu SDHCI_QUIRK_NO_HISPD_BIT) 2480872e21SWolfram Sang 25a6b44888Syangbo lu /* pltfm-specific */ 26a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_LE 0x20 27f4932cfdSyangbo lu 28a6b44888Syangbo lu /* 29a6b44888Syangbo lu * eSDHC register definition 30a6b44888Syangbo lu */ 31a6b44888Syangbo lu 32e87d2db2Syangbo lu /* Present State Register */ 33e87d2db2Syangbo lu #define ESDHC_PRSSTAT 0x24 34e87d2db2Syangbo lu #define ESDHC_CLOCK_STABLE 0x00000008 35e87d2db2Syangbo lu 36a6b44888Syangbo lu /* Protocol Control Register */ 37a6b44888Syangbo lu #define ESDHC_PROCTL 0x28 38ea35645aSyangbo lu #define ESDHC_VOLT_SEL 0x00000400 39a6b44888Syangbo lu #define ESDHC_CTRL_4BITBUS (0x1 << 1) 40a6b44888Syangbo lu #define ESDHC_CTRL_8BITBUS (0x2 << 1) 41a6b44888Syangbo lu #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 42a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_RES 0x01 43a6b44888Syangbo lu 44a6b44888Syangbo lu /* System Control Register */ 4580872e21SWolfram Sang #define ESDHC_SYSTEM_CONTROL 0x2c 4680872e21SWolfram Sang #define ESDHC_CLOCK_MASK 0x0000fff0 4780872e21SWolfram Sang #define ESDHC_PREDIV_SHIFT 8 4880872e21SWolfram Sang #define ESDHC_DIVIDER_SHIFT 4 49e87d2db2Syangbo lu #define ESDHC_CLOCK_SDCLKEN 0x00000008 5080872e21SWolfram Sang #define ESDHC_CLOCK_PEREN 0x00000004 5180872e21SWolfram Sang #define ESDHC_CLOCK_HCKEN 0x00000002 5280872e21SWolfram Sang #define ESDHC_CLOCK_IPGEN 0x00000001 5380872e21SWolfram Sang 542f3110ccSyangbo lu /* Host Controller Capabilities Register 2 */ 552f3110ccSyangbo lu #define ESDHC_CAPABILITIES_1 0x114 562f3110ccSyangbo lu 57ba49cbd0Syangbo lu /* Tuning Block Control Register */ 58ba49cbd0Syangbo lu #define ESDHC_TBCTL 0x120 5954e08d9aSYangbo Lu #define ESDHC_HS400_WNDW_ADJUST 0x00000040 6054e08d9aSYangbo Lu #define ESDHC_HS400_MODE 0x00000010 61ba49cbd0Syangbo lu #define ESDHC_TB_EN 0x00000004 62b1f378abSYinbo Zhu #define ESDHC_TBPTR 0x128 63ba49cbd0Syangbo lu 6454e08d9aSYangbo Lu /* SD Clock Control Register */ 6554e08d9aSYangbo Lu #define ESDHC_SDCLKCTL 0x144 6654e08d9aSYangbo Lu #define ESDHC_LPBK_CLK_SEL 0x80000000 6754e08d9aSYangbo Lu #define ESDHC_CMD_CLK_CTL 0x00008000 6854e08d9aSYangbo Lu 6954e08d9aSYangbo Lu /* SD Timing Control Register */ 7054e08d9aSYangbo Lu #define ESDHC_SDTIMNGCTL 0x148 7154e08d9aSYangbo Lu #define ESDHC_FLW_CTL_BG 0x00008000 7254e08d9aSYangbo Lu 7354e08d9aSYangbo Lu /* DLL Config 0 Register */ 7454e08d9aSYangbo Lu #define ESDHC_DLLCFG0 0x160 7554e08d9aSYangbo Lu #define ESDHC_DLL_ENABLE 0x80000000 7654e08d9aSYangbo Lu #define ESDHC_DLL_FREQ_SEL 0x08000000 7754e08d9aSYangbo Lu 7848e304ccSYangbo Lu /* DLL Config 1 Register */ 7948e304ccSYangbo Lu #define ESDHC_DLLCFG1 0x164 8048e304ccSYangbo Lu #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000 8148e304ccSYangbo Lu 8254e08d9aSYangbo Lu /* DLL Status 0 Register */ 8354e08d9aSYangbo Lu #define ESDHC_DLLSTAT0 0x170 8454e08d9aSYangbo Lu #define ESDHC_DLL_STS_SLV_LOCK 0x08000000 8554e08d9aSYangbo Lu 86a6b44888Syangbo lu /* Control Register for DMA transfer */ 8780872e21SWolfram Sang #define ESDHC_DMA_SYSCTL 0x40c 8819c3a0efSyangbo lu #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 89ba49cbd0Syangbo lu #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000 9080872e21SWolfram Sang #define ESDHC_DMA_SNOOP 0x00000040 9180872e21SWolfram Sang 9280872e21SWolfram Sang #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 93