180872e21SWolfram Sang /* 280872e21SWolfram Sang * Freescale eSDHC controller driver generics for OF and pltfm. 380872e21SWolfram Sang * 480872e21SWolfram Sang * Copyright (c) 2007 Freescale Semiconductor, Inc. 580872e21SWolfram Sang * Copyright (c) 2009 MontaVista Software, Inc. 680872e21SWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 780872e21SWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 880872e21SWolfram Sang * 980872e21SWolfram Sang * This program is free software; you can redistribute it and/or modify 1080872e21SWolfram Sang * it under the terms of the GNU General Public License as published by 1180872e21SWolfram Sang * the Free Software Foundation; either version 2 of the License. 1280872e21SWolfram Sang */ 1380872e21SWolfram Sang 1480872e21SWolfram Sang #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 1580872e21SWolfram Sang #define _DRIVERS_MMC_SDHCI_ESDHC_H 1680872e21SWolfram Sang 1780872e21SWolfram Sang /* 1880872e21SWolfram Sang * Ops and quirks for the Freescale eSDHC controller. 1980872e21SWolfram Sang */ 2080872e21SWolfram Sang 2180872e21SWolfram Sang #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 22cbb45093SBenoît Thébaudeau SDHCI_QUIRK_32BIT_DMA_ADDR | \ 2380872e21SWolfram Sang SDHCI_QUIRK_NO_BUSY_IRQ | \ 2480872e21SWolfram Sang SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 2567b589a2SYangbo Lu SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 2667b589a2SYangbo Lu SDHCI_QUIRK_NO_HISPD_BIT) 2780872e21SWolfram Sang 28a6b44888Syangbo lu /* pltfm-specific */ 29a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_LE 0x20 30f4932cfdSyangbo lu 31a6b44888Syangbo lu /* 32a6b44888Syangbo lu * eSDHC register definition 33a6b44888Syangbo lu */ 34a6b44888Syangbo lu 35e87d2db2Syangbo lu /* Present State Register */ 36e87d2db2Syangbo lu #define ESDHC_PRSSTAT 0x24 37e87d2db2Syangbo lu #define ESDHC_CLOCK_STABLE 0x00000008 38e87d2db2Syangbo lu 39a6b44888Syangbo lu /* Protocol Control Register */ 40a6b44888Syangbo lu #define ESDHC_PROCTL 0x28 41ea35645aSyangbo lu #define ESDHC_VOLT_SEL 0x00000400 42a6b44888Syangbo lu #define ESDHC_CTRL_4BITBUS (0x1 << 1) 43a6b44888Syangbo lu #define ESDHC_CTRL_8BITBUS (0x2 << 1) 44a6b44888Syangbo lu #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 45a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_RES 0x01 46a6b44888Syangbo lu 47a6b44888Syangbo lu /* System Control Register */ 4880872e21SWolfram Sang #define ESDHC_SYSTEM_CONTROL 0x2c 4980872e21SWolfram Sang #define ESDHC_CLOCK_MASK 0x0000fff0 5080872e21SWolfram Sang #define ESDHC_PREDIV_SHIFT 8 5180872e21SWolfram Sang #define ESDHC_DIVIDER_SHIFT 4 52e87d2db2Syangbo lu #define ESDHC_CLOCK_SDCLKEN 0x00000008 5380872e21SWolfram Sang #define ESDHC_CLOCK_PEREN 0x00000004 5480872e21SWolfram Sang #define ESDHC_CLOCK_HCKEN 0x00000002 5580872e21SWolfram Sang #define ESDHC_CLOCK_IPGEN 0x00000001 5680872e21SWolfram Sang 572f3110ccSyangbo lu /* Host Controller Capabilities Register 2 */ 582f3110ccSyangbo lu #define ESDHC_CAPABILITIES_1 0x114 592f3110ccSyangbo lu 60ba49cbd0Syangbo lu /* Tuning Block Control Register */ 61ba49cbd0Syangbo lu #define ESDHC_TBCTL 0x120 6254e08d9aSYangbo Lu #define ESDHC_HS400_WNDW_ADJUST 0x00000040 6354e08d9aSYangbo Lu #define ESDHC_HS400_MODE 0x00000010 64ba49cbd0Syangbo lu #define ESDHC_TB_EN 0x00000004 65b1f378abSYinbo Zhu #define ESDHC_TBPTR 0x128 66ba49cbd0Syangbo lu 6754e08d9aSYangbo Lu /* SD Clock Control Register */ 6854e08d9aSYangbo Lu #define ESDHC_SDCLKCTL 0x144 6954e08d9aSYangbo Lu #define ESDHC_LPBK_CLK_SEL 0x80000000 7054e08d9aSYangbo Lu #define ESDHC_CMD_CLK_CTL 0x00008000 7154e08d9aSYangbo Lu 7254e08d9aSYangbo Lu /* SD Timing Control Register */ 7354e08d9aSYangbo Lu #define ESDHC_SDTIMNGCTL 0x148 7454e08d9aSYangbo Lu #define ESDHC_FLW_CTL_BG 0x00008000 7554e08d9aSYangbo Lu 7654e08d9aSYangbo Lu /* DLL Config 0 Register */ 7754e08d9aSYangbo Lu #define ESDHC_DLLCFG0 0x160 7854e08d9aSYangbo Lu #define ESDHC_DLL_ENABLE 0x80000000 7954e08d9aSYangbo Lu #define ESDHC_DLL_FREQ_SEL 0x08000000 8054e08d9aSYangbo Lu 81*48e304ccSYangbo Lu /* DLL Config 1 Register */ 82*48e304ccSYangbo Lu #define ESDHC_DLLCFG1 0x164 83*48e304ccSYangbo Lu #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000 84*48e304ccSYangbo Lu 8554e08d9aSYangbo Lu /* DLL Status 0 Register */ 8654e08d9aSYangbo Lu #define ESDHC_DLLSTAT0 0x170 8754e08d9aSYangbo Lu #define ESDHC_DLL_STS_SLV_LOCK 0x08000000 8854e08d9aSYangbo Lu 89a6b44888Syangbo lu /* Control Register for DMA transfer */ 9080872e21SWolfram Sang #define ESDHC_DMA_SYSCTL 0x40c 9119c3a0efSyangbo lu #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 92ba49cbd0Syangbo lu #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000 9380872e21SWolfram Sang #define ESDHC_DMA_SNOOP 0x00000040 9480872e21SWolfram Sang 9580872e21SWolfram Sang #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 96