180872e21SWolfram Sang /* 280872e21SWolfram Sang * Freescale eSDHC controller driver generics for OF and pltfm. 380872e21SWolfram Sang * 480872e21SWolfram Sang * Copyright (c) 2007 Freescale Semiconductor, Inc. 580872e21SWolfram Sang * Copyright (c) 2009 MontaVista Software, Inc. 680872e21SWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 780872e21SWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 880872e21SWolfram Sang * 980872e21SWolfram Sang * This program is free software; you can redistribute it and/or modify 1080872e21SWolfram Sang * it under the terms of the GNU General Public License as published by 1180872e21SWolfram Sang * the Free Software Foundation; either version 2 of the License. 1280872e21SWolfram Sang */ 1380872e21SWolfram Sang 1480872e21SWolfram Sang #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 1580872e21SWolfram Sang #define _DRIVERS_MMC_SDHCI_ESDHC_H 1680872e21SWolfram Sang 1780872e21SWolfram Sang /* 1880872e21SWolfram Sang * Ops and quirks for the Freescale eSDHC controller. 1980872e21SWolfram Sang */ 2080872e21SWolfram Sang 2180872e21SWolfram Sang #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 2280872e21SWolfram Sang SDHCI_QUIRK_NO_BUSY_IRQ | \ 2380872e21SWolfram Sang SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 2467b589a2SYangbo Lu SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 2567b589a2SYangbo Lu SDHCI_QUIRK_NO_HISPD_BIT) 2680872e21SWolfram Sang 27a6b44888Syangbo lu /* pltfm-specific */ 28a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_LE 0x20 29f4932cfdSyangbo lu 30a6b44888Syangbo lu /* 31a6b44888Syangbo lu * eSDHC register definition 32a6b44888Syangbo lu */ 33a6b44888Syangbo lu 34e87d2db2Syangbo lu /* Present State Register */ 35e87d2db2Syangbo lu #define ESDHC_PRSSTAT 0x24 36e87d2db2Syangbo lu #define ESDHC_CLOCK_STABLE 0x00000008 37e87d2db2Syangbo lu 38a6b44888Syangbo lu /* Protocol Control Register */ 39a6b44888Syangbo lu #define ESDHC_PROCTL 0x28 40a6b44888Syangbo lu #define ESDHC_CTRL_4BITBUS (0x1 << 1) 41a6b44888Syangbo lu #define ESDHC_CTRL_8BITBUS (0x2 << 1) 42a6b44888Syangbo lu #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 43a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_RES 0x01 44a6b44888Syangbo lu 45a6b44888Syangbo lu /* System Control Register */ 4680872e21SWolfram Sang #define ESDHC_SYSTEM_CONTROL 0x2c 4780872e21SWolfram Sang #define ESDHC_CLOCK_MASK 0x0000fff0 4880872e21SWolfram Sang #define ESDHC_PREDIV_SHIFT 8 4980872e21SWolfram Sang #define ESDHC_DIVIDER_SHIFT 4 50e87d2db2Syangbo lu #define ESDHC_CLOCK_SDCLKEN 0x00000008 5180872e21SWolfram Sang #define ESDHC_CLOCK_PEREN 0x00000004 5280872e21SWolfram Sang #define ESDHC_CLOCK_HCKEN 0x00000002 5380872e21SWolfram Sang #define ESDHC_CLOCK_IPGEN 0x00000001 5480872e21SWolfram Sang 55a6b44888Syangbo lu /* Control Register for DMA transfer */ 5680872e21SWolfram Sang #define ESDHC_DMA_SYSCTL 0x40c 57*19c3a0efSyangbo lu #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 5880872e21SWolfram Sang #define ESDHC_DMA_SNOOP 0x00000040 5980872e21SWolfram Sang 6080872e21SWolfram Sang #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 61