184a14ae8SThomas Gleixner /* SPDX-License-Identifier: GPL-2.0-only */ 280872e21SWolfram Sang /* 380872e21SWolfram Sang * Freescale eSDHC controller driver generics for OF and pltfm. 480872e21SWolfram Sang * 580872e21SWolfram Sang * Copyright (c) 2007 Freescale Semiconductor, Inc. 680872e21SWolfram Sang * Copyright (c) 2009 MontaVista Software, Inc. 780872e21SWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 8*011fde48SYangbo Lu * Copyright 2020 NXP 930e1028dSWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 1080872e21SWolfram Sang */ 1180872e21SWolfram Sang 1280872e21SWolfram Sang #ifndef _DRIVERS_MMC_SDHCI_ESDHC_H 1380872e21SWolfram Sang #define _DRIVERS_MMC_SDHCI_ESDHC_H 1480872e21SWolfram Sang 1580872e21SWolfram Sang /* 1680872e21SWolfram Sang * Ops and quirks for the Freescale eSDHC controller. 1780872e21SWolfram Sang */ 1880872e21SWolfram Sang 1980872e21SWolfram Sang #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \ 20cbb45093SBenoît Thébaudeau SDHCI_QUIRK_32BIT_DMA_ADDR | \ 2180872e21SWolfram Sang SDHCI_QUIRK_NO_BUSY_IRQ | \ 2280872e21SWolfram Sang SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \ 2367b589a2SYangbo Lu SDHCI_QUIRK_PIO_NEEDS_DELAY | \ 2467b589a2SYangbo Lu SDHCI_QUIRK_NO_HISPD_BIT) 2580872e21SWolfram Sang 26a6b44888Syangbo lu /* pltfm-specific */ 27a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_LE 0x20 28f4932cfdSyangbo lu 29a6b44888Syangbo lu /* 30a6b44888Syangbo lu * eSDHC register definition 31a6b44888Syangbo lu */ 32a6b44888Syangbo lu 33e87d2db2Syangbo lu /* Present State Register */ 34e87d2db2Syangbo lu #define ESDHC_PRSSTAT 0x24 35f581e909SHaibo Chen #define ESDHC_CLOCK_GATE_OFF 0x00000080 36e87d2db2Syangbo lu #define ESDHC_CLOCK_STABLE 0x00000008 37e87d2db2Syangbo lu 38a6b44888Syangbo lu /* Protocol Control Register */ 39a6b44888Syangbo lu #define ESDHC_PROCTL 0x28 40ea35645aSyangbo lu #define ESDHC_VOLT_SEL 0x00000400 41a6b44888Syangbo lu #define ESDHC_CTRL_4BITBUS (0x1 << 1) 42a6b44888Syangbo lu #define ESDHC_CTRL_8BITBUS (0x2 << 1) 43a6b44888Syangbo lu #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 44a6b44888Syangbo lu #define ESDHC_HOST_CONTROL_RES 0x01 45a6b44888Syangbo lu 46a6b44888Syangbo lu /* System Control Register */ 4780872e21SWolfram Sang #define ESDHC_SYSTEM_CONTROL 0x2c 4880872e21SWolfram Sang #define ESDHC_CLOCK_MASK 0x0000fff0 4980872e21SWolfram Sang #define ESDHC_PREDIV_SHIFT 8 5080872e21SWolfram Sang #define ESDHC_DIVIDER_SHIFT 4 51e87d2db2Syangbo lu #define ESDHC_CLOCK_SDCLKEN 0x00000008 5280872e21SWolfram Sang #define ESDHC_CLOCK_PEREN 0x00000004 5380872e21SWolfram Sang #define ESDHC_CLOCK_HCKEN 0x00000002 5480872e21SWolfram Sang #define ESDHC_CLOCK_IPGEN 0x00000001 5580872e21SWolfram Sang 5622dc132dSYangbo Lu /* System Control 2 Register */ 5722dc132dSYangbo Lu #define ESDHC_SYSTEM_CONTROL_2 0x3c 5822dc132dSYangbo Lu #define ESDHC_SMPCLKSEL 0x00800000 5922dc132dSYangbo Lu #define ESDHC_EXTN 0x00400000 6022dc132dSYangbo Lu 612f3110ccSyangbo lu /* Host Controller Capabilities Register 2 */ 622f3110ccSyangbo lu #define ESDHC_CAPABILITIES_1 0x114 632f3110ccSyangbo lu 64ba49cbd0Syangbo lu /* Tuning Block Control Register */ 65ba49cbd0Syangbo lu #define ESDHC_TBCTL 0x120 6654e08d9aSYangbo Lu #define ESDHC_HS400_WNDW_ADJUST 0x00000040 6754e08d9aSYangbo Lu #define ESDHC_HS400_MODE 0x00000010 68ba49cbd0Syangbo lu #define ESDHC_TB_EN 0x00000004 6922dc132dSYangbo Lu #define ESDHC_TB_MODE_MASK 0x00000003 7022dc132dSYangbo Lu #define ESDHC_TB_MODE_SW 0x00000003 7122dc132dSYangbo Lu #define ESDHC_TB_MODE_3 0x00000002 7222dc132dSYangbo Lu 7322dc132dSYangbo Lu #define ESDHC_TBSTAT 0x124 7422dc132dSYangbo Lu 75b1f378abSYinbo Zhu #define ESDHC_TBPTR 0x128 7622dc132dSYangbo Lu #define ESDHC_WNDW_STRT_PTR_SHIFT 8 7722dc132dSYangbo Lu #define ESDHC_WNDW_STRT_PTR_MASK (0x7f << 8) 7822dc132dSYangbo Lu #define ESDHC_WNDW_END_PTR_MASK 0x7f 79ba49cbd0Syangbo lu 8054e08d9aSYangbo Lu /* SD Clock Control Register */ 8154e08d9aSYangbo Lu #define ESDHC_SDCLKCTL 0x144 8254e08d9aSYangbo Lu #define ESDHC_LPBK_CLK_SEL 0x80000000 8354e08d9aSYangbo Lu #define ESDHC_CMD_CLK_CTL 0x00008000 8454e08d9aSYangbo Lu 8554e08d9aSYangbo Lu /* SD Timing Control Register */ 8654e08d9aSYangbo Lu #define ESDHC_SDTIMNGCTL 0x148 8754e08d9aSYangbo Lu #define ESDHC_FLW_CTL_BG 0x00008000 8854e08d9aSYangbo Lu 8954e08d9aSYangbo Lu /* DLL Config 0 Register */ 9054e08d9aSYangbo Lu #define ESDHC_DLLCFG0 0x160 9154e08d9aSYangbo Lu #define ESDHC_DLL_ENABLE 0x80000000 92*011fde48SYangbo Lu #define ESDHC_DLL_RESET 0x40000000 9354e08d9aSYangbo Lu #define ESDHC_DLL_FREQ_SEL 0x08000000 9454e08d9aSYangbo Lu 9548e304ccSYangbo Lu /* DLL Config 1 Register */ 9648e304ccSYangbo Lu #define ESDHC_DLLCFG1 0x164 9748e304ccSYangbo Lu #define ESDHC_DLL_PD_PULSE_STRETCH_SEL 0x80000000 9848e304ccSYangbo Lu 9954e08d9aSYangbo Lu /* DLL Status 0 Register */ 10054e08d9aSYangbo Lu #define ESDHC_DLLSTAT0 0x170 10154e08d9aSYangbo Lu #define ESDHC_DLL_STS_SLV_LOCK 0x08000000 10254e08d9aSYangbo Lu 103a6b44888Syangbo lu /* Control Register for DMA transfer */ 10480872e21SWolfram Sang #define ESDHC_DMA_SYSCTL 0x40c 10519c3a0efSyangbo lu #define ESDHC_PERIPHERAL_CLK_SEL 0x00080000 106ba49cbd0Syangbo lu #define ESDHC_FLUSH_ASYNC_FIFO 0x00040000 10780872e21SWolfram Sang #define ESDHC_DMA_SNOOP 0x00000040 10880872e21SWolfram Sang 10980872e21SWolfram Sang #endif /* _DRIVERS_MMC_SDHCI_ESDHC_H */ 110