1 /* 2 * Freescale eSDHC i.MX controller driver for the platform bus. 3 * 4 * derived from the OF-version. 5 * 6 * Copyright (c) 2010 Pengutronix e.K. 7 * Author: Wolfram Sang <w.sang@pengutronix.de> 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License. 12 */ 13 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/err.h> 17 #include <linux/clk.h> 18 #include <linux/gpio.h> 19 #include <linux/module.h> 20 #include <linux/slab.h> 21 #include <linux/mmc/host.h> 22 #include <linux/mmc/mmc.h> 23 #include <linux/mmc/sdio.h> 24 #include <linux/mmc/slot-gpio.h> 25 #include <linux/of.h> 26 #include <linux/of_device.h> 27 #include <linux/of_gpio.h> 28 #include <linux/pinctrl/consumer.h> 29 #include <linux/platform_data/mmc-esdhc-imx.h> 30 #include "sdhci-pltfm.h" 31 #include "sdhci-esdhc.h" 32 33 #define ESDHC_CTRL_D3CD 0x08 34 /* VENDOR SPEC register */ 35 #define ESDHC_VENDOR_SPEC 0xc0 36 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 37 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 38 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 39 #define ESDHC_WTMK_LVL 0x44 40 #define ESDHC_MIX_CTRL 0x48 41 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 42 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 43 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 44 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 45 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 46 /* Bits 3 and 6 are not SDHCI standard definitions */ 47 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 48 49 /* dll control register */ 50 #define ESDHC_DLL_CTRL 0x60 51 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 52 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 53 54 /* tune control register */ 55 #define ESDHC_TUNE_CTRL_STATUS 0x68 56 #define ESDHC_TUNE_CTRL_STEP 1 57 #define ESDHC_TUNE_CTRL_MIN 0 58 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 59 60 #define ESDHC_TUNING_CTRL 0xcc 61 #define ESDHC_STD_TUNING_EN (1 << 24) 62 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 63 #define ESDHC_TUNING_START_TAP 0x1 64 65 #define ESDHC_TUNING_BLOCK_PATTERN_LEN 64 66 67 /* pinctrl state */ 68 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 69 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 70 71 /* 72 * Our interpretation of the SDHCI_HOST_CONTROL register 73 */ 74 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 75 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 76 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 77 78 /* 79 * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 80 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 81 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 82 * Define this macro DMA error INT for fsl eSDHC 83 */ 84 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 85 86 /* 87 * The CMDTYPE of the CMD register (offset 0xE) should be set to 88 * "11" when the STOP CMD12 is issued on imx53 to abort one 89 * open ended multi-blk IO. Otherwise the TC INT wouldn't 90 * be generated. 91 * In exact block transfer, the controller doesn't complete the 92 * operations automatically as required at the end of the 93 * transfer and remains on hold if the abort command is not sent. 94 * As a result, the TC flag is not asserted and SW received timeout 95 * exeception. Bit1 of Vendor Spec registor is used to fix it. 96 */ 97 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 98 /* 99 * The flag enables the workaround for ESDHC errata ENGcm07207 which 100 * affects i.MX25 and i.MX35. 101 */ 102 #define ESDHC_FLAG_ENGCM07207 BIT(2) 103 /* 104 * The flag tells that the ESDHC controller is an USDHC block that is 105 * integrated on the i.MX6 series. 106 */ 107 #define ESDHC_FLAG_USDHC BIT(3) 108 /* The IP supports manual tuning process */ 109 #define ESDHC_FLAG_MAN_TUNING BIT(4) 110 /* The IP supports standard tuning process */ 111 #define ESDHC_FLAG_STD_TUNING BIT(5) 112 /* The IP has SDHCI_CAPABILITIES_1 register */ 113 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 114 115 struct esdhc_soc_data { 116 u32 flags; 117 }; 118 119 static struct esdhc_soc_data esdhc_imx25_data = { 120 .flags = ESDHC_FLAG_ENGCM07207, 121 }; 122 123 static struct esdhc_soc_data esdhc_imx35_data = { 124 .flags = ESDHC_FLAG_ENGCM07207, 125 }; 126 127 static struct esdhc_soc_data esdhc_imx51_data = { 128 .flags = 0, 129 }; 130 131 static struct esdhc_soc_data esdhc_imx53_data = { 132 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 133 }; 134 135 static struct esdhc_soc_data usdhc_imx6q_data = { 136 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING, 137 }; 138 139 static struct esdhc_soc_data usdhc_imx6sl_data = { 140 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 141 | ESDHC_FLAG_HAVE_CAP1, 142 }; 143 144 struct pltfm_imx_data { 145 u32 scratchpad; 146 struct pinctrl *pinctrl; 147 struct pinctrl_state *pins_default; 148 struct pinctrl_state *pins_100mhz; 149 struct pinctrl_state *pins_200mhz; 150 const struct esdhc_soc_data *socdata; 151 struct esdhc_platform_data boarddata; 152 struct clk *clk_ipg; 153 struct clk *clk_ahb; 154 struct clk *clk_per; 155 enum { 156 NO_CMD_PENDING, /* no multiblock command pending*/ 157 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 158 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 159 } multiblock_status; 160 u32 uhs_mode; 161 u32 is_ddr; 162 }; 163 164 static struct platform_device_id imx_esdhc_devtype[] = { 165 { 166 .name = "sdhci-esdhc-imx25", 167 .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 168 }, { 169 .name = "sdhci-esdhc-imx35", 170 .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 171 }, { 172 .name = "sdhci-esdhc-imx51", 173 .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 174 }, { 175 /* sentinel */ 176 } 177 }; 178 MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 179 180 static const struct of_device_id imx_esdhc_dt_ids[] = { 181 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 182 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 183 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 184 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 185 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 186 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 187 { /* sentinel */ } 188 }; 189 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 190 191 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 192 { 193 return data->socdata == &esdhc_imx25_data; 194 } 195 196 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 197 { 198 return data->socdata == &esdhc_imx53_data; 199 } 200 201 static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 202 { 203 return data->socdata == &usdhc_imx6q_data; 204 } 205 206 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 207 { 208 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 209 } 210 211 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 212 { 213 void __iomem *base = host->ioaddr + (reg & ~0x3); 214 u32 shift = (reg & 0x3) * 8; 215 216 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 217 } 218 219 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 220 { 221 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 222 struct pltfm_imx_data *imx_data = pltfm_host->priv; 223 u32 val = readl(host->ioaddr + reg); 224 225 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 226 u32 fsl_prss = val; 227 /* save the least 20 bits */ 228 val = fsl_prss & 0x000FFFFF; 229 /* move dat[0-3] bits */ 230 val |= (fsl_prss & 0x0F000000) >> 4; 231 /* move cmd line bit */ 232 val |= (fsl_prss & 0x00800000) << 1; 233 } 234 235 if (unlikely(reg == SDHCI_CAPABILITIES)) { 236 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 237 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 238 val &= 0xffff0000; 239 240 /* In FSL esdhc IC module, only bit20 is used to indicate the 241 * ADMA2 capability of esdhc, but this bit is messed up on 242 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 243 * don't actually support ADMA2). So set the BROKEN_ADMA 244 * uirk on MX25/35 platforms. 245 */ 246 247 if (val & SDHCI_CAN_DO_ADMA1) { 248 val &= ~SDHCI_CAN_DO_ADMA1; 249 val |= SDHCI_CAN_DO_ADMA2; 250 } 251 } 252 253 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 254 if (esdhc_is_usdhc(imx_data)) { 255 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 256 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 257 else 258 /* imx6q/dl does not have cap_1 register, fake one */ 259 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 260 | SDHCI_SUPPORT_SDR50 261 | SDHCI_USE_SDR50_TUNING; 262 } 263 } 264 265 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 266 val = 0; 267 val |= 0xFF << SDHCI_MAX_CURRENT_330_SHIFT; 268 val |= 0xFF << SDHCI_MAX_CURRENT_300_SHIFT; 269 val |= 0xFF << SDHCI_MAX_CURRENT_180_SHIFT; 270 } 271 272 if (unlikely(reg == SDHCI_INT_STATUS)) { 273 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 274 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 275 val |= SDHCI_INT_ADMA_ERROR; 276 } 277 278 /* 279 * mask off the interrupt we get in response to the manually 280 * sent CMD12 281 */ 282 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 283 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 284 val &= ~SDHCI_INT_RESPONSE; 285 writel(SDHCI_INT_RESPONSE, host->ioaddr + 286 SDHCI_INT_STATUS); 287 imx_data->multiblock_status = NO_CMD_PENDING; 288 } 289 } 290 291 return val; 292 } 293 294 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 295 { 296 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 297 struct pltfm_imx_data *imx_data = pltfm_host->priv; 298 u32 data; 299 300 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 301 if (val & SDHCI_INT_CARD_INT) { 302 /* 303 * Clear and then set D3CD bit to avoid missing the 304 * card interrupt. This is a eSDHC controller problem 305 * so we need to apply the following workaround: clear 306 * and set D3CD bit will make eSDHC re-sample the card 307 * interrupt. In case a card interrupt was lost, 308 * re-sample it by the following steps. 309 */ 310 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 311 data &= ~ESDHC_CTRL_D3CD; 312 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 313 data |= ESDHC_CTRL_D3CD; 314 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 315 } 316 } 317 318 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 319 && (reg == SDHCI_INT_STATUS) 320 && (val & SDHCI_INT_DATA_END))) { 321 u32 v; 322 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 323 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 324 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 325 326 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 327 { 328 /* send a manual CMD12 with RESPTYP=none */ 329 data = MMC_STOP_TRANSMISSION << 24 | 330 SDHCI_CMD_ABORTCMD << 16; 331 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 332 imx_data->multiblock_status = WAIT_FOR_INT; 333 } 334 } 335 336 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 337 if (val & SDHCI_INT_ADMA_ERROR) { 338 val &= ~SDHCI_INT_ADMA_ERROR; 339 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 340 } 341 } 342 343 writel(val, host->ioaddr + reg); 344 } 345 346 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 347 { 348 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 349 struct pltfm_imx_data *imx_data = pltfm_host->priv; 350 u16 ret = 0; 351 u32 val; 352 353 if (unlikely(reg == SDHCI_HOST_VERSION)) { 354 reg ^= 2; 355 if (esdhc_is_usdhc(imx_data)) { 356 /* 357 * The usdhc register returns a wrong host version. 358 * Correct it here. 359 */ 360 return SDHCI_SPEC_300; 361 } 362 } 363 364 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 365 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 366 if (val & ESDHC_VENDOR_SPEC_VSELECT) 367 ret |= SDHCI_CTRL_VDD_180; 368 369 if (esdhc_is_usdhc(imx_data)) { 370 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 371 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 372 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 373 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 374 val = readl(host->ioaddr + SDHCI_ACMD12_ERR); 375 } 376 377 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 378 ret |= SDHCI_CTRL_EXEC_TUNING; 379 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 380 ret |= SDHCI_CTRL_TUNED_CLK; 381 382 ret |= (imx_data->uhs_mode & SDHCI_CTRL_UHS_MASK); 383 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 384 385 return ret; 386 } 387 388 return readw(host->ioaddr + reg); 389 } 390 391 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 392 { 393 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 394 struct pltfm_imx_data *imx_data = pltfm_host->priv; 395 u32 new_val = 0; 396 397 switch (reg) { 398 case SDHCI_CLOCK_CONTROL: 399 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 400 if (val & SDHCI_CLOCK_CARD_EN) 401 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 402 else 403 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 404 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 405 return; 406 case SDHCI_HOST_CONTROL2: 407 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 408 if (val & SDHCI_CTRL_VDD_180) 409 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 410 else 411 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 412 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 413 imx_data->uhs_mode = val & SDHCI_CTRL_UHS_MASK; 414 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 415 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 416 if (val & SDHCI_CTRL_TUNED_CLK) 417 new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 418 else 419 new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 420 writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 421 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 422 u32 v = readl(host->ioaddr + SDHCI_ACMD12_ERR); 423 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 424 new_val = readl(host->ioaddr + ESDHC_TUNING_CTRL); 425 if (val & SDHCI_CTRL_EXEC_TUNING) { 426 new_val |= ESDHC_STD_TUNING_EN | 427 ESDHC_TUNING_START_TAP; 428 v |= ESDHC_MIX_CTRL_EXE_TUNE; 429 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 430 } else { 431 new_val &= ~ESDHC_STD_TUNING_EN; 432 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 433 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 434 } 435 436 if (val & SDHCI_CTRL_TUNED_CLK) 437 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 438 else 439 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 440 441 writel(new_val, host->ioaddr + ESDHC_TUNING_CTRL); 442 writel(v, host->ioaddr + SDHCI_ACMD12_ERR); 443 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 444 } 445 return; 446 case SDHCI_TRANSFER_MODE: 447 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 448 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 449 && (host->cmd->data->blocks > 1) 450 && (host->cmd->data->flags & MMC_DATA_READ)) { 451 u32 v; 452 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 453 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 454 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 455 } 456 457 if (esdhc_is_usdhc(imx_data)) { 458 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 459 /* Swap AC23 bit */ 460 if (val & SDHCI_TRNS_AUTO_CMD23) { 461 val &= ~SDHCI_TRNS_AUTO_CMD23; 462 val |= ESDHC_MIX_CTRL_AC23EN; 463 } 464 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 465 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 466 } else { 467 /* 468 * Postpone this write, we must do it together with a 469 * command write that is down below. 470 */ 471 imx_data->scratchpad = val; 472 } 473 return; 474 case SDHCI_COMMAND: 475 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 476 val |= SDHCI_CMD_ABORTCMD; 477 478 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 479 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 480 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 481 482 if (esdhc_is_usdhc(imx_data)) 483 writel(val << 16, 484 host->ioaddr + SDHCI_TRANSFER_MODE); 485 else 486 writel(val << 16 | imx_data->scratchpad, 487 host->ioaddr + SDHCI_TRANSFER_MODE); 488 return; 489 case SDHCI_BLOCK_SIZE: 490 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 491 break; 492 } 493 esdhc_clrset_le(host, 0xffff, val, reg); 494 } 495 496 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 497 { 498 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 499 struct pltfm_imx_data *imx_data = pltfm_host->priv; 500 u32 new_val; 501 u32 mask; 502 503 switch (reg) { 504 case SDHCI_POWER_CONTROL: 505 /* 506 * FSL put some DMA bits here 507 * If your board has a regulator, code should be here 508 */ 509 return; 510 case SDHCI_HOST_CONTROL: 511 /* FSL messed up here, so we need to manually compose it. */ 512 new_val = val & SDHCI_CTRL_LED; 513 /* ensure the endianness */ 514 new_val |= ESDHC_HOST_CONTROL_LE; 515 /* bits 8&9 are reserved on mx25 */ 516 if (!is_imx25_esdhc(imx_data)) { 517 /* DMA mode bits are shifted */ 518 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 519 } 520 521 /* 522 * Do not touch buswidth bits here. This is done in 523 * esdhc_pltfm_bus_width. 524 * Do not touch the D3CD bit either which is used for the 525 * SDIO interrupt errata workaround. 526 */ 527 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 528 529 esdhc_clrset_le(host, mask, new_val, reg); 530 return; 531 } 532 esdhc_clrset_le(host, 0xff, val, reg); 533 534 /* 535 * The esdhc has a design violation to SDHC spec which tells 536 * that software reset should not affect card detection circuit. 537 * But esdhc clears its SYSCTL register bits [0..2] during the 538 * software reset. This will stop those clocks that card detection 539 * circuit relies on. To work around it, we turn the clocks on back 540 * to keep card detection circuit functional. 541 */ 542 if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) { 543 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 544 /* 545 * The reset on usdhc fails to clear MIX_CTRL register. 546 * Do it manually here. 547 */ 548 if (esdhc_is_usdhc(imx_data)) { 549 writel(0, host->ioaddr + ESDHC_MIX_CTRL); 550 imx_data->is_ddr = 0; 551 } 552 } 553 } 554 555 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 556 { 557 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 558 struct pltfm_imx_data *imx_data = pltfm_host->priv; 559 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 560 561 u32 f_host = clk_get_rate(pltfm_host->clk); 562 563 if (boarddata->f_max && (boarddata->f_max < f_host)) 564 return boarddata->f_max; 565 else 566 return f_host; 567 } 568 569 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 570 { 571 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 572 573 return clk_get_rate(pltfm_host->clk) / 256 / 16; 574 } 575 576 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 577 unsigned int clock) 578 { 579 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 580 struct pltfm_imx_data *imx_data = pltfm_host->priv; 581 unsigned int host_clock = clk_get_rate(pltfm_host->clk); 582 int pre_div = 2; 583 int div = 1; 584 u32 temp, val; 585 586 if (clock == 0) { 587 if (esdhc_is_usdhc(imx_data)) { 588 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 589 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 590 host->ioaddr + ESDHC_VENDOR_SPEC); 591 } 592 goto out; 593 } 594 595 if (esdhc_is_usdhc(imx_data) && !imx_data->is_ddr) 596 pre_div = 1; 597 598 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 599 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 600 | ESDHC_CLOCK_MASK); 601 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 602 603 while (host_clock / pre_div / 16 > clock && pre_div < 256) 604 pre_div *= 2; 605 606 while (host_clock / pre_div / div > clock && div < 16) 607 div++; 608 609 host->mmc->actual_clock = host_clock / pre_div / div; 610 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 611 clock, host->mmc->actual_clock); 612 613 if (imx_data->is_ddr) 614 pre_div >>= 2; 615 else 616 pre_div >>= 1; 617 div--; 618 619 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 620 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 621 | (div << ESDHC_DIVIDER_SHIFT) 622 | (pre_div << ESDHC_PREDIV_SHIFT)); 623 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 624 625 if (esdhc_is_usdhc(imx_data)) { 626 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 627 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 628 host->ioaddr + ESDHC_VENDOR_SPEC); 629 } 630 631 mdelay(1); 632 out: 633 host->clock = clock; 634 } 635 636 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 637 { 638 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 639 struct pltfm_imx_data *imx_data = pltfm_host->priv; 640 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 641 642 switch (boarddata->wp_type) { 643 case ESDHC_WP_GPIO: 644 return mmc_gpio_get_ro(host->mmc); 645 case ESDHC_WP_CONTROLLER: 646 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 647 SDHCI_WRITE_PROTECT); 648 case ESDHC_WP_NONE: 649 break; 650 } 651 652 return -ENOSYS; 653 } 654 655 static int esdhc_pltfm_bus_width(struct sdhci_host *host, int width) 656 { 657 u32 ctrl; 658 659 switch (width) { 660 case MMC_BUS_WIDTH_8: 661 ctrl = ESDHC_CTRL_8BITBUS; 662 break; 663 case MMC_BUS_WIDTH_4: 664 ctrl = ESDHC_CTRL_4BITBUS; 665 break; 666 default: 667 ctrl = 0; 668 break; 669 } 670 671 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 672 SDHCI_HOST_CONTROL); 673 674 return 0; 675 } 676 677 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 678 { 679 u32 reg; 680 681 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 682 mdelay(1); 683 684 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 685 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 686 ESDHC_MIX_CTRL_FBCLK_SEL; 687 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 688 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 689 dev_dbg(mmc_dev(host->mmc), 690 "tunning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 691 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 692 } 693 694 static void esdhc_request_done(struct mmc_request *mrq) 695 { 696 complete(&mrq->completion); 697 } 698 699 static int esdhc_send_tuning_cmd(struct sdhci_host *host, u32 opcode) 700 { 701 struct mmc_command cmd = {0}; 702 struct mmc_request mrq = {0}; 703 struct mmc_data data = {0}; 704 struct scatterlist sg; 705 char tuning_pattern[ESDHC_TUNING_BLOCK_PATTERN_LEN]; 706 707 cmd.opcode = opcode; 708 cmd.arg = 0; 709 cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; 710 711 data.blksz = ESDHC_TUNING_BLOCK_PATTERN_LEN; 712 data.blocks = 1; 713 data.flags = MMC_DATA_READ; 714 data.sg = &sg; 715 data.sg_len = 1; 716 717 sg_init_one(&sg, tuning_pattern, sizeof(tuning_pattern)); 718 719 mrq.cmd = &cmd; 720 mrq.cmd->mrq = &mrq; 721 mrq.data = &data; 722 mrq.data->mrq = &mrq; 723 mrq.cmd->data = mrq.data; 724 725 mrq.done = esdhc_request_done; 726 init_completion(&(mrq.completion)); 727 728 disable_irq(host->irq); 729 spin_lock(&host->lock); 730 host->mrq = &mrq; 731 732 sdhci_send_command(host, mrq.cmd); 733 734 spin_unlock(&host->lock); 735 enable_irq(host->irq); 736 737 wait_for_completion(&mrq.completion); 738 739 if (cmd.error) 740 return cmd.error; 741 if (data.error) 742 return data.error; 743 744 return 0; 745 } 746 747 static void esdhc_post_tuning(struct sdhci_host *host) 748 { 749 u32 reg; 750 751 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 752 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 753 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 754 } 755 756 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 757 { 758 int min, max, avg, ret; 759 760 /* find the mininum delay first which can pass tuning */ 761 min = ESDHC_TUNE_CTRL_MIN; 762 while (min < ESDHC_TUNE_CTRL_MAX) { 763 esdhc_prepare_tuning(host, min); 764 if (!esdhc_send_tuning_cmd(host, opcode)) 765 break; 766 min += ESDHC_TUNE_CTRL_STEP; 767 } 768 769 /* find the maxinum delay which can not pass tuning */ 770 max = min + ESDHC_TUNE_CTRL_STEP; 771 while (max < ESDHC_TUNE_CTRL_MAX) { 772 esdhc_prepare_tuning(host, max); 773 if (esdhc_send_tuning_cmd(host, opcode)) { 774 max -= ESDHC_TUNE_CTRL_STEP; 775 break; 776 } 777 max += ESDHC_TUNE_CTRL_STEP; 778 } 779 780 /* use average delay to get the best timing */ 781 avg = (min + max) / 2; 782 esdhc_prepare_tuning(host, avg); 783 ret = esdhc_send_tuning_cmd(host, opcode); 784 esdhc_post_tuning(host); 785 786 dev_dbg(mmc_dev(host->mmc), "tunning %s at 0x%x ret %d\n", 787 ret ? "failed" : "passed", avg, ret); 788 789 return ret; 790 } 791 792 static int esdhc_change_pinstate(struct sdhci_host *host, 793 unsigned int uhs) 794 { 795 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 796 struct pltfm_imx_data *imx_data = pltfm_host->priv; 797 struct pinctrl_state *pinctrl; 798 799 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 800 801 if (IS_ERR(imx_data->pinctrl) || 802 IS_ERR(imx_data->pins_default) || 803 IS_ERR(imx_data->pins_100mhz) || 804 IS_ERR(imx_data->pins_200mhz)) 805 return -EINVAL; 806 807 switch (uhs) { 808 case MMC_TIMING_UHS_SDR50: 809 pinctrl = imx_data->pins_100mhz; 810 break; 811 case MMC_TIMING_UHS_SDR104: 812 pinctrl = imx_data->pins_200mhz; 813 break; 814 default: 815 /* back to default state for other legacy timing */ 816 pinctrl = imx_data->pins_default; 817 } 818 819 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 820 } 821 822 static int esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned int uhs) 823 { 824 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 825 struct pltfm_imx_data *imx_data = pltfm_host->priv; 826 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 827 828 switch (uhs) { 829 case MMC_TIMING_UHS_SDR12: 830 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR12; 831 break; 832 case MMC_TIMING_UHS_SDR25: 833 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR25; 834 break; 835 case MMC_TIMING_UHS_SDR50: 836 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR50; 837 break; 838 case MMC_TIMING_UHS_SDR104: 839 imx_data->uhs_mode = SDHCI_CTRL_UHS_SDR104; 840 break; 841 case MMC_TIMING_UHS_DDR50: 842 imx_data->uhs_mode = SDHCI_CTRL_UHS_DDR50; 843 writel(readl(host->ioaddr + ESDHC_MIX_CTRL) | 844 ESDHC_MIX_CTRL_DDREN, 845 host->ioaddr + ESDHC_MIX_CTRL); 846 imx_data->is_ddr = 1; 847 if (boarddata->delay_line) { 848 u32 v; 849 v = boarddata->delay_line << 850 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 851 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 852 if (is_imx53_esdhc(imx_data)) 853 v <<= 1; 854 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 855 } 856 break; 857 } 858 859 return esdhc_change_pinstate(host, uhs); 860 } 861 862 static struct sdhci_ops sdhci_esdhc_ops = { 863 .read_l = esdhc_readl_le, 864 .read_w = esdhc_readw_le, 865 .write_l = esdhc_writel_le, 866 .write_w = esdhc_writew_le, 867 .write_b = esdhc_writeb_le, 868 .set_clock = esdhc_pltfm_set_clock, 869 .get_max_clock = esdhc_pltfm_get_max_clock, 870 .get_min_clock = esdhc_pltfm_get_min_clock, 871 .get_ro = esdhc_pltfm_get_ro, 872 .platform_bus_width = esdhc_pltfm_bus_width, 873 .set_uhs_signaling = esdhc_set_uhs_signaling, 874 }; 875 876 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 877 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 878 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 879 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 880 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 881 .ops = &sdhci_esdhc_ops, 882 }; 883 884 #ifdef CONFIG_OF 885 static int 886 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 887 struct esdhc_platform_data *boarddata) 888 { 889 struct device_node *np = pdev->dev.of_node; 890 891 if (!np) 892 return -ENODEV; 893 894 if (of_get_property(np, "non-removable", NULL)) 895 boarddata->cd_type = ESDHC_CD_PERMANENT; 896 897 if (of_get_property(np, "fsl,cd-controller", NULL)) 898 boarddata->cd_type = ESDHC_CD_CONTROLLER; 899 900 if (of_get_property(np, "fsl,wp-controller", NULL)) 901 boarddata->wp_type = ESDHC_WP_CONTROLLER; 902 903 boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 904 if (gpio_is_valid(boarddata->cd_gpio)) 905 boarddata->cd_type = ESDHC_CD_GPIO; 906 907 boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 908 if (gpio_is_valid(boarddata->wp_gpio)) 909 boarddata->wp_type = ESDHC_WP_GPIO; 910 911 of_property_read_u32(np, "bus-width", &boarddata->max_bus_width); 912 913 of_property_read_u32(np, "max-frequency", &boarddata->f_max); 914 915 if (of_find_property(np, "no-1-8-v", NULL)) 916 boarddata->support_vsel = false; 917 else 918 boarddata->support_vsel = true; 919 920 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 921 boarddata->delay_line = 0; 922 923 return 0; 924 } 925 #else 926 static inline int 927 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 928 struct esdhc_platform_data *boarddata) 929 { 930 return -ENODEV; 931 } 932 #endif 933 934 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 935 { 936 const struct of_device_id *of_id = 937 of_match_device(imx_esdhc_dt_ids, &pdev->dev); 938 struct sdhci_pltfm_host *pltfm_host; 939 struct sdhci_host *host; 940 struct esdhc_platform_data *boarddata; 941 int err; 942 struct pltfm_imx_data *imx_data; 943 944 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 0); 945 if (IS_ERR(host)) 946 return PTR_ERR(host); 947 948 pltfm_host = sdhci_priv(host); 949 950 imx_data = devm_kzalloc(&pdev->dev, sizeof(*imx_data), GFP_KERNEL); 951 if (!imx_data) { 952 err = -ENOMEM; 953 goto free_sdhci; 954 } 955 956 imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 957 pdev->id_entry->driver_data; 958 pltfm_host->priv = imx_data; 959 960 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 961 if (IS_ERR(imx_data->clk_ipg)) { 962 err = PTR_ERR(imx_data->clk_ipg); 963 goto free_sdhci; 964 } 965 966 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 967 if (IS_ERR(imx_data->clk_ahb)) { 968 err = PTR_ERR(imx_data->clk_ahb); 969 goto free_sdhci; 970 } 971 972 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 973 if (IS_ERR(imx_data->clk_per)) { 974 err = PTR_ERR(imx_data->clk_per); 975 goto free_sdhci; 976 } 977 978 pltfm_host->clk = imx_data->clk_per; 979 980 clk_prepare_enable(imx_data->clk_per); 981 clk_prepare_enable(imx_data->clk_ipg); 982 clk_prepare_enable(imx_data->clk_ahb); 983 984 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 985 if (IS_ERR(imx_data->pinctrl)) { 986 err = PTR_ERR(imx_data->pinctrl); 987 goto disable_clk; 988 } 989 990 imx_data->pins_default = pinctrl_lookup_state(imx_data->pinctrl, 991 PINCTRL_STATE_DEFAULT); 992 if (IS_ERR(imx_data->pins_default)) { 993 err = PTR_ERR(imx_data->pins_default); 994 dev_err(mmc_dev(host->mmc), "could not get default state\n"); 995 goto disable_clk; 996 } 997 998 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 999 1000 if (imx_data->socdata->flags & ESDHC_FLAG_ENGCM07207) 1001 /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 1002 host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 1003 | SDHCI_QUIRK_BROKEN_ADMA; 1004 1005 /* 1006 * The imx6q ROM code will change the default watermark level setting 1007 * to something insane. Change it back here. 1008 */ 1009 if (esdhc_is_usdhc(imx_data)) { 1010 writel(0x08100810, host->ioaddr + ESDHC_WTMK_LVL); 1011 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1012 } 1013 1014 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1015 sdhci_esdhc_ops.platform_execute_tuning = 1016 esdhc_executing_tuning; 1017 boarddata = &imx_data->boarddata; 1018 if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 1019 if (!host->mmc->parent->platform_data) { 1020 dev_err(mmc_dev(host->mmc), "no board data!\n"); 1021 err = -EINVAL; 1022 goto disable_clk; 1023 } 1024 imx_data->boarddata = *((struct esdhc_platform_data *) 1025 host->mmc->parent->platform_data); 1026 } 1027 1028 /* write_protect */ 1029 if (boarddata->wp_type == ESDHC_WP_GPIO) { 1030 err = mmc_gpio_request_ro(host->mmc, boarddata->wp_gpio); 1031 if (err) { 1032 dev_err(mmc_dev(host->mmc), 1033 "failed to request write-protect gpio!\n"); 1034 goto disable_clk; 1035 } 1036 host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 1037 } 1038 1039 /* card_detect */ 1040 switch (boarddata->cd_type) { 1041 case ESDHC_CD_GPIO: 1042 err = mmc_gpio_request_cd(host->mmc, boarddata->cd_gpio, 0); 1043 if (err) { 1044 dev_err(mmc_dev(host->mmc), 1045 "failed to request card-detect gpio!\n"); 1046 goto disable_clk; 1047 } 1048 /* fall through */ 1049 1050 case ESDHC_CD_CONTROLLER: 1051 /* we have a working card_detect back */ 1052 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1053 break; 1054 1055 case ESDHC_CD_PERMANENT: 1056 host->mmc->caps = MMC_CAP_NONREMOVABLE; 1057 break; 1058 1059 case ESDHC_CD_NONE: 1060 break; 1061 } 1062 1063 switch (boarddata->max_bus_width) { 1064 case 8: 1065 host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 1066 break; 1067 case 4: 1068 host->mmc->caps |= MMC_CAP_4_BIT_DATA; 1069 break; 1070 case 1: 1071 default: 1072 host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 1073 break; 1074 } 1075 1076 /* sdr50 and sdr104 needs work on 1.8v signal voltage */ 1077 if ((boarddata->support_vsel) && esdhc_is_usdhc(imx_data)) { 1078 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1079 ESDHC_PINCTRL_STATE_100MHZ); 1080 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1081 ESDHC_PINCTRL_STATE_200MHZ); 1082 if (IS_ERR(imx_data->pins_100mhz) || 1083 IS_ERR(imx_data->pins_200mhz)) { 1084 dev_warn(mmc_dev(host->mmc), 1085 "could not get ultra high speed state, work on normal mode\n"); 1086 /* fall back to not support uhs by specify no 1.8v quirk */ 1087 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1088 } 1089 } else { 1090 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1091 } 1092 1093 err = sdhci_add_host(host); 1094 if (err) 1095 goto disable_clk; 1096 1097 return 0; 1098 1099 disable_clk: 1100 clk_disable_unprepare(imx_data->clk_per); 1101 clk_disable_unprepare(imx_data->clk_ipg); 1102 clk_disable_unprepare(imx_data->clk_ahb); 1103 free_sdhci: 1104 sdhci_pltfm_free(pdev); 1105 return err; 1106 } 1107 1108 static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 1109 { 1110 struct sdhci_host *host = platform_get_drvdata(pdev); 1111 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1112 struct pltfm_imx_data *imx_data = pltfm_host->priv; 1113 int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1114 1115 sdhci_remove_host(host, dead); 1116 1117 clk_disable_unprepare(imx_data->clk_per); 1118 clk_disable_unprepare(imx_data->clk_ipg); 1119 clk_disable_unprepare(imx_data->clk_ahb); 1120 1121 sdhci_pltfm_free(pdev); 1122 1123 return 0; 1124 } 1125 1126 static struct platform_driver sdhci_esdhc_imx_driver = { 1127 .driver = { 1128 .name = "sdhci-esdhc-imx", 1129 .owner = THIS_MODULE, 1130 .of_match_table = imx_esdhc_dt_ids, 1131 .pm = SDHCI_PLTFM_PMOPS, 1132 }, 1133 .id_table = imx_esdhc_devtype, 1134 .probe = sdhci_esdhc_imx_probe, 1135 .remove = sdhci_esdhc_imx_remove, 1136 }; 1137 1138 module_platform_driver(sdhci_esdhc_imx_driver); 1139 1140 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1141 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 1142 MODULE_LICENSE("GPL v2"); 1143