1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Freescale eSDHC i.MX controller driver for the platform bus. 4 * 5 * derived from the OF-version. 6 * 7 * Copyright (c) 2010 Pengutronix e.K. 8 * Author: Wolfram Sang <kernel@pengutronix.de> 9 */ 10 11 #include <linux/bitfield.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 #include <linux/delay.h> 15 #include <linux/err.h> 16 #include <linux/clk.h> 17 #include <linux/module.h> 18 #include <linux/slab.h> 19 #include <linux/pm_qos.h> 20 #include <linux/mmc/host.h> 21 #include <linux/mmc/mmc.h> 22 #include <linux/mmc/sdio.h> 23 #include <linux/mmc/slot-gpio.h> 24 #include <linux/of.h> 25 #include <linux/platform_device.h> 26 #include <linux/pinctrl/consumer.h> 27 #include <linux/pm_runtime.h> 28 #include "sdhci-cqhci.h" 29 #include "sdhci-pltfm.h" 30 #include "sdhci-esdhc.h" 31 #include "cqhci.h" 32 33 #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 34 #define ESDHC_CTRL_D3CD 0x08 35 #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 36 /* VENDOR SPEC register */ 37 #define ESDHC_VENDOR_SPEC 0xc0 38 #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 39 #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 40 #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 41 #define ESDHC_DEBUG_SEL_AND_STATUS_REG 0xc2 42 #define ESDHC_DEBUG_SEL_REG 0xc3 43 #define ESDHC_DEBUG_SEL_MASK 0xf 44 #define ESDHC_DEBUG_SEL_CMD_STATE 1 45 #define ESDHC_DEBUG_SEL_DATA_STATE 2 46 #define ESDHC_DEBUG_SEL_TRANS_STATE 3 47 #define ESDHC_DEBUG_SEL_DMA_STATE 4 48 #define ESDHC_DEBUG_SEL_ADMA_STATE 5 49 #define ESDHC_DEBUG_SEL_FIFO_STATE 6 50 #define ESDHC_DEBUG_SEL_ASYNC_FIFO_STATE 7 51 #define ESDHC_WTMK_LVL 0x44 52 #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 53 #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 54 #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 55 #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 56 #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 57 #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 58 #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 59 #define ESDHC_MIX_CTRL 0x48 60 #define ESDHC_MIX_CTRL_DDREN (1 << 3) 61 #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 62 #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 63 #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 64 #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 65 #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 66 #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 67 #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 68 /* Bits 3 and 6 are not SDHCI standard definitions */ 69 #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 70 /* Tuning bits */ 71 #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 72 73 /* dll control register */ 74 #define ESDHC_DLL_CTRL 0x60 75 #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 76 #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 77 78 /* tune control register */ 79 #define ESDHC_TUNE_CTRL_STATUS 0x68 80 #define ESDHC_TUNE_CTRL_STEP 1 81 #define ESDHC_TUNE_CTRL_MIN 0 82 #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 83 84 /* strobe dll register */ 85 #define ESDHC_STROBE_DLL_CTRL 0x70 86 #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 87 #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 88 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 89 #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 90 #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 91 92 #define ESDHC_STROBE_DLL_STATUS 0x74 93 #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 94 #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 95 96 #define ESDHC_VEND_SPEC2 0xc8 97 #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 98 #define ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN (1 << 4) 99 #define ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN (0 << 4) 100 #define ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN (2 << 4) 101 #define ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN (1 << 6) 102 #define ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK (7 << 4) 103 104 #define ESDHC_TUNING_CTRL 0xcc 105 #define ESDHC_STD_TUNING_EN (1 << 24) 106 /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 107 #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 108 #define ESDHC_TUNING_START_TAP_MASK 0x7f 109 #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) 110 #define ESDHC_TUNING_STEP_DEFAULT 0x1 111 #define ESDHC_TUNING_STEP_MASK 0x00070000 112 #define ESDHC_TUNING_STEP_SHIFT 16 113 114 /* pinctrl state */ 115 #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 116 #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 117 118 /* 119 * Our interpretation of the SDHCI_HOST_CONTROL register 120 */ 121 #define ESDHC_CTRL_4BITBUS (0x1 << 1) 122 #define ESDHC_CTRL_8BITBUS (0x2 << 1) 123 #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 124 #define USDHC_GET_BUSWIDTH(c) (c & ESDHC_CTRL_BUSWIDTH_MASK) 125 126 /* 127 * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 128 * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 129 * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 130 * Define this macro DMA error INT for fsl eSDHC 131 */ 132 #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 133 134 /* the address offset of CQHCI */ 135 #define ESDHC_CQHCI_ADDR_OFFSET 0x100 136 137 /* 138 * The CMDTYPE of the CMD register (offset 0xE) should be set to 139 * "11" when the STOP CMD12 is issued on imx53 to abort one 140 * open ended multi-blk IO. Otherwise the TC INT wouldn't 141 * be generated. 142 * In exact block transfer, the controller doesn't complete the 143 * operations automatically as required at the end of the 144 * transfer and remains on hold if the abort command is not sent. 145 * As a result, the TC flag is not asserted and SW received timeout 146 * exception. Bit1 of Vendor Spec register is used to fix it. 147 */ 148 #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 149 /* 150 * The flag tells that the ESDHC controller is an USDHC block that is 151 * integrated on the i.MX6 series. 152 */ 153 #define ESDHC_FLAG_USDHC BIT(3) 154 /* The IP supports manual tuning process */ 155 #define ESDHC_FLAG_MAN_TUNING BIT(4) 156 /* The IP supports standard tuning process */ 157 #define ESDHC_FLAG_STD_TUNING BIT(5) 158 /* The IP has SDHCI_CAPABILITIES_1 register */ 159 #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 160 /* 161 * The IP has erratum ERR004536 162 * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 163 * when reading data from the card 164 * This flag is also set for i.MX25 and i.MX35 in order to get 165 * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 166 */ 167 #define ESDHC_FLAG_ERR004536 BIT(7) 168 /* The IP supports HS200 mode */ 169 #define ESDHC_FLAG_HS200 BIT(8) 170 /* The IP supports HS400 mode */ 171 #define ESDHC_FLAG_HS400 BIT(9) 172 /* 173 * The IP has errata ERR010450 174 * uSDHC: At 1.8V due to the I/O timing limit, for SDR mode, SD card 175 * clock can't exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 176 */ 177 #define ESDHC_FLAG_ERR010450 BIT(10) 178 /* The IP supports HS400ES mode */ 179 #define ESDHC_FLAG_HS400_ES BIT(11) 180 /* The IP has Host Controller Interface for Command Queuing */ 181 #define ESDHC_FLAG_CQHCI BIT(12) 182 /* need request pmqos during low power */ 183 #define ESDHC_FLAG_PMQOS BIT(13) 184 /* The IP state got lost in low power mode */ 185 #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 186 /* The IP lost clock rate in PM_RUNTIME */ 187 #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 188 /* 189 * The IP do not support the ACMD23 feature completely when use ADMA mode. 190 * In ADMA mode, it only use the 16 bit block count of the register 0x4 191 * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will 192 * ignore the upper 16 bit of the CMD23's argument. This will block the reliable 193 * write operation in RPMB, because RPMB reliable write need to set the bit31 194 * of the CMD23's argument. 195 * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA 196 * do not has this limitation. so when these SoC use ADMA mode, it need to 197 * disable the ACMD23 feature. 198 */ 199 #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16) 200 201 /* ERR004536 is not applicable for the IP */ 202 #define ESDHC_FLAG_SKIP_ERR004536 BIT(17) 203 204 /* The IP does not have GPIO CD wake capabilities */ 205 #define ESDHC_FLAG_SKIP_CD_WAKE BIT(18) 206 207 enum wp_types { 208 ESDHC_WP_NONE, /* no WP, neither controller nor gpio */ 209 ESDHC_WP_CONTROLLER, /* mmc controller internal WP */ 210 ESDHC_WP_GPIO, /* external gpio pin for WP */ 211 }; 212 213 enum cd_types { 214 ESDHC_CD_NONE, /* no CD, neither controller nor gpio */ 215 ESDHC_CD_CONTROLLER, /* mmc controller internal CD */ 216 ESDHC_CD_GPIO, /* external gpio pin for CD */ 217 ESDHC_CD_PERMANENT, /* no CD, card permanently wired to host */ 218 }; 219 220 /* 221 * struct esdhc_platform_data - platform data for esdhc on i.MX 222 * 223 * ESDHC_WP(CD)_CONTROLLER type is not available on i.MX25/35. 224 * 225 * @wp_type: type of write_protect method (see wp_types enum above) 226 * @cd_type: type of card_detect method (see cd_types enum above) 227 */ 228 229 struct esdhc_platform_data { 230 enum wp_types wp_type; 231 enum cd_types cd_type; 232 int max_bus_width; 233 unsigned int delay_line; 234 unsigned int tuning_step; /* The delay cell steps in tuning procedure */ 235 unsigned int tuning_start_tap; /* The start delay cell point in tuning procedure */ 236 unsigned int strobe_dll_delay_target; /* The delay cell for strobe pad (read clock) */ 237 }; 238 239 struct esdhc_soc_data { 240 u32 flags; 241 }; 242 243 static const struct esdhc_soc_data esdhc_imx25_data = { 244 .flags = ESDHC_FLAG_ERR004536, 245 }; 246 247 static const struct esdhc_soc_data esdhc_imx35_data = { 248 .flags = ESDHC_FLAG_ERR004536, 249 }; 250 251 static const struct esdhc_soc_data esdhc_imx51_data = { 252 .flags = 0, 253 }; 254 255 static const struct esdhc_soc_data esdhc_imx53_data = { 256 .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 257 }; 258 259 static const struct esdhc_soc_data usdhc_imx6q_data = { 260 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 261 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 262 }; 263 264 static const struct esdhc_soc_data usdhc_imx6sl_data = { 265 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 266 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 267 | ESDHC_FLAG_HS200 268 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 269 }; 270 271 static const struct esdhc_soc_data usdhc_imx6sll_data = { 272 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 273 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 274 | ESDHC_FLAG_HS400 275 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 276 }; 277 278 static const struct esdhc_soc_data usdhc_imx6sx_data = { 279 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 280 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 281 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 282 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 283 }; 284 285 static const struct esdhc_soc_data usdhc_imx6ull_data = { 286 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 287 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 288 | ESDHC_FLAG_ERR010450 289 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 290 }; 291 292 static const struct esdhc_soc_data usdhc_imx7d_data = { 293 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 294 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 295 | ESDHC_FLAG_HS400 296 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 297 | ESDHC_FLAG_BROKEN_AUTO_CMD23, 298 }; 299 300 static struct esdhc_soc_data usdhc_s32g2_data = { 301 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 302 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 303 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 304 | ESDHC_FLAG_SKIP_ERR004536 | ESDHC_FLAG_SKIP_CD_WAKE, 305 }; 306 307 static struct esdhc_soc_data usdhc_imx7ulp_data = { 308 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 309 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 310 | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 311 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 312 }; 313 static struct esdhc_soc_data usdhc_imxrt1050_data = { 314 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 315 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200, 316 }; 317 318 static struct esdhc_soc_data usdhc_imx8qxp_data = { 319 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 320 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 321 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 322 | ESDHC_FLAG_STATE_LOST_IN_LPMODE 323 | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 324 }; 325 326 static struct esdhc_soc_data usdhc_imx8mm_data = { 327 .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 328 | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 329 | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 330 | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 331 }; 332 333 struct pltfm_imx_data { 334 u32 scratchpad; 335 struct pinctrl *pinctrl; 336 struct pinctrl_state *pins_100mhz; 337 struct pinctrl_state *pins_200mhz; 338 const struct esdhc_soc_data *socdata; 339 struct esdhc_platform_data boarddata; 340 struct clk *clk_ipg; 341 struct clk *clk_ahb; 342 struct clk *clk_per; 343 unsigned int actual_clock; 344 345 /* 346 * USDHC has one limition, require the SDIO device a different 347 * register setting. Driver has to recognize card type during 348 * the card init, but at this stage, mmc_host->card is not 349 * available. So involve this field to save the card type 350 * during card init through usdhc_init_card(). 351 */ 352 unsigned int init_card_type; 353 354 enum { 355 NO_CMD_PENDING, /* no multiblock command pending */ 356 MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 357 WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 358 } multiblock_status; 359 u32 is_ddr; 360 struct pm_qos_request pm_qos_req; 361 }; 362 363 static const struct of_device_id imx_esdhc_dt_ids[] = { 364 { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 365 { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 366 { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 367 { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 368 { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 369 { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 370 { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, }, 371 { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 372 { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 373 { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 374 { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 375 { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 376 { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 377 { .compatible = "fsl,imxrt1050-usdhc", .data = &usdhc_imxrt1050_data, }, 378 { .compatible = "nxp,s32g2-usdhc", .data = &usdhc_s32g2_data, }, 379 { /* sentinel */ } 380 }; 381 MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 382 383 static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 384 { 385 return data->socdata == &esdhc_imx25_data; 386 } 387 388 static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 389 { 390 return data->socdata == &esdhc_imx53_data; 391 } 392 393 static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 394 { 395 return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 396 } 397 398 static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 399 { 400 void __iomem *base = host->ioaddr + (reg & ~0x3); 401 u32 shift = (reg & 0x3) * 8; 402 403 writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 404 } 405 406 #define DRIVER_NAME "sdhci-esdhc-imx" 407 #define ESDHC_IMX_DUMP(f, x...) \ 408 pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x) 409 static void esdhc_dump_debug_regs(struct sdhci_host *host) 410 { 411 int i; 412 char *debug_status[7] = { 413 "cmd debug status", 414 "data debug status", 415 "trans debug status", 416 "dma debug status", 417 "adma debug status", 418 "fifo debug status", 419 "async fifo debug status" 420 }; 421 422 ESDHC_IMX_DUMP("========= ESDHC IMX DEBUG STATUS DUMP =========\n"); 423 for (i = 0; i < 7; i++) { 424 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 425 ESDHC_DEBUG_SEL_CMD_STATE + i, ESDHC_DEBUG_SEL_REG); 426 ESDHC_IMX_DUMP("%s: 0x%04x\n", debug_status[i], 427 readw(host->ioaddr + ESDHC_DEBUG_SEL_AND_STATUS_REG)); 428 } 429 430 esdhc_clrset_le(host, ESDHC_DEBUG_SEL_MASK, 0, ESDHC_DEBUG_SEL_REG); 431 432 } 433 434 static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) 435 { 436 u32 present_state; 437 int ret; 438 439 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, 440 (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); 441 if (ret == -ETIMEDOUT) 442 dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 443 } 444 445 /* Enable the auto tuning circuit to check the CMD line and BUS line */ 446 static inline void usdhc_auto_tuning_mode_sel_and_en(struct sdhci_host *host) 447 { 448 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 449 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 450 u32 buswidth, auto_tune_buswidth; 451 u32 reg; 452 453 buswidth = USDHC_GET_BUSWIDTH(readl(host->ioaddr + SDHCI_HOST_CONTROL)); 454 455 switch (buswidth) { 456 case ESDHC_CTRL_8BITBUS: 457 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_8BIT_EN; 458 break; 459 case ESDHC_CTRL_4BITBUS: 460 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_4BIT_EN; 461 break; 462 default: /* 1BITBUS */ 463 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 464 break; 465 } 466 467 /* 468 * For USDHC, auto tuning circuit can not handle the async sdio 469 * device interrupt correctly. When sdio device use 4 data lines, 470 * async sdio interrupt will use the shared DAT[1], if enable auto 471 * tuning circuit check these 4 data lines, include the DAT[1], 472 * this circuit will detect this interrupt, take this as a data on 473 * DAT[1], and adjust the delay cell wrongly. 474 * This is the hardware design limitation, to avoid this, for sdio 475 * device, config the auto tuning circuit only check DAT[0] and CMD 476 * line. 477 */ 478 if (imx_data->init_card_type == MMC_TYPE_SDIO) 479 auto_tune_buswidth = ESDHC_VEND_SPEC2_AUTO_TUNE_1BIT_EN; 480 481 esdhc_clrset_le(host, ESDHC_VEND_SPEC2_AUTO_TUNE_MODE_MASK, 482 auto_tune_buswidth | ESDHC_VEND_SPEC2_AUTO_TUNE_CMD_EN, 483 ESDHC_VEND_SPEC2); 484 485 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 486 reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 487 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 488 } 489 490 static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 491 { 492 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 493 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 494 u32 val = readl(host->ioaddr + reg); 495 496 if (unlikely(reg == SDHCI_PRESENT_STATE)) { 497 u32 fsl_prss = val; 498 /* save the least 20 bits */ 499 val = fsl_prss & 0x000FFFFF; 500 /* move dat[0-3] bits */ 501 val |= (fsl_prss & 0x0F000000) >> 4; 502 /* move cmd line bit */ 503 val |= (fsl_prss & 0x00800000) << 1; 504 } 505 506 if (unlikely(reg == SDHCI_CAPABILITIES)) { 507 /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 508 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 509 val &= 0xffff0000; 510 511 /* In FSL esdhc IC module, only bit20 is used to indicate the 512 * ADMA2 capability of esdhc, but this bit is messed up on 513 * some SOCs (e.g. on MX25, MX35 this bit is set, but they 514 * don't actually support ADMA2). So set the BROKEN_ADMA 515 * quirk on MX25/35 platforms. 516 */ 517 518 if (val & SDHCI_CAN_DO_ADMA1) { 519 val &= ~SDHCI_CAN_DO_ADMA1; 520 val |= SDHCI_CAN_DO_ADMA2; 521 } 522 } 523 524 if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 525 if (esdhc_is_usdhc(imx_data)) { 526 if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 527 val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 528 else 529 /* imx6q/dl does not have cap_1 register, fake one */ 530 val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 531 | SDHCI_SUPPORT_SDR50 532 | SDHCI_USE_SDR50_TUNING 533 | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, 534 SDHCI_TUNING_MODE_3); 535 536 /* 537 * Do not advertise faster UHS modes if there are no 538 * pinctrl states for 100MHz/200MHz. 539 */ 540 if (IS_ERR_OR_NULL(imx_data->pins_100mhz)) 541 val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); 542 if (IS_ERR_OR_NULL(imx_data->pins_200mhz)) 543 val &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 544 } 545 } 546 547 if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 548 val = 0; 549 val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF); 550 val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF); 551 val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF); 552 } 553 554 if (unlikely(reg == SDHCI_INT_STATUS)) { 555 if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 556 val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 557 val |= SDHCI_INT_ADMA_ERROR; 558 } 559 560 /* 561 * mask off the interrupt we get in response to the manually 562 * sent CMD12 563 */ 564 if ((imx_data->multiblock_status == WAIT_FOR_INT) && 565 ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 566 val &= ~SDHCI_INT_RESPONSE; 567 writel(SDHCI_INT_RESPONSE, host->ioaddr + 568 SDHCI_INT_STATUS); 569 imx_data->multiblock_status = NO_CMD_PENDING; 570 } 571 } 572 573 return val; 574 } 575 576 static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 577 { 578 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 579 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 580 u32 data; 581 582 if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 583 reg == SDHCI_INT_STATUS)) { 584 if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 585 /* 586 * Clear and then set D3CD bit to avoid missing the 587 * card interrupt. This is an eSDHC controller problem 588 * so we need to apply the following workaround: clear 589 * and set D3CD bit will make eSDHC re-sample the card 590 * interrupt. In case a card interrupt was lost, 591 * re-sample it by the following steps. 592 */ 593 data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 594 data &= ~ESDHC_CTRL_D3CD; 595 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 596 data |= ESDHC_CTRL_D3CD; 597 writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 598 } 599 600 if (val & SDHCI_INT_ADMA_ERROR) { 601 val &= ~SDHCI_INT_ADMA_ERROR; 602 val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 603 } 604 } 605 606 if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 607 && (reg == SDHCI_INT_STATUS) 608 && (val & SDHCI_INT_DATA_END))) { 609 u32 v; 610 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 611 v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 612 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 613 614 if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 615 { 616 /* send a manual CMD12 with RESPTYP=none */ 617 data = MMC_STOP_TRANSMISSION << 24 | 618 SDHCI_CMD_ABORTCMD << 16; 619 writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 620 imx_data->multiblock_status = WAIT_FOR_INT; 621 } 622 } 623 624 writel(val, host->ioaddr + reg); 625 } 626 627 static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 628 { 629 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 630 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 631 u16 ret = 0; 632 u32 val; 633 634 if (unlikely(reg == SDHCI_HOST_VERSION)) { 635 reg ^= 2; 636 if (esdhc_is_usdhc(imx_data)) { 637 /* 638 * The usdhc register returns a wrong host version. 639 * Correct it here. 640 */ 641 return SDHCI_SPEC_300; 642 } 643 } 644 645 if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 646 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 647 if (val & ESDHC_VENDOR_SPEC_VSELECT) 648 ret |= SDHCI_CTRL_VDD_180; 649 650 if (esdhc_is_usdhc(imx_data)) { 651 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 652 val = readl(host->ioaddr + ESDHC_MIX_CTRL); 653 else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 654 /* the std tuning bits is in ACMD12_ERR for imx6sl */ 655 val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 656 } 657 658 if (val & ESDHC_MIX_CTRL_EXE_TUNE) 659 ret |= SDHCI_CTRL_EXEC_TUNING; 660 if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 661 ret |= SDHCI_CTRL_TUNED_CLK; 662 663 ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 664 665 return ret; 666 } 667 668 if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 669 if (esdhc_is_usdhc(imx_data)) { 670 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 671 ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 672 /* Swap AC23 bit */ 673 if (m & ESDHC_MIX_CTRL_AC23EN) { 674 ret &= ~ESDHC_MIX_CTRL_AC23EN; 675 ret |= SDHCI_TRNS_AUTO_CMD23; 676 } 677 } else { 678 ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 679 } 680 681 return ret; 682 } 683 684 return readw(host->ioaddr + reg); 685 } 686 687 static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 688 { 689 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 690 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 691 u32 new_val = 0; 692 693 switch (reg) { 694 case SDHCI_CLOCK_CONTROL: 695 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 696 if (val & SDHCI_CLOCK_CARD_EN) 697 new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 698 else 699 new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 700 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 701 if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON)) 702 esdhc_wait_for_card_clock_gate_off(host); 703 return; 704 case SDHCI_HOST_CONTROL2: 705 new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 706 if (val & SDHCI_CTRL_VDD_180) 707 new_val |= ESDHC_VENDOR_SPEC_VSELECT; 708 else 709 new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 710 writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 711 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 712 u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 713 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 714 if (val & SDHCI_CTRL_TUNED_CLK) { 715 v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 716 } else { 717 v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 718 m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 719 } 720 721 if (val & SDHCI_CTRL_EXEC_TUNING) { 722 v |= ESDHC_MIX_CTRL_EXE_TUNE; 723 m |= ESDHC_MIX_CTRL_FBCLK_SEL; 724 } else { 725 v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 726 } 727 728 writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 729 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 730 } 731 return; 732 case SDHCI_TRANSFER_MODE: 733 if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 734 && (host->cmd->opcode == SD_IO_RW_EXTENDED) 735 && (host->cmd->data->blocks > 1) 736 && (host->cmd->data->flags & MMC_DATA_READ)) { 737 u32 v; 738 v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 739 v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 740 writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 741 } 742 743 if (esdhc_is_usdhc(imx_data)) { 744 u32 wml; 745 u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 746 /* Swap AC23 bit */ 747 if (val & SDHCI_TRNS_AUTO_CMD23) { 748 val &= ~SDHCI_TRNS_AUTO_CMD23; 749 val |= ESDHC_MIX_CTRL_AC23EN; 750 } 751 m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 752 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 753 754 /* Set watermark levels for PIO access to maximum value 755 * (128 words) to accommodate full 512 bytes buffer. 756 * For DMA access restore the levels to default value. 757 */ 758 m = readl(host->ioaddr + ESDHC_WTMK_LVL); 759 if (val & SDHCI_TRNS_DMA) { 760 wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 761 } else { 762 u8 ctrl; 763 wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 764 765 /* 766 * Since already disable DMA mode, so also need 767 * to clear the DMASEL. Otherwise, for standard 768 * tuning, when send tuning command, usdhc will 769 * still prefetch the ADMA script from wrong 770 * DMA address, then we will see IOMMU report 771 * some error which show lack of TLB mapping. 772 */ 773 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 774 ctrl &= ~SDHCI_CTRL_DMA_MASK; 775 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 776 } 777 m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 778 ESDHC_WTMK_LVL_WR_WML_MASK); 779 m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 780 (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 781 writel(m, host->ioaddr + ESDHC_WTMK_LVL); 782 } else { 783 /* 784 * Postpone this write, we must do it together with a 785 * command write that is down below. 786 */ 787 imx_data->scratchpad = val; 788 } 789 return; 790 case SDHCI_COMMAND: 791 if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 792 val |= SDHCI_CMD_ABORTCMD; 793 794 if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 795 (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 796 imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 797 798 if (esdhc_is_usdhc(imx_data)) 799 writel(val << 16, 800 host->ioaddr + SDHCI_TRANSFER_MODE); 801 else 802 writel(val << 16 | imx_data->scratchpad, 803 host->ioaddr + SDHCI_TRANSFER_MODE); 804 return; 805 case SDHCI_BLOCK_SIZE: 806 val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 807 break; 808 } 809 esdhc_clrset_le(host, 0xffff, val, reg); 810 } 811 812 static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 813 { 814 u8 ret; 815 u32 val; 816 817 switch (reg) { 818 case SDHCI_HOST_CONTROL: 819 val = readl(host->ioaddr + reg); 820 821 ret = val & SDHCI_CTRL_LED; 822 ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 823 ret |= (val & ESDHC_CTRL_4BITBUS); 824 ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 825 return ret; 826 } 827 828 return readb(host->ioaddr + reg); 829 } 830 831 static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 832 { 833 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 834 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 835 u32 new_val = 0; 836 u32 mask; 837 838 switch (reg) { 839 case SDHCI_POWER_CONTROL: 840 /* 841 * FSL put some DMA bits here 842 * If your board has a regulator, code should be here 843 */ 844 return; 845 case SDHCI_HOST_CONTROL: 846 /* FSL messed up here, so we need to manually compose it. */ 847 new_val = val & SDHCI_CTRL_LED; 848 /* ensure the endianness */ 849 new_val |= ESDHC_HOST_CONTROL_LE; 850 /* bits 8&9 are reserved on mx25 */ 851 if (!is_imx25_esdhc(imx_data)) { 852 /* DMA mode bits are shifted */ 853 new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 854 } 855 856 /* 857 * Do not touch buswidth bits here. This is done in 858 * esdhc_pltfm_bus_width. 859 * Do not touch the D3CD bit either which is used for the 860 * SDIO interrupt erratum workaround. 861 */ 862 mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 863 864 esdhc_clrset_le(host, mask, new_val, reg); 865 return; 866 case SDHCI_SOFTWARE_RESET: 867 if (val & SDHCI_RESET_DATA) 868 new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 869 break; 870 } 871 esdhc_clrset_le(host, 0xff, val, reg); 872 873 if (reg == SDHCI_SOFTWARE_RESET) { 874 if (val & SDHCI_RESET_ALL) { 875 /* 876 * The esdhc has a design violation to SDHC spec which 877 * tells that software reset should not affect card 878 * detection circuit. But esdhc clears its SYSCTL 879 * register bits [0..2] during the software reset. This 880 * will stop those clocks that card detection circuit 881 * relies on. To work around it, we turn the clocks on 882 * back to keep card detection circuit functional. 883 */ 884 esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 885 /* 886 * The reset on usdhc fails to clear MIX_CTRL register. 887 * Do it manually here. 888 */ 889 if (esdhc_is_usdhc(imx_data)) { 890 /* 891 * the tuning bits should be kept during reset 892 */ 893 new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 894 writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 895 host->ioaddr + ESDHC_MIX_CTRL); 896 imx_data->is_ddr = 0; 897 } 898 } else if (val & SDHCI_RESET_DATA) { 899 /* 900 * The eSDHC DAT line software reset clears at least the 901 * data transfer width on i.MX25, so make sure that the 902 * Host Control register is unaffected. 903 */ 904 esdhc_clrset_le(host, 0xff, new_val, 905 SDHCI_HOST_CONTROL); 906 } 907 } 908 } 909 910 static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 911 { 912 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 913 914 return pltfm_host->clock; 915 } 916 917 static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 918 { 919 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 920 921 return pltfm_host->clock / 256 / 16; 922 } 923 924 static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 925 unsigned int clock) 926 { 927 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 928 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 929 unsigned int host_clock = pltfm_host->clock; 930 int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 931 int pre_div = 1; 932 int div = 1; 933 int ret; 934 u32 temp, val; 935 936 if (esdhc_is_usdhc(imx_data)) { 937 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 938 writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 939 host->ioaddr + ESDHC_VENDOR_SPEC); 940 esdhc_wait_for_card_clock_gate_off(host); 941 } 942 943 if (clock == 0) { 944 host->mmc->actual_clock = 0; 945 return; 946 } 947 948 /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 949 if (is_imx53_esdhc(imx_data)) { 950 /* 951 * According to the i.MX53 reference manual, if DLLCTRL[10] can 952 * be set, then the controller is eSDHCv3, else it is eSDHCv2. 953 */ 954 val = readl(host->ioaddr + ESDHC_DLL_CTRL); 955 writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 956 temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 957 writel(val, host->ioaddr + ESDHC_DLL_CTRL); 958 if (temp & BIT(10)) 959 pre_div = 2; 960 } 961 962 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 963 temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 964 | ESDHC_CLOCK_MASK); 965 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 966 967 if ((imx_data->socdata->flags & ESDHC_FLAG_ERR010450) && 968 (!(host->quirks2 & SDHCI_QUIRK2_NO_1_8_V))) { 969 unsigned int max_clock; 970 971 max_clock = imx_data->is_ddr ? 45000000 : 150000000; 972 973 clock = min(clock, max_clock); 974 } 975 976 while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 977 pre_div < 256) 978 pre_div *= 2; 979 980 while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 981 div++; 982 983 host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 984 dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 985 clock, host->mmc->actual_clock); 986 987 pre_div >>= 1; 988 div--; 989 990 temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 991 temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 992 | (div << ESDHC_DIVIDER_SHIFT) 993 | (pre_div << ESDHC_PREDIV_SHIFT)); 994 sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 995 996 /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */ 997 ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, 998 (temp & ESDHC_CLOCK_STABLE), 2, 100); 999 if (ret == -ETIMEDOUT) 1000 dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); 1001 1002 if (esdhc_is_usdhc(imx_data)) { 1003 val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 1004 writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1005 host->ioaddr + ESDHC_VENDOR_SPEC); 1006 } 1007 1008 } 1009 1010 static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 1011 { 1012 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1013 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1014 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1015 1016 switch (boarddata->wp_type) { 1017 case ESDHC_WP_GPIO: 1018 return mmc_gpio_get_ro(host->mmc); 1019 case ESDHC_WP_CONTROLLER: 1020 return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 1021 SDHCI_WRITE_PROTECT); 1022 case ESDHC_WP_NONE: 1023 break; 1024 } 1025 1026 return -ENOSYS; 1027 } 1028 1029 static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 1030 { 1031 u32 ctrl; 1032 1033 switch (width) { 1034 case MMC_BUS_WIDTH_8: 1035 ctrl = ESDHC_CTRL_8BITBUS; 1036 break; 1037 case MMC_BUS_WIDTH_4: 1038 ctrl = ESDHC_CTRL_4BITBUS; 1039 break; 1040 default: 1041 ctrl = 0; 1042 break; 1043 } 1044 1045 esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 1046 SDHCI_HOST_CONTROL); 1047 } 1048 1049 static void esdhc_reset_tuning(struct sdhci_host *host) 1050 { 1051 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1052 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1053 u32 ctrl; 1054 int ret; 1055 1056 /* Reset the tuning circuit */ 1057 if (esdhc_is_usdhc(imx_data)) { 1058 ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1059 ctrl &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 1060 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1061 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1062 ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1063 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1064 writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1065 } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1066 writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1067 ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1068 ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1069 ctrl &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1070 writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1071 /* Make sure ESDHC_MIX_CTRL_EXE_TUNE cleared */ 1072 ret = readl_poll_timeout(host->ioaddr + SDHCI_AUTO_CMD_STATUS, 1073 ctrl, !(ctrl & ESDHC_MIX_CTRL_EXE_TUNE), 1, 50); 1074 if (ret == -ETIMEDOUT) 1075 dev_warn(mmc_dev(host->mmc), 1076 "Warning! clear execute tuning bit failed\n"); 1077 /* 1078 * SDHCI_INT_DATA_AVAIL is W1C bit, set this bit will clear the 1079 * usdhc IP internal logic flag execute_tuning_with_clr_buf, which 1080 * will finally make sure the normal data transfer logic correct. 1081 */ 1082 ctrl = readl(host->ioaddr + SDHCI_INT_STATUS); 1083 ctrl |= SDHCI_INT_DATA_AVAIL; 1084 writel(ctrl, host->ioaddr + SDHCI_INT_STATUS); 1085 } 1086 } 1087 } 1088 1089 static void usdhc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1090 { 1091 struct sdhci_host *host = mmc_priv(mmc); 1092 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1093 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1094 1095 imx_data->init_card_type = card->type; 1096 } 1097 1098 static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1099 { 1100 struct sdhci_host *host = mmc_priv(mmc); 1101 int err; 1102 1103 /* 1104 * i.MX uSDHC internally already uses a fixed optimized timing for 1105 * DDR50, normally does not require tuning for DDR50 mode. 1106 */ 1107 if (host->timing == MMC_TIMING_UHS_DDR50) 1108 return 0; 1109 1110 /* 1111 * Reset tuning circuit logic. If not, the previous tuning result 1112 * will impact current tuning, make current tuning can't set the 1113 * correct delay cell. 1114 */ 1115 esdhc_reset_tuning(host); 1116 err = sdhci_execute_tuning(mmc, opcode); 1117 /* If tuning done, enable auto tuning */ 1118 if (!err && !host->tuning_err) 1119 usdhc_auto_tuning_mode_sel_and_en(host); 1120 1121 return err; 1122 } 1123 1124 static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 1125 { 1126 u32 reg; 1127 u8 sw_rst; 1128 int ret; 1129 1130 /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 1131 mdelay(1); 1132 1133 /* IC suggest to reset USDHC before every tuning command */ 1134 esdhc_clrset_le(host, 0xff, SDHCI_RESET_ALL, SDHCI_SOFTWARE_RESET); 1135 ret = readb_poll_timeout(host->ioaddr + SDHCI_SOFTWARE_RESET, sw_rst, 1136 !(sw_rst & SDHCI_RESET_ALL), 10, 100); 1137 if (ret == -ETIMEDOUT) 1138 dev_warn(mmc_dev(host->mmc), 1139 "warning! RESET_ALL never complete before sending tuning command\n"); 1140 1141 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1142 reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 1143 ESDHC_MIX_CTRL_FBCLK_SEL; 1144 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1145 writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1146 dev_dbg(mmc_dev(host->mmc), 1147 "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 1148 val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 1149 } 1150 1151 static void esdhc_post_tuning(struct sdhci_host *host) 1152 { 1153 u32 reg; 1154 1155 reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 1156 reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 1157 writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 1158 } 1159 1160 /* 1161 * find the largest pass window, and use the average delay of this 1162 * largest window to get the best timing. 1163 */ 1164 static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 1165 { 1166 int min, max, avg, ret; 1167 int win_length, target_min, target_max, target_win_length; 1168 1169 min = ESDHC_TUNE_CTRL_MIN; 1170 max = ESDHC_TUNE_CTRL_MIN; 1171 target_win_length = 0; 1172 while (max < ESDHC_TUNE_CTRL_MAX) { 1173 /* find the mininum delay first which can pass tuning */ 1174 while (min < ESDHC_TUNE_CTRL_MAX) { 1175 esdhc_prepare_tuning(host, min); 1176 if (!mmc_send_tuning(host->mmc, opcode, NULL)) 1177 break; 1178 min += ESDHC_TUNE_CTRL_STEP; 1179 } 1180 1181 /* find the maxinum delay which can not pass tuning */ 1182 max = min + ESDHC_TUNE_CTRL_STEP; 1183 while (max < ESDHC_TUNE_CTRL_MAX) { 1184 esdhc_prepare_tuning(host, max); 1185 if (mmc_send_tuning(host->mmc, opcode, NULL)) { 1186 max -= ESDHC_TUNE_CTRL_STEP; 1187 break; 1188 } 1189 max += ESDHC_TUNE_CTRL_STEP; 1190 } 1191 1192 win_length = max - min + 1; 1193 /* get the largest pass window */ 1194 if (win_length > target_win_length) { 1195 target_win_length = win_length; 1196 target_min = min; 1197 target_max = max; 1198 } 1199 1200 /* continue to find the next pass window */ 1201 min = max + ESDHC_TUNE_CTRL_STEP; 1202 } 1203 1204 /* use average delay to get the best timing */ 1205 avg = (target_min + target_max) / 2; 1206 esdhc_prepare_tuning(host, avg); 1207 ret = mmc_send_tuning(host->mmc, opcode, NULL); 1208 esdhc_post_tuning(host); 1209 1210 dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 1211 ret ? "failed" : "passed", avg, ret); 1212 1213 return ret; 1214 } 1215 1216 static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 1217 { 1218 struct sdhci_host *host = mmc_priv(mmc); 1219 u32 m; 1220 1221 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1222 if (ios->enhanced_strobe) 1223 m |= ESDHC_MIX_CTRL_HS400_ES_EN; 1224 else 1225 m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 1226 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1227 } 1228 1229 static int esdhc_change_pinstate(struct sdhci_host *host, 1230 unsigned int uhs) 1231 { 1232 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1233 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1234 struct pinctrl_state *pinctrl; 1235 1236 dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 1237 1238 if (IS_ERR(imx_data->pinctrl) || 1239 IS_ERR(imx_data->pins_100mhz) || 1240 IS_ERR(imx_data->pins_200mhz)) 1241 return -EINVAL; 1242 1243 switch (uhs) { 1244 case MMC_TIMING_UHS_SDR50: 1245 case MMC_TIMING_UHS_DDR50: 1246 pinctrl = imx_data->pins_100mhz; 1247 break; 1248 case MMC_TIMING_UHS_SDR104: 1249 case MMC_TIMING_MMC_HS200: 1250 case MMC_TIMING_MMC_HS400: 1251 pinctrl = imx_data->pins_200mhz; 1252 break; 1253 default: 1254 /* back to default state for other legacy timing */ 1255 return pinctrl_select_default_state(mmc_dev(host->mmc)); 1256 } 1257 1258 return pinctrl_select_state(imx_data->pinctrl, pinctrl); 1259 } 1260 1261 /* 1262 * For HS400 eMMC, there is a data_strobe line. This signal is generated 1263 * by the device and used for data output and CRC status response output 1264 * in HS400 mode. The frequency of this signal follows the frequency of 1265 * CLK generated by host. The host receives the data which is aligned to the 1266 * edge of data_strobe line. Due to the time delay between CLK line and 1267 * data_strobe line, if the delay time is larger than one clock cycle, 1268 * then CLK and data_strobe line will be misaligned, read error shows up. 1269 */ 1270 static void esdhc_set_strobe_dll(struct sdhci_host *host) 1271 { 1272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1273 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1274 u32 strobe_delay; 1275 u32 v; 1276 int ret; 1277 1278 /* disable clock before enabling strobe dll */ 1279 writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 1280 ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 1281 host->ioaddr + ESDHC_VENDOR_SPEC); 1282 esdhc_wait_for_card_clock_gate_off(host); 1283 1284 /* force a reset on strobe dll */ 1285 writel(ESDHC_STROBE_DLL_CTRL_RESET, 1286 host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1287 /* clear the reset bit on strobe dll before any setting */ 1288 writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1289 1290 /* 1291 * enable strobe dll ctrl and adjust the delay target 1292 * for the uSDHC loopback read clock 1293 */ 1294 if (imx_data->boarddata.strobe_dll_delay_target) 1295 strobe_delay = imx_data->boarddata.strobe_dll_delay_target; 1296 else 1297 strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT; 1298 v = ESDHC_STROBE_DLL_CTRL_ENABLE | 1299 ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 1300 (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 1301 writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1302 1303 /* wait max 50us to get the REF/SLV lock */ 1304 ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, 1305 ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); 1306 if (ret == -ETIMEDOUT) 1307 dev_warn(mmc_dev(host->mmc), 1308 "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 1309 } 1310 1311 static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1312 { 1313 u32 m; 1314 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1315 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1316 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1317 1318 /* disable ddr mode and disable HS400 mode */ 1319 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1320 m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 1321 imx_data->is_ddr = 0; 1322 1323 switch (timing) { 1324 case MMC_TIMING_UHS_SDR12: 1325 case MMC_TIMING_UHS_SDR25: 1326 case MMC_TIMING_UHS_SDR50: 1327 case MMC_TIMING_UHS_SDR104: 1328 case MMC_TIMING_MMC_HS: 1329 case MMC_TIMING_MMC_HS200: 1330 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1331 break; 1332 case MMC_TIMING_UHS_DDR50: 1333 case MMC_TIMING_MMC_DDR52: 1334 m |= ESDHC_MIX_CTRL_DDREN; 1335 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1336 imx_data->is_ddr = 1; 1337 if (boarddata->delay_line) { 1338 u32 v; 1339 v = boarddata->delay_line << 1340 ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1341 (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1342 if (is_imx53_esdhc(imx_data)) 1343 v <<= 1; 1344 writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1345 } 1346 break; 1347 case MMC_TIMING_MMC_HS400: 1348 m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 1349 writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1350 imx_data->is_ddr = 1; 1351 /* update clock after enable DDR for strobe DLL lock */ 1352 host->ops->set_clock(host, host->clock); 1353 esdhc_set_strobe_dll(host); 1354 break; 1355 case MMC_TIMING_LEGACY: 1356 default: 1357 esdhc_reset_tuning(host); 1358 break; 1359 } 1360 1361 esdhc_change_pinstate(host, timing); 1362 } 1363 1364 static void esdhc_reset(struct sdhci_host *host, u8 mask) 1365 { 1366 sdhci_and_cqhci_reset(host, mask); 1367 1368 sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 1369 sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 1370 } 1371 1372 static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 1373 { 1374 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1375 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1376 1377 /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 1378 return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 1379 } 1380 1381 static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1382 { 1383 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1384 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1385 1386 /* use maximum timeout counter */ 1387 esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1388 esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1389 SDHCI_TIMEOUT_CONTROL); 1390 } 1391 1392 static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1393 { 1394 int cmd_error = 0; 1395 int data_error = 0; 1396 1397 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1398 return intmask; 1399 1400 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1401 1402 return 0; 1403 } 1404 1405 static struct sdhci_ops sdhci_esdhc_ops = { 1406 .read_l = esdhc_readl_le, 1407 .read_w = esdhc_readw_le, 1408 .read_b = esdhc_readb_le, 1409 .write_l = esdhc_writel_le, 1410 .write_w = esdhc_writew_le, 1411 .write_b = esdhc_writeb_le, 1412 .set_clock = esdhc_pltfm_set_clock, 1413 .get_max_clock = esdhc_pltfm_get_max_clock, 1414 .get_min_clock = esdhc_pltfm_get_min_clock, 1415 .get_max_timeout_count = esdhc_get_max_timeout_count, 1416 .get_ro = esdhc_pltfm_get_ro, 1417 .set_timeout = esdhc_set_timeout, 1418 .set_bus_width = esdhc_pltfm_set_bus_width, 1419 .set_uhs_signaling = esdhc_set_uhs_signaling, 1420 .reset = esdhc_reset, 1421 .irq = esdhc_cqhci_irq, 1422 .dump_vendor_regs = esdhc_dump_debug_regs, 1423 }; 1424 1425 static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 1426 .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 1427 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 1428 | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 1429 | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 1430 .ops = &sdhci_esdhc_ops, 1431 }; 1432 1433 static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1434 { 1435 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1436 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1437 struct cqhci_host *cq_host = host->mmc->cqe_private; 1438 u32 tmp; 1439 1440 if (esdhc_is_usdhc(imx_data)) { 1441 /* 1442 * The imx6q ROM code will change the default watermark 1443 * level setting to something insane. Change it back here. 1444 */ 1445 writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1446 1447 /* 1448 * ROM code will change the bit burst_length_enable setting 1449 * to zero if this usdhc is chosen to boot system. Change 1450 * it back here, otherwise it will impact the performance a 1451 * lot. This bit is used to enable/disable the burst length 1452 * for the external AHB2AXI bridge. It's useful especially 1453 * for INCR transfer because without burst length indicator, 1454 * the AHB2AXI bridge does not know the burst length in 1455 * advance. And without burst length indicator, AHB INCR 1456 * transfer can only be converted to singles on the AXI side. 1457 */ 1458 writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1459 | ESDHC_BURST_LEN_EN_INCR, 1460 host->ioaddr + SDHCI_HOST_CONTROL); 1461 1462 /* 1463 * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1464 * TO1.1, it's harmless for MX6SL 1465 */ 1466 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_ERR004536)) { 1467 writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1468 host->ioaddr + 0x6c); 1469 } 1470 1471 /* disable DLL_CTRL delay line settings */ 1472 writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 1473 1474 /* 1475 * For the case of command with busy, if set the bit 1476 * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1477 * transfer complete interrupt when busy is deasserted. 1478 * When CQHCI use DCMD to send a CMD need R1b respons, 1479 * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1480 * otherwise DCMD will always meet timeout waiting for 1481 * hardware interrupt issue. 1482 */ 1483 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1484 tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1485 tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1486 writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1487 1488 host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1489 } 1490 1491 if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1492 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1493 tmp |= ESDHC_STD_TUNING_EN; 1494 1495 /* 1496 * ROM code or bootloader may config the start tap 1497 * and step, unmask them first. 1498 */ 1499 tmp &= ~(ESDHC_TUNING_START_TAP_MASK | ESDHC_TUNING_STEP_MASK); 1500 if (imx_data->boarddata.tuning_start_tap) 1501 tmp |= imx_data->boarddata.tuning_start_tap; 1502 else 1503 tmp |= ESDHC_TUNING_START_TAP_DEFAULT; 1504 1505 if (imx_data->boarddata.tuning_step) { 1506 tmp |= imx_data->boarddata.tuning_step 1507 << ESDHC_TUNING_STEP_SHIFT; 1508 } else { 1509 tmp |= ESDHC_TUNING_STEP_DEFAULT 1510 << ESDHC_TUNING_STEP_SHIFT; 1511 } 1512 1513 /* Disable the CMD CRC check for tuning, if not, need to 1514 * add some delay after every tuning command, because 1515 * hardware standard tuning logic will directly go to next 1516 * step once it detect the CMD CRC error, will not wait for 1517 * the card side to finally send out the tuning data, trigger 1518 * the buffer read ready interrupt immediately. If usdhc send 1519 * the next tuning command some eMMC card will stuck, can't 1520 * response, block the tuning procedure or the first command 1521 * after the whole tuning procedure always can't get any response. 1522 */ 1523 tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; 1524 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1525 } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1526 /* 1527 * ESDHC_STD_TUNING_EN may be configed in bootloader 1528 * or ROM code, so clear this bit here to make sure 1529 * the manual tuning can work. 1530 */ 1531 tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1532 tmp &= ~ESDHC_STD_TUNING_EN; 1533 writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1534 } 1535 1536 /* 1537 * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1538 * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let 1539 * the 1st linux configure power/clock for the 2nd Linux. 1540 * 1541 * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux 1542 * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. 1543 * After we clear the pending interrupt and halt CQCTL, issue gone. 1544 */ 1545 if (cq_host) { 1546 tmp = cqhci_readl(cq_host, CQHCI_IS); 1547 cqhci_writel(cq_host, tmp, CQHCI_IS); 1548 cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 1549 } 1550 } 1551 } 1552 1553 static void esdhc_cqe_enable(struct mmc_host *mmc) 1554 { 1555 struct sdhci_host *host = mmc_priv(mmc); 1556 struct cqhci_host *cq_host = mmc->cqe_private; 1557 u32 reg; 1558 u16 mode; 1559 int count = 10; 1560 1561 /* 1562 * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1563 * the case after tuning, so ensure the buffer is drained. 1564 */ 1565 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1566 while (reg & SDHCI_DATA_AVAILABLE) { 1567 sdhci_readl(host, SDHCI_BUFFER); 1568 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1569 if (count-- == 0) { 1570 dev_warn(mmc_dev(host->mmc), 1571 "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1572 break; 1573 } 1574 mdelay(1); 1575 } 1576 1577 /* 1578 * Runtime resume will reset the entire host controller, which 1579 * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1580 * Here set DMAEN and BCEN when enable CMDQ. 1581 */ 1582 mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1583 if (host->flags & SDHCI_REQ_USE_DMA) 1584 mode |= SDHCI_TRNS_DMA; 1585 if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1586 mode |= SDHCI_TRNS_BLK_CNT_EN; 1587 sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1588 1589 /* 1590 * Though Runtime resume reset the entire host controller, 1591 * but do not impact the CQHCI side, need to clear the 1592 * HALT bit, avoid CQHCI stuck in the first request when 1593 * system resume back. 1594 */ 1595 cqhci_writel(cq_host, 0, CQHCI_CTL); 1596 if (cqhci_readl(cq_host, CQHCI_CTL) & CQHCI_HALT) 1597 dev_err(mmc_dev(host->mmc), 1598 "failed to exit halt state when enable CQE\n"); 1599 1600 1601 sdhci_cqe_enable(mmc); 1602 } 1603 1604 static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1605 { 1606 sdhci_dumpregs(mmc_priv(mmc)); 1607 } 1608 1609 static const struct cqhci_host_ops esdhc_cqhci_ops = { 1610 .enable = esdhc_cqe_enable, 1611 .disable = sdhci_cqe_disable, 1612 .dumpregs = esdhc_sdhci_dumpregs, 1613 }; 1614 1615 static int 1616 sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 1617 struct sdhci_host *host, 1618 struct pltfm_imx_data *imx_data) 1619 { 1620 struct device_node *np = pdev->dev.of_node; 1621 struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1622 int ret; 1623 1624 if (of_property_read_bool(np, "fsl,wp-controller")) 1625 boarddata->wp_type = ESDHC_WP_CONTROLLER; 1626 1627 /* 1628 * If we have this property, then activate WP check. 1629 * Retrieveing and requesting the actual WP GPIO will happen 1630 * in the call to mmc_of_parse(). 1631 */ 1632 if (of_property_read_bool(np, "wp-gpios")) 1633 boarddata->wp_type = ESDHC_WP_GPIO; 1634 1635 of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1636 of_property_read_u32(np, "fsl,tuning-start-tap", 1637 &boarddata->tuning_start_tap); 1638 1639 of_property_read_u32(np, "fsl,strobe-dll-delay-target", 1640 &boarddata->strobe_dll_delay_target); 1641 if (of_property_read_bool(np, "no-1-8-v")) 1642 host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1643 1644 if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1645 boarddata->delay_line = 0; 1646 1647 mmc_of_parse_voltage(host->mmc, &host->ocr_mask); 1648 1649 if (esdhc_is_usdhc(imx_data) && !IS_ERR(imx_data->pinctrl)) { 1650 imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 1651 ESDHC_PINCTRL_STATE_100MHZ); 1652 imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 1653 ESDHC_PINCTRL_STATE_200MHZ); 1654 } 1655 1656 /* call to generic mmc_of_parse to support additional capabilities */ 1657 ret = mmc_of_parse(host->mmc); 1658 if (ret) 1659 return ret; 1660 1661 /* HS400/HS400ES require 8 bit bus */ 1662 if (!(host->mmc->caps & MMC_CAP_8_BIT_DATA)) 1663 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1664 1665 if (mmc_gpio_get_cd(host->mmc) >= 0) 1666 host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 1667 1668 return 0; 1669 } 1670 1671 static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 1672 { 1673 struct sdhci_pltfm_host *pltfm_host; 1674 struct sdhci_host *host; 1675 struct cqhci_host *cq_host; 1676 int err; 1677 struct pltfm_imx_data *imx_data; 1678 1679 host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1680 sizeof(*imx_data)); 1681 if (IS_ERR(host)) 1682 return PTR_ERR(host); 1683 1684 pltfm_host = sdhci_priv(host); 1685 1686 imx_data = sdhci_pltfm_priv(pltfm_host); 1687 1688 imx_data->socdata = device_get_match_data(&pdev->dev); 1689 1690 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1691 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1692 1693 imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 1694 if (IS_ERR(imx_data->clk_ipg)) { 1695 err = PTR_ERR(imx_data->clk_ipg); 1696 goto free_sdhci; 1697 } 1698 1699 imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1700 if (IS_ERR(imx_data->clk_ahb)) { 1701 err = PTR_ERR(imx_data->clk_ahb); 1702 goto free_sdhci; 1703 } 1704 1705 imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 1706 if (IS_ERR(imx_data->clk_per)) { 1707 err = PTR_ERR(imx_data->clk_per); 1708 goto free_sdhci; 1709 } 1710 1711 pltfm_host->clk = imx_data->clk_per; 1712 err = clk_prepare_enable(imx_data->clk_per); 1713 if (err) 1714 goto free_sdhci; 1715 err = clk_prepare_enable(imx_data->clk_ipg); 1716 if (err) 1717 goto disable_per_clk; 1718 err = clk_prepare_enable(imx_data->clk_ahb); 1719 if (err) 1720 goto disable_ipg_clk; 1721 1722 pltfm_host->clock = clk_get_rate(pltfm_host->clk); 1723 if (!pltfm_host->clock) { 1724 dev_err(mmc_dev(host->mmc), "could not get clk rate\n"); 1725 err = -EINVAL; 1726 goto disable_ahb_clk; 1727 } 1728 1729 imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1730 if (IS_ERR(imx_data->pinctrl)) 1731 dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1732 1733 if (esdhc_is_usdhc(imx_data)) { 1734 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 1735 host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1736 1737 /* GPIO CD can be set as a wakeup source */ 1738 if (!(imx_data->socdata->flags & ESDHC_FLAG_SKIP_CD_WAKE)) 1739 host->mmc->caps |= MMC_CAP_CD_WAKE; 1740 1741 if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 1742 host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1743 1744 /* clear tuning bits in case ROM has set it already */ 1745 writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1746 writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1747 writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1748 1749 /* 1750 * Link usdhc specific mmc_host_ops execute_tuning function, 1751 * to replace the standard one in sdhci_ops. 1752 */ 1753 host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 1754 1755 /* 1756 * Link usdhc specific mmc_host_ops init card function, 1757 * to distinguish the card type. 1758 */ 1759 host->mmc_host_ops.init_card = usdhc_init_card; 1760 } 1761 1762 if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 1763 sdhci_esdhc_ops.platform_execute_tuning = 1764 esdhc_executing_tuning; 1765 1766 if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 1767 host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 1768 1769 if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 1770 host->mmc->caps2 |= MMC_CAP2_HS400; 1771 1772 if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) 1773 host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; 1774 1775 if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1776 host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1777 host->mmc_host_ops.hs400_enhanced_strobe = 1778 esdhc_hs400_enhanced_strobe; 1779 } 1780 1781 if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1782 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1783 cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 1784 if (!cq_host) { 1785 err = -ENOMEM; 1786 goto disable_ahb_clk; 1787 } 1788 1789 cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1790 cq_host->ops = &esdhc_cqhci_ops; 1791 1792 err = cqhci_init(cq_host, host->mmc, false); 1793 if (err) 1794 goto disable_ahb_clk; 1795 } 1796 1797 err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 1798 if (err) 1799 goto disable_ahb_clk; 1800 1801 sdhci_esdhc_imx_hwinit(host); 1802 1803 err = sdhci_add_host(host); 1804 if (err) 1805 goto disable_ahb_clk; 1806 1807 /* 1808 * Setup the wakeup capability here, let user to decide 1809 * whether need to enable this wakeup through sysfs interface. 1810 */ 1811 if ((host->mmc->pm_caps & MMC_PM_KEEP_POWER) && 1812 (host->mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ)) 1813 device_set_wakeup_capable(&pdev->dev, true); 1814 1815 pm_runtime_set_active(&pdev->dev); 1816 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1817 pm_runtime_use_autosuspend(&pdev->dev); 1818 pm_suspend_ignore_children(&pdev->dev, 1); 1819 pm_runtime_enable(&pdev->dev); 1820 1821 return 0; 1822 1823 disable_ahb_clk: 1824 clk_disable_unprepare(imx_data->clk_ahb); 1825 disable_ipg_clk: 1826 clk_disable_unprepare(imx_data->clk_ipg); 1827 disable_per_clk: 1828 clk_disable_unprepare(imx_data->clk_per); 1829 free_sdhci: 1830 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1831 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1832 sdhci_pltfm_free(pdev); 1833 return err; 1834 } 1835 1836 static void sdhci_esdhc_imx_remove(struct platform_device *pdev) 1837 { 1838 struct sdhci_host *host = platform_get_drvdata(pdev); 1839 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1840 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1841 int dead; 1842 1843 pm_runtime_get_sync(&pdev->dev); 1844 dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 1845 pm_runtime_disable(&pdev->dev); 1846 pm_runtime_put_noidle(&pdev->dev); 1847 1848 sdhci_remove_host(host, dead); 1849 1850 clk_disable_unprepare(imx_data->clk_per); 1851 clk_disable_unprepare(imx_data->clk_ipg); 1852 clk_disable_unprepare(imx_data->clk_ahb); 1853 1854 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1855 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1856 1857 sdhci_pltfm_free(pdev); 1858 } 1859 1860 #ifdef CONFIG_PM_SLEEP 1861 static int sdhci_esdhc_suspend(struct device *dev) 1862 { 1863 struct sdhci_host *host = dev_get_drvdata(dev); 1864 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1865 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1866 int ret; 1867 1868 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1869 ret = cqhci_suspend(host->mmc); 1870 if (ret) 1871 return ret; 1872 } 1873 1874 if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 1875 (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 1876 mmc_retune_timer_stop(host->mmc); 1877 mmc_retune_needed(host->mmc); 1878 } 1879 1880 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1881 mmc_retune_needed(host->mmc); 1882 1883 ret = sdhci_suspend_host(host); 1884 if (ret) 1885 return ret; 1886 1887 ret = pinctrl_pm_select_sleep_state(dev); 1888 if (ret) 1889 return ret; 1890 1891 ret = mmc_gpio_set_cd_wake(host->mmc, true); 1892 1893 return ret; 1894 } 1895 1896 static int sdhci_esdhc_resume(struct device *dev) 1897 { 1898 struct sdhci_host *host = dev_get_drvdata(dev); 1899 int ret; 1900 1901 ret = pinctrl_pm_select_default_state(dev); 1902 if (ret) 1903 return ret; 1904 1905 /* re-initialize hw state in case it's lost in low power mode */ 1906 sdhci_esdhc_imx_hwinit(host); 1907 1908 ret = sdhci_resume_host(host); 1909 if (ret) 1910 return ret; 1911 1912 if (host->mmc->caps2 & MMC_CAP2_CQE) 1913 ret = cqhci_resume(host->mmc); 1914 1915 if (!ret) 1916 ret = mmc_gpio_set_cd_wake(host->mmc, false); 1917 1918 return ret; 1919 } 1920 #endif 1921 1922 #ifdef CONFIG_PM 1923 static int sdhci_esdhc_runtime_suspend(struct device *dev) 1924 { 1925 struct sdhci_host *host = dev_get_drvdata(dev); 1926 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1927 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1928 int ret; 1929 1930 if (host->mmc->caps2 & MMC_CAP2_CQE) { 1931 ret = cqhci_suspend(host->mmc); 1932 if (ret) 1933 return ret; 1934 } 1935 1936 ret = sdhci_runtime_suspend_host(host); 1937 if (ret) 1938 return ret; 1939 1940 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1941 mmc_retune_needed(host->mmc); 1942 1943 imx_data->actual_clock = host->mmc->actual_clock; 1944 esdhc_pltfm_set_clock(host, 0); 1945 clk_disable_unprepare(imx_data->clk_per); 1946 clk_disable_unprepare(imx_data->clk_ipg); 1947 clk_disable_unprepare(imx_data->clk_ahb); 1948 1949 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1950 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 1951 1952 return ret; 1953 } 1954 1955 static int sdhci_esdhc_runtime_resume(struct device *dev) 1956 { 1957 struct sdhci_host *host = dev_get_drvdata(dev); 1958 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1959 struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1960 int err; 1961 1962 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1963 cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 1964 1965 if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 1966 clk_set_rate(imx_data->clk_per, pltfm_host->clock); 1967 1968 err = clk_prepare_enable(imx_data->clk_ahb); 1969 if (err) 1970 goto remove_pm_qos_request; 1971 1972 err = clk_prepare_enable(imx_data->clk_per); 1973 if (err) 1974 goto disable_ahb_clk; 1975 1976 err = clk_prepare_enable(imx_data->clk_ipg); 1977 if (err) 1978 goto disable_per_clk; 1979 1980 esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1981 1982 err = sdhci_runtime_resume_host(host, 0); 1983 if (err) 1984 goto disable_ipg_clk; 1985 1986 if (host->mmc->caps2 & MMC_CAP2_CQE) 1987 err = cqhci_resume(host->mmc); 1988 1989 return err; 1990 1991 disable_ipg_clk: 1992 clk_disable_unprepare(imx_data->clk_ipg); 1993 disable_per_clk: 1994 clk_disable_unprepare(imx_data->clk_per); 1995 disable_ahb_clk: 1996 clk_disable_unprepare(imx_data->clk_ahb); 1997 remove_pm_qos_request: 1998 if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1999 cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 2000 return err; 2001 } 2002 #endif 2003 2004 static const struct dev_pm_ops sdhci_esdhc_pmops = { 2005 SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 2006 SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 2007 sdhci_esdhc_runtime_resume, NULL) 2008 }; 2009 2010 static struct platform_driver sdhci_esdhc_imx_driver = { 2011 .driver = { 2012 .name = "sdhci-esdhc-imx", 2013 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2014 .of_match_table = imx_esdhc_dt_ids, 2015 .pm = &sdhci_esdhc_pmops, 2016 }, 2017 .probe = sdhci_esdhc_imx_probe, 2018 .remove_new = sdhci_esdhc_imx_remove, 2019 }; 2020 2021 module_platform_driver(sdhci_esdhc_imx_driver); 2022 2023 MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 2024 MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 2025 MODULE_LICENSE("GPL v2"); 2026