195f25efeSWolfram Sang /* 295f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 395f25efeSWolfram Sang * 495f25efeSWolfram Sang * derived from the OF-version. 595f25efeSWolfram Sang * 695f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 795f25efeSWolfram Sang * Author: Wolfram Sang <w.sang@pengutronix.de> 895f25efeSWolfram Sang * 995f25efeSWolfram Sang * This program is free software; you can redistribute it and/or modify 1095f25efeSWolfram Sang * it under the terms of the GNU General Public License as published by 1195f25efeSWolfram Sang * the Free Software Foundation; either version 2 of the License. 1295f25efeSWolfram Sang */ 1395f25efeSWolfram Sang 1495f25efeSWolfram Sang #include <linux/io.h> 1595f25efeSWolfram Sang #include <linux/delay.h> 1695f25efeSWolfram Sang #include <linux/err.h> 1795f25efeSWolfram Sang #include <linux/clk.h> 180c6d49ceSWolfram Sang #include <linux/gpio.h> 1966506f76SShawn Guo #include <linux/module.h> 20e149860dSRichard Zhu #include <linux/slab.h> 2195f25efeSWolfram Sang #include <linux/mmc/host.h> 2258ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2358ac8177SRichard Zhu #include <linux/mmc/sdio.h> 24abfafc2dSShawn Guo #include <linux/of.h> 25abfafc2dSShawn Guo #include <linux/of_device.h> 26abfafc2dSShawn Guo #include <linux/of_gpio.h> 27e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 28*82906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 2995f25efeSWolfram Sang #include "sdhci-pltfm.h" 3095f25efeSWolfram Sang #include "sdhci-esdhc.h" 3195f25efeSWolfram Sang 320d58864bSTony Lin #define SDHCI_CTRL_D3CD 0x08 3358ac8177SRichard Zhu /* VENDOR SPEC register */ 3458ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC 0xC0 3558ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC_SDIO_QUIRK 0x00000002 36f750ba9bSShawn Guo #define SDHCI_WTMK_LVL 0x44 3795a2482aSShawn Guo #define SDHCI_MIX_CTRL 0x48 3858ac8177SRichard Zhu 3958ac8177SRichard Zhu /* 4097e4ba6aSRichard Zhu * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC: 4197e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 4297e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 4397e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 4497e4ba6aSRichard Zhu */ 4597e4ba6aSRichard Zhu #define SDHCI_INT_VENDOR_SPEC_DMA_ERR 0x10000000 4697e4ba6aSRichard Zhu 4797e4ba6aSRichard Zhu /* 4858ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 4958ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 5058ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 5158ac8177SRichard Zhu * be generated. 5258ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 5358ac8177SRichard Zhu * operations automatically as required at the end of the 5458ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 5558ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 5658ac8177SRichard Zhu * exeception. Bit1 of Vendor Spec registor is used to fix it. 5758ac8177SRichard Zhu */ 5858ac8177SRichard Zhu #define ESDHC_FLAG_MULTIBLK_NO_INT (1 << 1) 59e149860dSRichard Zhu 6057ed3314SShawn Guo enum imx_esdhc_type { 6157ed3314SShawn Guo IMX25_ESDHC, 6257ed3314SShawn Guo IMX35_ESDHC, 6357ed3314SShawn Guo IMX51_ESDHC, 6457ed3314SShawn Guo IMX53_ESDHC, 6595a2482aSShawn Guo IMX6Q_USDHC, 6657ed3314SShawn Guo }; 6757ed3314SShawn Guo 68e149860dSRichard Zhu struct pltfm_imx_data { 69e149860dSRichard Zhu int flags; 70e149860dSRichard Zhu u32 scratchpad; 7157ed3314SShawn Guo enum imx_esdhc_type devtype; 72e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 73842afc02SShawn Guo struct esdhc_platform_data boarddata; 7452dac615SSascha Hauer struct clk *clk_ipg; 7552dac615SSascha Hauer struct clk *clk_ahb; 7652dac615SSascha Hauer struct clk *clk_per; 77e149860dSRichard Zhu }; 78e149860dSRichard Zhu 7957ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = { 8057ed3314SShawn Guo { 8157ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 8257ed3314SShawn Guo .driver_data = IMX25_ESDHC, 8357ed3314SShawn Guo }, { 8457ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 8557ed3314SShawn Guo .driver_data = IMX35_ESDHC, 8657ed3314SShawn Guo }, { 8757ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 8857ed3314SShawn Guo .driver_data = IMX51_ESDHC, 8957ed3314SShawn Guo }, { 9057ed3314SShawn Guo .name = "sdhci-esdhc-imx53", 9157ed3314SShawn Guo .driver_data = IMX53_ESDHC, 9257ed3314SShawn Guo }, { 9395a2482aSShawn Guo .name = "sdhci-usdhc-imx6q", 9495a2482aSShawn Guo .driver_data = IMX6Q_USDHC, 9595a2482aSShawn Guo }, { 9657ed3314SShawn Guo /* sentinel */ 9757ed3314SShawn Guo } 9857ed3314SShawn Guo }; 9957ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 10057ed3314SShawn Guo 101abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 102abfafc2dSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], }, 103abfafc2dSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], }, 104abfafc2dSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], }, 105abfafc2dSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], }, 10695a2482aSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], }, 107abfafc2dSShawn Guo { /* sentinel */ } 108abfafc2dSShawn Guo }; 109abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 110abfafc2dSShawn Guo 11157ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 11257ed3314SShawn Guo { 11357ed3314SShawn Guo return data->devtype == IMX25_ESDHC; 11457ed3314SShawn Guo } 11557ed3314SShawn Guo 11657ed3314SShawn Guo static inline int is_imx35_esdhc(struct pltfm_imx_data *data) 11757ed3314SShawn Guo { 11857ed3314SShawn Guo return data->devtype == IMX35_ESDHC; 11957ed3314SShawn Guo } 12057ed3314SShawn Guo 12157ed3314SShawn Guo static inline int is_imx51_esdhc(struct pltfm_imx_data *data) 12257ed3314SShawn Guo { 12357ed3314SShawn Guo return data->devtype == IMX51_ESDHC; 12457ed3314SShawn Guo } 12557ed3314SShawn Guo 12657ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 12757ed3314SShawn Guo { 12857ed3314SShawn Guo return data->devtype == IMX53_ESDHC; 12957ed3314SShawn Guo } 13057ed3314SShawn Guo 13195a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 13295a2482aSShawn Guo { 13395a2482aSShawn Guo return data->devtype == IMX6Q_USDHC; 13495a2482aSShawn Guo } 13595a2482aSShawn Guo 13695f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 13795f25efeSWolfram Sang { 13895f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 13995f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 14095f25efeSWolfram Sang 14195f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 14295f25efeSWolfram Sang } 14395f25efeSWolfram Sang 1447e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 1457e29c306SWolfram Sang { 146842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 147842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 148842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1497e29c306SWolfram Sang 150913413c3SShawn Guo /* fake CARD_PRESENT flag */ 151913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 152913413c3SShawn Guo 153913413c3SShawn Guo if (unlikely((reg == SDHCI_PRESENT_STATE) 154913413c3SShawn Guo && gpio_is_valid(boarddata->cd_gpio))) { 155913413c3SShawn Guo if (gpio_get_value(boarddata->cd_gpio)) 1567e29c306SWolfram Sang /* no card, if a valid gpio says so... */ 157803862a6SShawn Guo val &= ~SDHCI_CARD_PRESENT; 1587e29c306SWolfram Sang else 1597e29c306SWolfram Sang /* ... in all other cases assume card is present */ 1607e29c306SWolfram Sang val |= SDHCI_CARD_PRESENT; 1617e29c306SWolfram Sang } 1627e29c306SWolfram Sang 16397e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 16497e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 16597e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 16697e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 16797e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 16897e4ba6aSRichard Zhu * uirk on MX25/35 platforms. 16997e4ba6aSRichard Zhu */ 17097e4ba6aSRichard Zhu 17197e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 17297e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 17397e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 17497e4ba6aSRichard Zhu } 17597e4ba6aSRichard Zhu } 17697e4ba6aSRichard Zhu 17797e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 17897e4ba6aSRichard Zhu if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) { 17997e4ba6aSRichard Zhu val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR; 18097e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 18197e4ba6aSRichard Zhu } 18297e4ba6aSRichard Zhu } 18397e4ba6aSRichard Zhu 1847e29c306SWolfram Sang return val; 1857e29c306SWolfram Sang } 1867e29c306SWolfram Sang 1877e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 1887e29c306SWolfram Sang { 189e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 190e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 191842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1920d58864bSTony Lin u32 data; 193e149860dSRichard Zhu 1940d58864bSTony Lin if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 1950d58864bSTony Lin if (boarddata->cd_type == ESDHC_CD_GPIO) 1967e29c306SWolfram Sang /* 1970d58864bSTony Lin * These interrupts won't work with a custom 1980d58864bSTony Lin * card_detect gpio (only applied to mx25/35) 1997e29c306SWolfram Sang */ 2007e29c306SWolfram Sang val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); 2017e29c306SWolfram Sang 2020d58864bSTony Lin if (val & SDHCI_INT_CARD_INT) { 2030d58864bSTony Lin /* 2040d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 2050d58864bSTony Lin * card interrupt. This is a eSDHC controller problem 2060d58864bSTony Lin * so we need to apply the following workaround: clear 2070d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 2080d58864bSTony Lin * interrupt. In case a card interrupt was lost, 2090d58864bSTony Lin * re-sample it by the following steps. 2100d58864bSTony Lin */ 2110d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 2120d58864bSTony Lin data &= ~SDHCI_CTRL_D3CD; 2130d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 2140d58864bSTony Lin data |= SDHCI_CTRL_D3CD; 2150d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 2160d58864bSTony Lin } 2170d58864bSTony Lin } 2180d58864bSTony Lin 21958ac8177SRichard Zhu if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 22058ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 22158ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 22258ac8177SRichard Zhu u32 v; 22358ac8177SRichard Zhu v = readl(host->ioaddr + SDHCI_VENDOR_SPEC); 22458ac8177SRichard Zhu v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK; 22558ac8177SRichard Zhu writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); 22658ac8177SRichard Zhu } 22758ac8177SRichard Zhu 22897e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) { 22997e4ba6aSRichard Zhu if (val & SDHCI_INT_ADMA_ERROR) { 23097e4ba6aSRichard Zhu val &= ~SDHCI_INT_ADMA_ERROR; 23197e4ba6aSRichard Zhu val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR; 23297e4ba6aSRichard Zhu } 23397e4ba6aSRichard Zhu } 23497e4ba6aSRichard Zhu 2357e29c306SWolfram Sang writel(val, host->ioaddr + reg); 2367e29c306SWolfram Sang } 2377e29c306SWolfram Sang 23895f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 23995f25efeSWolfram Sang { 24095a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 24195a2482aSShawn Guo u16 val = readw(host->ioaddr + (reg ^ 2)); 24295a2482aSShawn Guo /* 24395a2482aSShawn Guo * uSDHC supports SDHCI v3.0, but it's encoded as value 24495a2482aSShawn Guo * 0x3 in host controller version register, which violates 24595a2482aSShawn Guo * SDHCI_SPEC_300 definition. Work it around here. 24695a2482aSShawn Guo */ 24795a2482aSShawn Guo if ((val & SDHCI_SPEC_VER_MASK) == 3) 24895a2482aSShawn Guo return --val; 24995a2482aSShawn Guo } 25095f25efeSWolfram Sang 25195f25efeSWolfram Sang return readw(host->ioaddr + reg); 25295f25efeSWolfram Sang } 25395f25efeSWolfram Sang 25495f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 25595f25efeSWolfram Sang { 25695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 257e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 25895f25efeSWolfram Sang 25995f25efeSWolfram Sang switch (reg) { 26095f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 26195f25efeSWolfram Sang /* 26295f25efeSWolfram Sang * Postpone this write, we must do it together with a 26395f25efeSWolfram Sang * command write that is down below. 26495f25efeSWolfram Sang */ 26558ac8177SRichard Zhu if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 26658ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 26758ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 26858ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 26958ac8177SRichard Zhu u32 v; 27058ac8177SRichard Zhu v = readl(host->ioaddr + SDHCI_VENDOR_SPEC); 27158ac8177SRichard Zhu v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK; 27258ac8177SRichard Zhu writel(v, host->ioaddr + SDHCI_VENDOR_SPEC); 27358ac8177SRichard Zhu } 274e149860dSRichard Zhu imx_data->scratchpad = val; 27595f25efeSWolfram Sang return; 27695f25efeSWolfram Sang case SDHCI_COMMAND: 2775b6b0ad6SSascha Hauer if ((host->cmd->opcode == MMC_STOP_TRANSMISSION || 2785b6b0ad6SSascha Hauer host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 2795b6b0ad6SSascha Hauer (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 28058ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 28195a2482aSShawn Guo 28295a2482aSShawn Guo if (is_imx6q_usdhc(imx_data)) { 28395a2482aSShawn Guo u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL); 28495a2482aSShawn Guo m = imx_data->scratchpad | (m & 0xffff0000); 28595a2482aSShawn Guo writel(m, host->ioaddr + SDHCI_MIX_CTRL); 28695a2482aSShawn Guo writel(val << 16, 28795a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 28895a2482aSShawn Guo } else { 289e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 29095f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 29195a2482aSShawn Guo } 29295f25efeSWolfram Sang return; 29395f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 29495f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 29595f25efeSWolfram Sang break; 29695f25efeSWolfram Sang } 29795f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 29895f25efeSWolfram Sang } 29995f25efeSWolfram Sang 30095f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 30195f25efeSWolfram Sang { 3029a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3039a0985b7SWilson Callan struct pltfm_imx_data *imx_data = pltfm_host->priv; 30495f25efeSWolfram Sang u32 new_val; 30595f25efeSWolfram Sang 30695f25efeSWolfram Sang switch (reg) { 30795f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 30895f25efeSWolfram Sang /* 30995f25efeSWolfram Sang * FSL put some DMA bits here 31095f25efeSWolfram Sang * If your board has a regulator, code should be here 31195f25efeSWolfram Sang */ 31295f25efeSWolfram Sang return; 31395f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 3140d58864bSTony Lin /* FSL messed up here, so we can just keep those three */ 3150d58864bSTony Lin new_val = val & (SDHCI_CTRL_LED | \ 3160d58864bSTony Lin SDHCI_CTRL_4BITBUS | \ 3170d58864bSTony Lin SDHCI_CTRL_D3CD); 31895f25efeSWolfram Sang /* ensure the endianess */ 31995f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 3209a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 3219a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 32295f25efeSWolfram Sang /* DMA mode bits are shifted */ 32395f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 3249a0985b7SWilson Callan } 32595f25efeSWolfram Sang 32695f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, new_val, reg); 32795f25efeSWolfram Sang return; 32895f25efeSWolfram Sang } 32995f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 330913413c3SShawn Guo 331913413c3SShawn Guo /* 332913413c3SShawn Guo * The esdhc has a design violation to SDHC spec which tells 333913413c3SShawn Guo * that software reset should not affect card detection circuit. 334913413c3SShawn Guo * But esdhc clears its SYSCTL register bits [0..2] during the 335913413c3SShawn Guo * software reset. This will stop those clocks that card detection 336913413c3SShawn Guo * circuit relies on. To work around it, we turn the clocks on back 337913413c3SShawn Guo * to keep card detection circuit functional. 338913413c3SShawn Guo */ 339913413c3SShawn Guo if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1)) 340913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 34195f25efeSWolfram Sang } 34295f25efeSWolfram Sang 34395f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 34495f25efeSWolfram Sang { 34595f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 34695f25efeSWolfram Sang 34795f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk); 34895f25efeSWolfram Sang } 34995f25efeSWolfram Sang 35095f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 35195f25efeSWolfram Sang { 35295f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 35395f25efeSWolfram Sang 35495f25efeSWolfram Sang return clk_get_rate(pltfm_host->clk) / 256 / 16; 35595f25efeSWolfram Sang } 35695f25efeSWolfram Sang 357913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 358913413c3SShawn Guo { 359842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 360842afc02SShawn Guo struct pltfm_imx_data *imx_data = pltfm_host->priv; 361842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 362913413c3SShawn Guo 363913413c3SShawn Guo switch (boarddata->wp_type) { 364913413c3SShawn Guo case ESDHC_WP_GPIO: 365913413c3SShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 366913413c3SShawn Guo return gpio_get_value(boarddata->wp_gpio); 367913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 368913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 369913413c3SShawn Guo SDHCI_WRITE_PROTECT); 370913413c3SShawn Guo case ESDHC_WP_NONE: 371913413c3SShawn Guo break; 372913413c3SShawn Guo } 373913413c3SShawn Guo 374913413c3SShawn Guo return -ENOSYS; 375913413c3SShawn Guo } 376913413c3SShawn Guo 3770c6d49ceSWolfram Sang static struct sdhci_ops sdhci_esdhc_ops = { 378e149860dSRichard Zhu .read_l = esdhc_readl_le, 3790c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 380e149860dSRichard Zhu .write_l = esdhc_writel_le, 3810c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 3820c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 3830c6d49ceSWolfram Sang .set_clock = esdhc_set_clock, 3840c6d49ceSWolfram Sang .get_max_clock = esdhc_pltfm_get_max_clock, 3850c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 386913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 3870c6d49ceSWolfram Sang }; 3880c6d49ceSWolfram Sang 38985d6509dSShawn Guo static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 39097e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 39197e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 39297e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 39385d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 39485d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 39585d6509dSShawn Guo }; 39685d6509dSShawn Guo 3977e29c306SWolfram Sang static irqreturn_t cd_irq(int irq, void *data) 3987e29c306SWolfram Sang { 3997e29c306SWolfram Sang struct sdhci_host *sdhost = (struct sdhci_host *)data; 4007e29c306SWolfram Sang 4017e29c306SWolfram Sang tasklet_schedule(&sdhost->card_tasklet); 4027e29c306SWolfram Sang return IRQ_HANDLED; 4037e29c306SWolfram Sang }; 4047e29c306SWolfram Sang 405abfafc2dSShawn Guo #ifdef CONFIG_OF 406abfafc2dSShawn Guo static int __devinit 407abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 408abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 409abfafc2dSShawn Guo { 410abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 411abfafc2dSShawn Guo 412abfafc2dSShawn Guo if (!np) 413abfafc2dSShawn Guo return -ENODEV; 414abfafc2dSShawn Guo 4157f217794SArnd Bergmann if (of_get_property(np, "non-removable", NULL)) 416abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_PERMANENT; 417abfafc2dSShawn Guo 418abfafc2dSShawn Guo if (of_get_property(np, "fsl,cd-controller", NULL)) 419abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_CONTROLLER; 420abfafc2dSShawn Guo 421abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 422abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 423abfafc2dSShawn Guo 424abfafc2dSShawn Guo boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0); 425abfafc2dSShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 426abfafc2dSShawn Guo boarddata->cd_type = ESDHC_CD_GPIO; 427abfafc2dSShawn Guo 428abfafc2dSShawn Guo boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0); 429abfafc2dSShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 430abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 431abfafc2dSShawn Guo 432abfafc2dSShawn Guo return 0; 433abfafc2dSShawn Guo } 434abfafc2dSShawn Guo #else 435abfafc2dSShawn Guo static inline int 436abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 437abfafc2dSShawn Guo struct esdhc_platform_data *boarddata) 438abfafc2dSShawn Guo { 439abfafc2dSShawn Guo return -ENODEV; 440abfafc2dSShawn Guo } 441abfafc2dSShawn Guo #endif 442abfafc2dSShawn Guo 44385d6509dSShawn Guo static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev) 44495f25efeSWolfram Sang { 445abfafc2dSShawn Guo const struct of_device_id *of_id = 446abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 44785d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 44885d6509dSShawn Guo struct sdhci_host *host; 44985d6509dSShawn Guo struct esdhc_platform_data *boarddata; 4500c6d49ceSWolfram Sang int err; 451e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 45295f25efeSWolfram Sang 45385d6509dSShawn Guo host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata); 45485d6509dSShawn Guo if (IS_ERR(host)) 45585d6509dSShawn Guo return PTR_ERR(host); 45685d6509dSShawn Guo 45785d6509dSShawn Guo pltfm_host = sdhci_priv(host); 45885d6509dSShawn Guo 45985d6509dSShawn Guo imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL); 460abfafc2dSShawn Guo if (!imx_data) { 461abfafc2dSShawn Guo err = -ENOMEM; 462abfafc2dSShawn Guo goto err_imx_data; 463abfafc2dSShawn Guo } 46457ed3314SShawn Guo 465abfafc2dSShawn Guo if (of_id) 466abfafc2dSShawn Guo pdev->id_entry = of_id->data; 46757ed3314SShawn Guo imx_data->devtype = pdev->id_entry->driver_data; 46885d6509dSShawn Guo pltfm_host->priv = imx_data; 46985d6509dSShawn Guo 47052dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 47152dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 47252dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 47385d6509dSShawn Guo goto err_clk_get; 47495f25efeSWolfram Sang } 47552dac615SSascha Hauer 47652dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 47752dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 47852dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 47952dac615SSascha Hauer goto err_clk_get; 48052dac615SSascha Hauer } 48152dac615SSascha Hauer 48252dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 48352dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 48452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 48552dac615SSascha Hauer goto err_clk_get; 48652dac615SSascha Hauer } 48752dac615SSascha Hauer 48852dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 48952dac615SSascha Hauer 49052dac615SSascha Hauer clk_prepare_enable(imx_data->clk_per); 49152dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ipg); 49252dac615SSascha Hauer clk_prepare_enable(imx_data->clk_ahb); 49395f25efeSWolfram Sang 494e62d8b8fSDong Aisheng imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 495e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 496e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 497e62d8b8fSDong Aisheng goto pin_err; 498e62d8b8fSDong Aisheng } 499e62d8b8fSDong Aisheng 50037865fe9SEric Bénard host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 50137865fe9SEric Bénard 50257ed3314SShawn Guo if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) 5030c6d49ceSWolfram Sang /* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */ 50497e4ba6aSRichard Zhu host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK 50597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA; 5060c6d49ceSWolfram Sang 50757ed3314SShawn Guo if (is_imx53_esdhc(imx_data)) 50858ac8177SRichard Zhu imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT; 50958ac8177SRichard Zhu 510f750ba9bSShawn Guo /* 511f750ba9bSShawn Guo * The imx6q ROM code will change the default watermark level setting 512f750ba9bSShawn Guo * to something insane. Change it back here. 513f750ba9bSShawn Guo */ 514f750ba9bSShawn Guo if (is_imx6q_usdhc(imx_data)) 515f750ba9bSShawn Guo writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL); 516f750ba9bSShawn Guo 517abfafc2dSShawn Guo boarddata = &imx_data->boarddata; 518abfafc2dSShawn Guo if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) { 519842afc02SShawn Guo if (!host->mmc->parent->platform_data) { 520913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "no board data!\n"); 521913413c3SShawn Guo err = -EINVAL; 522913413c3SShawn Guo goto no_board_data; 523913413c3SShawn Guo } 524842afc02SShawn Guo imx_data->boarddata = *((struct esdhc_platform_data *) 525842afc02SShawn Guo host->mmc->parent->platform_data); 526abfafc2dSShawn Guo } 527913413c3SShawn Guo 528913413c3SShawn Guo /* write_protect */ 529913413c3SShawn Guo if (boarddata->wp_type == ESDHC_WP_GPIO) { 5300c6d49ceSWolfram Sang err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP"); 5310c6d49ceSWolfram Sang if (err) { 5320c6d49ceSWolfram Sang dev_warn(mmc_dev(host->mmc), 5330c6d49ceSWolfram Sang "no write-protect pin available!\n"); 534913413c3SShawn Guo boarddata->wp_gpio = -EINVAL; 535913413c3SShawn Guo } 536913413c3SShawn Guo } else { 537913413c3SShawn Guo boarddata->wp_gpio = -EINVAL; 5380c6d49ceSWolfram Sang } 5397e29c306SWolfram Sang 540913413c3SShawn Guo /* card_detect */ 541913413c3SShawn Guo if (boarddata->cd_type != ESDHC_CD_GPIO) 542913413c3SShawn Guo boarddata->cd_gpio = -EINVAL; 543913413c3SShawn Guo 544913413c3SShawn Guo switch (boarddata->cd_type) { 545913413c3SShawn Guo case ESDHC_CD_GPIO: 5467e29c306SWolfram Sang err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD"); 5477e29c306SWolfram Sang if (err) { 548913413c3SShawn Guo dev_err(mmc_dev(host->mmc), 5497e29c306SWolfram Sang "no card-detect pin available!\n"); 5507e29c306SWolfram Sang goto no_card_detect_pin; 5510c6d49ceSWolfram Sang } 55216a790bcSEric Bénard 5537e29c306SWolfram Sang err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq, 5547e29c306SWolfram Sang IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, 5557e29c306SWolfram Sang mmc_hostname(host->mmc), host); 5567e29c306SWolfram Sang if (err) { 557913413c3SShawn Guo dev_err(mmc_dev(host->mmc), "request irq error\n"); 5587e29c306SWolfram Sang goto no_card_detect_irq; 5597e29c306SWolfram Sang } 560913413c3SShawn Guo /* fall through */ 5617e29c306SWolfram Sang 562913413c3SShawn Guo case ESDHC_CD_CONTROLLER: 563913413c3SShawn Guo /* we have a working card_detect back */ 5647e29c306SWolfram Sang host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 565913413c3SShawn Guo break; 566913413c3SShawn Guo 567913413c3SShawn Guo case ESDHC_CD_PERMANENT: 568913413c3SShawn Guo host->mmc->caps = MMC_CAP_NONREMOVABLE; 569913413c3SShawn Guo break; 570913413c3SShawn Guo 571913413c3SShawn Guo case ESDHC_CD_NONE: 572913413c3SShawn Guo break; 5737e29c306SWolfram Sang } 5747e29c306SWolfram Sang 57585d6509dSShawn Guo err = sdhci_add_host(host); 57685d6509dSShawn Guo if (err) 57785d6509dSShawn Guo goto err_add_host; 57885d6509dSShawn Guo 5797e29c306SWolfram Sang return 0; 5807e29c306SWolfram Sang 58185d6509dSShawn Guo err_add_host: 582913413c3SShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 583913413c3SShawn Guo free_irq(gpio_to_irq(boarddata->cd_gpio), host); 584913413c3SShawn Guo no_card_detect_irq: 585913413c3SShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) 586913413c3SShawn Guo gpio_free(boarddata->cd_gpio); 587913413c3SShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 588913413c3SShawn Guo gpio_free(boarddata->wp_gpio); 589913413c3SShawn Guo no_card_detect_pin: 590913413c3SShawn Guo no_board_data: 591e62d8b8fSDong Aisheng pin_err: 59252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 59352dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 59452dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 59585d6509dSShawn Guo err_clk_get: 596913413c3SShawn Guo kfree(imx_data); 597abfafc2dSShawn Guo err_imx_data: 59885d6509dSShawn Guo sdhci_pltfm_free(pdev); 59985d6509dSShawn Guo return err; 60095f25efeSWolfram Sang } 60195f25efeSWolfram Sang 60285d6509dSShawn Guo static int __devexit sdhci_esdhc_imx_remove(struct platform_device *pdev) 60395f25efeSWolfram Sang { 60485d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 60595f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 606e149860dSRichard Zhu struct pltfm_imx_data *imx_data = pltfm_host->priv; 607842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 60885d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 60985d6509dSShawn Guo 61085d6509dSShawn Guo sdhci_remove_host(host, dead); 6110c6d49ceSWolfram Sang 612913413c3SShawn Guo if (gpio_is_valid(boarddata->wp_gpio)) 6130c6d49ceSWolfram Sang gpio_free(boarddata->wp_gpio); 61495f25efeSWolfram Sang 615913413c3SShawn Guo if (gpio_is_valid(boarddata->cd_gpio)) { 6167e29c306SWolfram Sang free_irq(gpio_to_irq(boarddata->cd_gpio), host); 617913413c3SShawn Guo gpio_free(boarddata->cd_gpio); 6187e29c306SWolfram Sang } 6197e29c306SWolfram Sang 62052dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 62152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 62252dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 62352dac615SSascha Hauer 624e149860dSRichard Zhu kfree(imx_data); 62585d6509dSShawn Guo 62685d6509dSShawn Guo sdhci_pltfm_free(pdev); 62785d6509dSShawn Guo 62885d6509dSShawn Guo return 0; 62995f25efeSWolfram Sang } 63095f25efeSWolfram Sang 63185d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 63285d6509dSShawn Guo .driver = { 63385d6509dSShawn Guo .name = "sdhci-esdhc-imx", 63485d6509dSShawn Guo .owner = THIS_MODULE, 635abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 63629495aa0SManuel Lauss .pm = SDHCI_PLTFM_PMOPS, 63785d6509dSShawn Guo }, 63857ed3314SShawn Guo .id_table = imx_esdhc_devtype, 63985d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 64085d6509dSShawn Guo .remove = __devexit_p(sdhci_esdhc_imx_remove), 64195f25efeSWolfram Sang }; 64285d6509dSShawn Guo 643d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 64485d6509dSShawn Guo 64585d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 64685d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>"); 64785d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 648