xref: /linux/drivers/mmc/host/sdhci-esdhc-imx.c (revision 5b6b0ad6e572b32a641116aaa5f897ffebe31e44)
195f25efeSWolfram Sang /*
295f25efeSWolfram Sang  * Freescale eSDHC i.MX controller driver for the platform bus.
395f25efeSWolfram Sang  *
495f25efeSWolfram Sang  * derived from the OF-version.
595f25efeSWolfram Sang  *
695f25efeSWolfram Sang  * Copyright (c) 2010 Pengutronix e.K.
795f25efeSWolfram Sang  *   Author: Wolfram Sang <w.sang@pengutronix.de>
895f25efeSWolfram Sang  *
995f25efeSWolfram Sang  * This program is free software; you can redistribute it and/or modify
1095f25efeSWolfram Sang  * it under the terms of the GNU General Public License as published by
1195f25efeSWolfram Sang  * the Free Software Foundation; either version 2 of the License.
1295f25efeSWolfram Sang  */
1395f25efeSWolfram Sang 
1495f25efeSWolfram Sang #include <linux/io.h>
1595f25efeSWolfram Sang #include <linux/delay.h>
1695f25efeSWolfram Sang #include <linux/err.h>
1795f25efeSWolfram Sang #include <linux/clk.h>
180c6d49ceSWolfram Sang #include <linux/gpio.h>
1966506f76SShawn Guo #include <linux/module.h>
20e149860dSRichard Zhu #include <linux/slab.h>
2195f25efeSWolfram Sang #include <linux/mmc/host.h>
2258ac8177SRichard Zhu #include <linux/mmc/mmc.h>
2358ac8177SRichard Zhu #include <linux/mmc/sdio.h>
24abfafc2dSShawn Guo #include <linux/of.h>
25abfafc2dSShawn Guo #include <linux/of_device.h>
26abfafc2dSShawn Guo #include <linux/of_gpio.h>
270c6d49ceSWolfram Sang #include <mach/esdhc.h>
2895f25efeSWolfram Sang #include "sdhci-pltfm.h"
2995f25efeSWolfram Sang #include "sdhci-esdhc.h"
3095f25efeSWolfram Sang 
310d58864bSTony Lin #define	SDHCI_CTRL_D3CD			0x08
3258ac8177SRichard Zhu /* VENDOR SPEC register */
3358ac8177SRichard Zhu #define SDHCI_VENDOR_SPEC		0xC0
3458ac8177SRichard Zhu #define  SDHCI_VENDOR_SPEC_SDIO_QUIRK	0x00000002
35f750ba9bSShawn Guo #define SDHCI_WTMK_LVL			0x44
3695a2482aSShawn Guo #define SDHCI_MIX_CTRL			0x48
3758ac8177SRichard Zhu 
3858ac8177SRichard Zhu /*
3997e4ba6aSRichard Zhu  * There is an INT DMA ERR mis-match between eSDHC and STD SDHC SPEC:
4097e4ba6aSRichard Zhu  * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design,
4197e4ba6aSRichard Zhu  * but bit28 is used as the INT DMA ERR in fsl eSDHC design.
4297e4ba6aSRichard Zhu  * Define this macro DMA error INT for fsl eSDHC
4397e4ba6aSRichard Zhu  */
4497e4ba6aSRichard Zhu #define SDHCI_INT_VENDOR_SPEC_DMA_ERR	0x10000000
4597e4ba6aSRichard Zhu 
4697e4ba6aSRichard Zhu /*
4758ac8177SRichard Zhu  * The CMDTYPE of the CMD register (offset 0xE) should be set to
4858ac8177SRichard Zhu  * "11" when the STOP CMD12 is issued on imx53 to abort one
4958ac8177SRichard Zhu  * open ended multi-blk IO. Otherwise the TC INT wouldn't
5058ac8177SRichard Zhu  * be generated.
5158ac8177SRichard Zhu  * In exact block transfer, the controller doesn't complete the
5258ac8177SRichard Zhu  * operations automatically as required at the end of the
5358ac8177SRichard Zhu  * transfer and remains on hold if the abort command is not sent.
5458ac8177SRichard Zhu  * As a result, the TC flag is not asserted and SW  received timeout
5558ac8177SRichard Zhu  * exeception. Bit1 of Vendor Spec registor is used to fix it.
5658ac8177SRichard Zhu  */
5758ac8177SRichard Zhu #define ESDHC_FLAG_MULTIBLK_NO_INT	(1 << 1)
58e149860dSRichard Zhu 
5957ed3314SShawn Guo enum imx_esdhc_type {
6057ed3314SShawn Guo 	IMX25_ESDHC,
6157ed3314SShawn Guo 	IMX35_ESDHC,
6257ed3314SShawn Guo 	IMX51_ESDHC,
6357ed3314SShawn Guo 	IMX53_ESDHC,
6495a2482aSShawn Guo 	IMX6Q_USDHC,
6557ed3314SShawn Guo };
6657ed3314SShawn Guo 
67e149860dSRichard Zhu struct pltfm_imx_data {
68e149860dSRichard Zhu 	int flags;
69e149860dSRichard Zhu 	u32 scratchpad;
7057ed3314SShawn Guo 	enum imx_esdhc_type devtype;
71842afc02SShawn Guo 	struct esdhc_platform_data boarddata;
72e149860dSRichard Zhu };
73e149860dSRichard Zhu 
7457ed3314SShawn Guo static struct platform_device_id imx_esdhc_devtype[] = {
7557ed3314SShawn Guo 	{
7657ed3314SShawn Guo 		.name = "sdhci-esdhc-imx25",
7757ed3314SShawn Guo 		.driver_data = IMX25_ESDHC,
7857ed3314SShawn Guo 	}, {
7957ed3314SShawn Guo 		.name = "sdhci-esdhc-imx35",
8057ed3314SShawn Guo 		.driver_data = IMX35_ESDHC,
8157ed3314SShawn Guo 	}, {
8257ed3314SShawn Guo 		.name = "sdhci-esdhc-imx51",
8357ed3314SShawn Guo 		.driver_data = IMX51_ESDHC,
8457ed3314SShawn Guo 	}, {
8557ed3314SShawn Guo 		.name = "sdhci-esdhc-imx53",
8657ed3314SShawn Guo 		.driver_data = IMX53_ESDHC,
8757ed3314SShawn Guo 	}, {
8895a2482aSShawn Guo 		.name = "sdhci-usdhc-imx6q",
8995a2482aSShawn Guo 		.driver_data = IMX6Q_USDHC,
9095a2482aSShawn Guo 	}, {
9157ed3314SShawn Guo 		/* sentinel */
9257ed3314SShawn Guo 	}
9357ed3314SShawn Guo };
9457ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype);
9557ed3314SShawn Guo 
96abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = {
97abfafc2dSShawn Guo 	{ .compatible = "fsl,imx25-esdhc", .data = &imx_esdhc_devtype[IMX25_ESDHC], },
98abfafc2dSShawn Guo 	{ .compatible = "fsl,imx35-esdhc", .data = &imx_esdhc_devtype[IMX35_ESDHC], },
99abfafc2dSShawn Guo 	{ .compatible = "fsl,imx51-esdhc", .data = &imx_esdhc_devtype[IMX51_ESDHC], },
100abfafc2dSShawn Guo 	{ .compatible = "fsl,imx53-esdhc", .data = &imx_esdhc_devtype[IMX53_ESDHC], },
10195a2482aSShawn Guo 	{ .compatible = "fsl,imx6q-usdhc", .data = &imx_esdhc_devtype[IMX6Q_USDHC], },
102abfafc2dSShawn Guo 	{ /* sentinel */ }
103abfafc2dSShawn Guo };
104abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids);
105abfafc2dSShawn Guo 
10657ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data)
10757ed3314SShawn Guo {
10857ed3314SShawn Guo 	return data->devtype == IMX25_ESDHC;
10957ed3314SShawn Guo }
11057ed3314SShawn Guo 
11157ed3314SShawn Guo static inline int is_imx35_esdhc(struct pltfm_imx_data *data)
11257ed3314SShawn Guo {
11357ed3314SShawn Guo 	return data->devtype == IMX35_ESDHC;
11457ed3314SShawn Guo }
11557ed3314SShawn Guo 
11657ed3314SShawn Guo static inline int is_imx51_esdhc(struct pltfm_imx_data *data)
11757ed3314SShawn Guo {
11857ed3314SShawn Guo 	return data->devtype == IMX51_ESDHC;
11957ed3314SShawn Guo }
12057ed3314SShawn Guo 
12157ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data)
12257ed3314SShawn Guo {
12357ed3314SShawn Guo 	return data->devtype == IMX53_ESDHC;
12457ed3314SShawn Guo }
12557ed3314SShawn Guo 
12695a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data)
12795a2482aSShawn Guo {
12895a2482aSShawn Guo 	return data->devtype == IMX6Q_USDHC;
12995a2482aSShawn Guo }
13095a2482aSShawn Guo 
13195f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg)
13295f25efeSWolfram Sang {
13395f25efeSWolfram Sang 	void __iomem *base = host->ioaddr + (reg & ~0x3);
13495f25efeSWolfram Sang 	u32 shift = (reg & 0x3) * 8;
13595f25efeSWolfram Sang 
13695f25efeSWolfram Sang 	writel(((readl(base) & ~(mask << shift)) | (val << shift)), base);
13795f25efeSWolfram Sang }
13895f25efeSWolfram Sang 
1397e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
1407e29c306SWolfram Sang {
141842afc02SShawn Guo 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
142842afc02SShawn Guo 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
143842afc02SShawn Guo 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1447e29c306SWolfram Sang 
145913413c3SShawn Guo 	/* fake CARD_PRESENT flag */
146913413c3SShawn Guo 	u32 val = readl(host->ioaddr + reg);
147913413c3SShawn Guo 
148913413c3SShawn Guo 	if (unlikely((reg == SDHCI_PRESENT_STATE)
149913413c3SShawn Guo 			&& gpio_is_valid(boarddata->cd_gpio))) {
150913413c3SShawn Guo 		if (gpio_get_value(boarddata->cd_gpio))
1517e29c306SWolfram Sang 			/* no card, if a valid gpio says so... */
152803862a6SShawn Guo 			val &= ~SDHCI_CARD_PRESENT;
1537e29c306SWolfram Sang 		else
1547e29c306SWolfram Sang 			/* ... in all other cases assume card is present */
1557e29c306SWolfram Sang 			val |= SDHCI_CARD_PRESENT;
1567e29c306SWolfram Sang 	}
1577e29c306SWolfram Sang 
15897e4ba6aSRichard Zhu 	if (unlikely(reg == SDHCI_CAPABILITIES)) {
15997e4ba6aSRichard Zhu 		/* In FSL esdhc IC module, only bit20 is used to indicate the
16097e4ba6aSRichard Zhu 		 * ADMA2 capability of esdhc, but this bit is messed up on
16197e4ba6aSRichard Zhu 		 * some SOCs (e.g. on MX25, MX35 this bit is set, but they
16297e4ba6aSRichard Zhu 		 * don't actually support ADMA2). So set the BROKEN_ADMA
16397e4ba6aSRichard Zhu 		 * uirk on MX25/35 platforms.
16497e4ba6aSRichard Zhu 		 */
16597e4ba6aSRichard Zhu 
16697e4ba6aSRichard Zhu 		if (val & SDHCI_CAN_DO_ADMA1) {
16797e4ba6aSRichard Zhu 			val &= ~SDHCI_CAN_DO_ADMA1;
16897e4ba6aSRichard Zhu 			val |= SDHCI_CAN_DO_ADMA2;
16997e4ba6aSRichard Zhu 		}
17097e4ba6aSRichard Zhu 	}
17197e4ba6aSRichard Zhu 
17297e4ba6aSRichard Zhu 	if (unlikely(reg == SDHCI_INT_STATUS)) {
17397e4ba6aSRichard Zhu 		if (val & SDHCI_INT_VENDOR_SPEC_DMA_ERR) {
17497e4ba6aSRichard Zhu 			val &= ~SDHCI_INT_VENDOR_SPEC_DMA_ERR;
17597e4ba6aSRichard Zhu 			val |= SDHCI_INT_ADMA_ERROR;
17697e4ba6aSRichard Zhu 		}
17797e4ba6aSRichard Zhu 	}
17897e4ba6aSRichard Zhu 
1797e29c306SWolfram Sang 	return val;
1807e29c306SWolfram Sang }
1817e29c306SWolfram Sang 
1827e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
1837e29c306SWolfram Sang {
184e149860dSRichard Zhu 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
185e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
186842afc02SShawn Guo 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
1870d58864bSTony Lin 	u32 data;
188e149860dSRichard Zhu 
1890d58864bSTony Lin 	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
1900d58864bSTony Lin 		if (boarddata->cd_type == ESDHC_CD_GPIO)
1917e29c306SWolfram Sang 			/*
1920d58864bSTony Lin 			 * These interrupts won't work with a custom
1930d58864bSTony Lin 			 * card_detect gpio (only applied to mx25/35)
1947e29c306SWolfram Sang 			 */
1957e29c306SWolfram Sang 			val &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT);
1967e29c306SWolfram Sang 
1970d58864bSTony Lin 		if (val & SDHCI_INT_CARD_INT) {
1980d58864bSTony Lin 			/*
1990d58864bSTony Lin 			 * Clear and then set D3CD bit to avoid missing the
2000d58864bSTony Lin 			 * card interrupt.  This is a eSDHC controller problem
2010d58864bSTony Lin 			 * so we need to apply the following workaround: clear
2020d58864bSTony Lin 			 * and set D3CD bit will make eSDHC re-sample the card
2030d58864bSTony Lin 			 * interrupt. In case a card interrupt was lost,
2040d58864bSTony Lin 			 * re-sample it by the following steps.
2050d58864bSTony Lin 			 */
2060d58864bSTony Lin 			data = readl(host->ioaddr + SDHCI_HOST_CONTROL);
2070d58864bSTony Lin 			data &= ~SDHCI_CTRL_D3CD;
2080d58864bSTony Lin 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
2090d58864bSTony Lin 			data |= SDHCI_CTRL_D3CD;
2100d58864bSTony Lin 			writel(data, host->ioaddr + SDHCI_HOST_CONTROL);
2110d58864bSTony Lin 		}
2120d58864bSTony Lin 	}
2130d58864bSTony Lin 
21458ac8177SRichard Zhu 	if (unlikely((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
21558ac8177SRichard Zhu 				&& (reg == SDHCI_INT_STATUS)
21658ac8177SRichard Zhu 				&& (val & SDHCI_INT_DATA_END))) {
21758ac8177SRichard Zhu 			u32 v;
21858ac8177SRichard Zhu 			v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
21958ac8177SRichard Zhu 			v &= ~SDHCI_VENDOR_SPEC_SDIO_QUIRK;
22058ac8177SRichard Zhu 			writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
22158ac8177SRichard Zhu 	}
22258ac8177SRichard Zhu 
22397e4ba6aSRichard Zhu 	if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
22497e4ba6aSRichard Zhu 		if (val & SDHCI_INT_ADMA_ERROR) {
22597e4ba6aSRichard Zhu 			val &= ~SDHCI_INT_ADMA_ERROR;
22697e4ba6aSRichard Zhu 			val |= SDHCI_INT_VENDOR_SPEC_DMA_ERR;
22797e4ba6aSRichard Zhu 		}
22897e4ba6aSRichard Zhu 	}
22997e4ba6aSRichard Zhu 
2307e29c306SWolfram Sang 	writel(val, host->ioaddr + reg);
2317e29c306SWolfram Sang }
2327e29c306SWolfram Sang 
23395f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg)
23495f25efeSWolfram Sang {
23595a2482aSShawn Guo 	if (unlikely(reg == SDHCI_HOST_VERSION)) {
23695a2482aSShawn Guo 		u16 val = readw(host->ioaddr + (reg ^ 2));
23795a2482aSShawn Guo 		/*
23895a2482aSShawn Guo 		 * uSDHC supports SDHCI v3.0, but it's encoded as value
23995a2482aSShawn Guo 		 * 0x3 in host controller version register, which violates
24095a2482aSShawn Guo 		 * SDHCI_SPEC_300 definition.  Work it around here.
24195a2482aSShawn Guo 		 */
24295a2482aSShawn Guo 		if ((val & SDHCI_SPEC_VER_MASK) == 3)
24395a2482aSShawn Guo 			return --val;
24495a2482aSShawn Guo 	}
24595f25efeSWolfram Sang 
24695f25efeSWolfram Sang 	return readw(host->ioaddr + reg);
24795f25efeSWolfram Sang }
24895f25efeSWolfram Sang 
24995f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
25095f25efeSWolfram Sang {
25195f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
252e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
25395f25efeSWolfram Sang 
25495f25efeSWolfram Sang 	switch (reg) {
25595f25efeSWolfram Sang 	case SDHCI_TRANSFER_MODE:
25695f25efeSWolfram Sang 		/*
25795f25efeSWolfram Sang 		 * Postpone this write, we must do it together with a
25895f25efeSWolfram Sang 		 * command write that is down below.
25995f25efeSWolfram Sang 		 */
26058ac8177SRichard Zhu 		if ((imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT)
26158ac8177SRichard Zhu 				&& (host->cmd->opcode == SD_IO_RW_EXTENDED)
26258ac8177SRichard Zhu 				&& (host->cmd->data->blocks > 1)
26358ac8177SRichard Zhu 				&& (host->cmd->data->flags & MMC_DATA_READ)) {
26458ac8177SRichard Zhu 			u32 v;
26558ac8177SRichard Zhu 			v = readl(host->ioaddr + SDHCI_VENDOR_SPEC);
26658ac8177SRichard Zhu 			v |= SDHCI_VENDOR_SPEC_SDIO_QUIRK;
26758ac8177SRichard Zhu 			writel(v, host->ioaddr + SDHCI_VENDOR_SPEC);
26858ac8177SRichard Zhu 		}
269e149860dSRichard Zhu 		imx_data->scratchpad = val;
27095f25efeSWolfram Sang 		return;
27195f25efeSWolfram Sang 	case SDHCI_COMMAND:
272*5b6b0ad6SSascha Hauer 		if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
273*5b6b0ad6SSascha Hauer 		     host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
274*5b6b0ad6SSascha Hauer 	            (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
27558ac8177SRichard Zhu 			val |= SDHCI_CMD_ABORTCMD;
27695a2482aSShawn Guo 
27795a2482aSShawn Guo 		if (is_imx6q_usdhc(imx_data)) {
27895a2482aSShawn Guo 			u32 m = readl(host->ioaddr + SDHCI_MIX_CTRL);
27995a2482aSShawn Guo 			m = imx_data->scratchpad | (m & 0xffff0000);
28095a2482aSShawn Guo 			writel(m, host->ioaddr + SDHCI_MIX_CTRL);
28195a2482aSShawn Guo 			writel(val << 16,
28295a2482aSShawn Guo 			       host->ioaddr + SDHCI_TRANSFER_MODE);
28395a2482aSShawn Guo 		} else {
284e149860dSRichard Zhu 			writel(val << 16 | imx_data->scratchpad,
28595f25efeSWolfram Sang 			       host->ioaddr + SDHCI_TRANSFER_MODE);
28695a2482aSShawn Guo 		}
28795f25efeSWolfram Sang 		return;
28895f25efeSWolfram Sang 	case SDHCI_BLOCK_SIZE:
28995f25efeSWolfram Sang 		val &= ~SDHCI_MAKE_BLKSZ(0x7, 0);
29095f25efeSWolfram Sang 		break;
29195f25efeSWolfram Sang 	}
29295f25efeSWolfram Sang 	esdhc_clrset_le(host, 0xffff, val, reg);
29395f25efeSWolfram Sang }
29495f25efeSWolfram Sang 
29595f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
29695f25efeSWolfram Sang {
29795f25efeSWolfram Sang 	u32 new_val;
29895f25efeSWolfram Sang 
29995f25efeSWolfram Sang 	switch (reg) {
30095f25efeSWolfram Sang 	case SDHCI_POWER_CONTROL:
30195f25efeSWolfram Sang 		/*
30295f25efeSWolfram Sang 		 * FSL put some DMA bits here
30395f25efeSWolfram Sang 		 * If your board has a regulator, code should be here
30495f25efeSWolfram Sang 		 */
30595f25efeSWolfram Sang 		return;
30695f25efeSWolfram Sang 	case SDHCI_HOST_CONTROL:
3070d58864bSTony Lin 		/* FSL messed up here, so we can just keep those three */
3080d58864bSTony Lin 		new_val = val & (SDHCI_CTRL_LED | \
3090d58864bSTony Lin 				SDHCI_CTRL_4BITBUS | \
3100d58864bSTony Lin 				SDHCI_CTRL_D3CD);
31195f25efeSWolfram Sang 		/* ensure the endianess */
31295f25efeSWolfram Sang 		new_val |= ESDHC_HOST_CONTROL_LE;
31395f25efeSWolfram Sang 		/* DMA mode bits are shifted */
31495f25efeSWolfram Sang 		new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5;
31595f25efeSWolfram Sang 
31695f25efeSWolfram Sang 		esdhc_clrset_le(host, 0xffff, new_val, reg);
31795f25efeSWolfram Sang 		return;
31895f25efeSWolfram Sang 	}
31995f25efeSWolfram Sang 	esdhc_clrset_le(host, 0xff, val, reg);
320913413c3SShawn Guo 
321913413c3SShawn Guo 	/*
322913413c3SShawn Guo 	 * The esdhc has a design violation to SDHC spec which tells
323913413c3SShawn Guo 	 * that software reset should not affect card detection circuit.
324913413c3SShawn Guo 	 * But esdhc clears its SYSCTL register bits [0..2] during the
325913413c3SShawn Guo 	 * software reset.  This will stop those clocks that card detection
326913413c3SShawn Guo 	 * circuit relies on.  To work around it, we turn the clocks on back
327913413c3SShawn Guo 	 * to keep card detection circuit functional.
328913413c3SShawn Guo 	 */
329913413c3SShawn Guo 	if ((reg == SDHCI_SOFTWARE_RESET) && (val & 1))
330913413c3SShawn Guo 		esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL);
33195f25efeSWolfram Sang }
33295f25efeSWolfram Sang 
33395f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host)
33495f25efeSWolfram Sang {
33595f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
33695f25efeSWolfram Sang 
33795f25efeSWolfram Sang 	return clk_get_rate(pltfm_host->clk);
33895f25efeSWolfram Sang }
33995f25efeSWolfram Sang 
34095f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host)
34195f25efeSWolfram Sang {
34295f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
34395f25efeSWolfram Sang 
34495f25efeSWolfram Sang 	return clk_get_rate(pltfm_host->clk) / 256 / 16;
34595f25efeSWolfram Sang }
34695f25efeSWolfram Sang 
347913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host)
348913413c3SShawn Guo {
349842afc02SShawn Guo 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
350842afc02SShawn Guo 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
351842afc02SShawn Guo 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
352913413c3SShawn Guo 
353913413c3SShawn Guo 	switch (boarddata->wp_type) {
354913413c3SShawn Guo 	case ESDHC_WP_GPIO:
355913413c3SShawn Guo 		if (gpio_is_valid(boarddata->wp_gpio))
356913413c3SShawn Guo 			return gpio_get_value(boarddata->wp_gpio);
357913413c3SShawn Guo 	case ESDHC_WP_CONTROLLER:
358913413c3SShawn Guo 		return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) &
359913413c3SShawn Guo 			       SDHCI_WRITE_PROTECT);
360913413c3SShawn Guo 	case ESDHC_WP_NONE:
361913413c3SShawn Guo 		break;
362913413c3SShawn Guo 	}
363913413c3SShawn Guo 
364913413c3SShawn Guo 	return -ENOSYS;
365913413c3SShawn Guo }
366913413c3SShawn Guo 
3670c6d49ceSWolfram Sang static struct sdhci_ops sdhci_esdhc_ops = {
368e149860dSRichard Zhu 	.read_l = esdhc_readl_le,
3690c6d49ceSWolfram Sang 	.read_w = esdhc_readw_le,
370e149860dSRichard Zhu 	.write_l = esdhc_writel_le,
3710c6d49ceSWolfram Sang 	.write_w = esdhc_writew_le,
3720c6d49ceSWolfram Sang 	.write_b = esdhc_writeb_le,
3730c6d49ceSWolfram Sang 	.set_clock = esdhc_set_clock,
3740c6d49ceSWolfram Sang 	.get_max_clock = esdhc_pltfm_get_max_clock,
3750c6d49ceSWolfram Sang 	.get_min_clock = esdhc_pltfm_get_min_clock,
376913413c3SShawn Guo 	.get_ro = esdhc_pltfm_get_ro,
3770c6d49ceSWolfram Sang };
3780c6d49ceSWolfram Sang 
37985d6509dSShawn Guo static struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = {
38097e4ba6aSRichard Zhu 	.quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT
38197e4ba6aSRichard Zhu 			| SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
38297e4ba6aSRichard Zhu 			| SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC
38385d6509dSShawn Guo 			| SDHCI_QUIRK_BROKEN_CARD_DETECTION,
38485d6509dSShawn Guo 	.ops = &sdhci_esdhc_ops,
38585d6509dSShawn Guo };
38685d6509dSShawn Guo 
3877e29c306SWolfram Sang static irqreturn_t cd_irq(int irq, void *data)
3887e29c306SWolfram Sang {
3897e29c306SWolfram Sang 	struct sdhci_host *sdhost = (struct sdhci_host *)data;
3907e29c306SWolfram Sang 
3917e29c306SWolfram Sang 	tasklet_schedule(&sdhost->card_tasklet);
3927e29c306SWolfram Sang 	return IRQ_HANDLED;
3937e29c306SWolfram Sang };
3947e29c306SWolfram Sang 
395abfafc2dSShawn Guo #ifdef CONFIG_OF
396abfafc2dSShawn Guo static int __devinit
397abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
398abfafc2dSShawn Guo 			 struct esdhc_platform_data *boarddata)
399abfafc2dSShawn Guo {
400abfafc2dSShawn Guo 	struct device_node *np = pdev->dev.of_node;
401abfafc2dSShawn Guo 
402abfafc2dSShawn Guo 	if (!np)
403abfafc2dSShawn Guo 		return -ENODEV;
404abfafc2dSShawn Guo 
405abfafc2dSShawn Guo 	if (of_get_property(np, "fsl,card-wired", NULL))
406abfafc2dSShawn Guo 		boarddata->cd_type = ESDHC_CD_PERMANENT;
407abfafc2dSShawn Guo 
408abfafc2dSShawn Guo 	if (of_get_property(np, "fsl,cd-controller", NULL))
409abfafc2dSShawn Guo 		boarddata->cd_type = ESDHC_CD_CONTROLLER;
410abfafc2dSShawn Guo 
411abfafc2dSShawn Guo 	if (of_get_property(np, "fsl,wp-controller", NULL))
412abfafc2dSShawn Guo 		boarddata->wp_type = ESDHC_WP_CONTROLLER;
413abfafc2dSShawn Guo 
414abfafc2dSShawn Guo 	boarddata->cd_gpio = of_get_named_gpio(np, "cd-gpios", 0);
415abfafc2dSShawn Guo 	if (gpio_is_valid(boarddata->cd_gpio))
416abfafc2dSShawn Guo 		boarddata->cd_type = ESDHC_CD_GPIO;
417abfafc2dSShawn Guo 
418abfafc2dSShawn Guo 	boarddata->wp_gpio = of_get_named_gpio(np, "wp-gpios", 0);
419abfafc2dSShawn Guo 	if (gpio_is_valid(boarddata->wp_gpio))
420abfafc2dSShawn Guo 		boarddata->wp_type = ESDHC_WP_GPIO;
421abfafc2dSShawn Guo 
422abfafc2dSShawn Guo 	return 0;
423abfafc2dSShawn Guo }
424abfafc2dSShawn Guo #else
425abfafc2dSShawn Guo static inline int
426abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev,
427abfafc2dSShawn Guo 			 struct esdhc_platform_data *boarddata)
428abfafc2dSShawn Guo {
429abfafc2dSShawn Guo 	return -ENODEV;
430abfafc2dSShawn Guo }
431abfafc2dSShawn Guo #endif
432abfafc2dSShawn Guo 
43385d6509dSShawn Guo static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev)
43495f25efeSWolfram Sang {
435abfafc2dSShawn Guo 	const struct of_device_id *of_id =
436abfafc2dSShawn Guo 			of_match_device(imx_esdhc_dt_ids, &pdev->dev);
43785d6509dSShawn Guo 	struct sdhci_pltfm_host *pltfm_host;
43885d6509dSShawn Guo 	struct sdhci_host *host;
43985d6509dSShawn Guo 	struct esdhc_platform_data *boarddata;
44095f25efeSWolfram Sang 	struct clk *clk;
4410c6d49ceSWolfram Sang 	int err;
442e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data;
44395f25efeSWolfram Sang 
44485d6509dSShawn Guo 	host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata);
44585d6509dSShawn Guo 	if (IS_ERR(host))
44685d6509dSShawn Guo 		return PTR_ERR(host);
44785d6509dSShawn Guo 
44885d6509dSShawn Guo 	pltfm_host = sdhci_priv(host);
44985d6509dSShawn Guo 
45085d6509dSShawn Guo 	imx_data = kzalloc(sizeof(struct pltfm_imx_data), GFP_KERNEL);
451abfafc2dSShawn Guo 	if (!imx_data) {
452abfafc2dSShawn Guo 		err = -ENOMEM;
453abfafc2dSShawn Guo 		goto err_imx_data;
454abfafc2dSShawn Guo 	}
45557ed3314SShawn Guo 
456abfafc2dSShawn Guo 	if (of_id)
457abfafc2dSShawn Guo 		pdev->id_entry = of_id->data;
45857ed3314SShawn Guo 	imx_data->devtype = pdev->id_entry->driver_data;
45985d6509dSShawn Guo 	pltfm_host->priv = imx_data;
46085d6509dSShawn Guo 
46195f25efeSWolfram Sang 	clk = clk_get(mmc_dev(host->mmc), NULL);
46295f25efeSWolfram Sang 	if (IS_ERR(clk)) {
46395f25efeSWolfram Sang 		dev_err(mmc_dev(host->mmc), "clk err\n");
46485d6509dSShawn Guo 		err = PTR_ERR(clk);
46585d6509dSShawn Guo 		goto err_clk_get;
46695f25efeSWolfram Sang 	}
46795f25efeSWolfram Sang 	clk_enable(clk);
46895f25efeSWolfram Sang 	pltfm_host->clk = clk;
46995f25efeSWolfram Sang 
47057ed3314SShawn Guo 	if (!is_imx25_esdhc(imx_data))
47137865fe9SEric Bénard 		host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
47237865fe9SEric Bénard 
47357ed3314SShawn Guo 	if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data))
4740c6d49ceSWolfram Sang 		/* Fix errata ENGcm07207 present on i.MX25 and i.MX35 */
47597e4ba6aSRichard Zhu 		host->quirks |= SDHCI_QUIRK_NO_MULTIBLOCK
47697e4ba6aSRichard Zhu 			| SDHCI_QUIRK_BROKEN_ADMA;
4770c6d49ceSWolfram Sang 
47857ed3314SShawn Guo 	if (is_imx53_esdhc(imx_data))
47958ac8177SRichard Zhu 		imx_data->flags |= ESDHC_FLAG_MULTIBLK_NO_INT;
48058ac8177SRichard Zhu 
481f750ba9bSShawn Guo 	/*
482f750ba9bSShawn Guo 	 * The imx6q ROM code will change the default watermark level setting
483f750ba9bSShawn Guo 	 * to something insane.  Change it back here.
484f750ba9bSShawn Guo 	 */
485f750ba9bSShawn Guo 	if (is_imx6q_usdhc(imx_data))
486f750ba9bSShawn Guo 		writel(0x08100810, host->ioaddr + SDHCI_WTMK_LVL);
487f750ba9bSShawn Guo 
488abfafc2dSShawn Guo 	boarddata = &imx_data->boarddata;
489abfafc2dSShawn Guo 	if (sdhci_esdhc_imx_probe_dt(pdev, boarddata) < 0) {
490842afc02SShawn Guo 		if (!host->mmc->parent->platform_data) {
491913413c3SShawn Guo 			dev_err(mmc_dev(host->mmc), "no board data!\n");
492913413c3SShawn Guo 			err = -EINVAL;
493913413c3SShawn Guo 			goto no_board_data;
494913413c3SShawn Guo 		}
495842afc02SShawn Guo 		imx_data->boarddata = *((struct esdhc_platform_data *)
496842afc02SShawn Guo 					host->mmc->parent->platform_data);
497abfafc2dSShawn Guo 	}
498913413c3SShawn Guo 
499913413c3SShawn Guo 	/* write_protect */
500913413c3SShawn Guo 	if (boarddata->wp_type == ESDHC_WP_GPIO) {
5010c6d49ceSWolfram Sang 		err = gpio_request_one(boarddata->wp_gpio, GPIOF_IN, "ESDHC_WP");
5020c6d49ceSWolfram Sang 		if (err) {
5030c6d49ceSWolfram Sang 			dev_warn(mmc_dev(host->mmc),
5040c6d49ceSWolfram Sang 				 "no write-protect pin available!\n");
505913413c3SShawn Guo 			boarddata->wp_gpio = -EINVAL;
506913413c3SShawn Guo 		}
507913413c3SShawn Guo 	} else {
508913413c3SShawn Guo 		boarddata->wp_gpio = -EINVAL;
5090c6d49ceSWolfram Sang 	}
5107e29c306SWolfram Sang 
511913413c3SShawn Guo 	/* card_detect */
512913413c3SShawn Guo 	if (boarddata->cd_type != ESDHC_CD_GPIO)
513913413c3SShawn Guo 		boarddata->cd_gpio = -EINVAL;
514913413c3SShawn Guo 
515913413c3SShawn Guo 	switch (boarddata->cd_type) {
516913413c3SShawn Guo 	case ESDHC_CD_GPIO:
5177e29c306SWolfram Sang 		err = gpio_request_one(boarddata->cd_gpio, GPIOF_IN, "ESDHC_CD");
5187e29c306SWolfram Sang 		if (err) {
519913413c3SShawn Guo 			dev_err(mmc_dev(host->mmc),
5207e29c306SWolfram Sang 				"no card-detect pin available!\n");
5217e29c306SWolfram Sang 			goto no_card_detect_pin;
5220c6d49ceSWolfram Sang 		}
52316a790bcSEric Bénard 
5247e29c306SWolfram Sang 		err = request_irq(gpio_to_irq(boarddata->cd_gpio), cd_irq,
5257e29c306SWolfram Sang 				 IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
5267e29c306SWolfram Sang 				 mmc_hostname(host->mmc), host);
5277e29c306SWolfram Sang 		if (err) {
528913413c3SShawn Guo 			dev_err(mmc_dev(host->mmc), "request irq error\n");
5297e29c306SWolfram Sang 			goto no_card_detect_irq;
5307e29c306SWolfram Sang 		}
531913413c3SShawn Guo 		/* fall through */
5327e29c306SWolfram Sang 
533913413c3SShawn Guo 	case ESDHC_CD_CONTROLLER:
534913413c3SShawn Guo 		/* we have a working card_detect back */
5357e29c306SWolfram Sang 		host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION;
536913413c3SShawn Guo 		break;
537913413c3SShawn Guo 
538913413c3SShawn Guo 	case ESDHC_CD_PERMANENT:
539913413c3SShawn Guo 		host->mmc->caps = MMC_CAP_NONREMOVABLE;
540913413c3SShawn Guo 		break;
541913413c3SShawn Guo 
542913413c3SShawn Guo 	case ESDHC_CD_NONE:
543913413c3SShawn Guo 		break;
5447e29c306SWolfram Sang 	}
5457e29c306SWolfram Sang 
54685d6509dSShawn Guo 	err = sdhci_add_host(host);
54785d6509dSShawn Guo 	if (err)
54885d6509dSShawn Guo 		goto err_add_host;
54985d6509dSShawn Guo 
5507e29c306SWolfram Sang 	return 0;
5517e29c306SWolfram Sang 
55285d6509dSShawn Guo err_add_host:
553913413c3SShawn Guo 	if (gpio_is_valid(boarddata->cd_gpio))
554913413c3SShawn Guo 		free_irq(gpio_to_irq(boarddata->cd_gpio), host);
555913413c3SShawn Guo no_card_detect_irq:
556913413c3SShawn Guo 	if (gpio_is_valid(boarddata->cd_gpio))
557913413c3SShawn Guo 		gpio_free(boarddata->cd_gpio);
558913413c3SShawn Guo 	if (gpio_is_valid(boarddata->wp_gpio))
559913413c3SShawn Guo 		gpio_free(boarddata->wp_gpio);
560913413c3SShawn Guo no_card_detect_pin:
561913413c3SShawn Guo no_board_data:
56285d6509dSShawn Guo 	clk_disable(pltfm_host->clk);
56385d6509dSShawn Guo 	clk_put(pltfm_host->clk);
56485d6509dSShawn Guo err_clk_get:
565913413c3SShawn Guo 	kfree(imx_data);
566abfafc2dSShawn Guo err_imx_data:
56785d6509dSShawn Guo 	sdhci_pltfm_free(pdev);
56885d6509dSShawn Guo 	return err;
56995f25efeSWolfram Sang }
57095f25efeSWolfram Sang 
57185d6509dSShawn Guo static int __devexit sdhci_esdhc_imx_remove(struct platform_device *pdev)
57295f25efeSWolfram Sang {
57385d6509dSShawn Guo 	struct sdhci_host *host = platform_get_drvdata(pdev);
57495f25efeSWolfram Sang 	struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
575e149860dSRichard Zhu 	struct pltfm_imx_data *imx_data = pltfm_host->priv;
576842afc02SShawn Guo 	struct esdhc_platform_data *boarddata = &imx_data->boarddata;
57785d6509dSShawn Guo 	int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff);
57885d6509dSShawn Guo 
57985d6509dSShawn Guo 	sdhci_remove_host(host, dead);
5800c6d49ceSWolfram Sang 
581913413c3SShawn Guo 	if (gpio_is_valid(boarddata->wp_gpio))
5820c6d49ceSWolfram Sang 		gpio_free(boarddata->wp_gpio);
58395f25efeSWolfram Sang 
584913413c3SShawn Guo 	if (gpio_is_valid(boarddata->cd_gpio)) {
5857e29c306SWolfram Sang 		free_irq(gpio_to_irq(boarddata->cd_gpio), host);
586913413c3SShawn Guo 		gpio_free(boarddata->cd_gpio);
5877e29c306SWolfram Sang 	}
5887e29c306SWolfram Sang 
58995f25efeSWolfram Sang 	clk_disable(pltfm_host->clk);
59095f25efeSWolfram Sang 	clk_put(pltfm_host->clk);
591e149860dSRichard Zhu 	kfree(imx_data);
59285d6509dSShawn Guo 
59385d6509dSShawn Guo 	sdhci_pltfm_free(pdev);
59485d6509dSShawn Guo 
59585d6509dSShawn Guo 	return 0;
59695f25efeSWolfram Sang }
59795f25efeSWolfram Sang 
59885d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = {
59985d6509dSShawn Guo 	.driver		= {
60085d6509dSShawn Guo 		.name	= "sdhci-esdhc-imx",
60185d6509dSShawn Guo 		.owner	= THIS_MODULE,
602abfafc2dSShawn Guo 		.of_match_table = imx_esdhc_dt_ids,
60329495aa0SManuel Lauss 		.pm	= SDHCI_PLTFM_PMOPS,
60485d6509dSShawn Guo 	},
60557ed3314SShawn Guo 	.id_table	= imx_esdhc_devtype,
60685d6509dSShawn Guo 	.probe		= sdhci_esdhc_imx_probe,
60785d6509dSShawn Guo 	.remove		= __devexit_p(sdhci_esdhc_imx_remove),
60895f25efeSWolfram Sang };
60985d6509dSShawn Guo 
610d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver);
61185d6509dSShawn Guo 
61285d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC");
61385d6509dSShawn Guo MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
61485d6509dSShawn Guo MODULE_LICENSE("GPL v2");
615