1a6e7e407SFabio Estevam // SPDX-License-Identifier: GPL-2.0 295f25efeSWolfram Sang /* 395f25efeSWolfram Sang * Freescale eSDHC i.MX controller driver for the platform bus. 495f25efeSWolfram Sang * 595f25efeSWolfram Sang * derived from the OF-version. 695f25efeSWolfram Sang * 795f25efeSWolfram Sang * Copyright (c) 2010 Pengutronix e.K. 8035ff831SWolfram Sang * Author: Wolfram Sang <kernel@pengutronix.de> 995f25efeSWolfram Sang */ 1095f25efeSWolfram Sang 11a8e809ecSMasahiro Yamada #include <linux/bitfield.h> 1295f25efeSWolfram Sang #include <linux/io.h> 13f581e909SHaibo Chen #include <linux/iopoll.h> 1495f25efeSWolfram Sang #include <linux/delay.h> 1595f25efeSWolfram Sang #include <linux/err.h> 1695f25efeSWolfram Sang #include <linux/clk.h> 1766506f76SShawn Guo #include <linux/module.h> 18e149860dSRichard Zhu #include <linux/slab.h> 191c4989b0SBOUGH CHEN #include <linux/pm_qos.h> 2095f25efeSWolfram Sang #include <linux/mmc/host.h> 2158ac8177SRichard Zhu #include <linux/mmc/mmc.h> 2258ac8177SRichard Zhu #include <linux/mmc/sdio.h> 23fbe5fdd1SShawn Guo #include <linux/mmc/slot-gpio.h> 24abfafc2dSShawn Guo #include <linux/of.h> 25abfafc2dSShawn Guo #include <linux/of_device.h> 26e62d8b8fSDong Aisheng #include <linux/pinctrl/consumer.h> 2782906b13SArnd Bergmann #include <linux/platform_data/mmc-esdhc-imx.h> 2889d7e5c1SDong Aisheng #include <linux/pm_runtime.h> 2995f25efeSWolfram Sang #include "sdhci-pltfm.h" 3095f25efeSWolfram Sang #include "sdhci-esdhc.h" 31bb6e3581SBOUGH CHEN #include "cqhci.h" 3295f25efeSWolfram Sang 33a215186dSHaibo Chen #define ESDHC_SYS_CTRL_DTOCV_MASK 0x0f 3460bf6396SShawn Guo #define ESDHC_CTRL_D3CD 0x08 35fd44954eSHaibo Chen #define ESDHC_BURST_LEN_EN_INCR (1 << 27) 3658ac8177SRichard Zhu /* VENDOR SPEC register */ 3760bf6396SShawn Guo #define ESDHC_VENDOR_SPEC 0xc0 3860bf6396SShawn Guo #define ESDHC_VENDOR_SPEC_SDIO_QUIRK (1 << 1) 390322191eSDong Aisheng #define ESDHC_VENDOR_SPEC_VSELECT (1 << 1) 40fed2f6e2SDong Aisheng #define ESDHC_VENDOR_SPEC_FRC_SDCLK_ON (1 << 8) 4160bf6396SShawn Guo #define ESDHC_WTMK_LVL 0x44 42cc17e129SDong Aisheng #define ESDHC_WTMK_DEFAULT_VAL 0x10401040 433fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_MASK 0x000000FF 443fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_RD_WML_SHIFT 0 453fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_MASK 0x00FF0000 463fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WR_WML_SHIFT 16 473fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_DEF 64 483fbd4322SAndrew Gabbasov #define ESDHC_WTMK_LVL_WML_VAL_MAX 128 4960bf6396SShawn Guo #define ESDHC_MIX_CTRL 0x48 50de5bdbffSDong Aisheng #define ESDHC_MIX_CTRL_DDREN (1 << 3) 512a15f981SShawn Guo #define ESDHC_MIX_CTRL_AC23EN (1 << 7) 520322191eSDong Aisheng #define ESDHC_MIX_CTRL_EXE_TUNE (1 << 22) 530322191eSDong Aisheng #define ESDHC_MIX_CTRL_SMPCLK_SEL (1 << 23) 540b330e38SDong Aisheng #define ESDHC_MIX_CTRL_AUTO_TUNE_EN (1 << 24) 550322191eSDong Aisheng #define ESDHC_MIX_CTRL_FBCLK_SEL (1 << 25) 5628b07674SHaibo Chen #define ESDHC_MIX_CTRL_HS400_EN (1 << 26) 57029e2476SBOUGH CHEN #define ESDHC_MIX_CTRL_HS400_ES_EN (1 << 27) 582a15f981SShawn Guo /* Bits 3 and 6 are not SDHCI standard definitions */ 592a15f981SShawn Guo #define ESDHC_MIX_CTRL_SDHCI_MASK 0xb7 60d131a71cSDong Aisheng /* Tuning bits */ 61d131a71cSDong Aisheng #define ESDHC_MIX_CTRL_TUNING_MASK 0x03c00000 6258ac8177SRichard Zhu 63602519b2SDong Aisheng /* dll control register */ 64602519b2SDong Aisheng #define ESDHC_DLL_CTRL 0x60 65602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_VAL_SHIFT 9 66602519b2SDong Aisheng #define ESDHC_DLL_OVERRIDE_EN_SHIFT 8 67602519b2SDong Aisheng 680322191eSDong Aisheng /* tune control register */ 690322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STATUS 0x68 700322191eSDong Aisheng #define ESDHC_TUNE_CTRL_STEP 1 710322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MIN 0 720322191eSDong Aisheng #define ESDHC_TUNE_CTRL_MAX ((1 << 7) - 1) 730322191eSDong Aisheng 7428b07674SHaibo Chen /* strobe dll register */ 7528b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL 0x70 7628b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_ENABLE (1 << 0) 7728b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_RESET (1 << 1) 785bd2acdcSHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT 0x7 7928b07674SHaibo Chen #define ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT 3 802eaf5a53SBOUGH CHEN #define ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT (4 << 20) 8128b07674SHaibo Chen 8228b07674SHaibo Chen #define ESDHC_STROBE_DLL_STATUS 0x74 8328b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_REF_LOCK (1 << 1) 8428b07674SHaibo Chen #define ESDHC_STROBE_DLL_STS_SLV_LOCK 0x1 8528b07674SHaibo Chen 86bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2 0xc8 87bcdb5301SBOUGH CHEN #define ESDHC_VEND_SPEC2_EN_BUSY_IRQ (1 << 8) 88bcdb5301SBOUGH CHEN 896e9fd28eSDong Aisheng #define ESDHC_TUNING_CTRL 0xcc 906e9fd28eSDong Aisheng #define ESDHC_STD_TUNING_EN (1 << 24) 916e9fd28eSDong Aisheng /* NOTE: the minimum valid tuning start tap for mx6sl is 1 */ 92d87fc966SDong Aisheng #define ESDHC_TUNING_START_TAP_DEFAULT 0x1 931194be8cSHaibo Chen #define ESDHC_TUNING_START_TAP_MASK 0x7f 94*16e40e5bSHaibo Chen #define ESDHC_TUNING_CMD_CRC_CHECK_DISABLE (1 << 7) 95260ecb3cSHaibo Chen #define ESDHC_TUNING_STEP_MASK 0x00070000 96d407e30bSHaibo Chen #define ESDHC_TUNING_STEP_SHIFT 16 976e9fd28eSDong Aisheng 98ad93220dSDong Aisheng /* pinctrl state */ 99ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_100MHZ "state_100mhz" 100ad93220dSDong Aisheng #define ESDHC_PINCTRL_STATE_200MHZ "state_200mhz" 101ad93220dSDong Aisheng 10258ac8177SRichard Zhu /* 103af51079eSSascha Hauer * Our interpretation of the SDHCI_HOST_CONTROL register 104af51079eSSascha Hauer */ 105af51079eSSascha Hauer #define ESDHC_CTRL_4BITBUS (0x1 << 1) 106af51079eSSascha Hauer #define ESDHC_CTRL_8BITBUS (0x2 << 1) 107af51079eSSascha Hauer #define ESDHC_CTRL_BUSWIDTH_MASK (0x3 << 1) 108af51079eSSascha Hauer 109af51079eSSascha Hauer /* 110d04f8d5bSBenoît Thébaudeau * There is an INT DMA ERR mismatch between eSDHC and STD SDHC SPEC: 11197e4ba6aSRichard Zhu * Bit25 is used in STD SPEC, and is reserved in fsl eSDHC design, 11297e4ba6aSRichard Zhu * but bit28 is used as the INT DMA ERR in fsl eSDHC design. 11397e4ba6aSRichard Zhu * Define this macro DMA error INT for fsl eSDHC 11497e4ba6aSRichard Zhu */ 11560bf6396SShawn Guo #define ESDHC_INT_VENDOR_SPEC_DMA_ERR (1 << 28) 11697e4ba6aSRichard Zhu 117bb6e3581SBOUGH CHEN /* the address offset of CQHCI */ 118bb6e3581SBOUGH CHEN #define ESDHC_CQHCI_ADDR_OFFSET 0x100 119bb6e3581SBOUGH CHEN 12097e4ba6aSRichard Zhu /* 12158ac8177SRichard Zhu * The CMDTYPE of the CMD register (offset 0xE) should be set to 12258ac8177SRichard Zhu * "11" when the STOP CMD12 is issued on imx53 to abort one 12358ac8177SRichard Zhu * open ended multi-blk IO. Otherwise the TC INT wouldn't 12458ac8177SRichard Zhu * be generated. 12558ac8177SRichard Zhu * In exact block transfer, the controller doesn't complete the 12658ac8177SRichard Zhu * operations automatically as required at the end of the 12758ac8177SRichard Zhu * transfer and remains on hold if the abort command is not sent. 12858ac8177SRichard Zhu * As a result, the TC flag is not asserted and SW received timeout 129d04f8d5bSBenoît Thébaudeau * exception. Bit1 of Vendor Spec register is used to fix it. 13058ac8177SRichard Zhu */ 13131fbb301SShawn Guo #define ESDHC_FLAG_MULTIBLK_NO_INT BIT(1) 13231fbb301SShawn Guo /* 1339d61c009SShawn Guo * The flag tells that the ESDHC controller is an USDHC block that is 1349d61c009SShawn Guo * integrated on the i.MX6 series. 1359d61c009SShawn Guo */ 1369d61c009SShawn Guo #define ESDHC_FLAG_USDHC BIT(3) 1376e9fd28eSDong Aisheng /* The IP supports manual tuning process */ 1386e9fd28eSDong Aisheng #define ESDHC_FLAG_MAN_TUNING BIT(4) 1396e9fd28eSDong Aisheng /* The IP supports standard tuning process */ 1406e9fd28eSDong Aisheng #define ESDHC_FLAG_STD_TUNING BIT(5) 1416e9fd28eSDong Aisheng /* The IP has SDHCI_CAPABILITIES_1 register */ 1426e9fd28eSDong Aisheng #define ESDHC_FLAG_HAVE_CAP1 BIT(6) 14318094430SDong Aisheng /* 144d04f8d5bSBenoît Thébaudeau * The IP has erratum ERR004536 14518094430SDong Aisheng * uSDHC: ADMA Length Mismatch Error occurs if the AHB read access is slow, 14618094430SDong Aisheng * when reading data from the card 147667123f6SBenoît Thébaudeau * This flag is also set for i.MX25 and i.MX35 in order to get 148667123f6SBenoît Thébaudeau * SDHCI_QUIRK_BROKEN_ADMA, but for different reasons (ADMA capability bits). 14918094430SDong Aisheng */ 15018094430SDong Aisheng #define ESDHC_FLAG_ERR004536 BIT(7) 1514245afffSDong Aisheng /* The IP supports HS200 mode */ 1524245afffSDong Aisheng #define ESDHC_FLAG_HS200 BIT(8) 15328b07674SHaibo Chen /* The IP supports HS400 mode */ 15428b07674SHaibo Chen #define ESDHC_FLAG_HS400 BIT(9) 155af6a50d4SBOUGH CHEN /* 156af6a50d4SBOUGH CHEN * The IP has errata ERR010450 157af6a50d4SBOUGH CHEN * uSDHC: Due to the I/O timing limit, for SDR mode, SD card clock can't 158af6a50d4SBOUGH CHEN * exceed 150MHz, for DDR mode, SD card clock can't exceed 45MHz. 159af6a50d4SBOUGH CHEN */ 160af6a50d4SBOUGH CHEN #define ESDHC_FLAG_ERR010450 BIT(10) 161029e2476SBOUGH CHEN /* The IP supports HS400ES mode */ 162029e2476SBOUGH CHEN #define ESDHC_FLAG_HS400_ES BIT(11) 163bb6e3581SBOUGH CHEN /* The IP has Host Controller Interface for Command Queuing */ 164bb6e3581SBOUGH CHEN #define ESDHC_FLAG_CQHCI BIT(12) 1651c4989b0SBOUGH CHEN /* need request pmqos during low power */ 1661c4989b0SBOUGH CHEN #define ESDHC_FLAG_PMQOS BIT(13) 167a26a4f1bSHaibo Chen /* The IP state got lost in low power mode */ 168a26a4f1bSHaibo Chen #define ESDHC_FLAG_STATE_LOST_IN_LPMODE BIT(14) 1695c11f1ffSHaibo Chen /* The IP lost clock rate in PM_RUNTIME */ 1705c11f1ffSHaibo Chen #define ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME BIT(15) 17174898cbcSHaibo Chen /* 17274898cbcSHaibo Chen * The IP do not support the ACMD23 feature completely when use ADMA mode. 17374898cbcSHaibo Chen * In ADMA mode, it only use the 16 bit block count of the register 0x4 17474898cbcSHaibo Chen * (BLOCK_ATT) as the CMD23's argument for ACMD23 mode, which means it will 17574898cbcSHaibo Chen * ignore the upper 16 bit of the CMD23's argument. This will block the reliable 17674898cbcSHaibo Chen * write operation in RPMB, because RPMB reliable write need to set the bit31 17774898cbcSHaibo Chen * of the CMD23's argument. 17874898cbcSHaibo Chen * imx6qpdl/imx6sx/imx6sl/imx7d has this limitation only for ADMA mode, SDMA 17974898cbcSHaibo Chen * do not has this limitation. so when these SoC use ADMA mode, it need to 18074898cbcSHaibo Chen * disable the ACMD23 feature. 18174898cbcSHaibo Chen */ 18274898cbcSHaibo Chen #define ESDHC_FLAG_BROKEN_AUTO_CMD23 BIT(16) 183e149860dSRichard Zhu 184f47c4bbfSShawn Guo struct esdhc_soc_data { 185f47c4bbfSShawn Guo u32 flags; 186f47c4bbfSShawn Guo }; 187f47c4bbfSShawn Guo 1884f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx25_data = { 189667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 190f47c4bbfSShawn Guo }; 191f47c4bbfSShawn Guo 1924f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx35_data = { 193667123f6SBenoît Thébaudeau .flags = ESDHC_FLAG_ERR004536, 194f47c4bbfSShawn Guo }; 195f47c4bbfSShawn Guo 1964f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx51_data = { 197f47c4bbfSShawn Guo .flags = 0, 198f47c4bbfSShawn Guo }; 199f47c4bbfSShawn Guo 2004f100012SAndrey Smirnov static const struct esdhc_soc_data esdhc_imx53_data = { 201f47c4bbfSShawn Guo .flags = ESDHC_FLAG_MULTIBLK_NO_INT, 202f47c4bbfSShawn Guo }; 203f47c4bbfSShawn Guo 2044f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6q_data = { 20574898cbcSHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_MAN_TUNING 20674898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 2076e9fd28eSDong Aisheng }; 2086e9fd28eSDong Aisheng 2094f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sl_data = { 2106e9fd28eSDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 2114245afffSDong Aisheng | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_ERR004536 21274898cbcSHaibo Chen | ESDHC_FLAG_HS200 21374898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 21474898cbcSHaibo Chen }; 21574898cbcSHaibo Chen 21674898cbcSHaibo Chen static const struct esdhc_soc_data usdhc_imx6sll_data = { 21774898cbcSHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 21874898cbcSHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 21986b59671SHaibo Chen | ESDHC_FLAG_HS400 22074898cbcSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 22157ed3314SShawn Guo }; 22257ed3314SShawn Guo 2234f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx6sx_data = { 224913d4951SDong Aisheng .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 225a26a4f1bSHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 22674898cbcSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE 22774898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 228913d4951SDong Aisheng }; 229913d4951SDong Aisheng 230af6a50d4SBOUGH CHEN static const struct esdhc_soc_data usdhc_imx6ull_data = { 231af6a50d4SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 232af6a50d4SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 233a26a4f1bSHaibo Chen | ESDHC_FLAG_ERR010450 234a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 235af6a50d4SBOUGH CHEN }; 236af6a50d4SBOUGH CHEN 2374f100012SAndrey Smirnov static const struct esdhc_soc_data usdhc_imx7d_data = { 23828b07674SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 23928b07674SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 240a26a4f1bSHaibo Chen | ESDHC_FLAG_HS400 24174898cbcSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE 24274898cbcSHaibo Chen | ESDHC_FLAG_BROKEN_AUTO_CMD23, 24328b07674SHaibo Chen }; 24428b07674SHaibo Chen 2451c4989b0SBOUGH CHEN static struct esdhc_soc_data usdhc_imx7ulp_data = { 2461c4989b0SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 2471c4989b0SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 248a26a4f1bSHaibo Chen | ESDHC_FLAG_PMQOS | ESDHC_FLAG_HS400 249a26a4f1bSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 2501c4989b0SBOUGH CHEN }; 2511c4989b0SBOUGH CHEN 252029e2476SBOUGH CHEN static struct esdhc_soc_data usdhc_imx8qxp_data = { 253029e2476SBOUGH CHEN .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 254029e2476SBOUGH CHEN | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 255bb6e3581SBOUGH CHEN | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 256a26a4f1bSHaibo Chen | ESDHC_FLAG_CQHCI 2575c11f1ffSHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE 2585c11f1ffSHaibo Chen | ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME, 259029e2476SBOUGH CHEN }; 260029e2476SBOUGH CHEN 261cde5e8e9SHaibo Chen static struct esdhc_soc_data usdhc_imx8mm_data = { 262cde5e8e9SHaibo Chen .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING 263cde5e8e9SHaibo Chen | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 264cde5e8e9SHaibo Chen | ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES 265cde5e8e9SHaibo Chen | ESDHC_FLAG_CQHCI 266cde5e8e9SHaibo Chen | ESDHC_FLAG_STATE_LOST_IN_LPMODE, 267e149860dSRichard Zhu }; 268e149860dSRichard Zhu 269e149860dSRichard Zhu struct pltfm_imx_data { 270e149860dSRichard Zhu u32 scratchpad; 271e62d8b8fSDong Aisheng struct pinctrl *pinctrl; 272ad93220dSDong Aisheng struct pinctrl_state *pins_100mhz; 273ad93220dSDong Aisheng struct pinctrl_state *pins_200mhz; 274f47c4bbfSShawn Guo const struct esdhc_soc_data *socdata; 275842afc02SShawn Guo struct esdhc_platform_data boarddata; 27652dac615SSascha Hauer struct clk *clk_ipg; 27752dac615SSascha Hauer struct clk *clk_ahb; 27852dac615SSascha Hauer struct clk *clk_per; 2793602785bSMichael Trimarchi unsigned int actual_clock; 280361b8482SLucas Stach enum { 281361b8482SLucas Stach NO_CMD_PENDING, /* no multiblock command pending */ 282361b8482SLucas Stach MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */ 283361b8482SLucas Stach WAIT_FOR_INT, /* sent CMD12, waiting for response INT */ 284361b8482SLucas Stach } multiblock_status; 285de5bdbffSDong Aisheng u32 is_ddr; 2861c4989b0SBOUGH CHEN struct pm_qos_request pm_qos_req; 287e149860dSRichard Zhu }; 288e149860dSRichard Zhu 289f8cbf461SKrzysztof Kozlowski static const struct platform_device_id imx_esdhc_devtype[] = { 29057ed3314SShawn Guo { 29157ed3314SShawn Guo .name = "sdhci-esdhc-imx25", 292f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx25_data, 29357ed3314SShawn Guo }, { 29457ed3314SShawn Guo .name = "sdhci-esdhc-imx35", 295f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx35_data, 29657ed3314SShawn Guo }, { 29757ed3314SShawn Guo .name = "sdhci-esdhc-imx51", 298f47c4bbfSShawn Guo .driver_data = (kernel_ulong_t) &esdhc_imx51_data, 29957ed3314SShawn Guo }, { 30057ed3314SShawn Guo /* sentinel */ 30157ed3314SShawn Guo } 30257ed3314SShawn Guo }; 30357ed3314SShawn Guo MODULE_DEVICE_TABLE(platform, imx_esdhc_devtype); 30457ed3314SShawn Guo 305abfafc2dSShawn Guo static const struct of_device_id imx_esdhc_dt_ids[] = { 306f47c4bbfSShawn Guo { .compatible = "fsl,imx25-esdhc", .data = &esdhc_imx25_data, }, 307f47c4bbfSShawn Guo { .compatible = "fsl,imx35-esdhc", .data = &esdhc_imx35_data, }, 308f47c4bbfSShawn Guo { .compatible = "fsl,imx51-esdhc", .data = &esdhc_imx51_data, }, 309f47c4bbfSShawn Guo { .compatible = "fsl,imx53-esdhc", .data = &esdhc_imx53_data, }, 310913d4951SDong Aisheng { .compatible = "fsl,imx6sx-usdhc", .data = &usdhc_imx6sx_data, }, 3116e9fd28eSDong Aisheng { .compatible = "fsl,imx6sl-usdhc", .data = &usdhc_imx6sl_data, }, 31274898cbcSHaibo Chen { .compatible = "fsl,imx6sll-usdhc", .data = &usdhc_imx6sll_data, }, 313f47c4bbfSShawn Guo { .compatible = "fsl,imx6q-usdhc", .data = &usdhc_imx6q_data, }, 314af6a50d4SBOUGH CHEN { .compatible = "fsl,imx6ull-usdhc", .data = &usdhc_imx6ull_data, }, 31528b07674SHaibo Chen { .compatible = "fsl,imx7d-usdhc", .data = &usdhc_imx7d_data, }, 3161c4989b0SBOUGH CHEN { .compatible = "fsl,imx7ulp-usdhc", .data = &usdhc_imx7ulp_data, }, 317029e2476SBOUGH CHEN { .compatible = "fsl,imx8qxp-usdhc", .data = &usdhc_imx8qxp_data, }, 318cde5e8e9SHaibo Chen { .compatible = "fsl,imx8mm-usdhc", .data = &usdhc_imx8mm_data, }, 319abfafc2dSShawn Guo { /* sentinel */ } 320abfafc2dSShawn Guo }; 321abfafc2dSShawn Guo MODULE_DEVICE_TABLE(of, imx_esdhc_dt_ids); 322abfafc2dSShawn Guo 32357ed3314SShawn Guo static inline int is_imx25_esdhc(struct pltfm_imx_data *data) 32457ed3314SShawn Guo { 325f47c4bbfSShawn Guo return data->socdata == &esdhc_imx25_data; 32657ed3314SShawn Guo } 32757ed3314SShawn Guo 32857ed3314SShawn Guo static inline int is_imx53_esdhc(struct pltfm_imx_data *data) 32957ed3314SShawn Guo { 330f47c4bbfSShawn Guo return data->socdata == &esdhc_imx53_data; 33157ed3314SShawn Guo } 33257ed3314SShawn Guo 33395a2482aSShawn Guo static inline int is_imx6q_usdhc(struct pltfm_imx_data *data) 33495a2482aSShawn Guo { 335f47c4bbfSShawn Guo return data->socdata == &usdhc_imx6q_data; 33695a2482aSShawn Guo } 33795a2482aSShawn Guo 3389d61c009SShawn Guo static inline int esdhc_is_usdhc(struct pltfm_imx_data *data) 3399d61c009SShawn Guo { 340f47c4bbfSShawn Guo return !!(data->socdata->flags & ESDHC_FLAG_USDHC); 3419d61c009SShawn Guo } 3429d61c009SShawn Guo 34395f25efeSWolfram Sang static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, int reg) 34495f25efeSWolfram Sang { 34595f25efeSWolfram Sang void __iomem *base = host->ioaddr + (reg & ~0x3); 34695f25efeSWolfram Sang u32 shift = (reg & 0x3) * 8; 34795f25efeSWolfram Sang 34895f25efeSWolfram Sang writel(((readl(base) & ~(mask << shift)) | (val << shift)), base); 34995f25efeSWolfram Sang } 35095f25efeSWolfram Sang 351f581e909SHaibo Chen static inline void esdhc_wait_for_card_clock_gate_off(struct sdhci_host *host) 352f581e909SHaibo Chen { 353f581e909SHaibo Chen u32 present_state; 354f581e909SHaibo Chen int ret; 355f581e909SHaibo Chen 356f581e909SHaibo Chen ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, present_state, 357f581e909SHaibo Chen (present_state & ESDHC_CLOCK_GATE_OFF), 2, 100); 358f581e909SHaibo Chen if (ret == -ETIMEDOUT) 359f581e909SHaibo Chen dev_warn(mmc_dev(host->mmc), "%s: card clock still not gate off in 100us!.\n", __func__); 360f581e909SHaibo Chen } 361f581e909SHaibo Chen 3627e29c306SWolfram Sang static u32 esdhc_readl_le(struct sdhci_host *host, int reg) 3637e29c306SWolfram Sang { 364361b8482SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 365070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 366913413c3SShawn Guo u32 val = readl(host->ioaddr + reg); 367913413c3SShawn Guo 3680322191eSDong Aisheng if (unlikely(reg == SDHCI_PRESENT_STATE)) { 3690322191eSDong Aisheng u32 fsl_prss = val; 3700322191eSDong Aisheng /* save the least 20 bits */ 3710322191eSDong Aisheng val = fsl_prss & 0x000FFFFF; 3720322191eSDong Aisheng /* move dat[0-3] bits */ 3730322191eSDong Aisheng val |= (fsl_prss & 0x0F000000) >> 4; 3740322191eSDong Aisheng /* move cmd line bit */ 3750322191eSDong Aisheng val |= (fsl_prss & 0x00800000) << 1; 3760322191eSDong Aisheng } 3770322191eSDong Aisheng 37897e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_CAPABILITIES)) { 3796b4fb671SDong Aisheng /* ignore bit[0-15] as it stores cap_1 register val for mx6sl */ 3806b4fb671SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3816b4fb671SDong Aisheng val &= 0xffff0000; 3826b4fb671SDong Aisheng 38397e4ba6aSRichard Zhu /* In FSL esdhc IC module, only bit20 is used to indicate the 38497e4ba6aSRichard Zhu * ADMA2 capability of esdhc, but this bit is messed up on 38597e4ba6aSRichard Zhu * some SOCs (e.g. on MX25, MX35 this bit is set, but they 38697e4ba6aSRichard Zhu * don't actually support ADMA2). So set the BROKEN_ADMA 387d04f8d5bSBenoît Thébaudeau * quirk on MX25/35 platforms. 38897e4ba6aSRichard Zhu */ 38997e4ba6aSRichard Zhu 39097e4ba6aSRichard Zhu if (val & SDHCI_CAN_DO_ADMA1) { 39197e4ba6aSRichard Zhu val &= ~SDHCI_CAN_DO_ADMA1; 39297e4ba6aSRichard Zhu val |= SDHCI_CAN_DO_ADMA2; 39397e4ba6aSRichard Zhu } 39497e4ba6aSRichard Zhu } 39597e4ba6aSRichard Zhu 3966e9fd28eSDong Aisheng if (unlikely(reg == SDHCI_CAPABILITIES_1)) { 3976e9fd28eSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 3986e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_HAVE_CAP1) 3996e9fd28eSDong Aisheng val = readl(host->ioaddr + SDHCI_CAPABILITIES) & 0xFFFF; 4006e9fd28eSDong Aisheng else 4016e9fd28eSDong Aisheng /* imx6q/dl does not have cap_1 register, fake one */ 4020322191eSDong Aisheng val = SDHCI_SUPPORT_DDR50 | SDHCI_SUPPORT_SDR104 403888824bbSDong Aisheng | SDHCI_SUPPORT_SDR50 404da0295ffSDong Aisheng | SDHCI_USE_SDR50_TUNING 405a8e809ecSMasahiro Yamada | FIELD_PREP(SDHCI_RETUNING_MODE_MASK, 406a8e809ecSMasahiro Yamada SDHCI_TUNING_MODE_3); 40728b07674SHaibo Chen 40828b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 40928b07674SHaibo Chen val |= SDHCI_SUPPORT_HS400; 41092748beaSStefan Agner 41192748beaSStefan Agner /* 41292748beaSStefan Agner * Do not advertise faster UHS modes if there are no 41392748beaSStefan Agner * pinctrl states for 100MHz/200MHz. 41492748beaSStefan Agner */ 41592748beaSStefan Agner if (IS_ERR_OR_NULL(imx_data->pins_100mhz) || 41692748beaSStefan Agner IS_ERR_OR_NULL(imx_data->pins_200mhz)) 41792748beaSStefan Agner val &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50 41892748beaSStefan Agner | SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_HS400); 4196e9fd28eSDong Aisheng } 4206e9fd28eSDong Aisheng } 4210322191eSDong Aisheng 4229d61c009SShawn Guo if (unlikely(reg == SDHCI_MAX_CURRENT) && esdhc_is_usdhc(imx_data)) { 4230322191eSDong Aisheng val = 0; 424804a65b3SMasahiro Yamada val |= FIELD_PREP(SDHCI_MAX_CURRENT_330_MASK, 0xFF); 425804a65b3SMasahiro Yamada val |= FIELD_PREP(SDHCI_MAX_CURRENT_300_MASK, 0xFF); 426804a65b3SMasahiro Yamada val |= FIELD_PREP(SDHCI_MAX_CURRENT_180_MASK, 0xFF); 4270322191eSDong Aisheng } 4280322191eSDong Aisheng 42997e4ba6aSRichard Zhu if (unlikely(reg == SDHCI_INT_STATUS)) { 43060bf6396SShawn Guo if (val & ESDHC_INT_VENDOR_SPEC_DMA_ERR) { 43160bf6396SShawn Guo val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR; 43297e4ba6aSRichard Zhu val |= SDHCI_INT_ADMA_ERROR; 43397e4ba6aSRichard Zhu } 434361b8482SLucas Stach 435361b8482SLucas Stach /* 436361b8482SLucas Stach * mask off the interrupt we get in response to the manually 437361b8482SLucas Stach * sent CMD12 438361b8482SLucas Stach */ 439361b8482SLucas Stach if ((imx_data->multiblock_status == WAIT_FOR_INT) && 440361b8482SLucas Stach ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) { 441361b8482SLucas Stach val &= ~SDHCI_INT_RESPONSE; 442361b8482SLucas Stach writel(SDHCI_INT_RESPONSE, host->ioaddr + 443361b8482SLucas Stach SDHCI_INT_STATUS); 444361b8482SLucas Stach imx_data->multiblock_status = NO_CMD_PENDING; 445361b8482SLucas Stach } 44697e4ba6aSRichard Zhu } 44797e4ba6aSRichard Zhu 4487e29c306SWolfram Sang return val; 4497e29c306SWolfram Sang } 4507e29c306SWolfram Sang 4517e29c306SWolfram Sang static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg) 4527e29c306SWolfram Sang { 453e149860dSRichard Zhu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 454070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 4550d58864bSTony Lin u32 data; 456e149860dSRichard Zhu 45777da3da0SAaron Brice if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE || 45877da3da0SAaron Brice reg == SDHCI_INT_STATUS)) { 459b7321042SDong Aisheng if ((val & SDHCI_INT_CARD_INT) && !esdhc_is_usdhc(imx_data)) { 4600d58864bSTony Lin /* 4610d58864bSTony Lin * Clear and then set D3CD bit to avoid missing the 462d04f8d5bSBenoît Thébaudeau * card interrupt. This is an eSDHC controller problem 4630d58864bSTony Lin * so we need to apply the following workaround: clear 4640d58864bSTony Lin * and set D3CD bit will make eSDHC re-sample the card 4650d58864bSTony Lin * interrupt. In case a card interrupt was lost, 4660d58864bSTony Lin * re-sample it by the following steps. 4670d58864bSTony Lin */ 4680d58864bSTony Lin data = readl(host->ioaddr + SDHCI_HOST_CONTROL); 46960bf6396SShawn Guo data &= ~ESDHC_CTRL_D3CD; 4700d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 47160bf6396SShawn Guo data |= ESDHC_CTRL_D3CD; 4720d58864bSTony Lin writel(data, host->ioaddr + SDHCI_HOST_CONTROL); 4730d58864bSTony Lin } 474915be485SDong Aisheng 475915be485SDong Aisheng if (val & SDHCI_INT_ADMA_ERROR) { 476915be485SDong Aisheng val &= ~SDHCI_INT_ADMA_ERROR; 477915be485SDong Aisheng val |= ESDHC_INT_VENDOR_SPEC_DMA_ERR; 478915be485SDong Aisheng } 4790d58864bSTony Lin } 4800d58864bSTony Lin 481f47c4bbfSShawn Guo if (unlikely((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 48258ac8177SRichard Zhu && (reg == SDHCI_INT_STATUS) 48358ac8177SRichard Zhu && (val & SDHCI_INT_DATA_END))) { 48458ac8177SRichard Zhu u32 v; 48560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 48660bf6396SShawn Guo v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK; 48760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 488361b8482SLucas Stach 489361b8482SLucas Stach if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS) 490361b8482SLucas Stach { 491361b8482SLucas Stach /* send a manual CMD12 with RESPTYP=none */ 492361b8482SLucas Stach data = MMC_STOP_TRANSMISSION << 24 | 493361b8482SLucas Stach SDHCI_CMD_ABORTCMD << 16; 494361b8482SLucas Stach writel(data, host->ioaddr + SDHCI_TRANSFER_MODE); 495361b8482SLucas Stach imx_data->multiblock_status = WAIT_FOR_INT; 496361b8482SLucas Stach } 49758ac8177SRichard Zhu } 49858ac8177SRichard Zhu 4997e29c306SWolfram Sang writel(val, host->ioaddr + reg); 5007e29c306SWolfram Sang } 5017e29c306SWolfram Sang 50295f25efeSWolfram Sang static u16 esdhc_readw_le(struct sdhci_host *host, int reg) 50395f25efeSWolfram Sang { 504ef4d0888SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 505070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 5060322191eSDong Aisheng u16 ret = 0; 5070322191eSDong Aisheng u32 val; 508ef4d0888SShawn Guo 50995a2482aSShawn Guo if (unlikely(reg == SDHCI_HOST_VERSION)) { 510ef4d0888SShawn Guo reg ^= 2; 5119d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 51295a2482aSShawn Guo /* 513ef4d0888SShawn Guo * The usdhc register returns a wrong host version. 514ef4d0888SShawn Guo * Correct it here. 51595a2482aSShawn Guo */ 516ef4d0888SShawn Guo return SDHCI_SPEC_300; 517ef4d0888SShawn Guo } 51895a2482aSShawn Guo } 51995f25efeSWolfram Sang 5200322191eSDong Aisheng if (unlikely(reg == SDHCI_HOST_CONTROL2)) { 5210322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5220322191eSDong Aisheng if (val & ESDHC_VENDOR_SPEC_VSELECT) 5230322191eSDong Aisheng ret |= SDHCI_CTRL_VDD_180; 5240322191eSDong Aisheng 5259d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 5266e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 5270322191eSDong Aisheng val = readl(host->ioaddr + ESDHC_MIX_CTRL); 5286e9fd28eSDong Aisheng else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) 5296e9fd28eSDong Aisheng /* the std tuning bits is in ACMD12_ERR for imx6sl */ 530869f8a69SAdrian Hunter val = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5316e9fd28eSDong Aisheng } 5326e9fd28eSDong Aisheng 5330322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_EXE_TUNE) 5340322191eSDong Aisheng ret |= SDHCI_CTRL_EXEC_TUNING; 5350322191eSDong Aisheng if (val & ESDHC_MIX_CTRL_SMPCLK_SEL) 5360322191eSDong Aisheng ret |= SDHCI_CTRL_TUNED_CLK; 5370322191eSDong Aisheng 5380322191eSDong Aisheng ret &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; 5390322191eSDong Aisheng 5400322191eSDong Aisheng return ret; 5410322191eSDong Aisheng } 5420322191eSDong Aisheng 5437dd109efSDong Aisheng if (unlikely(reg == SDHCI_TRANSFER_MODE)) { 5447dd109efSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 5457dd109efSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5467dd109efSDong Aisheng ret = m & ESDHC_MIX_CTRL_SDHCI_MASK; 5477dd109efSDong Aisheng /* Swap AC23 bit */ 5487dd109efSDong Aisheng if (m & ESDHC_MIX_CTRL_AC23EN) { 5497dd109efSDong Aisheng ret &= ~ESDHC_MIX_CTRL_AC23EN; 5507dd109efSDong Aisheng ret |= SDHCI_TRNS_AUTO_CMD23; 5517dd109efSDong Aisheng } 5527dd109efSDong Aisheng } else { 5537dd109efSDong Aisheng ret = readw(host->ioaddr + SDHCI_TRANSFER_MODE); 5547dd109efSDong Aisheng } 5557dd109efSDong Aisheng 5567dd109efSDong Aisheng return ret; 5577dd109efSDong Aisheng } 5587dd109efSDong Aisheng 55995f25efeSWolfram Sang return readw(host->ioaddr + reg); 56095f25efeSWolfram Sang } 56195f25efeSWolfram Sang 56295f25efeSWolfram Sang static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg) 56395f25efeSWolfram Sang { 56495f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 565070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 5660322191eSDong Aisheng u32 new_val = 0; 56795f25efeSWolfram Sang 56895f25efeSWolfram Sang switch (reg) { 5690322191eSDong Aisheng case SDHCI_CLOCK_CONTROL: 5700322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5710322191eSDong Aisheng if (val & SDHCI_CLOCK_CARD_EN) 5720322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5730322191eSDong Aisheng else 5740322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON; 5750322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 576f581e909SHaibo Chen if (!(new_val & ESDHC_VENDOR_SPEC_FRC_SDCLK_ON)) 577f581e909SHaibo Chen esdhc_wait_for_card_clock_gate_off(host); 5780322191eSDong Aisheng return; 5790322191eSDong Aisheng case SDHCI_HOST_CONTROL2: 5800322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 5810322191eSDong Aisheng if (val & SDHCI_CTRL_VDD_180) 5820322191eSDong Aisheng new_val |= ESDHC_VENDOR_SPEC_VSELECT; 5830322191eSDong Aisheng else 5840322191eSDong Aisheng new_val &= ~ESDHC_VENDOR_SPEC_VSELECT; 5850322191eSDong Aisheng writel(new_val, host->ioaddr + ESDHC_VENDOR_SPEC); 5866e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 5870322191eSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 588da0295ffSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 5890322191eSDong Aisheng new_val |= ESDHC_MIX_CTRL_SMPCLK_SEL; 590da0295ffSDong Aisheng new_val |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 591da0295ffSDong Aisheng } else { 5920322191eSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 593da0295ffSDong Aisheng new_val &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 594da0295ffSDong Aisheng } 5950322191eSDong Aisheng writel(new_val , host->ioaddr + ESDHC_MIX_CTRL); 5966e9fd28eSDong Aisheng } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 597869f8a69SAdrian Hunter u32 v = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 5986e9fd28eSDong Aisheng u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 5998b2bb0adSDong Aisheng if (val & SDHCI_CTRL_TUNED_CLK) { 6008b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_SMPCLK_SEL; 6016e9fd28eSDong Aisheng } else { 6028b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 6036e9fd28eSDong Aisheng m &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 6040b330e38SDong Aisheng m &= ~ESDHC_MIX_CTRL_AUTO_TUNE_EN; 6056e9fd28eSDong Aisheng } 6066e9fd28eSDong Aisheng 6078b2bb0adSDong Aisheng if (val & SDHCI_CTRL_EXEC_TUNING) { 6088b2bb0adSDong Aisheng v |= ESDHC_MIX_CTRL_EXE_TUNE; 6098b2bb0adSDong Aisheng m |= ESDHC_MIX_CTRL_FBCLK_SEL; 6100b330e38SDong Aisheng m |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 6118b2bb0adSDong Aisheng } else { 6128b2bb0adSDong Aisheng v &= ~ESDHC_MIX_CTRL_EXE_TUNE; 6138b2bb0adSDong Aisheng } 6146e9fd28eSDong Aisheng 615869f8a69SAdrian Hunter writel(v, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 6166e9fd28eSDong Aisheng writel(m, host->ioaddr + ESDHC_MIX_CTRL); 6176e9fd28eSDong Aisheng } 6180322191eSDong Aisheng return; 61995f25efeSWolfram Sang case SDHCI_TRANSFER_MODE: 620f47c4bbfSShawn Guo if ((imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT) 62158ac8177SRichard Zhu && (host->cmd->opcode == SD_IO_RW_EXTENDED) 62258ac8177SRichard Zhu && (host->cmd->data->blocks > 1) 62358ac8177SRichard Zhu && (host->cmd->data->flags & MMC_DATA_READ)) { 62458ac8177SRichard Zhu u32 v; 62560bf6396SShawn Guo v = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 62660bf6396SShawn Guo v |= ESDHC_VENDOR_SPEC_SDIO_QUIRK; 62760bf6396SShawn Guo writel(v, host->ioaddr + ESDHC_VENDOR_SPEC); 62858ac8177SRichard Zhu } 62969f54698SShawn Guo 6309d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 6313fbd4322SAndrew Gabbasov u32 wml; 63269f54698SShawn Guo u32 m = readl(host->ioaddr + ESDHC_MIX_CTRL); 6332a15f981SShawn Guo /* Swap AC23 bit */ 6342a15f981SShawn Guo if (val & SDHCI_TRNS_AUTO_CMD23) { 6352a15f981SShawn Guo val &= ~SDHCI_TRNS_AUTO_CMD23; 6362a15f981SShawn Guo val |= ESDHC_MIX_CTRL_AC23EN; 6372a15f981SShawn Guo } 6382a15f981SShawn Guo m = val | (m & ~ESDHC_MIX_CTRL_SDHCI_MASK); 63969f54698SShawn Guo writel(m, host->ioaddr + ESDHC_MIX_CTRL); 6403fbd4322SAndrew Gabbasov 6413fbd4322SAndrew Gabbasov /* Set watermark levels for PIO access to maximum value 6423fbd4322SAndrew Gabbasov * (128 words) to accommodate full 512 bytes buffer. 6433fbd4322SAndrew Gabbasov * For DMA access restore the levels to default value. 6443fbd4322SAndrew Gabbasov */ 6453fbd4322SAndrew Gabbasov m = readl(host->ioaddr + ESDHC_WTMK_LVL); 646e534b82fSHaibo Chen if (val & SDHCI_TRNS_DMA) { 6473fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_DEF; 648e534b82fSHaibo Chen } else { 649e534b82fSHaibo Chen u8 ctrl; 6503fbd4322SAndrew Gabbasov wml = ESDHC_WTMK_LVL_WML_VAL_MAX; 651e534b82fSHaibo Chen 652e534b82fSHaibo Chen /* 653e534b82fSHaibo Chen * Since already disable DMA mode, so also need 654e534b82fSHaibo Chen * to clear the DMASEL. Otherwise, for standard 655e534b82fSHaibo Chen * tuning, when send tuning command, usdhc will 656e534b82fSHaibo Chen * still prefetch the ADMA script from wrong 657e534b82fSHaibo Chen * DMA address, then we will see IOMMU report 658e534b82fSHaibo Chen * some error which show lack of TLB mapping. 659e534b82fSHaibo Chen */ 660e534b82fSHaibo Chen ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 661e534b82fSHaibo Chen ctrl &= ~SDHCI_CTRL_DMA_MASK; 662e534b82fSHaibo Chen sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 663e534b82fSHaibo Chen } 6643fbd4322SAndrew Gabbasov m &= ~(ESDHC_WTMK_LVL_RD_WML_MASK | 6653fbd4322SAndrew Gabbasov ESDHC_WTMK_LVL_WR_WML_MASK); 6663fbd4322SAndrew Gabbasov m |= (wml << ESDHC_WTMK_LVL_RD_WML_SHIFT) | 6673fbd4322SAndrew Gabbasov (wml << ESDHC_WTMK_LVL_WR_WML_SHIFT); 6683fbd4322SAndrew Gabbasov writel(m, host->ioaddr + ESDHC_WTMK_LVL); 66969f54698SShawn Guo } else { 67069f54698SShawn Guo /* 67169f54698SShawn Guo * Postpone this write, we must do it together with a 67269f54698SShawn Guo * command write that is down below. 67369f54698SShawn Guo */ 674e149860dSRichard Zhu imx_data->scratchpad = val; 67569f54698SShawn Guo } 67695f25efeSWolfram Sang return; 67795f25efeSWolfram Sang case SDHCI_COMMAND: 678361b8482SLucas Stach if (host->cmd->opcode == MMC_STOP_TRANSMISSION) 67958ac8177SRichard Zhu val |= SDHCI_CMD_ABORTCMD; 68095a2482aSShawn Guo 681361b8482SLucas Stach if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) && 682f47c4bbfSShawn Guo (imx_data->socdata->flags & ESDHC_FLAG_MULTIBLK_NO_INT)) 683361b8482SLucas Stach imx_data->multiblock_status = MULTIBLK_IN_PROCESS; 684361b8482SLucas Stach 6859d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) 68695a2482aSShawn Guo writel(val << 16, 68795a2482aSShawn Guo host->ioaddr + SDHCI_TRANSFER_MODE); 68869f54698SShawn Guo else 689e149860dSRichard Zhu writel(val << 16 | imx_data->scratchpad, 69095f25efeSWolfram Sang host->ioaddr + SDHCI_TRANSFER_MODE); 69195f25efeSWolfram Sang return; 69295f25efeSWolfram Sang case SDHCI_BLOCK_SIZE: 69395f25efeSWolfram Sang val &= ~SDHCI_MAKE_BLKSZ(0x7, 0); 69495f25efeSWolfram Sang break; 69595f25efeSWolfram Sang } 69695f25efeSWolfram Sang esdhc_clrset_le(host, 0xffff, val, reg); 69795f25efeSWolfram Sang } 69895f25efeSWolfram Sang 69977da3da0SAaron Brice static u8 esdhc_readb_le(struct sdhci_host *host, int reg) 70077da3da0SAaron Brice { 70177da3da0SAaron Brice u8 ret; 70277da3da0SAaron Brice u32 val; 70377da3da0SAaron Brice 70477da3da0SAaron Brice switch (reg) { 70577da3da0SAaron Brice case SDHCI_HOST_CONTROL: 70677da3da0SAaron Brice val = readl(host->ioaddr + reg); 70777da3da0SAaron Brice 70877da3da0SAaron Brice ret = val & SDHCI_CTRL_LED; 70977da3da0SAaron Brice ret |= (val >> 5) & SDHCI_CTRL_DMA_MASK; 71077da3da0SAaron Brice ret |= (val & ESDHC_CTRL_4BITBUS); 71177da3da0SAaron Brice ret |= (val & ESDHC_CTRL_8BITBUS) << 3; 71277da3da0SAaron Brice return ret; 71377da3da0SAaron Brice } 71477da3da0SAaron Brice 71577da3da0SAaron Brice return readb(host->ioaddr + reg); 71677da3da0SAaron Brice } 71777da3da0SAaron Brice 71895f25efeSWolfram Sang static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg) 71995f25efeSWolfram Sang { 7209a0985b7SWilson Callan struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 721070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 72281a0a8bcSBenoît Thébaudeau u32 new_val = 0; 723af51079eSSascha Hauer u32 mask; 72495f25efeSWolfram Sang 72595f25efeSWolfram Sang switch (reg) { 72695f25efeSWolfram Sang case SDHCI_POWER_CONTROL: 72795f25efeSWolfram Sang /* 72895f25efeSWolfram Sang * FSL put some DMA bits here 72995f25efeSWolfram Sang * If your board has a regulator, code should be here 73095f25efeSWolfram Sang */ 73195f25efeSWolfram Sang return; 73295f25efeSWolfram Sang case SDHCI_HOST_CONTROL: 7336b40d182SShawn Guo /* FSL messed up here, so we need to manually compose it. */ 734af51079eSSascha Hauer new_val = val & SDHCI_CTRL_LED; 7357122bbb0SMasanari Iida /* ensure the endianness */ 73695f25efeSWolfram Sang new_val |= ESDHC_HOST_CONTROL_LE; 7379a0985b7SWilson Callan /* bits 8&9 are reserved on mx25 */ 7389a0985b7SWilson Callan if (!is_imx25_esdhc(imx_data)) { 73995f25efeSWolfram Sang /* DMA mode bits are shifted */ 74095f25efeSWolfram Sang new_val |= (val & SDHCI_CTRL_DMA_MASK) << 5; 7419a0985b7SWilson Callan } 74295f25efeSWolfram Sang 743af51079eSSascha Hauer /* 744af51079eSSascha Hauer * Do not touch buswidth bits here. This is done in 745af51079eSSascha Hauer * esdhc_pltfm_bus_width. 746f6825748SMartin Fuzzey * Do not touch the D3CD bit either which is used for the 747d04f8d5bSBenoît Thébaudeau * SDIO interrupt erratum workaround. 748af51079eSSascha Hauer */ 749f6825748SMartin Fuzzey mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD); 750af51079eSSascha Hauer 751af51079eSSascha Hauer esdhc_clrset_le(host, mask, new_val, reg); 75295f25efeSWolfram Sang return; 75381a0a8bcSBenoît Thébaudeau case SDHCI_SOFTWARE_RESET: 75481a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_DATA) 75581a0a8bcSBenoît Thébaudeau new_val = readl(host->ioaddr + SDHCI_HOST_CONTROL); 75681a0a8bcSBenoît Thébaudeau break; 75795f25efeSWolfram Sang } 75895f25efeSWolfram Sang esdhc_clrset_le(host, 0xff, val, reg); 759913413c3SShawn Guo 76081a0a8bcSBenoît Thébaudeau if (reg == SDHCI_SOFTWARE_RESET) { 76181a0a8bcSBenoît Thébaudeau if (val & SDHCI_RESET_ALL) { 762913413c3SShawn Guo /* 76381a0a8bcSBenoît Thébaudeau * The esdhc has a design violation to SDHC spec which 76481a0a8bcSBenoît Thébaudeau * tells that software reset should not affect card 76581a0a8bcSBenoît Thébaudeau * detection circuit. But esdhc clears its SYSCTL 76681a0a8bcSBenoît Thébaudeau * register bits [0..2] during the software reset. This 76781a0a8bcSBenoît Thébaudeau * will stop those clocks that card detection circuit 76881a0a8bcSBenoît Thébaudeau * relies on. To work around it, we turn the clocks on 76981a0a8bcSBenoît Thébaudeau * back to keep card detection circuit functional. 770913413c3SShawn Guo */ 771913413c3SShawn Guo esdhc_clrset_le(host, 0x7, 0x7, ESDHC_SYSTEM_CONTROL); 77258c8c4fbSShawn Guo /* 77358c8c4fbSShawn Guo * The reset on usdhc fails to clear MIX_CTRL register. 77458c8c4fbSShawn Guo * Do it manually here. 77558c8c4fbSShawn Guo */ 776de5bdbffSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 77781a0a8bcSBenoît Thébaudeau /* 77881a0a8bcSBenoît Thébaudeau * the tuning bits should be kept during reset 77981a0a8bcSBenoît Thébaudeau */ 780d131a71cSDong Aisheng new_val = readl(host->ioaddr + ESDHC_MIX_CTRL); 781d131a71cSDong Aisheng writel(new_val & ESDHC_MIX_CTRL_TUNING_MASK, 782d131a71cSDong Aisheng host->ioaddr + ESDHC_MIX_CTRL); 783de5bdbffSDong Aisheng imx_data->is_ddr = 0; 784de5bdbffSDong Aisheng } 78581a0a8bcSBenoît Thébaudeau } else if (val & SDHCI_RESET_DATA) { 78681a0a8bcSBenoît Thébaudeau /* 78781a0a8bcSBenoît Thébaudeau * The eSDHC DAT line software reset clears at least the 78881a0a8bcSBenoît Thébaudeau * data transfer width on i.MX25, so make sure that the 78981a0a8bcSBenoît Thébaudeau * Host Control register is unaffected. 79081a0a8bcSBenoît Thébaudeau */ 79181a0a8bcSBenoît Thébaudeau esdhc_clrset_le(host, 0xff, new_val, 79281a0a8bcSBenoît Thébaudeau SDHCI_HOST_CONTROL); 79381a0a8bcSBenoît Thébaudeau } 79458c8c4fbSShawn Guo } 79595f25efeSWolfram Sang } 79695f25efeSWolfram Sang 7970ddf03c9SLucas Stach static unsigned int esdhc_pltfm_get_max_clock(struct sdhci_host *host) 7980ddf03c9SLucas Stach { 7990ddf03c9SLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 8000ddf03c9SLucas Stach 801a974862fSDong Aisheng return pltfm_host->clock; 8020ddf03c9SLucas Stach } 8030ddf03c9SLucas Stach 80495f25efeSWolfram Sang static unsigned int esdhc_pltfm_get_min_clock(struct sdhci_host *host) 80595f25efeSWolfram Sang { 80695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 80795f25efeSWolfram Sang 808a974862fSDong Aisheng return pltfm_host->clock / 256 / 16; 80995f25efeSWolfram Sang } 81095f25efeSWolfram Sang 8118ba9580aSLucas Stach static inline void esdhc_pltfm_set_clock(struct sdhci_host *host, 8128ba9580aSLucas Stach unsigned int clock) 8138ba9580aSLucas Stach { 8148ba9580aSLucas Stach struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 815070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 816a974862fSDong Aisheng unsigned int host_clock = pltfm_host->clock; 8175143c953SBenoît Thébaudeau int ddr_pre_div = imx_data->is_ddr ? 2 : 1; 8185143c953SBenoît Thébaudeau int pre_div = 1; 819d31fc00aSDong Aisheng int div = 1; 820f581e909SHaibo Chen int ret; 821fed2f6e2SDong Aisheng u32 temp, val; 8228ba9580aSLucas Stach 8239d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 824fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 825fed2f6e2SDong Aisheng writel(val & ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 826fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 827f581e909SHaibo Chen esdhc_wait_for_card_clock_gate_off(host); 828fed2f6e2SDong Aisheng } 82973e736f8SStefan Agner 83073e736f8SStefan Agner if (clock == 0) { 83173e736f8SStefan Agner host->mmc->actual_clock = 0; 832373073efSRussell King return; 833fed2f6e2SDong Aisheng } 834d31fc00aSDong Aisheng 835499ed50fSBenoît Thébaudeau /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */ 836499ed50fSBenoît Thébaudeau if (is_imx53_esdhc(imx_data)) { 837499ed50fSBenoît Thébaudeau /* 838499ed50fSBenoît Thébaudeau * According to the i.MX53 reference manual, if DLLCTRL[10] can 839499ed50fSBenoît Thébaudeau * be set, then the controller is eSDHCv3, else it is eSDHCv2. 840499ed50fSBenoît Thébaudeau */ 841499ed50fSBenoît Thébaudeau val = readl(host->ioaddr + ESDHC_DLL_CTRL); 842499ed50fSBenoît Thébaudeau writel(val | BIT(10), host->ioaddr + ESDHC_DLL_CTRL); 843499ed50fSBenoît Thébaudeau temp = readl(host->ioaddr + ESDHC_DLL_CTRL); 844499ed50fSBenoît Thébaudeau writel(val, host->ioaddr + ESDHC_DLL_CTRL); 845499ed50fSBenoît Thébaudeau if (temp & BIT(10)) 846499ed50fSBenoît Thébaudeau pre_div = 2; 847499ed50fSBenoît Thébaudeau } 848499ed50fSBenoît Thébaudeau 849d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 850d31fc00aSDong Aisheng temp &= ~(ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 851d31fc00aSDong Aisheng | ESDHC_CLOCK_MASK); 852d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 853d31fc00aSDong Aisheng 854af6a50d4SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_ERR010450) { 855af6a50d4SBOUGH CHEN unsigned int max_clock; 856af6a50d4SBOUGH CHEN 857af6a50d4SBOUGH CHEN max_clock = imx_data->is_ddr ? 45000000 : 150000000; 858af6a50d4SBOUGH CHEN 859af6a50d4SBOUGH CHEN clock = min(clock, max_clock); 860af6a50d4SBOUGH CHEN } 861af6a50d4SBOUGH CHEN 8625143c953SBenoît Thébaudeau while (host_clock / (16 * pre_div * ddr_pre_div) > clock && 8635143c953SBenoît Thébaudeau pre_div < 256) 864d31fc00aSDong Aisheng pre_div *= 2; 865d31fc00aSDong Aisheng 8665143c953SBenoît Thébaudeau while (host_clock / (div * pre_div * ddr_pre_div) > clock && div < 16) 867d31fc00aSDong Aisheng div++; 868d31fc00aSDong Aisheng 8695143c953SBenoît Thébaudeau host->mmc->actual_clock = host_clock / (div * pre_div * ddr_pre_div); 870d31fc00aSDong Aisheng dev_dbg(mmc_dev(host->mmc), "desired SD clock: %d, actual: %d\n", 871e76b8559SDong Aisheng clock, host->mmc->actual_clock); 872d31fc00aSDong Aisheng 873d31fc00aSDong Aisheng pre_div >>= 1; 874d31fc00aSDong Aisheng div--; 875d31fc00aSDong Aisheng 876d31fc00aSDong Aisheng temp = sdhci_readl(host, ESDHC_SYSTEM_CONTROL); 877d31fc00aSDong Aisheng temp |= (ESDHC_CLOCK_IPGEN | ESDHC_CLOCK_HCKEN | ESDHC_CLOCK_PEREN 878d31fc00aSDong Aisheng | (div << ESDHC_DIVIDER_SHIFT) 879d31fc00aSDong Aisheng | (pre_div << ESDHC_PREDIV_SHIFT)); 880d31fc00aSDong Aisheng sdhci_writel(host, temp, ESDHC_SYSTEM_CONTROL); 881fed2f6e2SDong Aisheng 882f581e909SHaibo Chen /* need to wait the bit 3 of the PRSSTAT to be set, make sure card clock is stable */ 883f581e909SHaibo Chen ret = readl_poll_timeout(host->ioaddr + ESDHC_PRSSTAT, temp, 884f581e909SHaibo Chen (temp & ESDHC_CLOCK_STABLE), 2, 100); 885f581e909SHaibo Chen if (ret == -ETIMEDOUT) 886f581e909SHaibo Chen dev_warn(mmc_dev(host->mmc), "card clock still not stable in 100us!.\n"); 887f581e909SHaibo Chen 8889d61c009SShawn Guo if (esdhc_is_usdhc(imx_data)) { 889fed2f6e2SDong Aisheng val = readl(host->ioaddr + ESDHC_VENDOR_SPEC); 890fed2f6e2SDong Aisheng writel(val | ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 891fed2f6e2SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 892fed2f6e2SDong Aisheng } 893fed2f6e2SDong Aisheng 8948ba9580aSLucas Stach } 8958ba9580aSLucas Stach 896913413c3SShawn Guo static unsigned int esdhc_pltfm_get_ro(struct sdhci_host *host) 897913413c3SShawn Guo { 898842afc02SShawn Guo struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 899070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 900842afc02SShawn Guo struct esdhc_platform_data *boarddata = &imx_data->boarddata; 901913413c3SShawn Guo 902913413c3SShawn Guo switch (boarddata->wp_type) { 903913413c3SShawn Guo case ESDHC_WP_GPIO: 904fbe5fdd1SShawn Guo return mmc_gpio_get_ro(host->mmc); 905913413c3SShawn Guo case ESDHC_WP_CONTROLLER: 906913413c3SShawn Guo return !(readl(host->ioaddr + SDHCI_PRESENT_STATE) & 907913413c3SShawn Guo SDHCI_WRITE_PROTECT); 908913413c3SShawn Guo case ESDHC_WP_NONE: 909913413c3SShawn Guo break; 910913413c3SShawn Guo } 911913413c3SShawn Guo 912913413c3SShawn Guo return -ENOSYS; 913913413c3SShawn Guo } 914913413c3SShawn Guo 9152317f56cSRussell King static void esdhc_pltfm_set_bus_width(struct sdhci_host *host, int width) 916af51079eSSascha Hauer { 917af51079eSSascha Hauer u32 ctrl; 918af51079eSSascha Hauer 919af51079eSSascha Hauer switch (width) { 920af51079eSSascha Hauer case MMC_BUS_WIDTH_8: 921af51079eSSascha Hauer ctrl = ESDHC_CTRL_8BITBUS; 922af51079eSSascha Hauer break; 923af51079eSSascha Hauer case MMC_BUS_WIDTH_4: 924af51079eSSascha Hauer ctrl = ESDHC_CTRL_4BITBUS; 925af51079eSSascha Hauer break; 926af51079eSSascha Hauer default: 927af51079eSSascha Hauer ctrl = 0; 928af51079eSSascha Hauer break; 929af51079eSSascha Hauer } 930af51079eSSascha Hauer 931af51079eSSascha Hauer esdhc_clrset_le(host, ESDHC_CTRL_BUSWIDTH_MASK, ctrl, 932af51079eSSascha Hauer SDHCI_HOST_CONTROL); 933af51079eSSascha Hauer } 934af51079eSSascha Hauer 935de3e1dd0SBOUGH CHEN static int usdhc_execute_tuning(struct mmc_host *mmc, u32 opcode) 936de3e1dd0SBOUGH CHEN { 937de3e1dd0SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 938de3e1dd0SBOUGH CHEN 939de3e1dd0SBOUGH CHEN /* 940de3e1dd0SBOUGH CHEN * i.MX uSDHC internally already uses a fixed optimized timing for 941de3e1dd0SBOUGH CHEN * DDR50, normally does not require tuning for DDR50 mode. 942de3e1dd0SBOUGH CHEN */ 943de3e1dd0SBOUGH CHEN if (host->timing == MMC_TIMING_UHS_DDR50) 944de3e1dd0SBOUGH CHEN return 0; 945de3e1dd0SBOUGH CHEN 946de3e1dd0SBOUGH CHEN return sdhci_execute_tuning(mmc, opcode); 947de3e1dd0SBOUGH CHEN } 948de3e1dd0SBOUGH CHEN 9490322191eSDong Aisheng static void esdhc_prepare_tuning(struct sdhci_host *host, u32 val) 9500322191eSDong Aisheng { 9510322191eSDong Aisheng u32 reg; 9520322191eSDong Aisheng 9530322191eSDong Aisheng /* FIXME: delay a bit for card to be ready for next tuning due to errors */ 9540322191eSDong Aisheng mdelay(1); 9550322191eSDong Aisheng 9560322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 9570322191eSDong Aisheng reg |= ESDHC_MIX_CTRL_EXE_TUNE | ESDHC_MIX_CTRL_SMPCLK_SEL | 9580322191eSDong Aisheng ESDHC_MIX_CTRL_FBCLK_SEL; 9590322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 9600322191eSDong Aisheng writel(val << 8, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 9610322191eSDong Aisheng dev_dbg(mmc_dev(host->mmc), 962d04f8d5bSBenoît Thébaudeau "tuning with delay 0x%x ESDHC_TUNE_CTRL_STATUS 0x%x\n", 9630322191eSDong Aisheng val, readl(host->ioaddr + ESDHC_TUNE_CTRL_STATUS)); 9640322191eSDong Aisheng } 9650322191eSDong Aisheng 9660322191eSDong Aisheng static void esdhc_post_tuning(struct sdhci_host *host) 9670322191eSDong Aisheng { 9680322191eSDong Aisheng u32 reg; 9690322191eSDong Aisheng 9700322191eSDong Aisheng reg = readl(host->ioaddr + ESDHC_MIX_CTRL); 9710322191eSDong Aisheng reg &= ~ESDHC_MIX_CTRL_EXE_TUNE; 972da0295ffSDong Aisheng reg |= ESDHC_MIX_CTRL_AUTO_TUNE_EN; 9730322191eSDong Aisheng writel(reg, host->ioaddr + ESDHC_MIX_CTRL); 9740322191eSDong Aisheng } 9750322191eSDong Aisheng 9760322191eSDong Aisheng static int esdhc_executing_tuning(struct sdhci_host *host, u32 opcode) 9770322191eSDong Aisheng { 9780322191eSDong Aisheng int min, max, avg, ret; 9790322191eSDong Aisheng 9800322191eSDong Aisheng /* find the mininum delay first which can pass tuning */ 9810322191eSDong Aisheng min = ESDHC_TUNE_CTRL_MIN; 9820322191eSDong Aisheng while (min < ESDHC_TUNE_CTRL_MAX) { 9830322191eSDong Aisheng esdhc_prepare_tuning(host, min); 9849979dbe5SChaotian Jing if (!mmc_send_tuning(host->mmc, opcode, NULL)) 9850322191eSDong Aisheng break; 9860322191eSDong Aisheng min += ESDHC_TUNE_CTRL_STEP; 9870322191eSDong Aisheng } 9880322191eSDong Aisheng 9890322191eSDong Aisheng /* find the maxinum delay which can not pass tuning */ 9900322191eSDong Aisheng max = min + ESDHC_TUNE_CTRL_STEP; 9910322191eSDong Aisheng while (max < ESDHC_TUNE_CTRL_MAX) { 9920322191eSDong Aisheng esdhc_prepare_tuning(host, max); 9939979dbe5SChaotian Jing if (mmc_send_tuning(host->mmc, opcode, NULL)) { 9940322191eSDong Aisheng max -= ESDHC_TUNE_CTRL_STEP; 9950322191eSDong Aisheng break; 9960322191eSDong Aisheng } 9970322191eSDong Aisheng max += ESDHC_TUNE_CTRL_STEP; 9980322191eSDong Aisheng } 9990322191eSDong Aisheng 10000322191eSDong Aisheng /* use average delay to get the best timing */ 10010322191eSDong Aisheng avg = (min + max) / 2; 10020322191eSDong Aisheng esdhc_prepare_tuning(host, avg); 10039979dbe5SChaotian Jing ret = mmc_send_tuning(host->mmc, opcode, NULL); 10040322191eSDong Aisheng esdhc_post_tuning(host); 10050322191eSDong Aisheng 1006d04f8d5bSBenoît Thébaudeau dev_dbg(mmc_dev(host->mmc), "tuning %s at 0x%x ret %d\n", 10070322191eSDong Aisheng ret ? "failed" : "passed", avg, ret); 10080322191eSDong Aisheng 10090322191eSDong Aisheng return ret; 10100322191eSDong Aisheng } 10110322191eSDong Aisheng 1012029e2476SBOUGH CHEN static void esdhc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) 1013029e2476SBOUGH CHEN { 1014029e2476SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 1015029e2476SBOUGH CHEN u32 m; 1016029e2476SBOUGH CHEN 1017029e2476SBOUGH CHEN m = readl(host->ioaddr + ESDHC_MIX_CTRL); 1018029e2476SBOUGH CHEN if (ios->enhanced_strobe) 1019029e2476SBOUGH CHEN m |= ESDHC_MIX_CTRL_HS400_ES_EN; 1020029e2476SBOUGH CHEN else 1021029e2476SBOUGH CHEN m &= ~ESDHC_MIX_CTRL_HS400_ES_EN; 1022029e2476SBOUGH CHEN writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1023029e2476SBOUGH CHEN } 1024029e2476SBOUGH CHEN 1025ad93220dSDong Aisheng static int esdhc_change_pinstate(struct sdhci_host *host, 1026ad93220dSDong Aisheng unsigned int uhs) 1027ad93220dSDong Aisheng { 1028ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1029070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1030ad93220dSDong Aisheng struct pinctrl_state *pinctrl; 1031ad93220dSDong Aisheng 1032ad93220dSDong Aisheng dev_dbg(mmc_dev(host->mmc), "change pinctrl state for uhs %d\n", uhs); 1033ad93220dSDong Aisheng 1034ad93220dSDong Aisheng if (IS_ERR(imx_data->pinctrl) || 1035ad93220dSDong Aisheng IS_ERR(imx_data->pins_100mhz) || 1036ad93220dSDong Aisheng IS_ERR(imx_data->pins_200mhz)) 1037ad93220dSDong Aisheng return -EINVAL; 1038ad93220dSDong Aisheng 1039ad93220dSDong Aisheng switch (uhs) { 1040ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 10419f327845SHaibo Chen case MMC_TIMING_UHS_DDR50: 1042ad93220dSDong Aisheng pinctrl = imx_data->pins_100mhz; 1043ad93220dSDong Aisheng break; 1044ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 1045429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 104628b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 1047ad93220dSDong Aisheng pinctrl = imx_data->pins_200mhz; 1048ad93220dSDong Aisheng break; 1049ad93220dSDong Aisheng default: 1050ad93220dSDong Aisheng /* back to default state for other legacy timing */ 10512480b720SUlf Hansson return pinctrl_select_default_state(mmc_dev(host->mmc)); 1052ad93220dSDong Aisheng } 1053ad93220dSDong Aisheng 1054ad93220dSDong Aisheng return pinctrl_select_state(imx_data->pinctrl, pinctrl); 1055ad93220dSDong Aisheng } 1056ad93220dSDong Aisheng 105728b07674SHaibo Chen /* 1058d04f8d5bSBenoît Thébaudeau * For HS400 eMMC, there is a data_strobe line. This signal is generated 105928b07674SHaibo Chen * by the device and used for data output and CRC status response output 106028b07674SHaibo Chen * in HS400 mode. The frequency of this signal follows the frequency of 1061d04f8d5bSBenoît Thébaudeau * CLK generated by host. The host receives the data which is aligned to the 106228b07674SHaibo Chen * edge of data_strobe line. Due to the time delay between CLK line and 106328b07674SHaibo Chen * data_strobe line, if the delay time is larger than one clock cycle, 1064d04f8d5bSBenoît Thébaudeau * then CLK and data_strobe line will be misaligned, read error shows up. 106528b07674SHaibo Chen */ 106628b07674SHaibo Chen static void esdhc_set_strobe_dll(struct sdhci_host *host) 106728b07674SHaibo Chen { 10685bd2acdcSHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 10695bd2acdcSHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 10705bd2acdcSHaibo Chen u32 strobe_delay; 107128b07674SHaibo Chen u32 v; 1072373e800bSHaibo Chen int ret; 107328b07674SHaibo Chen 10747ac6da26SDong Aisheng /* disable clock before enabling strobe dll */ 10757ac6da26SDong Aisheng writel(readl(host->ioaddr + ESDHC_VENDOR_SPEC) & 10767ac6da26SDong Aisheng ~ESDHC_VENDOR_SPEC_FRC_SDCLK_ON, 10777ac6da26SDong Aisheng host->ioaddr + ESDHC_VENDOR_SPEC); 1078f581e909SHaibo Chen esdhc_wait_for_card_clock_gate_off(host); 10797ac6da26SDong Aisheng 108028b07674SHaibo Chen /* force a reset on strobe dll */ 108128b07674SHaibo Chen writel(ESDHC_STROBE_DLL_CTRL_RESET, 108228b07674SHaibo Chen host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10832eaf5a53SBOUGH CHEN /* clear the reset bit on strobe dll before any setting */ 10842eaf5a53SBOUGH CHEN writel(0, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 10852eaf5a53SBOUGH CHEN 108628b07674SHaibo Chen /* 108728b07674SHaibo Chen * enable strobe dll ctrl and adjust the delay target 108828b07674SHaibo Chen * for the uSDHC loopback read clock 108928b07674SHaibo Chen */ 10905bd2acdcSHaibo Chen if (imx_data->boarddata.strobe_dll_delay_target) 10915bd2acdcSHaibo Chen strobe_delay = imx_data->boarddata.strobe_dll_delay_target; 10925bd2acdcSHaibo Chen else 10935bd2acdcSHaibo Chen strobe_delay = ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT; 109428b07674SHaibo Chen v = ESDHC_STROBE_DLL_CTRL_ENABLE | 10952eaf5a53SBOUGH CHEN ESDHC_STROBE_DLL_CTRL_SLV_UPDATE_INT_DEFAULT | 10965bd2acdcSHaibo Chen (strobe_delay << ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT); 109728b07674SHaibo Chen writel(v, host->ioaddr + ESDHC_STROBE_DLL_CTRL); 1098373e800bSHaibo Chen 1099373e800bSHaibo Chen /* wait max 50us to get the REF/SLV lock */ 1100373e800bSHaibo Chen ret = readl_poll_timeout(host->ioaddr + ESDHC_STROBE_DLL_STATUS, v, 1101373e800bSHaibo Chen ((v & ESDHC_STROBE_DLL_STS_REF_LOCK) && (v & ESDHC_STROBE_DLL_STS_SLV_LOCK)), 1, 50); 1102373e800bSHaibo Chen if (ret == -ETIMEDOUT) 110328b07674SHaibo Chen dev_warn(mmc_dev(host->mmc), 1104373e800bSHaibo Chen "warning! HS400 strobe DLL status REF/SLV not lock in 50us, STROBE DLL status is %x!\n", v); 110528b07674SHaibo Chen } 110628b07674SHaibo Chen 1107d9370424SHaibo Chen static void esdhc_reset_tuning(struct sdhci_host *host) 1108d9370424SHaibo Chen { 1109d9370424SHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1110d9370424SHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1111d9370424SHaibo Chen u32 ctrl; 1112d9370424SHaibo Chen 1113d04f8d5bSBenoît Thébaudeau /* Reset the tuning circuit */ 1114d9370424SHaibo Chen if (esdhc_is_usdhc(imx_data)) { 1115d9370424SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1116d9370424SHaibo Chen ctrl = readl(host->ioaddr + ESDHC_MIX_CTRL); 1117d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1118d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_FBCLK_SEL; 1119d9370424SHaibo Chen writel(ctrl, host->ioaddr + ESDHC_MIX_CTRL); 1120d9370424SHaibo Chen writel(0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1121d9370424SHaibo Chen } else if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 1122869f8a69SAdrian Hunter ctrl = readl(host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1123d9370424SHaibo Chen ctrl &= ~ESDHC_MIX_CTRL_SMPCLK_SEL; 1124869f8a69SAdrian Hunter writel(ctrl, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1125d9370424SHaibo Chen } 1126d9370424SHaibo Chen } 1127d9370424SHaibo Chen } 1128d9370424SHaibo Chen 1129850a29b8SRussell King static void esdhc_set_uhs_signaling(struct sdhci_host *host, unsigned timing) 1130ad93220dSDong Aisheng { 113128b07674SHaibo Chen u32 m; 1132ad93220dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1133070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1134602519b2SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 1135ad93220dSDong Aisheng 113628b07674SHaibo Chen /* disable ddr mode and disable HS400 mode */ 113728b07674SHaibo Chen m = readl(host->ioaddr + ESDHC_MIX_CTRL); 113828b07674SHaibo Chen m &= ~(ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN); 113928b07674SHaibo Chen imx_data->is_ddr = 0; 114028b07674SHaibo Chen 1141850a29b8SRussell King switch (timing) { 1142ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR12: 1143ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR25: 1144ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR50: 1145ad93220dSDong Aisheng case MMC_TIMING_UHS_SDR104: 1146de0a0decSBOUGH CHEN case MMC_TIMING_MMC_HS: 1147429a5b45SDong Aisheng case MMC_TIMING_MMC_HS200: 114828b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1149ad93220dSDong Aisheng break; 1150ad93220dSDong Aisheng case MMC_TIMING_UHS_DDR50: 115169f5bf38SAisheng Dong case MMC_TIMING_MMC_DDR52: 115228b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN; 115328b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 1154de5bdbffSDong Aisheng imx_data->is_ddr = 1; 1155602519b2SDong Aisheng if (boarddata->delay_line) { 1156602519b2SDong Aisheng u32 v; 1157602519b2SDong Aisheng v = boarddata->delay_line << 1158602519b2SDong Aisheng ESDHC_DLL_OVERRIDE_VAL_SHIFT | 1159602519b2SDong Aisheng (1 << ESDHC_DLL_OVERRIDE_EN_SHIFT); 1160602519b2SDong Aisheng if (is_imx53_esdhc(imx_data)) 1161602519b2SDong Aisheng v <<= 1; 1162602519b2SDong Aisheng writel(v, host->ioaddr + ESDHC_DLL_CTRL); 1163602519b2SDong Aisheng } 1164ad93220dSDong Aisheng break; 116528b07674SHaibo Chen case MMC_TIMING_MMC_HS400: 116628b07674SHaibo Chen m |= ESDHC_MIX_CTRL_DDREN | ESDHC_MIX_CTRL_HS400_EN; 116728b07674SHaibo Chen writel(m, host->ioaddr + ESDHC_MIX_CTRL); 116828b07674SHaibo Chen imx_data->is_ddr = 1; 11697ac6da26SDong Aisheng /* update clock after enable DDR for strobe DLL lock */ 11707ac6da26SDong Aisheng host->ops->set_clock(host, host->clock); 117128b07674SHaibo Chen esdhc_set_strobe_dll(host); 117228b07674SHaibo Chen break; 1173d9370424SHaibo Chen case MMC_TIMING_LEGACY: 1174d9370424SHaibo Chen default: 1175d9370424SHaibo Chen esdhc_reset_tuning(host); 1176d9370424SHaibo Chen break; 1177ad93220dSDong Aisheng } 1178ad93220dSDong Aisheng 1179850a29b8SRussell King esdhc_change_pinstate(host, timing); 1180ad93220dSDong Aisheng } 1181ad93220dSDong Aisheng 11820718e59aSRussell King static void esdhc_reset(struct sdhci_host *host, u8 mask) 11830718e59aSRussell King { 11840718e59aSRussell King sdhci_reset(host, mask); 11850718e59aSRussell King 11860718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); 11870718e59aSRussell King sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); 11880718e59aSRussell King } 11890718e59aSRussell King 119010fd0ad9SAisheng Dong static unsigned int esdhc_get_max_timeout_count(struct sdhci_host *host) 119110fd0ad9SAisheng Dong { 119210fd0ad9SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1193070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 119410fd0ad9SAisheng Dong 1195d04f8d5bSBenoît Thébaudeau /* Doc Erratum: the uSDHC actual maximum timeout count is 1 << 29 */ 11962fb0b02bSHaibo Chen return esdhc_is_usdhc(imx_data) ? 1 << 29 : 1 << 27; 119710fd0ad9SAisheng Dong } 119810fd0ad9SAisheng Dong 1199e33eb8e2SAisheng Dong static void esdhc_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) 1200e33eb8e2SAisheng Dong { 1201e33eb8e2SAisheng Dong struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1202070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1203e33eb8e2SAisheng Dong 1204e33eb8e2SAisheng Dong /* use maximum timeout counter */ 1205a215186dSHaibo Chen esdhc_clrset_le(host, ESDHC_SYS_CTRL_DTOCV_MASK, 1206a215186dSHaibo Chen esdhc_is_usdhc(imx_data) ? 0xF : 0xE, 1207e33eb8e2SAisheng Dong SDHCI_TIMEOUT_CONTROL); 1208e33eb8e2SAisheng Dong } 1209e33eb8e2SAisheng Dong 1210bb6e3581SBOUGH CHEN static u32 esdhc_cqhci_irq(struct sdhci_host *host, u32 intmask) 1211bb6e3581SBOUGH CHEN { 1212bb6e3581SBOUGH CHEN int cmd_error = 0; 1213bb6e3581SBOUGH CHEN int data_error = 0; 1214bb6e3581SBOUGH CHEN 1215bb6e3581SBOUGH CHEN if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 1216bb6e3581SBOUGH CHEN return intmask; 1217bb6e3581SBOUGH CHEN 1218bb6e3581SBOUGH CHEN cqhci_irq(host->mmc, intmask, cmd_error, data_error); 1219bb6e3581SBOUGH CHEN 1220bb6e3581SBOUGH CHEN return 0; 1221bb6e3581SBOUGH CHEN } 1222bb6e3581SBOUGH CHEN 12236e9fd28eSDong Aisheng static struct sdhci_ops sdhci_esdhc_ops = { 1224e149860dSRichard Zhu .read_l = esdhc_readl_le, 12250c6d49ceSWolfram Sang .read_w = esdhc_readw_le, 122677da3da0SAaron Brice .read_b = esdhc_readb_le, 1227e149860dSRichard Zhu .write_l = esdhc_writel_le, 12280c6d49ceSWolfram Sang .write_w = esdhc_writew_le, 12290c6d49ceSWolfram Sang .write_b = esdhc_writeb_le, 12308ba9580aSLucas Stach .set_clock = esdhc_pltfm_set_clock, 12310ddf03c9SLucas Stach .get_max_clock = esdhc_pltfm_get_max_clock, 12320c6d49ceSWolfram Sang .get_min_clock = esdhc_pltfm_get_min_clock, 123310fd0ad9SAisheng Dong .get_max_timeout_count = esdhc_get_max_timeout_count, 1234913413c3SShawn Guo .get_ro = esdhc_pltfm_get_ro, 1235e33eb8e2SAisheng Dong .set_timeout = esdhc_set_timeout, 12362317f56cSRussell King .set_bus_width = esdhc_pltfm_set_bus_width, 1237ad93220dSDong Aisheng .set_uhs_signaling = esdhc_set_uhs_signaling, 12380718e59aSRussell King .reset = esdhc_reset, 1239bb6e3581SBOUGH CHEN .irq = esdhc_cqhci_irq, 12400c6d49ceSWolfram Sang }; 12410c6d49ceSWolfram Sang 12421db5eebfSLars-Peter Clausen static const struct sdhci_pltfm_data sdhci_esdhc_imx_pdata = { 124397e4ba6aSRichard Zhu .quirks = ESDHC_DEFAULT_QUIRKS | SDHCI_QUIRK_NO_HISPD_BIT 124497e4ba6aSRichard Zhu | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC 124597e4ba6aSRichard Zhu | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC 124685d6509dSShawn Guo | SDHCI_QUIRK_BROKEN_CARD_DETECTION, 124785d6509dSShawn Guo .ops = &sdhci_esdhc_ops, 124885d6509dSShawn Guo }; 124985d6509dSShawn Guo 1250f3f5cf3dSDong Aisheng static void sdhci_esdhc_imx_hwinit(struct sdhci_host *host) 1251f3f5cf3dSDong Aisheng { 1252f3f5cf3dSDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1253f3f5cf3dSDong Aisheng struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1254982cf37dSHaibo Chen struct cqhci_host *cq_host = host->mmc->cqe_private; 12552b16cf32SDong Aisheng int tmp; 1256f3f5cf3dSDong Aisheng 1257f3f5cf3dSDong Aisheng if (esdhc_is_usdhc(imx_data)) { 1258f3f5cf3dSDong Aisheng /* 1259f3f5cf3dSDong Aisheng * The imx6q ROM code will change the default watermark 1260f3f5cf3dSDong Aisheng * level setting to something insane. Change it back here. 1261f3f5cf3dSDong Aisheng */ 1262f3f5cf3dSDong Aisheng writel(ESDHC_WTMK_DEFAULT_VAL, host->ioaddr + ESDHC_WTMK_LVL); 1263f3f5cf3dSDong Aisheng 1264f3f5cf3dSDong Aisheng /* 1265f3f5cf3dSDong Aisheng * ROM code will change the bit burst_length_enable setting 1266d04f8d5bSBenoît Thébaudeau * to zero if this usdhc is chosen to boot system. Change 1267f3f5cf3dSDong Aisheng * it back here, otherwise it will impact the performance a 1268f3f5cf3dSDong Aisheng * lot. This bit is used to enable/disable the burst length 1269d04f8d5bSBenoît Thébaudeau * for the external AHB2AXI bridge. It's useful especially 1270f3f5cf3dSDong Aisheng * for INCR transfer because without burst length indicator, 1271f3f5cf3dSDong Aisheng * the AHB2AXI bridge does not know the burst length in 1272f3f5cf3dSDong Aisheng * advance. And without burst length indicator, AHB INCR 1273f3f5cf3dSDong Aisheng * transfer can only be converted to singles on the AXI side. 1274f3f5cf3dSDong Aisheng */ 1275f3f5cf3dSDong Aisheng writel(readl(host->ioaddr + SDHCI_HOST_CONTROL) 1276f3f5cf3dSDong Aisheng | ESDHC_BURST_LEN_EN_INCR, 1277f3f5cf3dSDong Aisheng host->ioaddr + SDHCI_HOST_CONTROL); 1278e30be063SBOUGH CHEN 1279f3f5cf3dSDong Aisheng /* 1280d04f8d5bSBenoît Thébaudeau * erratum ESDHC_FLAG_ERR004536 fix for MX6Q TO1.2 and MX6DL 1281f3f5cf3dSDong Aisheng * TO1.1, it's harmless for MX6SL 1282f3f5cf3dSDong Aisheng */ 1283e30be063SBOUGH CHEN writel(readl(host->ioaddr + 0x6c) & ~BIT(7), 1284f3f5cf3dSDong Aisheng host->ioaddr + 0x6c); 1285f3f5cf3dSDong Aisheng 1286f3f5cf3dSDong Aisheng /* disable DLL_CTRL delay line settings */ 1287f3f5cf3dSDong Aisheng writel(0x0, host->ioaddr + ESDHC_DLL_CTRL); 12882b16cf32SDong Aisheng 1289bcdb5301SBOUGH CHEN /* 1290bcdb5301SBOUGH CHEN * For the case of command with busy, if set the bit 1291bcdb5301SBOUGH CHEN * ESDHC_VEND_SPEC2_EN_BUSY_IRQ, USDHC will generate a 1292bcdb5301SBOUGH CHEN * transfer complete interrupt when busy is deasserted. 1293bcdb5301SBOUGH CHEN * When CQHCI use DCMD to send a CMD need R1b respons, 1294bcdb5301SBOUGH CHEN * CQHCI require to set ESDHC_VEND_SPEC2_EN_BUSY_IRQ, 1295bcdb5301SBOUGH CHEN * otherwise DCMD will always meet timeout waiting for 1296bcdb5301SBOUGH CHEN * hardware interrupt issue. 1297bcdb5301SBOUGH CHEN */ 1298bcdb5301SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1299bcdb5301SBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_VEND_SPEC2); 1300bcdb5301SBOUGH CHEN tmp |= ESDHC_VEND_SPEC2_EN_BUSY_IRQ; 1301bcdb5301SBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_VEND_SPEC2); 1302bcdb5301SBOUGH CHEN 1303bcdb5301SBOUGH CHEN host->quirks &= ~SDHCI_QUIRK_NO_BUSY_IRQ; 1304bcdb5301SBOUGH CHEN } 1305bcdb5301SBOUGH CHEN 13062b16cf32SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_STD_TUNING) { 13072b16cf32SDong Aisheng tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 13082b16cf32SDong Aisheng tmp |= ESDHC_STD_TUNING_EN | 13092b16cf32SDong Aisheng ESDHC_TUNING_START_TAP_DEFAULT; 13102b16cf32SDong Aisheng if (imx_data->boarddata.tuning_start_tap) { 13112b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_START_TAP_MASK; 13122b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_start_tap; 13132b16cf32SDong Aisheng } 13142b16cf32SDong Aisheng 13152b16cf32SDong Aisheng if (imx_data->boarddata.tuning_step) { 13162b16cf32SDong Aisheng tmp &= ~ESDHC_TUNING_STEP_MASK; 13172b16cf32SDong Aisheng tmp |= imx_data->boarddata.tuning_step 13182b16cf32SDong Aisheng << ESDHC_TUNING_STEP_SHIFT; 13192b16cf32SDong Aisheng } 1320*16e40e5bSHaibo Chen 1321*16e40e5bSHaibo Chen /* Disable the CMD CRC check for tuning, if not, need to 1322*16e40e5bSHaibo Chen * add some delay after every tuning command, because 1323*16e40e5bSHaibo Chen * hardware standard tuning logic will directly go to next 1324*16e40e5bSHaibo Chen * step once it detect the CMD CRC error, will not wait for 1325*16e40e5bSHaibo Chen * the card side to finally send out the tuning data, trigger 1326*16e40e5bSHaibo Chen * the buffer read ready interrupt immediately. If usdhc send 1327*16e40e5bSHaibo Chen * the next tuning command some eMMC card will stuck, can't 1328*16e40e5bSHaibo Chen * response, block the tuning procedure or the first command 1329*16e40e5bSHaibo Chen * after the whole tuning procedure always can't get any response. 1330*16e40e5bSHaibo Chen */ 1331*16e40e5bSHaibo Chen tmp |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE; 13322b16cf32SDong Aisheng writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 1333a98c557eSBOUGH CHEN } else if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) { 1334a98c557eSBOUGH CHEN /* 1335a98c557eSBOUGH CHEN * ESDHC_STD_TUNING_EN may be configed in bootloader 1336a98c557eSBOUGH CHEN * or ROM code, so clear this bit here to make sure 1337a98c557eSBOUGH CHEN * the manual tuning can work. 1338a98c557eSBOUGH CHEN */ 1339a98c557eSBOUGH CHEN tmp = readl(host->ioaddr + ESDHC_TUNING_CTRL); 1340a98c557eSBOUGH CHEN tmp &= ~ESDHC_STD_TUNING_EN; 1341a98c557eSBOUGH CHEN writel(tmp, host->ioaddr + ESDHC_TUNING_CTRL); 13422b16cf32SDong Aisheng } 1343982cf37dSHaibo Chen 1344982cf37dSHaibo Chen /* 1345982cf37dSHaibo Chen * On i.MX8MM, we are running Dual Linux OS, with 1st Linux using SD Card 1346982cf37dSHaibo Chen * as rootfs storage, 2nd Linux using eMMC as rootfs storage. We let the 1347982cf37dSHaibo Chen * the 1st linux configure power/clock for the 2nd Linux. 1348982cf37dSHaibo Chen * 1349982cf37dSHaibo Chen * When the 2nd Linux is booting into rootfs stage, we let the 1st Linux 1350982cf37dSHaibo Chen * to destroy the 2nd linux, then restart the 2nd linux, we met SDHCI dump. 1351982cf37dSHaibo Chen * After we clear the pending interrupt and halt CQCTL, issue gone. 1352982cf37dSHaibo Chen */ 1353982cf37dSHaibo Chen if (cq_host) { 1354982cf37dSHaibo Chen tmp = cqhci_readl(cq_host, CQHCI_IS); 1355982cf37dSHaibo Chen cqhci_writel(cq_host, tmp, CQHCI_IS); 1356982cf37dSHaibo Chen cqhci_writel(cq_host, CQHCI_HALT, CQHCI_CTL); 1357982cf37dSHaibo Chen } 1358f3f5cf3dSDong Aisheng } 1359f3f5cf3dSDong Aisheng } 1360f3f5cf3dSDong Aisheng 1361bb6e3581SBOUGH CHEN static void esdhc_cqe_enable(struct mmc_host *mmc) 1362bb6e3581SBOUGH CHEN { 1363bb6e3581SBOUGH CHEN struct sdhci_host *host = mmc_priv(mmc); 136485236d2bSBOUGH CHEN struct cqhci_host *cq_host = mmc->cqe_private; 1365bb6e3581SBOUGH CHEN u32 reg; 1366bb6e3581SBOUGH CHEN u16 mode; 1367bb6e3581SBOUGH CHEN int count = 10; 1368bb6e3581SBOUGH CHEN 1369bb6e3581SBOUGH CHEN /* 1370bb6e3581SBOUGH CHEN * CQE gets stuck if it sees Buffer Read Enable bit set, which can be 1371bb6e3581SBOUGH CHEN * the case after tuning, so ensure the buffer is drained. 1372bb6e3581SBOUGH CHEN */ 1373bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1374bb6e3581SBOUGH CHEN while (reg & SDHCI_DATA_AVAILABLE) { 1375bb6e3581SBOUGH CHEN sdhci_readl(host, SDHCI_BUFFER); 1376bb6e3581SBOUGH CHEN reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 1377bb6e3581SBOUGH CHEN if (count-- == 0) { 1378bb6e3581SBOUGH CHEN dev_warn(mmc_dev(host->mmc), 1379bb6e3581SBOUGH CHEN "CQE may get stuck because the Buffer Read Enable bit is set\n"); 1380bb6e3581SBOUGH CHEN break; 1381bb6e3581SBOUGH CHEN } 1382bb6e3581SBOUGH CHEN mdelay(1); 1383bb6e3581SBOUGH CHEN } 1384bb6e3581SBOUGH CHEN 1385bb6e3581SBOUGH CHEN /* 1386bb6e3581SBOUGH CHEN * Runtime resume will reset the entire host controller, which 1387bb6e3581SBOUGH CHEN * will also clear the DMAEN/BCEN of register ESDHC_MIX_CTRL. 1388bb6e3581SBOUGH CHEN * Here set DMAEN and BCEN when enable CMDQ. 1389bb6e3581SBOUGH CHEN */ 1390bb6e3581SBOUGH CHEN mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); 1391bb6e3581SBOUGH CHEN if (host->flags & SDHCI_REQ_USE_DMA) 1392bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_DMA; 1393bb6e3581SBOUGH CHEN if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) 1394bb6e3581SBOUGH CHEN mode |= SDHCI_TRNS_BLK_CNT_EN; 1395bb6e3581SBOUGH CHEN sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); 1396bb6e3581SBOUGH CHEN 139785236d2bSBOUGH CHEN /* 139885236d2bSBOUGH CHEN * Though Runtime resume reset the entire host controller, 139985236d2bSBOUGH CHEN * but do not impact the CQHCI side, need to clear the 140085236d2bSBOUGH CHEN * HALT bit, avoid CQHCI stuck in the first request when 140185236d2bSBOUGH CHEN * system resume back. 140285236d2bSBOUGH CHEN */ 140385236d2bSBOUGH CHEN cqhci_writel(cq_host, 0, CQHCI_CTL); 140485236d2bSBOUGH CHEN if (cqhci_readl(cq_host, CQHCI_CTL) && CQHCI_HALT) 140585236d2bSBOUGH CHEN dev_err(mmc_dev(host->mmc), 140685236d2bSBOUGH CHEN "failed to exit halt state when enable CQE\n"); 140785236d2bSBOUGH CHEN 140885236d2bSBOUGH CHEN 1409bb6e3581SBOUGH CHEN sdhci_cqe_enable(mmc); 1410bb6e3581SBOUGH CHEN } 1411bb6e3581SBOUGH CHEN 1412bb6e3581SBOUGH CHEN static void esdhc_sdhci_dumpregs(struct mmc_host *mmc) 1413bb6e3581SBOUGH CHEN { 1414bb6e3581SBOUGH CHEN sdhci_dumpregs(mmc_priv(mmc)); 1415bb6e3581SBOUGH CHEN } 1416bb6e3581SBOUGH CHEN 1417bb6e3581SBOUGH CHEN static const struct cqhci_host_ops esdhc_cqhci_ops = { 1418bb6e3581SBOUGH CHEN .enable = esdhc_cqe_enable, 1419bb6e3581SBOUGH CHEN .disable = sdhci_cqe_disable, 1420bb6e3581SBOUGH CHEN .dumpregs = esdhc_sdhci_dumpregs, 1421bb6e3581SBOUGH CHEN }; 1422bb6e3581SBOUGH CHEN 1423abfafc2dSShawn Guo #ifdef CONFIG_OF 1424c3be1efdSBill Pemberton static int 1425abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 142607bf2b54SSascha Hauer struct sdhci_host *host, 142791fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1428abfafc2dSShawn Guo { 1429abfafc2dSShawn Guo struct device_node *np = pdev->dev.of_node; 143091fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 14314800e87aSDong Aisheng int ret; 1432abfafc2dSShawn Guo 1433abfafc2dSShawn Guo if (of_get_property(np, "fsl,wp-controller", NULL)) 1434abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_CONTROLLER; 1435abfafc2dSShawn Guo 143674ff81e1SLinus Walleij /* 143774ff81e1SLinus Walleij * If we have this property, then activate WP check. 143874ff81e1SLinus Walleij * Retrieveing and requesting the actual WP GPIO will happen 143974ff81e1SLinus Walleij * in the call to mmc_of_parse(). 144074ff81e1SLinus Walleij */ 144174ff81e1SLinus Walleij if (of_property_read_bool(np, "wp-gpios")) 1442abfafc2dSShawn Guo boarddata->wp_type = ESDHC_WP_GPIO; 1443abfafc2dSShawn Guo 1444d407e30bSHaibo Chen of_property_read_u32(np, "fsl,tuning-step", &boarddata->tuning_step); 1445d87fc966SDong Aisheng of_property_read_u32(np, "fsl,tuning-start-tap", 1446d87fc966SDong Aisheng &boarddata->tuning_start_tap); 1447d407e30bSHaibo Chen 14485bd2acdcSHaibo Chen of_property_read_u32(np, "fsl,strobe-dll-delay-target", 14495bd2acdcSHaibo Chen &boarddata->strobe_dll_delay_target); 1450ad93220dSDong Aisheng if (of_find_property(np, "no-1-8-v", NULL)) 145186f495c5SStefan Agner host->quirks2 |= SDHCI_QUIRK2_NO_1_8_V; 1452ad93220dSDong Aisheng 1453602519b2SDong Aisheng if (of_property_read_u32(np, "fsl,delay-line", &boarddata->delay_line)) 1454602519b2SDong Aisheng boarddata->delay_line = 0; 1455602519b2SDong Aisheng 145607bf2b54SSascha Hauer mmc_of_parse_voltage(np, &host->ocr_mask); 145707bf2b54SSascha Hauer 14582480b720SUlf Hansson if (esdhc_is_usdhc(imx_data)) { 145991fa4252SDong Aisheng imx_data->pins_100mhz = pinctrl_lookup_state(imx_data->pinctrl, 146091fa4252SDong Aisheng ESDHC_PINCTRL_STATE_100MHZ); 146191fa4252SDong Aisheng imx_data->pins_200mhz = pinctrl_lookup_state(imx_data->pinctrl, 146291fa4252SDong Aisheng ESDHC_PINCTRL_STATE_200MHZ); 146391fa4252SDong Aisheng } 146491fa4252SDong Aisheng 146515064119SFabio Estevam /* call to generic mmc_of_parse to support additional capabilities */ 14664800e87aSDong Aisheng ret = mmc_of_parse(host->mmc); 14674800e87aSDong Aisheng if (ret) 14684800e87aSDong Aisheng return ret; 14694800e87aSDong Aisheng 1470287980e4SArnd Bergmann if (mmc_gpio_get_cd(host->mmc) >= 0) 14714800e87aSDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 14724800e87aSDong Aisheng 14734800e87aSDong Aisheng return 0; 1474abfafc2dSShawn Guo } 1475abfafc2dSShawn Guo #else 1476abfafc2dSShawn Guo static inline int 1477abfafc2dSShawn Guo sdhci_esdhc_imx_probe_dt(struct platform_device *pdev, 147807bf2b54SSascha Hauer struct sdhci_host *host, 147991fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 1480abfafc2dSShawn Guo { 1481abfafc2dSShawn Guo return -ENODEV; 1482abfafc2dSShawn Guo } 1483abfafc2dSShawn Guo #endif 1484abfafc2dSShawn Guo 148591fa4252SDong Aisheng static int sdhci_esdhc_imx_probe_nondt(struct platform_device *pdev, 148691fa4252SDong Aisheng struct sdhci_host *host, 148791fa4252SDong Aisheng struct pltfm_imx_data *imx_data) 148891fa4252SDong Aisheng { 148991fa4252SDong Aisheng struct esdhc_platform_data *boarddata = &imx_data->boarddata; 149091fa4252SDong Aisheng int err; 149191fa4252SDong Aisheng 149291fa4252SDong Aisheng if (!host->mmc->parent->platform_data) { 149391fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), "no board data!\n"); 149491fa4252SDong Aisheng return -EINVAL; 149591fa4252SDong Aisheng } 149691fa4252SDong Aisheng 149791fa4252SDong Aisheng imx_data->boarddata = *((struct esdhc_platform_data *) 149891fa4252SDong Aisheng host->mmc->parent->platform_data); 149991fa4252SDong Aisheng /* write_protect */ 150091fa4252SDong Aisheng if (boarddata->wp_type == ESDHC_WP_GPIO) { 15019073d10bSMichał Mirosław host->mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH; 15029073d10bSMichał Mirosław 1503d0052ad9SMichał Mirosław err = mmc_gpiod_request_ro(host->mmc, "wp", 0, 0); 150491fa4252SDong Aisheng if (err) { 150591fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 150691fa4252SDong Aisheng "failed to request write-protect gpio!\n"); 150791fa4252SDong Aisheng return err; 150891fa4252SDong Aisheng } 150991fa4252SDong Aisheng } 151091fa4252SDong Aisheng 151191fa4252SDong Aisheng /* card_detect */ 151291fa4252SDong Aisheng switch (boarddata->cd_type) { 151391fa4252SDong Aisheng case ESDHC_CD_GPIO: 1514d0052ad9SMichał Mirosław err = mmc_gpiod_request_cd(host->mmc, "cd", 0, false, 0); 151591fa4252SDong Aisheng if (err) { 151691fa4252SDong Aisheng dev_err(mmc_dev(host->mmc), 151791fa4252SDong Aisheng "failed to request card-detect gpio!\n"); 151891fa4252SDong Aisheng return err; 151991fa4252SDong Aisheng } 152091fa4252SDong Aisheng /* fall through */ 152191fa4252SDong Aisheng 152291fa4252SDong Aisheng case ESDHC_CD_CONTROLLER: 152391fa4252SDong Aisheng /* we have a working card_detect back */ 152491fa4252SDong Aisheng host->quirks &= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION; 152591fa4252SDong Aisheng break; 152691fa4252SDong Aisheng 152791fa4252SDong Aisheng case ESDHC_CD_PERMANENT: 152891fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_NONREMOVABLE; 152991fa4252SDong Aisheng break; 153091fa4252SDong Aisheng 153191fa4252SDong Aisheng case ESDHC_CD_NONE: 153291fa4252SDong Aisheng break; 153391fa4252SDong Aisheng } 153491fa4252SDong Aisheng 153591fa4252SDong Aisheng switch (boarddata->max_bus_width) { 153691fa4252SDong Aisheng case 8: 153791fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA; 153891fa4252SDong Aisheng break; 153991fa4252SDong Aisheng case 4: 154091fa4252SDong Aisheng host->mmc->caps |= MMC_CAP_4_BIT_DATA; 154191fa4252SDong Aisheng break; 154291fa4252SDong Aisheng case 1: 154391fa4252SDong Aisheng default: 154491fa4252SDong Aisheng host->quirks |= SDHCI_QUIRK_FORCE_1_BIT_DATA; 154591fa4252SDong Aisheng break; 154691fa4252SDong Aisheng } 154791fa4252SDong Aisheng 154891fa4252SDong Aisheng return 0; 154991fa4252SDong Aisheng } 155091fa4252SDong Aisheng 1551c3be1efdSBill Pemberton static int sdhci_esdhc_imx_probe(struct platform_device *pdev) 155295f25efeSWolfram Sang { 1553abfafc2dSShawn Guo const struct of_device_id *of_id = 1554abfafc2dSShawn Guo of_match_device(imx_esdhc_dt_ids, &pdev->dev); 155585d6509dSShawn Guo struct sdhci_pltfm_host *pltfm_host; 155685d6509dSShawn Guo struct sdhci_host *host; 1557bb6e3581SBOUGH CHEN struct cqhci_host *cq_host; 15580c6d49ceSWolfram Sang int err; 1559e149860dSRichard Zhu struct pltfm_imx_data *imx_data; 156095f25efeSWolfram Sang 1561070e6d3fSJisheng Zhang host = sdhci_pltfm_init(pdev, &sdhci_esdhc_imx_pdata, 1562070e6d3fSJisheng Zhang sizeof(*imx_data)); 156385d6509dSShawn Guo if (IS_ERR(host)) 156485d6509dSShawn Guo return PTR_ERR(host); 156585d6509dSShawn Guo 156685d6509dSShawn Guo pltfm_host = sdhci_priv(host); 156785d6509dSShawn Guo 1568070e6d3fSJisheng Zhang imx_data = sdhci_pltfm_priv(pltfm_host); 156957ed3314SShawn Guo 1570f47c4bbfSShawn Guo imx_data->socdata = of_id ? of_id->data : (struct esdhc_soc_data *) 15713770ee8fSShawn Guo pdev->id_entry->driver_data; 157285d6509dSShawn Guo 15731c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1574d1b98305SRafael J. Wysocki cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 15751c4989b0SBOUGH CHEN 157652dac615SSascha Hauer imx_data->clk_ipg = devm_clk_get(&pdev->dev, "ipg"); 157752dac615SSascha Hauer if (IS_ERR(imx_data->clk_ipg)) { 157852dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ipg); 1579e3af31c6SShawn Guo goto free_sdhci; 158095f25efeSWolfram Sang } 158152dac615SSascha Hauer 158252dac615SSascha Hauer imx_data->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 158352dac615SSascha Hauer if (IS_ERR(imx_data->clk_ahb)) { 158452dac615SSascha Hauer err = PTR_ERR(imx_data->clk_ahb); 1585e3af31c6SShawn Guo goto free_sdhci; 158652dac615SSascha Hauer } 158752dac615SSascha Hauer 158852dac615SSascha Hauer imx_data->clk_per = devm_clk_get(&pdev->dev, "per"); 158952dac615SSascha Hauer if (IS_ERR(imx_data->clk_per)) { 159052dac615SSascha Hauer err = PTR_ERR(imx_data->clk_per); 1591e3af31c6SShawn Guo goto free_sdhci; 159252dac615SSascha Hauer } 159352dac615SSascha Hauer 159452dac615SSascha Hauer pltfm_host->clk = imx_data->clk_per; 1595a974862fSDong Aisheng pltfm_host->clock = clk_get_rate(pltfm_host->clk); 159617b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 159717b1eb7fSFabio Estevam if (err) 159817b1eb7fSFabio Estevam goto free_sdhci; 159917b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 160017b1eb7fSFabio Estevam if (err) 160117b1eb7fSFabio Estevam goto disable_per_clk; 160217b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ahb); 160317b1eb7fSFabio Estevam if (err) 160417b1eb7fSFabio Estevam goto disable_ipg_clk; 160595f25efeSWolfram Sang 1606ad93220dSDong Aisheng imx_data->pinctrl = devm_pinctrl_get(&pdev->dev); 1607e62d8b8fSDong Aisheng if (IS_ERR(imx_data->pinctrl)) { 1608e62d8b8fSDong Aisheng err = PTR_ERR(imx_data->pinctrl); 1609b62eee9fSHaibo Chen dev_warn(mmc_dev(host->mmc), "could not get pinctrl\n"); 1610e62d8b8fSDong Aisheng } 1611e62d8b8fSDong Aisheng 161269ed60e0SDong Aisheng if (esdhc_is_usdhc(imx_data)) { 161369ed60e0SDong Aisheng host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 161409c8192bSStefan Agner host->mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1615f6140462SHaibo Chen 1616f6140462SHaibo Chen /* GPIO CD can be set as a wakeup source */ 1617f6140462SHaibo Chen host->mmc->caps |= MMC_CAP_CD_WAKE; 1618f6140462SHaibo Chen 16194245afffSDong Aisheng if (!(imx_data->socdata->flags & ESDHC_FLAG_HS200)) 16204245afffSDong Aisheng host->quirks2 |= SDHCI_QUIRK2_BROKEN_HS200; 1621a75dcbf4SDong Aisheng 1622a75dcbf4SDong Aisheng /* clear tuning bits in case ROM has set it already */ 1623a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_MIX_CTRL); 1624869f8a69SAdrian Hunter writel(0x0, host->ioaddr + SDHCI_AUTO_CMD_STATUS); 1625a75dcbf4SDong Aisheng writel(0x0, host->ioaddr + ESDHC_TUNE_CTRL_STATUS); 1626de3e1dd0SBOUGH CHEN 1627de3e1dd0SBOUGH CHEN /* 1628de3e1dd0SBOUGH CHEN * Link usdhc specific mmc_host_ops execute_tuning function, 1629de3e1dd0SBOUGH CHEN * to replace the standard one in sdhci_ops. 1630de3e1dd0SBOUGH CHEN */ 1631de3e1dd0SBOUGH CHEN host->mmc_host_ops.execute_tuning = usdhc_execute_tuning; 163269ed60e0SDong Aisheng } 1633f750ba9bSShawn Guo 16346e9fd28eSDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_MAN_TUNING) 16356e9fd28eSDong Aisheng sdhci_esdhc_ops.platform_execute_tuning = 16366e9fd28eSDong Aisheng esdhc_executing_tuning; 16378b2bb0adSDong Aisheng 163818094430SDong Aisheng if (imx_data->socdata->flags & ESDHC_FLAG_ERR004536) 163918094430SDong Aisheng host->quirks |= SDHCI_QUIRK_BROKEN_ADMA; 164018094430SDong Aisheng 164128b07674SHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_HS400) 164228b07674SHaibo Chen host->quirks2 |= SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400; 164328b07674SHaibo Chen 164474898cbcSHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_BROKEN_AUTO_CMD23) 164574898cbcSHaibo Chen host->quirks2 |= SDHCI_QUIRK2_ACMD23_BROKEN; 164674898cbcSHaibo Chen 1647029e2476SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_HS400_ES) { 1648029e2476SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_HS400_ES; 1649029e2476SBOUGH CHEN host->mmc_host_ops.hs400_enhanced_strobe = 1650029e2476SBOUGH CHEN esdhc_hs400_enhanced_strobe; 1651029e2476SBOUGH CHEN } 1652029e2476SBOUGH CHEN 1653bb6e3581SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_CQHCI) { 1654bcdb5301SBOUGH CHEN host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 1655bb6e3581SBOUGH CHEN cq_host = devm_kzalloc(&pdev->dev, sizeof(*cq_host), GFP_KERNEL); 16569a633f3bSWei Yongjun if (!cq_host) { 16579a633f3bSWei Yongjun err = -ENOMEM; 1658bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1659bb6e3581SBOUGH CHEN } 1660bb6e3581SBOUGH CHEN 1661bb6e3581SBOUGH CHEN cq_host->mmio = host->ioaddr + ESDHC_CQHCI_ADDR_OFFSET; 1662bb6e3581SBOUGH CHEN cq_host->ops = &esdhc_cqhci_ops; 1663bb6e3581SBOUGH CHEN 1664bb6e3581SBOUGH CHEN err = cqhci_init(cq_host, host->mmc, false); 1665bb6e3581SBOUGH CHEN if (err) 1666bb6e3581SBOUGH CHEN goto disable_ahb_clk; 1667bb6e3581SBOUGH CHEN } 1668bb6e3581SBOUGH CHEN 166991fa4252SDong Aisheng if (of_id) 167091fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_dt(pdev, host, imx_data); 167191fa4252SDong Aisheng else 167291fa4252SDong Aisheng err = sdhci_esdhc_imx_probe_nondt(pdev, host, imx_data); 167391fa4252SDong Aisheng if (err) 167417b1eb7fSFabio Estevam goto disable_ahb_clk; 1675ad93220dSDong Aisheng 1676f3f5cf3dSDong Aisheng sdhci_esdhc_imx_hwinit(host); 1677f3f5cf3dSDong Aisheng 167885d6509dSShawn Guo err = sdhci_add_host(host); 167985d6509dSShawn Guo if (err) 168017b1eb7fSFabio Estevam goto disable_ahb_clk; 168185d6509dSShawn Guo 168289d7e5c1SDong Aisheng pm_runtime_set_active(&pdev->dev); 168389d7e5c1SDong Aisheng pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 168489d7e5c1SDong Aisheng pm_runtime_use_autosuspend(&pdev->dev); 168589d7e5c1SDong Aisheng pm_suspend_ignore_children(&pdev->dev, 1); 168677903c01SUlf Hansson pm_runtime_enable(&pdev->dev); 168789d7e5c1SDong Aisheng 16887e29c306SWolfram Sang return 0; 16897e29c306SWolfram Sang 169017b1eb7fSFabio Estevam disable_ahb_clk: 169152dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 169217b1eb7fSFabio Estevam disable_ipg_clk: 169317b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 169417b1eb7fSFabio Estevam disable_per_clk: 169517b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1696e3af31c6SShawn Guo free_sdhci: 16971c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1698d1b98305SRafael J. Wysocki cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 169985d6509dSShawn Guo sdhci_pltfm_free(pdev); 170085d6509dSShawn Guo return err; 170195f25efeSWolfram Sang } 170295f25efeSWolfram Sang 17036e0ee714SBill Pemberton static int sdhci_esdhc_imx_remove(struct platform_device *pdev) 170495f25efeSWolfram Sang { 170585d6509dSShawn Guo struct sdhci_host *host = platform_get_drvdata(pdev); 170695f25efeSWolfram Sang struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1707070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 170885d6509dSShawn Guo int dead = (readl(host->ioaddr + SDHCI_INT_STATUS) == 0xffffffff); 170985d6509dSShawn Guo 17100b414368SUlf Hansson pm_runtime_get_sync(&pdev->dev); 17110b414368SUlf Hansson pm_runtime_disable(&pdev->dev); 17120b414368SUlf Hansson pm_runtime_put_noidle(&pdev->dev); 17130b414368SUlf Hansson 171485d6509dSShawn Guo sdhci_remove_host(host, dead); 17150c6d49ceSWolfram Sang 171652dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_per); 171752dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ipg); 171852dac615SSascha Hauer clk_disable_unprepare(imx_data->clk_ahb); 171952dac615SSascha Hauer 17201c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1721d1b98305SRafael J. Wysocki cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 17221c4989b0SBOUGH CHEN 172385d6509dSShawn Guo sdhci_pltfm_free(pdev); 172485d6509dSShawn Guo 172585d6509dSShawn Guo return 0; 172695f25efeSWolfram Sang } 172795f25efeSWolfram Sang 17282788ed42SUlf Hansson #ifdef CONFIG_PM_SLEEP 172904143fbaSDong Aisheng static int sdhci_esdhc_suspend(struct device *dev) 173004143fbaSDong Aisheng { 17313e3274abSUlf Hansson struct sdhci_host *host = dev_get_drvdata(dev); 1732a26a4f1bSHaibo Chen struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1733a26a4f1bSHaibo Chen struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 1734bb6e3581SBOUGH CHEN int ret; 1735bb6e3581SBOUGH CHEN 1736bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1737bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1738bb6e3581SBOUGH CHEN if (ret) 1739bb6e3581SBOUGH CHEN return ret; 1740bb6e3581SBOUGH CHEN } 17413e3274abSUlf Hansson 1742a26a4f1bSHaibo Chen if ((imx_data->socdata->flags & ESDHC_FLAG_STATE_LOST_IN_LPMODE) && 1743a26a4f1bSHaibo Chen (host->tuning_mode != SDHCI_TUNING_MODE_1)) { 1744a26a4f1bSHaibo Chen mmc_retune_timer_stop(host->mmc); 1745a26a4f1bSHaibo Chen mmc_retune_needed(host->mmc); 1746a26a4f1bSHaibo Chen } 1747a26a4f1bSHaibo Chen 1748d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1749d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1750d38dcad4SAdrian Hunter 1751af8fade4SHaibo Chen ret = sdhci_suspend_host(host); 1752f6140462SHaibo Chen if (ret) 1753f6140462SHaibo Chen return ret; 1754f6140462SHaibo Chen 1755f6140462SHaibo Chen ret = pinctrl_pm_select_sleep_state(dev); 1756f6140462SHaibo Chen if (ret) 1757f6140462SHaibo Chen return ret; 1758f6140462SHaibo Chen 1759f6140462SHaibo Chen ret = mmc_gpio_set_cd_wake(host->mmc, true); 1760af8fade4SHaibo Chen 1761af8fade4SHaibo Chen return ret; 176204143fbaSDong Aisheng } 176304143fbaSDong Aisheng 176404143fbaSDong Aisheng static int sdhci_esdhc_resume(struct device *dev) 176504143fbaSDong Aisheng { 1766cc17e129SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 1767bb6e3581SBOUGH CHEN int ret; 1768cc17e129SDong Aisheng 1769af8fade4SHaibo Chen ret = pinctrl_pm_select_default_state(dev); 1770af8fade4SHaibo Chen if (ret) 1771af8fade4SHaibo Chen return ret; 1772af8fade4SHaibo Chen 177319dbfdd3SDong Aisheng /* re-initialize hw state in case it's lost in low power mode */ 177419dbfdd3SDong Aisheng sdhci_esdhc_imx_hwinit(host); 1775cc17e129SDong Aisheng 1776bb6e3581SBOUGH CHEN ret = sdhci_resume_host(host); 1777bb6e3581SBOUGH CHEN if (ret) 1778bb6e3581SBOUGH CHEN return ret; 1779bb6e3581SBOUGH CHEN 1780bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1781bb6e3581SBOUGH CHEN ret = cqhci_resume(host->mmc); 1782bb6e3581SBOUGH CHEN 1783f6140462SHaibo Chen if (!ret) 1784f6140462SHaibo Chen ret = mmc_gpio_set_cd_wake(host->mmc, false); 1785f6140462SHaibo Chen 1786bb6e3581SBOUGH CHEN return ret; 178704143fbaSDong Aisheng } 17882788ed42SUlf Hansson #endif 178904143fbaSDong Aisheng 17902788ed42SUlf Hansson #ifdef CONFIG_PM 179189d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_suspend(struct device *dev) 179289d7e5c1SDong Aisheng { 179389d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 179489d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1795070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 179689d7e5c1SDong Aisheng int ret; 179789d7e5c1SDong Aisheng 1798bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) { 1799bb6e3581SBOUGH CHEN ret = cqhci_suspend(host->mmc); 1800bb6e3581SBOUGH CHEN if (ret) 1801bb6e3581SBOUGH CHEN return ret; 1802bb6e3581SBOUGH CHEN } 1803bb6e3581SBOUGH CHEN 180489d7e5c1SDong Aisheng ret = sdhci_runtime_suspend_host(host); 1805371d39faSMichael Trimarchi if (ret) 1806371d39faSMichael Trimarchi return ret; 180789d7e5c1SDong Aisheng 1808d38dcad4SAdrian Hunter if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1809d38dcad4SAdrian Hunter mmc_retune_needed(host->mmc); 1810d38dcad4SAdrian Hunter 18113602785bSMichael Trimarchi imx_data->actual_clock = host->mmc->actual_clock; 18123602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, 0); 181389d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_per); 181489d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ipg); 181589d7e5c1SDong Aisheng clk_disable_unprepare(imx_data->clk_ahb); 181689d7e5c1SDong Aisheng 18171c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1818d1b98305SRafael J. Wysocki cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 18191c4989b0SBOUGH CHEN 182089d7e5c1SDong Aisheng return ret; 182189d7e5c1SDong Aisheng } 182289d7e5c1SDong Aisheng 182389d7e5c1SDong Aisheng static int sdhci_esdhc_runtime_resume(struct device *dev) 182489d7e5c1SDong Aisheng { 182589d7e5c1SDong Aisheng struct sdhci_host *host = dev_get_drvdata(dev); 182689d7e5c1SDong Aisheng struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1827070e6d3fSJisheng Zhang struct pltfm_imx_data *imx_data = sdhci_pltfm_priv(pltfm_host); 182817b1eb7fSFabio Estevam int err; 182989d7e5c1SDong Aisheng 18301c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1831d1b98305SRafael J. Wysocki cpu_latency_qos_add_request(&imx_data->pm_qos_req, 0); 18321c4989b0SBOUGH CHEN 18335c11f1ffSHaibo Chen if (imx_data->socdata->flags & ESDHC_FLAG_CLK_RATE_LOST_IN_PM_RUNTIME) 18345c11f1ffSHaibo Chen clk_set_rate(imx_data->clk_per, pltfm_host->clock); 18355c11f1ffSHaibo Chen 1836a0ad3087SMichael Trimarchi err = clk_prepare_enable(imx_data->clk_ahb); 1837a0ad3087SMichael Trimarchi if (err) 18381c4989b0SBOUGH CHEN goto remove_pm_qos_request; 1839a0ad3087SMichael Trimarchi 184017b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_per); 184117b1eb7fSFabio Estevam if (err) 1842a0ad3087SMichael Trimarchi goto disable_ahb_clk; 1843af5d2b7bSUlf Hansson 184417b1eb7fSFabio Estevam err = clk_prepare_enable(imx_data->clk_ipg); 184517b1eb7fSFabio Estevam if (err) 184617b1eb7fSFabio Estevam goto disable_per_clk; 1847af5d2b7bSUlf Hansson 18483602785bSMichael Trimarchi esdhc_pltfm_set_clock(host, imx_data->actual_clock); 1849a0ad3087SMichael Trimarchi 1850c6303c5dSBaolin Wang err = sdhci_runtime_resume_host(host, 0); 185117b1eb7fSFabio Estevam if (err) 1852a0ad3087SMichael Trimarchi goto disable_ipg_clk; 185389d7e5c1SDong Aisheng 1854bb6e3581SBOUGH CHEN if (host->mmc->caps2 & MMC_CAP2_CQE) 1855bb6e3581SBOUGH CHEN err = cqhci_resume(host->mmc); 1856bb6e3581SBOUGH CHEN 1857bb6e3581SBOUGH CHEN return err; 185817b1eb7fSFabio Estevam 185917b1eb7fSFabio Estevam disable_ipg_clk: 186017b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_ipg); 186117b1eb7fSFabio Estevam disable_per_clk: 186217b1eb7fSFabio Estevam clk_disable_unprepare(imx_data->clk_per); 1863a0ad3087SMichael Trimarchi disable_ahb_clk: 1864a0ad3087SMichael Trimarchi clk_disable_unprepare(imx_data->clk_ahb); 18651c4989b0SBOUGH CHEN remove_pm_qos_request: 18661c4989b0SBOUGH CHEN if (imx_data->socdata->flags & ESDHC_FLAG_PMQOS) 1867d1b98305SRafael J. Wysocki cpu_latency_qos_remove_request(&imx_data->pm_qos_req); 186817b1eb7fSFabio Estevam return err; 186989d7e5c1SDong Aisheng } 187089d7e5c1SDong Aisheng #endif 187189d7e5c1SDong Aisheng 187289d7e5c1SDong Aisheng static const struct dev_pm_ops sdhci_esdhc_pmops = { 187304143fbaSDong Aisheng SET_SYSTEM_SLEEP_PM_OPS(sdhci_esdhc_suspend, sdhci_esdhc_resume) 187489d7e5c1SDong Aisheng SET_RUNTIME_PM_OPS(sdhci_esdhc_runtime_suspend, 187589d7e5c1SDong Aisheng sdhci_esdhc_runtime_resume, NULL) 187689d7e5c1SDong Aisheng }; 187789d7e5c1SDong Aisheng 187885d6509dSShawn Guo static struct platform_driver sdhci_esdhc_imx_driver = { 187985d6509dSShawn Guo .driver = { 188085d6509dSShawn Guo .name = "sdhci-esdhc-imx", 1881abfafc2dSShawn Guo .of_match_table = imx_esdhc_dt_ids, 188289d7e5c1SDong Aisheng .pm = &sdhci_esdhc_pmops, 188385d6509dSShawn Guo }, 188457ed3314SShawn Guo .id_table = imx_esdhc_devtype, 188585d6509dSShawn Guo .probe = sdhci_esdhc_imx_probe, 18860433c143SBill Pemberton .remove = sdhci_esdhc_imx_remove, 188795f25efeSWolfram Sang }; 188885d6509dSShawn Guo 1889d1f81a64SAxel Lin module_platform_driver(sdhci_esdhc_imx_driver); 189085d6509dSShawn Guo 189185d6509dSShawn Guo MODULE_DESCRIPTION("SDHCI driver for Freescale i.MX eSDHC"); 1892035ff831SWolfram Sang MODULE_AUTHOR("Wolfram Sang <kernel@pengutronix.de>"); 189385d6509dSShawn Guo MODULE_LICENSE("GPL v2"); 1894