1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's 4 * 5 * Copyright (C) 2015 Broadcom Corporation 6 */ 7 8 #include <linux/io.h> 9 #include <linux/iopoll.h> 10 #include <linux/mmc/host.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/bitops.h> 14 #include <linux/delay.h> 15 16 #include "sdhci-cqhci.h" 17 #include "sdhci-pltfm.h" 18 #include "cqhci.h" 19 20 #define SDHCI_VENDOR 0x78 21 #define SDHCI_VENDOR_ENHANCED_STRB 0x1 22 #define SDHCI_VENDOR_GATE_SDCLK_EN 0x2 23 24 #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) 25 #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) 26 #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) 27 #define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4) 28 29 #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) 30 #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) 31 32 #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 33 34 struct sdhci_brcmstb_priv { 35 void __iomem *cfg_regs; 36 unsigned int flags; 37 struct clk *base_clk; 38 u32 base_freq_hz; 39 }; 40 41 struct brcmstb_match_priv { 42 void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); 43 struct sdhci_ops *ops; 44 const unsigned int flags; 45 }; 46 47 static inline void enable_clock_gating(struct sdhci_host *host) 48 { 49 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 50 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 51 u32 reg; 52 53 if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)) 54 return; 55 56 reg = sdhci_readl(host, SDHCI_VENDOR); 57 reg |= SDHCI_VENDOR_GATE_SDCLK_EN; 58 sdhci_writel(host, reg, SDHCI_VENDOR); 59 } 60 61 static void brcmstb_reset(struct sdhci_host *host, u8 mask) 62 { 63 sdhci_and_cqhci_reset(host, mask); 64 65 /* Reset will clear this, so re-enable it */ 66 enable_clock_gating(host); 67 } 68 69 static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask) 70 { 71 u32 new_mask = (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24; 72 int ret; 73 u32 reg; 74 75 /* 76 * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall 77 * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA 78 * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register 79 */ 80 new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN; 81 reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 82 sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL); 83 84 reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET); 85 86 ret = read_poll_timeout_atomic(sdhci_readb, reg, !(reg & mask), 87 10, 10000, false, 88 host, SDHCI_SOFTWARE_RESET); 89 90 if (ret) { 91 pr_err("%s: Reset 0x%x never completed.\n", 92 mmc_hostname(host->mmc), (int)mask); 93 sdhci_err_stats_inc(host, CTRL_TIMEOUT); 94 sdhci_dumpregs(host); 95 } 96 } 97 98 static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask) 99 { 100 /* take care of RESET_ALL as usual */ 101 if (mask & SDHCI_RESET_ALL) 102 sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL); 103 104 /* cmd and/or data treated differently on this core */ 105 if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) 106 brcmstb_sdhci_reset_cmd_data(host, mask); 107 108 /* Reset will clear this, so re-enable it */ 109 enable_clock_gating(host); 110 } 111 112 static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) 113 { 114 struct sdhci_host *host = mmc_priv(mmc); 115 116 u32 reg; 117 118 dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", 119 __func__); 120 reg = readl(host->ioaddr + SDHCI_VENDOR); 121 if (ios->enhanced_strobe) 122 reg |= SDHCI_VENDOR_ENHANCED_STRB; 123 else 124 reg &= ~SDHCI_VENDOR_ENHANCED_STRB; 125 writel(reg, host->ioaddr + SDHCI_VENDOR); 126 } 127 128 static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) 129 { 130 u16 clk; 131 132 host->mmc->actual_clock = 0; 133 134 clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 135 sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 136 137 if (clock == 0) 138 return; 139 140 sdhci_enable_clk(host, clk); 141 } 142 143 static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, 144 unsigned int timing) 145 { 146 u16 ctrl_2; 147 148 dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", 149 __func__, timing); 150 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 151 /* Select Bus Speed Mode for host */ 152 ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 153 if ((timing == MMC_TIMING_MMC_HS200) || 154 (timing == MMC_TIMING_UHS_SDR104)) 155 ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 156 else if (timing == MMC_TIMING_UHS_SDR12) 157 ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 158 else if (timing == MMC_TIMING_SD_HS || 159 timing == MMC_TIMING_MMC_HS || 160 timing == MMC_TIMING_UHS_SDR25) 161 ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 162 else if (timing == MMC_TIMING_UHS_SDR50) 163 ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 164 else if ((timing == MMC_TIMING_UHS_DDR50) || 165 (timing == MMC_TIMING_MMC_DDR52)) 166 ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 167 else if (timing == MMC_TIMING_MMC_HS400) 168 ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 169 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 170 } 171 172 static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) 173 { 174 sdhci_dumpregs(mmc_priv(mmc)); 175 } 176 177 static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) 178 { 179 struct sdhci_host *host = mmc_priv(mmc); 180 u32 reg; 181 182 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 183 while (reg & SDHCI_DATA_AVAILABLE) { 184 sdhci_readl(host, SDHCI_BUFFER); 185 reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 186 } 187 188 sdhci_cqe_enable(mmc); 189 } 190 191 static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = { 192 .enable = sdhci_brcmstb_cqe_enable, 193 .disable = sdhci_cqe_disable, 194 .dumpregs = sdhci_brcmstb_dumpregs, 195 }; 196 197 static struct sdhci_ops sdhci_brcmstb_ops = { 198 .set_clock = sdhci_set_clock, 199 .set_bus_width = sdhci_set_bus_width, 200 .reset = sdhci_reset, 201 .set_uhs_signaling = sdhci_set_uhs_signaling, 202 }; 203 204 static struct sdhci_ops sdhci_brcmstb_ops_7216 = { 205 .set_clock = sdhci_brcmstb_set_clock, 206 .set_bus_width = sdhci_set_bus_width, 207 .reset = brcmstb_reset, 208 .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 209 }; 210 211 static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { 212 .set_clock = sdhci_brcmstb_set_clock, 213 .set_bus_width = sdhci_set_bus_width, 214 .reset = brcmstb_reset_74165b0, 215 .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 216 }; 217 218 static struct brcmstb_match_priv match_priv_7425 = { 219 .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | 220 BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 221 .ops = &sdhci_brcmstb_ops, 222 }; 223 224 static struct brcmstb_match_priv match_priv_7445 = { 225 .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 226 .ops = &sdhci_brcmstb_ops, 227 }; 228 229 static const struct brcmstb_match_priv match_priv_7216 = { 230 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 231 .hs400es = sdhci_brcmstb_hs400es, 232 .ops = &sdhci_brcmstb_ops_7216, 233 }; 234 235 static struct brcmstb_match_priv match_priv_74165b0 = { 236 .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 237 .hs400es = sdhci_brcmstb_hs400es, 238 .ops = &sdhci_brcmstb_ops_74165b0, 239 }; 240 241 static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { 242 { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 243 { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 244 { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, 245 { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 }, 246 {}, 247 }; 248 249 static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) 250 { 251 int cmd_error = 0; 252 int data_error = 0; 253 254 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 255 return intmask; 256 257 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 258 259 return 0; 260 } 261 262 static int sdhci_brcmstb_add_host(struct sdhci_host *host, 263 struct sdhci_brcmstb_priv *priv) 264 { 265 struct cqhci_host *cq_host; 266 bool dma64; 267 int ret; 268 269 if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) 270 return sdhci_add_host(host); 271 272 dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); 273 host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 274 ret = sdhci_setup_host(host); 275 if (ret) 276 return ret; 277 278 cq_host = devm_kzalloc(mmc_dev(host->mmc), 279 sizeof(*cq_host), GFP_KERNEL); 280 if (!cq_host) { 281 ret = -ENOMEM; 282 goto cleanup; 283 } 284 285 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 286 cq_host->ops = &sdhci_brcmstb_cqhci_ops; 287 288 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 289 if (dma64) { 290 dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); 291 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 292 } 293 294 ret = cqhci_init(cq_host, host->mmc, dma64); 295 if (ret) 296 goto cleanup; 297 298 ret = __sdhci_add_host(host); 299 if (ret) 300 goto cleanup; 301 302 return 0; 303 304 cleanup: 305 sdhci_cleanup_host(host); 306 return ret; 307 } 308 309 static int sdhci_brcmstb_probe(struct platform_device *pdev) 310 { 311 const struct brcmstb_match_priv *match_priv; 312 struct sdhci_pltfm_data brcmstb_pdata; 313 struct sdhci_pltfm_host *pltfm_host; 314 const struct of_device_id *match; 315 struct sdhci_brcmstb_priv *priv; 316 u32 actual_clock_mhz; 317 struct sdhci_host *host; 318 struct clk *clk; 319 struct clk *base_clk = NULL; 320 int res; 321 322 match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); 323 match_priv = match->data; 324 325 dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); 326 327 clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 328 if (IS_ERR(clk)) 329 return dev_err_probe(&pdev->dev, PTR_ERR(clk), 330 "Failed to get and enable clock from Device Tree\n"); 331 332 memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); 333 brcmstb_pdata.ops = match_priv->ops; 334 host = sdhci_pltfm_init(pdev, &brcmstb_pdata, 335 sizeof(struct sdhci_brcmstb_priv)); 336 if (IS_ERR(host)) 337 return PTR_ERR(host); 338 339 pltfm_host = sdhci_priv(host); 340 priv = sdhci_pltfm_priv(pltfm_host); 341 if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 342 priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; 343 match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; 344 } 345 346 /* Map in the non-standard CFG registers */ 347 priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 348 if (IS_ERR(priv->cfg_regs)) { 349 res = PTR_ERR(priv->cfg_regs); 350 goto err; 351 } 352 353 sdhci_get_of_property(pdev); 354 res = mmc_of_parse(host->mmc); 355 if (res) 356 goto err; 357 358 /* 359 * Automatic clock gating does not work for SD cards that may 360 * voltage switch so only enable it for non-removable devices. 361 */ 362 if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && 363 (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 364 priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; 365 366 /* 367 * If the chip has enhanced strobe and it's enabled, add 368 * callback 369 */ 370 if (match_priv->hs400es && 371 (host->mmc->caps2 & MMC_CAP2_HS400_ES)) 372 host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; 373 374 /* 375 * Supply the existing CAPS, but clear the UHS modes. This 376 * will allow these modes to be specified by device tree 377 * properties through mmc_of_parse(). 378 */ 379 sdhci_read_caps(host); 380 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) 381 host->caps &= ~SDHCI_CAN_64BIT; 382 host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 383 SDHCI_SUPPORT_DDR50); 384 385 if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) 386 host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 387 388 if (!(match_priv->flags & BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY)) 389 host->mmc_host_ops.card_busy = NULL; 390 391 /* Change the base clock frequency if the DT property exists */ 392 if (device_property_read_u32(&pdev->dev, "clock-frequency", 393 &priv->base_freq_hz) != 0) 394 goto add_host; 395 396 base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); 397 if (IS_ERR(base_clk)) { 398 dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); 399 goto add_host; 400 } 401 402 res = clk_prepare_enable(base_clk); 403 if (res) 404 goto err; 405 406 /* set improved clock rate */ 407 clk_set_rate(base_clk, priv->base_freq_hz); 408 actual_clock_mhz = clk_get_rate(base_clk) / 1000000; 409 410 host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; 411 host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); 412 /* Disable presets because they are now incorrect */ 413 host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 414 415 dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", 416 actual_clock_mhz); 417 priv->base_clk = base_clk; 418 419 add_host: 420 res = sdhci_brcmstb_add_host(host, priv); 421 if (res) 422 goto err; 423 424 pltfm_host->clk = clk; 425 return res; 426 427 err: 428 sdhci_pltfm_free(pdev); 429 clk_disable_unprepare(base_clk); 430 return res; 431 } 432 433 static void sdhci_brcmstb_shutdown(struct platform_device *pdev) 434 { 435 sdhci_pltfm_suspend(&pdev->dev); 436 } 437 438 MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); 439 440 #ifdef CONFIG_PM_SLEEP 441 static int sdhci_brcmstb_suspend(struct device *dev) 442 { 443 struct sdhci_host *host = dev_get_drvdata(dev); 444 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 445 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 446 447 clk_disable_unprepare(priv->base_clk); 448 return sdhci_pltfm_suspend(dev); 449 } 450 451 static int sdhci_brcmstb_resume(struct device *dev) 452 { 453 struct sdhci_host *host = dev_get_drvdata(dev); 454 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 455 struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 456 int ret; 457 458 ret = sdhci_pltfm_resume(dev); 459 if (!ret && priv->base_freq_hz) { 460 ret = clk_prepare_enable(priv->base_clk); 461 /* 462 * Note: using clk_get_rate() below as clk_get_rate() 463 * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate() 464 * may do implicit get_rate() calls that do not honor 465 * CLK_GET_RATE_NOCACHE. 466 */ 467 if (!ret && 468 (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) 469 ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); 470 } 471 472 return ret; 473 } 474 #endif 475 476 static const struct dev_pm_ops sdhci_brcmstb_pmops = { 477 SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume) 478 }; 479 480 static struct platform_driver sdhci_brcmstb_driver = { 481 .driver = { 482 .name = "sdhci-brcmstb", 483 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 484 .pm = &sdhci_brcmstb_pmops, 485 .of_match_table = of_match_ptr(sdhci_brcm_of_match), 486 }, 487 .probe = sdhci_brcmstb_probe, 488 .remove_new = sdhci_pltfm_remove, 489 .shutdown = sdhci_brcmstb_shutdown, 490 }; 491 492 module_platform_driver(sdhci_brcmstb_driver); 493 494 MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs"); 495 MODULE_AUTHOR("Broadcom"); 496 MODULE_LICENSE("GPL v2"); 497