11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 2476bf3d6SAl Cooper /* 3476bf3d6SAl Cooper * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's 4476bf3d6SAl Cooper * 5476bf3d6SAl Cooper * Copyright (C) 2015 Broadcom Corporation 6476bf3d6SAl Cooper */ 7476bf3d6SAl Cooper 8476bf3d6SAl Cooper #include <linux/io.h> 9fe86da36SKamal Dasu #include <linux/iopoll.h> 10476bf3d6SAl Cooper #include <linux/mmc/host.h> 11476bf3d6SAl Cooper #include <linux/module.h> 12476bf3d6SAl Cooper #include <linux/of.h> 1378ab82fdSAl Cooper #include <linux/bitops.h> 14d46ba2d1SAl Cooper #include <linux/delay.h> 15476bf3d6SAl Cooper 1656baa208SBrian Norris #include "sdhci-cqhci.h" 17476bf3d6SAl Cooper #include "sdhci-pltfm.h" 18d46ba2d1SAl Cooper #include "cqhci.h" 19476bf3d6SAl Cooper 2078ab82fdSAl Cooper #define SDHCI_VENDOR 0x78 2178ab82fdSAl Cooper #define SDHCI_VENDOR_ENHANCED_STRB 0x1 226bcc55feSAl Cooper #define SDHCI_VENDOR_GATE_SDCLK_EN 0x2 2378ab82fdSAl Cooper 24f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0) 25f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1) 266bcc55feSAl Cooper #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2) 27*d77dc388SKamal Dasu #define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4) 28f3a70f99SAl Cooper 29f3a70f99SAl Cooper #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0) 306bcc55feSAl Cooper #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1) 3178ab82fdSAl Cooper 32d46ba2d1SAl Cooper #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200 33d46ba2d1SAl Cooper 3478ab82fdSAl Cooper struct sdhci_brcmstb_priv { 3578ab82fdSAl Cooper void __iomem *cfg_regs; 36f3a70f99SAl Cooper unsigned int flags; 3797904a59SKamal Dasu struct clk *base_clk; 3897904a59SKamal Dasu u32 base_freq_hz; 3978ab82fdSAl Cooper }; 4078ab82fdSAl Cooper 4178ab82fdSAl Cooper struct brcmstb_match_priv { 4278ab82fdSAl Cooper void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios); 43d46ba2d1SAl Cooper struct sdhci_ops *ops; 44f3a70f99SAl Cooper const unsigned int flags; 4578ab82fdSAl Cooper }; 4678ab82fdSAl Cooper 476bcc55feSAl Cooper static inline void enable_clock_gating(struct sdhci_host *host) 486bcc55feSAl Cooper { 49fe86da36SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 50fe86da36SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 516bcc55feSAl Cooper u32 reg; 526bcc55feSAl Cooper 53fe86da36SKamal Dasu if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK)) 54fe86da36SKamal Dasu return; 55fe86da36SKamal Dasu 566bcc55feSAl Cooper reg = sdhci_readl(host, SDHCI_VENDOR); 576bcc55feSAl Cooper reg |= SDHCI_VENDOR_GATE_SDCLK_EN; 586bcc55feSAl Cooper sdhci_writel(host, reg, SDHCI_VENDOR); 596bcc55feSAl Cooper } 606bcc55feSAl Cooper 610c9ee5baSUlf Hansson static void brcmstb_reset(struct sdhci_host *host, u8 mask) 626bcc55feSAl Cooper { 6356baa208SBrian Norris sdhci_and_cqhci_reset(host, mask); 646bcc55feSAl Cooper 656bcc55feSAl Cooper /* Reset will clear this, so re-enable it */ 66fe86da36SKamal Dasu enable_clock_gating(host); 67fe86da36SKamal Dasu } 68fe86da36SKamal Dasu 69fe86da36SKamal Dasu static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask) 70fe86da36SKamal Dasu { 71fe86da36SKamal Dasu u32 new_mask = (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24; 72fe86da36SKamal Dasu int ret; 73fe86da36SKamal Dasu u32 reg; 74fe86da36SKamal Dasu 75fe86da36SKamal Dasu /* 76fe86da36SKamal Dasu * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall 77fe86da36SKamal Dasu * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA 78fe86da36SKamal Dasu * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register 79fe86da36SKamal Dasu */ 80fe86da36SKamal Dasu new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN; 81fe86da36SKamal Dasu reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL); 82fe86da36SKamal Dasu sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL); 83fe86da36SKamal Dasu 84fe86da36SKamal Dasu reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET); 85fe86da36SKamal Dasu 86fe86da36SKamal Dasu ret = read_poll_timeout_atomic(sdhci_readb, reg, !(reg & mask), 87fe86da36SKamal Dasu 10, 10000, false, 88fe86da36SKamal Dasu host, SDHCI_SOFTWARE_RESET); 89fe86da36SKamal Dasu 90fe86da36SKamal Dasu if (ret) { 91fe86da36SKamal Dasu pr_err("%s: Reset 0x%x never completed.\n", 92fe86da36SKamal Dasu mmc_hostname(host->mmc), (int)mask); 93fe86da36SKamal Dasu sdhci_err_stats_inc(host, CTRL_TIMEOUT); 94fe86da36SKamal Dasu sdhci_dumpregs(host); 95fe86da36SKamal Dasu } 96fe86da36SKamal Dasu } 97fe86da36SKamal Dasu 98fe86da36SKamal Dasu static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask) 99fe86da36SKamal Dasu { 100fe86da36SKamal Dasu /* take care of RESET_ALL as usual */ 101fe86da36SKamal Dasu if (mask & SDHCI_RESET_ALL) 102fe86da36SKamal Dasu sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL); 103fe86da36SKamal Dasu 104fe86da36SKamal Dasu /* cmd and/or data treated differently on this core */ 105fe86da36SKamal Dasu if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) 106fe86da36SKamal Dasu brcmstb_sdhci_reset_cmd_data(host, mask); 107fe86da36SKamal Dasu 108fe86da36SKamal Dasu /* Reset will clear this, so re-enable it */ 1096bcc55feSAl Cooper enable_clock_gating(host); 1106bcc55feSAl Cooper } 1116bcc55feSAl Cooper 11278ab82fdSAl Cooper static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios) 11378ab82fdSAl Cooper { 11478ab82fdSAl Cooper struct sdhci_host *host = mmc_priv(mmc); 11578ab82fdSAl Cooper 11678ab82fdSAl Cooper u32 reg; 11778ab82fdSAl Cooper 11878ab82fdSAl Cooper dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n", 11978ab82fdSAl Cooper __func__); 12078ab82fdSAl Cooper reg = readl(host->ioaddr + SDHCI_VENDOR); 12178ab82fdSAl Cooper if (ios->enhanced_strobe) 12278ab82fdSAl Cooper reg |= SDHCI_VENDOR_ENHANCED_STRB; 12378ab82fdSAl Cooper else 12478ab82fdSAl Cooper reg &= ~SDHCI_VENDOR_ENHANCED_STRB; 12578ab82fdSAl Cooper writel(reg, host->ioaddr + SDHCI_VENDOR); 12678ab82fdSAl Cooper } 12778ab82fdSAl Cooper 128d46ba2d1SAl Cooper static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock) 129d46ba2d1SAl Cooper { 130d46ba2d1SAl Cooper u16 clk; 131d46ba2d1SAl Cooper 132d46ba2d1SAl Cooper host->mmc->actual_clock = 0; 133d46ba2d1SAl Cooper 134d46ba2d1SAl Cooper clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); 135d46ba2d1SAl Cooper sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); 136d46ba2d1SAl Cooper 137d46ba2d1SAl Cooper if (clock == 0) 138d46ba2d1SAl Cooper return; 139d46ba2d1SAl Cooper 140d46ba2d1SAl Cooper sdhci_enable_clk(host, clk); 141d46ba2d1SAl Cooper } 142d46ba2d1SAl Cooper 1432fefc7c5SAl Cooper static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host, 1442fefc7c5SAl Cooper unsigned int timing) 1452fefc7c5SAl Cooper { 1462fefc7c5SAl Cooper u16 ctrl_2; 1472fefc7c5SAl Cooper 1482fefc7c5SAl Cooper dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n", 1492fefc7c5SAl Cooper __func__, timing); 1502fefc7c5SAl Cooper ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); 1512fefc7c5SAl Cooper /* Select Bus Speed Mode for host */ 1522fefc7c5SAl Cooper ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; 1532fefc7c5SAl Cooper if ((timing == MMC_TIMING_MMC_HS200) || 1542fefc7c5SAl Cooper (timing == MMC_TIMING_UHS_SDR104)) 1552fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR104; 1562fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR12) 1572fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR12; 1582fefc7c5SAl Cooper else if (timing == MMC_TIMING_SD_HS || 1592fefc7c5SAl Cooper timing == MMC_TIMING_MMC_HS || 1602fefc7c5SAl Cooper timing == MMC_TIMING_UHS_SDR25) 1612fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR25; 1622fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR50) 1632fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR50; 1642fefc7c5SAl Cooper else if ((timing == MMC_TIMING_UHS_DDR50) || 1652fefc7c5SAl Cooper (timing == MMC_TIMING_MMC_DDR52)) 1662fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_DDR50; 1672fefc7c5SAl Cooper else if (timing == MMC_TIMING_MMC_HS400) 1682fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ 1692fefc7c5SAl Cooper sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); 1702fefc7c5SAl Cooper } 1712fefc7c5SAl Cooper 172d46ba2d1SAl Cooper static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc) 173d46ba2d1SAl Cooper { 174d46ba2d1SAl Cooper sdhci_dumpregs(mmc_priv(mmc)); 175d46ba2d1SAl Cooper } 176d46ba2d1SAl Cooper 177d46ba2d1SAl Cooper static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc) 178d46ba2d1SAl Cooper { 179d46ba2d1SAl Cooper struct sdhci_host *host = mmc_priv(mmc); 180d46ba2d1SAl Cooper u32 reg; 181d46ba2d1SAl Cooper 182d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 183d46ba2d1SAl Cooper while (reg & SDHCI_DATA_AVAILABLE) { 184d46ba2d1SAl Cooper sdhci_readl(host, SDHCI_BUFFER); 185d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE); 186d46ba2d1SAl Cooper } 187d46ba2d1SAl Cooper 188d46ba2d1SAl Cooper sdhci_cqe_enable(mmc); 189d46ba2d1SAl Cooper } 190d46ba2d1SAl Cooper 191d46ba2d1SAl Cooper static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = { 192d46ba2d1SAl Cooper .enable = sdhci_brcmstb_cqe_enable, 193d46ba2d1SAl Cooper .disable = sdhci_cqe_disable, 194d46ba2d1SAl Cooper .dumpregs = sdhci_brcmstb_dumpregs, 195d46ba2d1SAl Cooper }; 196d46ba2d1SAl Cooper 197d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops = { 198476bf3d6SAl Cooper .set_clock = sdhci_set_clock, 199476bf3d6SAl Cooper .set_bus_width = sdhci_set_bus_width, 200476bf3d6SAl Cooper .reset = sdhci_reset, 201476bf3d6SAl Cooper .set_uhs_signaling = sdhci_set_uhs_signaling, 202476bf3d6SAl Cooper }; 203476bf3d6SAl Cooper 204d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops_7216 = { 205d46ba2d1SAl Cooper .set_clock = sdhci_brcmstb_set_clock, 206d46ba2d1SAl Cooper .set_bus_width = sdhci_set_bus_width, 2076bcc55feSAl Cooper .reset = brcmstb_reset, 2082fefc7c5SAl Cooper .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 209d46ba2d1SAl Cooper }; 210d46ba2d1SAl Cooper 211fe86da36SKamal Dasu static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = { 212fe86da36SKamal Dasu .set_clock = sdhci_brcmstb_set_clock, 213fe86da36SKamal Dasu .set_bus_width = sdhci_set_bus_width, 214fe86da36SKamal Dasu .reset = brcmstb_reset_74165b0, 215fe86da36SKamal Dasu .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling, 216fe86da36SKamal Dasu }; 217fe86da36SKamal Dasu 218d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7425 = { 219f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT | 220f3a70f99SAl Cooper BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 221476bf3d6SAl Cooper .ops = &sdhci_brcmstb_ops, 222476bf3d6SAl Cooper }; 223476bf3d6SAl Cooper 224d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7445 = { 225f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT, 226d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops, 22778ab82fdSAl Cooper }; 22878ab82fdSAl Cooper 22978ab82fdSAl Cooper static const struct brcmstb_match_priv match_priv_7216 = { 2306bcc55feSAl Cooper .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 23178ab82fdSAl Cooper .hs400es = sdhci_brcmstb_hs400es, 232d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops_7216, 23378ab82fdSAl Cooper }; 23478ab82fdSAl Cooper 235fe86da36SKamal Dasu static struct brcmstb_match_priv match_priv_74165b0 = { 236fe86da36SKamal Dasu .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE, 237fe86da36SKamal Dasu .hs400es = sdhci_brcmstb_hs400es, 238fe86da36SKamal Dasu .ops = &sdhci_brcmstb_ops_74165b0, 239fe86da36SKamal Dasu }; 240fe86da36SKamal Dasu 241a234442cSBrian Norris static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = { 24278ab82fdSAl Cooper { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 }, 24378ab82fdSAl Cooper { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 }, 24478ab82fdSAl Cooper { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 }, 245fe86da36SKamal Dasu { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 }, 24678ab82fdSAl Cooper {}, 24778ab82fdSAl Cooper }; 24878ab82fdSAl Cooper 249d46ba2d1SAl Cooper static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask) 250d46ba2d1SAl Cooper { 251d46ba2d1SAl Cooper int cmd_error = 0; 252d46ba2d1SAl Cooper int data_error = 0; 253d46ba2d1SAl Cooper 254d46ba2d1SAl Cooper if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 255d46ba2d1SAl Cooper return intmask; 256d46ba2d1SAl Cooper 257d46ba2d1SAl Cooper cqhci_irq(host->mmc, intmask, cmd_error, data_error); 258d46ba2d1SAl Cooper 259d46ba2d1SAl Cooper return 0; 260d46ba2d1SAl Cooper } 261d46ba2d1SAl Cooper 262d46ba2d1SAl Cooper static int sdhci_brcmstb_add_host(struct sdhci_host *host, 263d46ba2d1SAl Cooper struct sdhci_brcmstb_priv *priv) 264d46ba2d1SAl Cooper { 265d46ba2d1SAl Cooper struct cqhci_host *cq_host; 266d46ba2d1SAl Cooper bool dma64; 267d46ba2d1SAl Cooper int ret; 268d46ba2d1SAl Cooper 269f3a70f99SAl Cooper if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0) 270d46ba2d1SAl Cooper return sdhci_add_host(host); 271d46ba2d1SAl Cooper 272d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n"); 273d46ba2d1SAl Cooper host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 274d46ba2d1SAl Cooper ret = sdhci_setup_host(host); 275d46ba2d1SAl Cooper if (ret) 276d46ba2d1SAl Cooper return ret; 277d46ba2d1SAl Cooper 278d46ba2d1SAl Cooper cq_host = devm_kzalloc(mmc_dev(host->mmc), 279d46ba2d1SAl Cooper sizeof(*cq_host), GFP_KERNEL); 280d46ba2d1SAl Cooper if (!cq_host) { 281d46ba2d1SAl Cooper ret = -ENOMEM; 282d46ba2d1SAl Cooper goto cleanup; 283d46ba2d1SAl Cooper } 284d46ba2d1SAl Cooper 285d46ba2d1SAl Cooper cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; 286d46ba2d1SAl Cooper cq_host->ops = &sdhci_brcmstb_cqhci_ops; 287d46ba2d1SAl Cooper 288d46ba2d1SAl Cooper dma64 = host->flags & SDHCI_USE_64_BIT_DMA; 289d46ba2d1SAl Cooper if (dma64) { 290d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n"); 291d46ba2d1SAl Cooper cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 292d46ba2d1SAl Cooper } 293d46ba2d1SAl Cooper 294d46ba2d1SAl Cooper ret = cqhci_init(cq_host, host->mmc, dma64); 295d46ba2d1SAl Cooper if (ret) 296d46ba2d1SAl Cooper goto cleanup; 297d46ba2d1SAl Cooper 298d46ba2d1SAl Cooper ret = __sdhci_add_host(host); 299d46ba2d1SAl Cooper if (ret) 300d46ba2d1SAl Cooper goto cleanup; 301d46ba2d1SAl Cooper 302d46ba2d1SAl Cooper return 0; 303d46ba2d1SAl Cooper 304d46ba2d1SAl Cooper cleanup: 305d46ba2d1SAl Cooper sdhci_cleanup_host(host); 306d46ba2d1SAl Cooper return ret; 307d46ba2d1SAl Cooper } 308d46ba2d1SAl Cooper 309476bf3d6SAl Cooper static int sdhci_brcmstb_probe(struct platform_device *pdev) 310476bf3d6SAl Cooper { 31178ab82fdSAl Cooper const struct brcmstb_match_priv *match_priv; 312d46ba2d1SAl Cooper struct sdhci_pltfm_data brcmstb_pdata; 313476bf3d6SAl Cooper struct sdhci_pltfm_host *pltfm_host; 31478ab82fdSAl Cooper const struct of_device_id *match; 31578ab82fdSAl Cooper struct sdhci_brcmstb_priv *priv; 31697904a59SKamal Dasu u32 actual_clock_mhz; 31778ab82fdSAl Cooper struct sdhci_host *host; 318476bf3d6SAl Cooper struct clk *clk; 319c3c0ed75SNathan Chancellor struct clk *base_clk = NULL; 320476bf3d6SAl Cooper int res; 321476bf3d6SAl Cooper 32278ab82fdSAl Cooper match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node); 32378ab82fdSAl Cooper match_priv = match->data; 32478ab82fdSAl Cooper 325d46ba2d1SAl Cooper dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible); 326d46ba2d1SAl Cooper 327b6c90da3SAdrian Hunter clk = devm_clk_get_optional_enabled(&pdev->dev, NULL); 328b41123f4SKrzysztof Kozlowski if (IS_ERR(clk)) 329b41123f4SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(clk), 330b6c90da3SAdrian Hunter "Failed to get and enable clock from Device Tree\n"); 331476bf3d6SAl Cooper 332d46ba2d1SAl Cooper memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata)); 333d46ba2d1SAl Cooper brcmstb_pdata.ops = match_priv->ops; 334d46ba2d1SAl Cooper host = sdhci_pltfm_init(pdev, &brcmstb_pdata, 33578ab82fdSAl Cooper sizeof(struct sdhci_brcmstb_priv)); 336b6c90da3SAdrian Hunter if (IS_ERR(host)) 337b6c90da3SAdrian Hunter return PTR_ERR(host); 338476bf3d6SAl Cooper 33978ab82fdSAl Cooper pltfm_host = sdhci_priv(host); 34078ab82fdSAl Cooper priv = sdhci_pltfm_priv(pltfm_host); 341f3a70f99SAl Cooper if (device_property_read_bool(&pdev->dev, "supports-cqe")) { 342f3a70f99SAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE; 343f3a70f99SAl Cooper match_priv->ops->irq = sdhci_brcmstb_cqhci_irq; 344f3a70f99SAl Cooper } 34578ab82fdSAl Cooper 34678ab82fdSAl Cooper /* Map in the non-standard CFG registers */ 34708623d74SYe Xingchen priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL); 34878ab82fdSAl Cooper if (IS_ERR(priv->cfg_regs)) { 34978ab82fdSAl Cooper res = PTR_ERR(priv->cfg_regs); 35078ab82fdSAl Cooper goto err; 35178ab82fdSAl Cooper } 35278ab82fdSAl Cooper 353476bf3d6SAl Cooper sdhci_get_of_property(pdev); 3541e20186eSStefan Wahren res = mmc_of_parse(host->mmc); 3551e20186eSStefan Wahren if (res) 3561e20186eSStefan Wahren goto err; 357476bf3d6SAl Cooper 358476bf3d6SAl Cooper /* 3596bcc55feSAl Cooper * Automatic clock gating does not work for SD cards that may 3606bcc55feSAl Cooper * voltage switch so only enable it for non-removable devices. 3616bcc55feSAl Cooper */ 3626bcc55feSAl Cooper if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) && 3636bcc55feSAl Cooper (host->mmc->caps & MMC_CAP_NONREMOVABLE)) 3646bcc55feSAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK; 3656bcc55feSAl Cooper 3666bcc55feSAl Cooper /* 36778ab82fdSAl Cooper * If the chip has enhanced strobe and it's enabled, add 36878ab82fdSAl Cooper * callback 36978ab82fdSAl Cooper */ 37078ab82fdSAl Cooper if (match_priv->hs400es && 37178ab82fdSAl Cooper (host->mmc->caps2 & MMC_CAP2_HS400_ES)) 37278ab82fdSAl Cooper host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es; 37378ab82fdSAl Cooper 37478ab82fdSAl Cooper /* 375476bf3d6SAl Cooper * Supply the existing CAPS, but clear the UHS modes. This 376476bf3d6SAl Cooper * will allow these modes to be specified by device tree 377476bf3d6SAl Cooper * properties through mmc_of_parse(). 378476bf3d6SAl Cooper */ 379759329edSAdrian Hunter sdhci_read_caps(host); 380f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT) 3816a3d8cedSJaedon Shin host->caps &= ~SDHCI_CAN_64BIT; 382476bf3d6SAl Cooper host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 | 383476bf3d6SAl Cooper SDHCI_SUPPORT_DDR50); 38478ab82fdSAl Cooper 385f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT) 38678ab82fdSAl Cooper host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; 387476bf3d6SAl Cooper 388*d77dc388SKamal Dasu if (!(match_priv->flags & BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY)) 389*d77dc388SKamal Dasu host->mmc_host_ops.card_busy = NULL; 390*d77dc388SKamal Dasu 39197904a59SKamal Dasu /* Change the base clock frequency if the DT property exists */ 39297904a59SKamal Dasu if (device_property_read_u32(&pdev->dev, "clock-frequency", 39397904a59SKamal Dasu &priv->base_freq_hz) != 0) 39497904a59SKamal Dasu goto add_host; 39597904a59SKamal Dasu 39697904a59SKamal Dasu base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq"); 39797904a59SKamal Dasu if (IS_ERR(base_clk)) { 39897904a59SKamal Dasu dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n"); 39997904a59SKamal Dasu goto add_host; 40097904a59SKamal Dasu } 40197904a59SKamal Dasu 40297904a59SKamal Dasu res = clk_prepare_enable(base_clk); 40397904a59SKamal Dasu if (res) 40497904a59SKamal Dasu goto err; 40597904a59SKamal Dasu 40697904a59SKamal Dasu /* set improved clock rate */ 40797904a59SKamal Dasu clk_set_rate(base_clk, priv->base_freq_hz); 40897904a59SKamal Dasu actual_clock_mhz = clk_get_rate(base_clk) / 1000000; 40997904a59SKamal Dasu 41097904a59SKamal Dasu host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK; 41197904a59SKamal Dasu host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT); 41297904a59SKamal Dasu /* Disable presets because they are now incorrect */ 41397904a59SKamal Dasu host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN; 41497904a59SKamal Dasu 41597904a59SKamal Dasu dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n", 41697904a59SKamal Dasu actual_clock_mhz); 41797904a59SKamal Dasu priv->base_clk = base_clk; 41897904a59SKamal Dasu 41997904a59SKamal Dasu add_host: 420d46ba2d1SAl Cooper res = sdhci_brcmstb_add_host(host, priv); 421476bf3d6SAl Cooper if (res) 422476bf3d6SAl Cooper goto err; 423476bf3d6SAl Cooper 424476bf3d6SAl Cooper pltfm_host->clk = clk; 425476bf3d6SAl Cooper return res; 426476bf3d6SAl Cooper 427476bf3d6SAl Cooper err: 428476bf3d6SAl Cooper sdhci_pltfm_free(pdev); 42997904a59SKamal Dasu clk_disable_unprepare(base_clk); 430476bf3d6SAl Cooper return res; 431476bf3d6SAl Cooper } 432476bf3d6SAl Cooper 433e7b5d63aSAl Cooper static void sdhci_brcmstb_shutdown(struct platform_device *pdev) 434e7b5d63aSAl Cooper { 4355b191dcbSAl Cooper sdhci_pltfm_suspend(&pdev->dev); 436e7b5d63aSAl Cooper } 437e7b5d63aSAl Cooper 438476bf3d6SAl Cooper MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match); 439476bf3d6SAl Cooper 44097904a59SKamal Dasu #ifdef CONFIG_PM_SLEEP 44197904a59SKamal Dasu static int sdhci_brcmstb_suspend(struct device *dev) 44297904a59SKamal Dasu { 44397904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev); 44497904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 44597904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 44697904a59SKamal Dasu 44797904a59SKamal Dasu clk_disable_unprepare(priv->base_clk); 44897904a59SKamal Dasu return sdhci_pltfm_suspend(dev); 44997904a59SKamal Dasu } 45097904a59SKamal Dasu 45197904a59SKamal Dasu static int sdhci_brcmstb_resume(struct device *dev) 45297904a59SKamal Dasu { 45397904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev); 45497904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 45597904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host); 45697904a59SKamal Dasu int ret; 45797904a59SKamal Dasu 45897904a59SKamal Dasu ret = sdhci_pltfm_resume(dev); 45997904a59SKamal Dasu if (!ret && priv->base_freq_hz) { 46097904a59SKamal Dasu ret = clk_prepare_enable(priv->base_clk); 461886201c7SKamal Dasu /* 462886201c7SKamal Dasu * Note: using clk_get_rate() below as clk_get_rate() 463886201c7SKamal Dasu * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate() 464886201c7SKamal Dasu * may do implicit get_rate() calls that do not honor 465886201c7SKamal Dasu * CLK_GET_RATE_NOCACHE. 466886201c7SKamal Dasu */ 467886201c7SKamal Dasu if (!ret && 468886201c7SKamal Dasu (clk_get_rate(priv->base_clk) != priv->base_freq_hz)) 46997904a59SKamal Dasu ret = clk_set_rate(priv->base_clk, priv->base_freq_hz); 47097904a59SKamal Dasu } 47197904a59SKamal Dasu 47297904a59SKamal Dasu return ret; 47397904a59SKamal Dasu } 47497904a59SKamal Dasu #endif 47597904a59SKamal Dasu 47697904a59SKamal Dasu static const struct dev_pm_ops sdhci_brcmstb_pmops = { 47797904a59SKamal Dasu SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume) 47897904a59SKamal Dasu }; 47997904a59SKamal Dasu 480476bf3d6SAl Cooper static struct platform_driver sdhci_brcmstb_driver = { 481476bf3d6SAl Cooper .driver = { 482476bf3d6SAl Cooper .name = "sdhci-brcmstb", 4832a99f3faSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 48497904a59SKamal Dasu .pm = &sdhci_brcmstb_pmops, 485476bf3d6SAl Cooper .of_match_table = of_match_ptr(sdhci_brcm_of_match), 486476bf3d6SAl Cooper }, 487476bf3d6SAl Cooper .probe = sdhci_brcmstb_probe, 488b6c90da3SAdrian Hunter .remove_new = sdhci_pltfm_remove, 489e7b5d63aSAl Cooper .shutdown = sdhci_brcmstb_shutdown, 490476bf3d6SAl Cooper }; 491476bf3d6SAl Cooper 492476bf3d6SAl Cooper module_platform_driver(sdhci_brcmstb_driver); 493476bf3d6SAl Cooper 494476bf3d6SAl Cooper MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs"); 495476bf3d6SAl Cooper MODULE_AUTHOR("Broadcom"); 496476bf3d6SAl Cooper MODULE_LICENSE("GPL v2"); 497