11802d0beSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
2476bf3d6SAl Cooper /*
3476bf3d6SAl Cooper * sdhci-brcmstb.c Support for SDHCI on Broadcom BRCMSTB SoC's
4476bf3d6SAl Cooper *
5476bf3d6SAl Cooper * Copyright (C) 2015 Broadcom Corporation
6476bf3d6SAl Cooper */
7476bf3d6SAl Cooper
8476bf3d6SAl Cooper #include <linux/io.h>
9fe86da36SKamal Dasu #include <linux/iopoll.h>
10476bf3d6SAl Cooper #include <linux/mmc/host.h>
11476bf3d6SAl Cooper #include <linux/module.h>
12476bf3d6SAl Cooper #include <linux/of.h>
1378ab82fdSAl Cooper #include <linux/bitops.h>
14d46ba2d1SAl Cooper #include <linux/delay.h>
15476bf3d6SAl Cooper
1656baa208SBrian Norris #include "sdhci-cqhci.h"
17476bf3d6SAl Cooper #include "sdhci-pltfm.h"
18d46ba2d1SAl Cooper #include "cqhci.h"
19476bf3d6SAl Cooper
2078ab82fdSAl Cooper #define SDHCI_VENDOR 0x78
2178ab82fdSAl Cooper #define SDHCI_VENDOR_ENHANCED_STRB 0x1
226bcc55feSAl Cooper #define SDHCI_VENDOR_GATE_SDCLK_EN 0x2
2378ab82fdSAl Cooper
24f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_NO_64BIT BIT(0)
25f3a70f99SAl Cooper #define BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT BIT(1)
266bcc55feSAl Cooper #define BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE BIT(2)
27d77dc388SKamal Dasu #define BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY BIT(4)
28f3a70f99SAl Cooper
29f3a70f99SAl Cooper #define BRCMSTB_PRIV_FLAGS_HAS_CQE BIT(0)
306bcc55feSAl Cooper #define BRCMSTB_PRIV_FLAGS_GATE_CLOCK BIT(1)
3178ab82fdSAl Cooper
32d46ba2d1SAl Cooper #define SDHCI_ARASAN_CQE_BASE_ADDR 0x200
33d46ba2d1SAl Cooper
34*78d08697SAndrea della Porta #define SDIO_CFG_CQ_CAPABILITY 0x4c
35*78d08697SAndrea della Porta #define SDIO_CFG_CQ_CAPABILITY_FMUL GENMASK(13, 12)
36*78d08697SAndrea della Porta
37*78d08697SAndrea della Porta #define SDIO_CFG_CTRL 0x0
38*78d08697SAndrea della Porta #define SDIO_CFG_CTRL_SDCD_N_TEST_EN BIT(31)
39*78d08697SAndrea della Porta #define SDIO_CFG_CTRL_SDCD_N_TEST_LEV BIT(30)
40*78d08697SAndrea della Porta
41*78d08697SAndrea della Porta #define SDIO_CFG_MAX_50MHZ_MODE 0x1ac
42*78d08697SAndrea della Porta #define SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE BIT(31)
43*78d08697SAndrea della Porta #define SDIO_CFG_MAX_50MHZ_MODE_ENABLE BIT(0)
44*78d08697SAndrea della Porta
45*78d08697SAndrea della Porta #define MMC_CAP_HSE_MASK (MMC_CAP2_HSX00_1_2V | MMC_CAP2_HSX00_1_8V)
46*78d08697SAndrea della Porta /* Select all SD UHS type I SDR speed above 50MB/s */
47*78d08697SAndrea della Porta #define MMC_CAP_UHS_I_SDR_MASK (MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104)
48*78d08697SAndrea della Porta
4978ab82fdSAl Cooper struct sdhci_brcmstb_priv {
5078ab82fdSAl Cooper void __iomem *cfg_regs;
51f3a70f99SAl Cooper unsigned int flags;
5297904a59SKamal Dasu struct clk *base_clk;
5397904a59SKamal Dasu u32 base_freq_hz;
5478ab82fdSAl Cooper };
5578ab82fdSAl Cooper
5678ab82fdSAl Cooper struct brcmstb_match_priv {
57*78d08697SAndrea della Porta void (*cfginit)(struct sdhci_host *host);
5878ab82fdSAl Cooper void (*hs400es)(struct mmc_host *mmc, struct mmc_ios *ios);
59d46ba2d1SAl Cooper struct sdhci_ops *ops;
60f3a70f99SAl Cooper const unsigned int flags;
6178ab82fdSAl Cooper };
6278ab82fdSAl Cooper
enable_clock_gating(struct sdhci_host * host)636bcc55feSAl Cooper static inline void enable_clock_gating(struct sdhci_host *host)
646bcc55feSAl Cooper {
65fe86da36SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
66fe86da36SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
676bcc55feSAl Cooper u32 reg;
686bcc55feSAl Cooper
69fe86da36SKamal Dasu if (!(priv->flags & BRCMSTB_PRIV_FLAGS_GATE_CLOCK))
70fe86da36SKamal Dasu return;
71fe86da36SKamal Dasu
726bcc55feSAl Cooper reg = sdhci_readl(host, SDHCI_VENDOR);
736bcc55feSAl Cooper reg |= SDHCI_VENDOR_GATE_SDCLK_EN;
746bcc55feSAl Cooper sdhci_writel(host, reg, SDHCI_VENDOR);
756bcc55feSAl Cooper }
766bcc55feSAl Cooper
brcmstb_reset(struct sdhci_host * host,u8 mask)770c9ee5baSUlf Hansson static void brcmstb_reset(struct sdhci_host *host, u8 mask)
786bcc55feSAl Cooper {
7956baa208SBrian Norris sdhci_and_cqhci_reset(host, mask);
806bcc55feSAl Cooper
816bcc55feSAl Cooper /* Reset will clear this, so re-enable it */
82fe86da36SKamal Dasu enable_clock_gating(host);
83fe86da36SKamal Dasu }
84fe86da36SKamal Dasu
brcmstb_sdhci_reset_cmd_data(struct sdhci_host * host,u8 mask)85fe86da36SKamal Dasu static void brcmstb_sdhci_reset_cmd_data(struct sdhci_host *host, u8 mask)
86fe86da36SKamal Dasu {
87fe86da36SKamal Dasu u32 new_mask = (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA)) << 24;
88fe86da36SKamal Dasu int ret;
89fe86da36SKamal Dasu u32 reg;
90fe86da36SKamal Dasu
91fe86da36SKamal Dasu /*
92fe86da36SKamal Dasu * SDHCI_CLOCK_CONTROL register CARD_EN and CLOCK_INT_EN bits shall
93fe86da36SKamal Dasu * be set along with SOFTWARE_RESET register RESET_CMD or RESET_DATA
94fe86da36SKamal Dasu * bits, hence access SDHCI_CLOCK_CONTROL register as 32-bit register
95fe86da36SKamal Dasu */
96fe86da36SKamal Dasu new_mask |= SDHCI_CLOCK_CARD_EN | SDHCI_CLOCK_INT_EN;
97fe86da36SKamal Dasu reg = sdhci_readl(host, SDHCI_CLOCK_CONTROL);
98fe86da36SKamal Dasu sdhci_writel(host, reg | new_mask, SDHCI_CLOCK_CONTROL);
99fe86da36SKamal Dasu
100fe86da36SKamal Dasu reg = sdhci_readb(host, SDHCI_SOFTWARE_RESET);
101fe86da36SKamal Dasu
102fe86da36SKamal Dasu ret = read_poll_timeout_atomic(sdhci_readb, reg, !(reg & mask),
103fe86da36SKamal Dasu 10, 10000, false,
104fe86da36SKamal Dasu host, SDHCI_SOFTWARE_RESET);
105fe86da36SKamal Dasu
106fe86da36SKamal Dasu if (ret) {
107fe86da36SKamal Dasu pr_err("%s: Reset 0x%x never completed.\n",
108fe86da36SKamal Dasu mmc_hostname(host->mmc), (int)mask);
109fe86da36SKamal Dasu sdhci_err_stats_inc(host, CTRL_TIMEOUT);
110fe86da36SKamal Dasu sdhci_dumpregs(host);
111fe86da36SKamal Dasu }
112fe86da36SKamal Dasu }
113fe86da36SKamal Dasu
brcmstb_reset_74165b0(struct sdhci_host * host,u8 mask)114fe86da36SKamal Dasu static void brcmstb_reset_74165b0(struct sdhci_host *host, u8 mask)
115fe86da36SKamal Dasu {
116fe86da36SKamal Dasu /* take care of RESET_ALL as usual */
117fe86da36SKamal Dasu if (mask & SDHCI_RESET_ALL)
118fe86da36SKamal Dasu sdhci_and_cqhci_reset(host, SDHCI_RESET_ALL);
119fe86da36SKamal Dasu
120fe86da36SKamal Dasu /* cmd and/or data treated differently on this core */
121fe86da36SKamal Dasu if (mask & (SDHCI_RESET_CMD | SDHCI_RESET_DATA))
122fe86da36SKamal Dasu brcmstb_sdhci_reset_cmd_data(host, mask);
123fe86da36SKamal Dasu
124fe86da36SKamal Dasu /* Reset will clear this, so re-enable it */
1256bcc55feSAl Cooper enable_clock_gating(host);
1266bcc55feSAl Cooper }
1276bcc55feSAl Cooper
sdhci_brcmstb_hs400es(struct mmc_host * mmc,struct mmc_ios * ios)12878ab82fdSAl Cooper static void sdhci_brcmstb_hs400es(struct mmc_host *mmc, struct mmc_ios *ios)
12978ab82fdSAl Cooper {
13078ab82fdSAl Cooper struct sdhci_host *host = mmc_priv(mmc);
13178ab82fdSAl Cooper
13278ab82fdSAl Cooper u32 reg;
13378ab82fdSAl Cooper
13478ab82fdSAl Cooper dev_dbg(mmc_dev(mmc), "%s(): Setting HS400-Enhanced-Strobe mode\n",
13578ab82fdSAl Cooper __func__);
13678ab82fdSAl Cooper reg = readl(host->ioaddr + SDHCI_VENDOR);
13778ab82fdSAl Cooper if (ios->enhanced_strobe)
13878ab82fdSAl Cooper reg |= SDHCI_VENDOR_ENHANCED_STRB;
13978ab82fdSAl Cooper else
14078ab82fdSAl Cooper reg &= ~SDHCI_VENDOR_ENHANCED_STRB;
14178ab82fdSAl Cooper writel(reg, host->ioaddr + SDHCI_VENDOR);
14278ab82fdSAl Cooper }
14378ab82fdSAl Cooper
sdhci_brcmstb_set_clock(struct sdhci_host * host,unsigned int clock)144d46ba2d1SAl Cooper static void sdhci_brcmstb_set_clock(struct sdhci_host *host, unsigned int clock)
145d46ba2d1SAl Cooper {
146d46ba2d1SAl Cooper u16 clk;
147d46ba2d1SAl Cooper
148d46ba2d1SAl Cooper host->mmc->actual_clock = 0;
149d46ba2d1SAl Cooper
150d46ba2d1SAl Cooper clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock);
151d46ba2d1SAl Cooper sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
152d46ba2d1SAl Cooper
153d46ba2d1SAl Cooper if (clock == 0)
154d46ba2d1SAl Cooper return;
155d46ba2d1SAl Cooper
156d46ba2d1SAl Cooper sdhci_enable_clk(host, clk);
157d46ba2d1SAl Cooper }
158d46ba2d1SAl Cooper
sdhci_brcmstb_set_uhs_signaling(struct sdhci_host * host,unsigned int timing)1592fefc7c5SAl Cooper static void sdhci_brcmstb_set_uhs_signaling(struct sdhci_host *host,
1602fefc7c5SAl Cooper unsigned int timing)
1612fefc7c5SAl Cooper {
1622fefc7c5SAl Cooper u16 ctrl_2;
1632fefc7c5SAl Cooper
1642fefc7c5SAl Cooper dev_dbg(mmc_dev(host->mmc), "%s: Setting UHS signaling for %d timing\n",
1652fefc7c5SAl Cooper __func__, timing);
1662fefc7c5SAl Cooper ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
1672fefc7c5SAl Cooper /* Select Bus Speed Mode for host */
1682fefc7c5SAl Cooper ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
1692fefc7c5SAl Cooper if ((timing == MMC_TIMING_MMC_HS200) ||
1702fefc7c5SAl Cooper (timing == MMC_TIMING_UHS_SDR104))
1712fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
1722fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR12)
1732fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
1742fefc7c5SAl Cooper else if (timing == MMC_TIMING_SD_HS ||
1752fefc7c5SAl Cooper timing == MMC_TIMING_MMC_HS ||
1762fefc7c5SAl Cooper timing == MMC_TIMING_UHS_SDR25)
1772fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
1782fefc7c5SAl Cooper else if (timing == MMC_TIMING_UHS_SDR50)
1792fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
1802fefc7c5SAl Cooper else if ((timing == MMC_TIMING_UHS_DDR50) ||
1812fefc7c5SAl Cooper (timing == MMC_TIMING_MMC_DDR52))
1822fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
1832fefc7c5SAl Cooper else if (timing == MMC_TIMING_MMC_HS400)
1842fefc7c5SAl Cooper ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */
1852fefc7c5SAl Cooper sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
1862fefc7c5SAl Cooper }
1872fefc7c5SAl Cooper
sdhci_brcmstb_cfginit_2712(struct sdhci_host * host)188*78d08697SAndrea della Porta static void sdhci_brcmstb_cfginit_2712(struct sdhci_host *host)
189*78d08697SAndrea della Porta {
190*78d08697SAndrea della Porta struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
191*78d08697SAndrea della Porta struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
192*78d08697SAndrea della Porta u32 reg;
193*78d08697SAndrea della Porta
194*78d08697SAndrea della Porta /*
195*78d08697SAndrea della Porta * If we support a speed that requires tuning,
196*78d08697SAndrea della Porta * then select the delay line PHY as the clock source.
197*78d08697SAndrea della Porta */
198*78d08697SAndrea della Porta if ((host->mmc->caps & MMC_CAP_UHS_I_SDR_MASK) || (host->mmc->caps2 & MMC_CAP_HSE_MASK)) {
199*78d08697SAndrea della Porta reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
200*78d08697SAndrea della Porta reg &= ~SDIO_CFG_MAX_50MHZ_MODE_ENABLE;
201*78d08697SAndrea della Porta reg |= SDIO_CFG_MAX_50MHZ_MODE_STRAP_OVERRIDE;
202*78d08697SAndrea della Porta writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_MAX_50MHZ_MODE);
203*78d08697SAndrea della Porta }
204*78d08697SAndrea della Porta
205*78d08697SAndrea della Porta if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) ||
206*78d08697SAndrea della Porta (host->mmc->caps & MMC_CAP_NEEDS_POLL)) {
207*78d08697SAndrea della Porta /* Force presence */
208*78d08697SAndrea della Porta reg = readl(brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
209*78d08697SAndrea della Porta reg &= ~SDIO_CFG_CTRL_SDCD_N_TEST_LEV;
210*78d08697SAndrea della Porta reg |= SDIO_CFG_CTRL_SDCD_N_TEST_EN;
211*78d08697SAndrea della Porta writel(reg, brcmstb_priv->cfg_regs + SDIO_CFG_CTRL);
212*78d08697SAndrea della Porta }
213*78d08697SAndrea della Porta }
214*78d08697SAndrea della Porta
sdhci_brcmstb_dumpregs(struct mmc_host * mmc)215d46ba2d1SAl Cooper static void sdhci_brcmstb_dumpregs(struct mmc_host *mmc)
216d46ba2d1SAl Cooper {
217d46ba2d1SAl Cooper sdhci_dumpregs(mmc_priv(mmc));
218d46ba2d1SAl Cooper }
219d46ba2d1SAl Cooper
sdhci_brcmstb_cqe_enable(struct mmc_host * mmc)220d46ba2d1SAl Cooper static void sdhci_brcmstb_cqe_enable(struct mmc_host *mmc)
221d46ba2d1SAl Cooper {
222d46ba2d1SAl Cooper struct sdhci_host *host = mmc_priv(mmc);
223d46ba2d1SAl Cooper u32 reg;
224d46ba2d1SAl Cooper
225d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
226d46ba2d1SAl Cooper while (reg & SDHCI_DATA_AVAILABLE) {
227d46ba2d1SAl Cooper sdhci_readl(host, SDHCI_BUFFER);
228d46ba2d1SAl Cooper reg = sdhci_readl(host, SDHCI_PRESENT_STATE);
229d46ba2d1SAl Cooper }
230d46ba2d1SAl Cooper
231d46ba2d1SAl Cooper sdhci_cqe_enable(mmc);
232d46ba2d1SAl Cooper }
233d46ba2d1SAl Cooper
234d46ba2d1SAl Cooper static const struct cqhci_host_ops sdhci_brcmstb_cqhci_ops = {
235d46ba2d1SAl Cooper .enable = sdhci_brcmstb_cqe_enable,
236d46ba2d1SAl Cooper .disable = sdhci_cqe_disable,
237d46ba2d1SAl Cooper .dumpregs = sdhci_brcmstb_dumpregs,
238d46ba2d1SAl Cooper };
239d46ba2d1SAl Cooper
240d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops = {
241476bf3d6SAl Cooper .set_clock = sdhci_set_clock,
242476bf3d6SAl Cooper .set_bus_width = sdhci_set_bus_width,
243476bf3d6SAl Cooper .reset = sdhci_reset,
244476bf3d6SAl Cooper .set_uhs_signaling = sdhci_set_uhs_signaling,
245476bf3d6SAl Cooper };
246476bf3d6SAl Cooper
247*78d08697SAndrea della Porta static struct sdhci_ops sdhci_brcmstb_ops_2712 = {
248*78d08697SAndrea della Porta .set_clock = sdhci_set_clock,
249*78d08697SAndrea della Porta .set_power = sdhci_set_power_and_bus_voltage,
250*78d08697SAndrea della Porta .set_bus_width = sdhci_set_bus_width,
251*78d08697SAndrea della Porta .reset = sdhci_reset,
252*78d08697SAndrea della Porta .set_uhs_signaling = sdhci_set_uhs_signaling,
253*78d08697SAndrea della Porta };
254*78d08697SAndrea della Porta
255d46ba2d1SAl Cooper static struct sdhci_ops sdhci_brcmstb_ops_7216 = {
256d46ba2d1SAl Cooper .set_clock = sdhci_brcmstb_set_clock,
257d46ba2d1SAl Cooper .set_bus_width = sdhci_set_bus_width,
2586bcc55feSAl Cooper .reset = brcmstb_reset,
2592fefc7c5SAl Cooper .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
260d46ba2d1SAl Cooper };
261d46ba2d1SAl Cooper
262fe86da36SKamal Dasu static struct sdhci_ops sdhci_brcmstb_ops_74165b0 = {
263fe86da36SKamal Dasu .set_clock = sdhci_brcmstb_set_clock,
264fe86da36SKamal Dasu .set_bus_width = sdhci_set_bus_width,
265fe86da36SKamal Dasu .reset = brcmstb_reset_74165b0,
266fe86da36SKamal Dasu .set_uhs_signaling = sdhci_brcmstb_set_uhs_signaling,
267fe86da36SKamal Dasu };
268fe86da36SKamal Dasu
269*78d08697SAndrea della Porta static const struct brcmstb_match_priv match_priv_2712 = {
270*78d08697SAndrea della Porta .cfginit = sdhci_brcmstb_cfginit_2712,
271*78d08697SAndrea della Porta .ops = &sdhci_brcmstb_ops_2712,
272*78d08697SAndrea della Porta };
273*78d08697SAndrea della Porta
274d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7425 = {
275f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_NO_64BIT |
276f3a70f99SAl Cooper BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
277476bf3d6SAl Cooper .ops = &sdhci_brcmstb_ops,
278476bf3d6SAl Cooper };
279476bf3d6SAl Cooper
280d46ba2d1SAl Cooper static struct brcmstb_match_priv match_priv_7445 = {
281f3a70f99SAl Cooper .flags = BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT,
282d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops,
28378ab82fdSAl Cooper };
28478ab82fdSAl Cooper
28578ab82fdSAl Cooper static const struct brcmstb_match_priv match_priv_7216 = {
2866bcc55feSAl Cooper .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
28778ab82fdSAl Cooper .hs400es = sdhci_brcmstb_hs400es,
288d46ba2d1SAl Cooper .ops = &sdhci_brcmstb_ops_7216,
28978ab82fdSAl Cooper };
29078ab82fdSAl Cooper
291fe86da36SKamal Dasu static struct brcmstb_match_priv match_priv_74165b0 = {
292fe86da36SKamal Dasu .flags = BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE,
293fe86da36SKamal Dasu .hs400es = sdhci_brcmstb_hs400es,
294fe86da36SKamal Dasu .ops = &sdhci_brcmstb_ops_74165b0,
295fe86da36SKamal Dasu };
296fe86da36SKamal Dasu
297a234442cSBrian Norris static const struct of_device_id __maybe_unused sdhci_brcm_of_match[] = {
298*78d08697SAndrea della Porta { .compatible = "brcm,bcm2712-sdhci", .data = &match_priv_2712 },
29978ab82fdSAl Cooper { .compatible = "brcm,bcm7425-sdhci", .data = &match_priv_7425 },
30078ab82fdSAl Cooper { .compatible = "brcm,bcm7445-sdhci", .data = &match_priv_7445 },
30178ab82fdSAl Cooper { .compatible = "brcm,bcm7216-sdhci", .data = &match_priv_7216 },
302fe86da36SKamal Dasu { .compatible = "brcm,bcm74165b0-sdhci", .data = &match_priv_74165b0 },
30378ab82fdSAl Cooper {},
30478ab82fdSAl Cooper };
30578ab82fdSAl Cooper
sdhci_brcmstb_cqhci_irq(struct sdhci_host * host,u32 intmask)306d46ba2d1SAl Cooper static u32 sdhci_brcmstb_cqhci_irq(struct sdhci_host *host, u32 intmask)
307d46ba2d1SAl Cooper {
308d46ba2d1SAl Cooper int cmd_error = 0;
309d46ba2d1SAl Cooper int data_error = 0;
310d46ba2d1SAl Cooper
311d46ba2d1SAl Cooper if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error))
312d46ba2d1SAl Cooper return intmask;
313d46ba2d1SAl Cooper
314d46ba2d1SAl Cooper cqhci_irq(host->mmc, intmask, cmd_error, data_error);
315d46ba2d1SAl Cooper
316d46ba2d1SAl Cooper return 0;
317d46ba2d1SAl Cooper }
318d46ba2d1SAl Cooper
sdhci_brcmstb_add_host(struct sdhci_host * host,struct sdhci_brcmstb_priv * priv)319d46ba2d1SAl Cooper static int sdhci_brcmstb_add_host(struct sdhci_host *host,
320d46ba2d1SAl Cooper struct sdhci_brcmstb_priv *priv)
321d46ba2d1SAl Cooper {
322d46ba2d1SAl Cooper struct cqhci_host *cq_host;
323d46ba2d1SAl Cooper bool dma64;
324d46ba2d1SAl Cooper int ret;
325d46ba2d1SAl Cooper
326f3a70f99SAl Cooper if ((priv->flags & BRCMSTB_PRIV_FLAGS_HAS_CQE) == 0)
327d46ba2d1SAl Cooper return sdhci_add_host(host);
328d46ba2d1SAl Cooper
329d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "CQE is enabled\n");
330d46ba2d1SAl Cooper host->mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
331d46ba2d1SAl Cooper ret = sdhci_setup_host(host);
332d46ba2d1SAl Cooper if (ret)
333d46ba2d1SAl Cooper return ret;
334d46ba2d1SAl Cooper
335d46ba2d1SAl Cooper cq_host = devm_kzalloc(mmc_dev(host->mmc),
336d46ba2d1SAl Cooper sizeof(*cq_host), GFP_KERNEL);
337d46ba2d1SAl Cooper if (!cq_host) {
338d46ba2d1SAl Cooper ret = -ENOMEM;
339d46ba2d1SAl Cooper goto cleanup;
340d46ba2d1SAl Cooper }
341d46ba2d1SAl Cooper
342d46ba2d1SAl Cooper cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR;
343d46ba2d1SAl Cooper cq_host->ops = &sdhci_brcmstb_cqhci_ops;
344d46ba2d1SAl Cooper
345d46ba2d1SAl Cooper dma64 = host->flags & SDHCI_USE_64_BIT_DMA;
346d46ba2d1SAl Cooper if (dma64) {
347d46ba2d1SAl Cooper dev_dbg(mmc_dev(host->mmc), "Using 64 bit DMA\n");
348d46ba2d1SAl Cooper cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
349d46ba2d1SAl Cooper }
350d46ba2d1SAl Cooper
351d46ba2d1SAl Cooper ret = cqhci_init(cq_host, host->mmc, dma64);
352d46ba2d1SAl Cooper if (ret)
353d46ba2d1SAl Cooper goto cleanup;
354d46ba2d1SAl Cooper
355d46ba2d1SAl Cooper ret = __sdhci_add_host(host);
356d46ba2d1SAl Cooper if (ret)
357d46ba2d1SAl Cooper goto cleanup;
358d46ba2d1SAl Cooper
359d46ba2d1SAl Cooper return 0;
360d46ba2d1SAl Cooper
361d46ba2d1SAl Cooper cleanup:
362d46ba2d1SAl Cooper sdhci_cleanup_host(host);
363d46ba2d1SAl Cooper return ret;
364d46ba2d1SAl Cooper }
365d46ba2d1SAl Cooper
sdhci_brcmstb_probe(struct platform_device * pdev)366476bf3d6SAl Cooper static int sdhci_brcmstb_probe(struct platform_device *pdev)
367476bf3d6SAl Cooper {
36878ab82fdSAl Cooper const struct brcmstb_match_priv *match_priv;
369d46ba2d1SAl Cooper struct sdhci_pltfm_data brcmstb_pdata;
370476bf3d6SAl Cooper struct sdhci_pltfm_host *pltfm_host;
37178ab82fdSAl Cooper const struct of_device_id *match;
37278ab82fdSAl Cooper struct sdhci_brcmstb_priv *priv;
37397904a59SKamal Dasu u32 actual_clock_mhz;
37478ab82fdSAl Cooper struct sdhci_host *host;
375476bf3d6SAl Cooper struct clk *clk;
376c3c0ed75SNathan Chancellor struct clk *base_clk = NULL;
377476bf3d6SAl Cooper int res;
378476bf3d6SAl Cooper
37978ab82fdSAl Cooper match = of_match_node(sdhci_brcm_of_match, pdev->dev.of_node);
38078ab82fdSAl Cooper match_priv = match->data;
38178ab82fdSAl Cooper
382d46ba2d1SAl Cooper dev_dbg(&pdev->dev, "Probe found match for %s\n", match->compatible);
383d46ba2d1SAl Cooper
384b6c90da3SAdrian Hunter clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);
385b41123f4SKrzysztof Kozlowski if (IS_ERR(clk))
386b41123f4SKrzysztof Kozlowski return dev_err_probe(&pdev->dev, PTR_ERR(clk),
387b6c90da3SAdrian Hunter "Failed to get and enable clock from Device Tree\n");
388476bf3d6SAl Cooper
389d46ba2d1SAl Cooper memset(&brcmstb_pdata, 0, sizeof(brcmstb_pdata));
390d46ba2d1SAl Cooper brcmstb_pdata.ops = match_priv->ops;
391d46ba2d1SAl Cooper host = sdhci_pltfm_init(pdev, &brcmstb_pdata,
39278ab82fdSAl Cooper sizeof(struct sdhci_brcmstb_priv));
393b6c90da3SAdrian Hunter if (IS_ERR(host))
394b6c90da3SAdrian Hunter return PTR_ERR(host);
395476bf3d6SAl Cooper
39678ab82fdSAl Cooper pltfm_host = sdhci_priv(host);
39778ab82fdSAl Cooper priv = sdhci_pltfm_priv(pltfm_host);
398f3a70f99SAl Cooper if (device_property_read_bool(&pdev->dev, "supports-cqe")) {
399f3a70f99SAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_HAS_CQE;
400f3a70f99SAl Cooper match_priv->ops->irq = sdhci_brcmstb_cqhci_irq;
401f3a70f99SAl Cooper }
40278ab82fdSAl Cooper
40378ab82fdSAl Cooper /* Map in the non-standard CFG registers */
40408623d74SYe Xingchen priv->cfg_regs = devm_platform_get_and_ioremap_resource(pdev, 1, NULL);
40578ab82fdSAl Cooper if (IS_ERR(priv->cfg_regs)) {
40678ab82fdSAl Cooper res = PTR_ERR(priv->cfg_regs);
40778ab82fdSAl Cooper goto err;
40878ab82fdSAl Cooper }
40978ab82fdSAl Cooper
410476bf3d6SAl Cooper sdhci_get_of_property(pdev);
4111e20186eSStefan Wahren res = mmc_of_parse(host->mmc);
4121e20186eSStefan Wahren if (res)
4131e20186eSStefan Wahren goto err;
414476bf3d6SAl Cooper
415476bf3d6SAl Cooper /*
4166bcc55feSAl Cooper * Automatic clock gating does not work for SD cards that may
4176bcc55feSAl Cooper * voltage switch so only enable it for non-removable devices.
4186bcc55feSAl Cooper */
4196bcc55feSAl Cooper if ((match_priv->flags & BRCMSTB_MATCH_FLAGS_HAS_CLOCK_GATE) &&
4206bcc55feSAl Cooper (host->mmc->caps & MMC_CAP_NONREMOVABLE))
4216bcc55feSAl Cooper priv->flags |= BRCMSTB_PRIV_FLAGS_GATE_CLOCK;
4226bcc55feSAl Cooper
4236bcc55feSAl Cooper /*
42478ab82fdSAl Cooper * If the chip has enhanced strobe and it's enabled, add
42578ab82fdSAl Cooper * callback
42678ab82fdSAl Cooper */
42778ab82fdSAl Cooper if (match_priv->hs400es &&
42878ab82fdSAl Cooper (host->mmc->caps2 & MMC_CAP2_HS400_ES))
42978ab82fdSAl Cooper host->mmc_host_ops.hs400_enhanced_strobe = match_priv->hs400es;
43078ab82fdSAl Cooper
431*78d08697SAndrea della Porta if (match_priv->cfginit)
432*78d08697SAndrea della Porta match_priv->cfginit(host);
433*78d08697SAndrea della Porta
43478ab82fdSAl Cooper /*
435476bf3d6SAl Cooper * Supply the existing CAPS, but clear the UHS modes. This
436476bf3d6SAl Cooper * will allow these modes to be specified by device tree
437476bf3d6SAl Cooper * properties through mmc_of_parse().
438476bf3d6SAl Cooper */
439759329edSAdrian Hunter sdhci_read_caps(host);
440f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_NO_64BIT)
4416a3d8cedSJaedon Shin host->caps &= ~SDHCI_CAN_64BIT;
442476bf3d6SAl Cooper host->caps1 &= ~(SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_SDR104 |
443476bf3d6SAl Cooper SDHCI_SUPPORT_DDR50);
44478ab82fdSAl Cooper
445f3a70f99SAl Cooper if (match_priv->flags & BRCMSTB_MATCH_FLAGS_BROKEN_TIMEOUT)
44678ab82fdSAl Cooper host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
447476bf3d6SAl Cooper
448d77dc388SKamal Dasu if (!(match_priv->flags & BRCMSTB_MATCH_FLAGS_USE_CARD_BUSY))
449d77dc388SKamal Dasu host->mmc_host_ops.card_busy = NULL;
450d77dc388SKamal Dasu
45197904a59SKamal Dasu /* Change the base clock frequency if the DT property exists */
45297904a59SKamal Dasu if (device_property_read_u32(&pdev->dev, "clock-frequency",
45397904a59SKamal Dasu &priv->base_freq_hz) != 0)
45497904a59SKamal Dasu goto add_host;
45597904a59SKamal Dasu
45697904a59SKamal Dasu base_clk = devm_clk_get_optional(&pdev->dev, "sdio_freq");
45797904a59SKamal Dasu if (IS_ERR(base_clk)) {
45897904a59SKamal Dasu dev_warn(&pdev->dev, "Clock for \"sdio_freq\" not found\n");
45997904a59SKamal Dasu goto add_host;
46097904a59SKamal Dasu }
46197904a59SKamal Dasu
46297904a59SKamal Dasu res = clk_prepare_enable(base_clk);
46397904a59SKamal Dasu if (res)
46497904a59SKamal Dasu goto err;
46597904a59SKamal Dasu
46697904a59SKamal Dasu /* set improved clock rate */
46797904a59SKamal Dasu clk_set_rate(base_clk, priv->base_freq_hz);
46897904a59SKamal Dasu actual_clock_mhz = clk_get_rate(base_clk) / 1000000;
46997904a59SKamal Dasu
47097904a59SKamal Dasu host->caps &= ~SDHCI_CLOCK_V3_BASE_MASK;
47197904a59SKamal Dasu host->caps |= (actual_clock_mhz << SDHCI_CLOCK_BASE_SHIFT);
47297904a59SKamal Dasu /* Disable presets because they are now incorrect */
47397904a59SKamal Dasu host->quirks2 |= SDHCI_QUIRK2_PRESET_VALUE_BROKEN;
47497904a59SKamal Dasu
47597904a59SKamal Dasu dev_dbg(&pdev->dev, "Base Clock Frequency changed to %dMHz\n",
47697904a59SKamal Dasu actual_clock_mhz);
47797904a59SKamal Dasu priv->base_clk = base_clk;
47897904a59SKamal Dasu
47997904a59SKamal Dasu add_host:
480d46ba2d1SAl Cooper res = sdhci_brcmstb_add_host(host, priv);
481476bf3d6SAl Cooper if (res)
482476bf3d6SAl Cooper goto err;
483476bf3d6SAl Cooper
484476bf3d6SAl Cooper pltfm_host->clk = clk;
485476bf3d6SAl Cooper return res;
486476bf3d6SAl Cooper
487476bf3d6SAl Cooper err:
488476bf3d6SAl Cooper sdhci_pltfm_free(pdev);
48997904a59SKamal Dasu clk_disable_unprepare(base_clk);
490476bf3d6SAl Cooper return res;
491476bf3d6SAl Cooper }
492476bf3d6SAl Cooper
sdhci_brcmstb_shutdown(struct platform_device * pdev)493e7b5d63aSAl Cooper static void sdhci_brcmstb_shutdown(struct platform_device *pdev)
494e7b5d63aSAl Cooper {
4955b191dcbSAl Cooper sdhci_pltfm_suspend(&pdev->dev);
496e7b5d63aSAl Cooper }
497e7b5d63aSAl Cooper
498476bf3d6SAl Cooper MODULE_DEVICE_TABLE(of, sdhci_brcm_of_match);
499476bf3d6SAl Cooper
50097904a59SKamal Dasu #ifdef CONFIG_PM_SLEEP
sdhci_brcmstb_suspend(struct device * dev)50197904a59SKamal Dasu static int sdhci_brcmstb_suspend(struct device *dev)
50297904a59SKamal Dasu {
50397904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev);
50497904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
50597904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
50697904a59SKamal Dasu
50797904a59SKamal Dasu clk_disable_unprepare(priv->base_clk);
50897904a59SKamal Dasu return sdhci_pltfm_suspend(dev);
50997904a59SKamal Dasu }
51097904a59SKamal Dasu
sdhci_brcmstb_resume(struct device * dev)51197904a59SKamal Dasu static int sdhci_brcmstb_resume(struct device *dev)
51297904a59SKamal Dasu {
51397904a59SKamal Dasu struct sdhci_host *host = dev_get_drvdata(dev);
51497904a59SKamal Dasu struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
51597904a59SKamal Dasu struct sdhci_brcmstb_priv *priv = sdhci_pltfm_priv(pltfm_host);
51697904a59SKamal Dasu int ret;
51797904a59SKamal Dasu
51897904a59SKamal Dasu ret = sdhci_pltfm_resume(dev);
51997904a59SKamal Dasu if (!ret && priv->base_freq_hz) {
52097904a59SKamal Dasu ret = clk_prepare_enable(priv->base_clk);
521886201c7SKamal Dasu /*
522886201c7SKamal Dasu * Note: using clk_get_rate() below as clk_get_rate()
523886201c7SKamal Dasu * honors CLK_GET_RATE_NOCACHE attribute, but clk_set_rate()
524886201c7SKamal Dasu * may do implicit get_rate() calls that do not honor
525886201c7SKamal Dasu * CLK_GET_RATE_NOCACHE.
526886201c7SKamal Dasu */
527886201c7SKamal Dasu if (!ret &&
528886201c7SKamal Dasu (clk_get_rate(priv->base_clk) != priv->base_freq_hz))
52997904a59SKamal Dasu ret = clk_set_rate(priv->base_clk, priv->base_freq_hz);
53097904a59SKamal Dasu }
53197904a59SKamal Dasu
53297904a59SKamal Dasu return ret;
53397904a59SKamal Dasu }
53497904a59SKamal Dasu #endif
53597904a59SKamal Dasu
53697904a59SKamal Dasu static const struct dev_pm_ops sdhci_brcmstb_pmops = {
53797904a59SKamal Dasu SET_SYSTEM_SLEEP_PM_OPS(sdhci_brcmstb_suspend, sdhci_brcmstb_resume)
53897904a59SKamal Dasu };
53997904a59SKamal Dasu
540476bf3d6SAl Cooper static struct platform_driver sdhci_brcmstb_driver = {
541476bf3d6SAl Cooper .driver = {
542476bf3d6SAl Cooper .name = "sdhci-brcmstb",
5432a99f3faSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
54497904a59SKamal Dasu .pm = &sdhci_brcmstb_pmops,
545476bf3d6SAl Cooper .of_match_table = of_match_ptr(sdhci_brcm_of_match),
546476bf3d6SAl Cooper },
547476bf3d6SAl Cooper .probe = sdhci_brcmstb_probe,
548b6c90da3SAdrian Hunter .remove_new = sdhci_pltfm_remove,
549e7b5d63aSAl Cooper .shutdown = sdhci_brcmstb_shutdown,
550476bf3d6SAl Cooper };
551476bf3d6SAl Cooper
552476bf3d6SAl Cooper module_platform_driver(sdhci_brcmstb_driver);
553476bf3d6SAl Cooper
554476bf3d6SAl Cooper MODULE_DESCRIPTION("SDHCI driver for Broadcom BRCMSTB SoCs");
555476bf3d6SAl Cooper MODULE_AUTHOR("Broadcom");
556476bf3d6SAl Cooper MODULE_LICENSE("GPL v2");
557