1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* Realtek PCI-Express SD/MMC Card Interface driver 3 * 4 * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. 5 * 6 * Author: 7 * Wei WANG <wei_wang@realsil.com.cn> 8 */ 9 10 #include <linux/pci.h> 11 #include <linux/module.h> 12 #include <linux/slab.h> 13 #include <linux/highmem.h> 14 #include <linux/delay.h> 15 #include <linux/platform_device.h> 16 #include <linux/workqueue.h> 17 #include <linux/mmc/host.h> 18 #include <linux/mmc/mmc.h> 19 #include <linux/mmc/sd.h> 20 #include <linux/mmc/sdio.h> 21 #include <linux/mmc/card.h> 22 #include <linux/rtsx_pci.h> 23 #include <linux/unaligned.h> 24 #include <linux/pm_runtime.h> 25 26 struct realtek_pci_sdmmc { 27 struct platform_device *pdev; 28 struct rtsx_pcr *pcr; 29 struct mmc_host *mmc; 30 struct mmc_request *mrq; 31 #define SDMMC_WORKQ_NAME "rtsx_pci_sdmmc_workq" 32 33 struct work_struct work; 34 struct mutex host_mutex; 35 36 u8 ssc_depth; 37 unsigned int clock; 38 bool vpclk; 39 bool double_clk; 40 bool eject; 41 bool initial_mode; 42 int prev_power_state; 43 int sg_count; 44 s32 cookie; 45 int cookie_sg_count; 46 bool using_cookie; 47 }; 48 49 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios); 50 51 static inline struct device *sdmmc_dev(struct realtek_pci_sdmmc *host) 52 { 53 return &(host->pdev->dev); 54 } 55 56 static inline void sd_clear_error(struct realtek_pci_sdmmc *host) 57 { 58 rtsx_pci_write_register(host->pcr, CARD_STOP, 59 SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR); 60 } 61 62 #ifdef DEBUG 63 static void dump_reg_range(struct realtek_pci_sdmmc *host, u16 start, u16 end) 64 { 65 u16 len = end - start + 1; 66 int i; 67 u8 data[8]; 68 69 for (i = 0; i < len; i += 8) { 70 int j; 71 int n = min(8, len - i); 72 73 memset(&data, 0, sizeof(data)); 74 for (j = 0; j < n; j++) 75 rtsx_pci_read_register(host->pcr, start + i + j, 76 data + j); 77 dev_dbg(sdmmc_dev(host), "0x%04X(%d): %8ph\n", 78 start + i, n, data); 79 } 80 } 81 82 static void sd_print_debug_regs(struct realtek_pci_sdmmc *host) 83 { 84 dump_reg_range(host, 0xFDA0, 0xFDB3); 85 dump_reg_range(host, 0xFD52, 0xFD69); 86 } 87 #else 88 #define sd_print_debug_regs(host) 89 #endif /* DEBUG */ 90 91 static inline int sd_get_cd_int(struct realtek_pci_sdmmc *host) 92 { 93 return rtsx_pci_readl(host->pcr, RTSX_BIPR) & SD_EXIST; 94 } 95 96 static void sd_cmd_set_sd_cmd(struct rtsx_pcr *pcr, struct mmc_command *cmd) 97 { 98 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CMD0, 0xFF, 99 SD_CMD_START | cmd->opcode); 100 rtsx_pci_write_be32(pcr, SD_CMD1, cmd->arg); 101 } 102 103 static void sd_cmd_set_data_len(struct rtsx_pcr *pcr, u16 blocks, u16 blksz) 104 { 105 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_L, 0xFF, blocks); 106 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BLOCK_CNT_H, 0xFF, blocks >> 8); 107 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_L, 0xFF, blksz); 108 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_BYTE_CNT_H, 0xFF, blksz >> 8); 109 } 110 111 static int sd_response_type(struct mmc_command *cmd) 112 { 113 switch (mmc_resp_type(cmd)) { 114 case MMC_RSP_NONE: 115 return SD_RSP_TYPE_R0; 116 case MMC_RSP_R1: 117 return SD_RSP_TYPE_R1; 118 case MMC_RSP_R1B: 119 return SD_RSP_TYPE_R1b; 120 case MMC_RSP_R2: 121 return SD_RSP_TYPE_R2; 122 case MMC_RSP_R3: 123 return SD_RSP_TYPE_R3; 124 default: 125 return -EINVAL; 126 } 127 } 128 129 static int sd_status_index(int resp_type) 130 { 131 if (resp_type == SD_RSP_TYPE_R0) 132 return 0; 133 else if (resp_type == SD_RSP_TYPE_R2) 134 return 16; 135 136 return 5; 137 } 138 /* 139 * sd_pre_dma_transfer - do dma_map_sg() or using cookie 140 * 141 * @pre: if called in pre_req() 142 * return: 143 * 0 - do dma_map_sg() 144 * 1 - using cookie 145 */ 146 static int sd_pre_dma_transfer(struct realtek_pci_sdmmc *host, 147 struct mmc_data *data, bool pre) 148 { 149 struct rtsx_pcr *pcr = host->pcr; 150 int read = data->flags & MMC_DATA_READ; 151 int count = 0; 152 int using_cookie = 0; 153 154 if (!pre && data->host_cookie && data->host_cookie != host->cookie) { 155 dev_err(sdmmc_dev(host), 156 "error: data->host_cookie = %d, host->cookie = %d\n", 157 data->host_cookie, host->cookie); 158 data->host_cookie = 0; 159 } 160 161 if (pre || data->host_cookie != host->cookie) { 162 count = rtsx_pci_dma_map_sg(pcr, data->sg, data->sg_len, read); 163 } else { 164 count = host->cookie_sg_count; 165 using_cookie = 1; 166 } 167 168 if (pre) { 169 host->cookie_sg_count = count; 170 if (++host->cookie < 0) 171 host->cookie = 1; 172 data->host_cookie = host->cookie; 173 } else { 174 host->sg_count = count; 175 } 176 177 return using_cookie; 178 } 179 180 static void sdmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 181 { 182 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 183 struct mmc_data *data = mrq->data; 184 185 if (data->host_cookie) { 186 dev_err(sdmmc_dev(host), 187 "error: reset data->host_cookie = %d\n", 188 data->host_cookie); 189 data->host_cookie = 0; 190 } 191 192 sd_pre_dma_transfer(host, data, true); 193 dev_dbg(sdmmc_dev(host), "pre dma sg: %d\n", host->cookie_sg_count); 194 } 195 196 static void sdmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 197 int err) 198 { 199 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 200 struct rtsx_pcr *pcr = host->pcr; 201 struct mmc_data *data = mrq->data; 202 int read = data->flags & MMC_DATA_READ; 203 204 rtsx_pci_dma_unmap_sg(pcr, data->sg, data->sg_len, read); 205 data->host_cookie = 0; 206 } 207 208 static void sd_send_cmd_get_rsp(struct realtek_pci_sdmmc *host, 209 struct mmc_command *cmd) 210 { 211 struct rtsx_pcr *pcr = host->pcr; 212 u8 cmd_idx = (u8)cmd->opcode; 213 u32 arg = cmd->arg; 214 int err = 0; 215 int timeout = 100; 216 int i; 217 u8 *ptr; 218 int rsp_type; 219 int stat_idx; 220 bool clock_toggled = false; 221 222 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 223 __func__, cmd_idx, arg); 224 225 rsp_type = sd_response_type(cmd); 226 if (rsp_type < 0) 227 goto out; 228 229 stat_idx = sd_status_index(rsp_type); 230 231 if (rsp_type == SD_RSP_TYPE_R1b) 232 timeout = cmd->busy_timeout ? cmd->busy_timeout : 3000; 233 234 if (cmd->opcode == SD_SWITCH_VOLTAGE) { 235 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 236 0xFF, SD_CLK_TOGGLE_EN); 237 if (err < 0) 238 goto out; 239 240 clock_toggled = true; 241 } 242 243 rtsx_pci_init_cmd(pcr); 244 sd_cmd_set_sd_cmd(pcr, cmd); 245 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, rsp_type); 246 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 247 0x01, PINGPONG_BUFFER); 248 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 249 0xFF, SD_TM_CMD_RSP | SD_TRANSFER_START); 250 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 251 SD_TRANSFER_END | SD_STAT_IDLE, 252 SD_TRANSFER_END | SD_STAT_IDLE); 253 254 if (rsp_type == SD_RSP_TYPE_R2) { 255 /* Read data from ping-pong buffer */ 256 for (i = PPBUF_BASE2; i < PPBUF_BASE2 + 16; i++) 257 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 258 } else if (rsp_type != SD_RSP_TYPE_R0) { 259 /* Read data from SD_CMDx registers */ 260 for (i = SD_CMD0; i <= SD_CMD4; i++) 261 rtsx_pci_add_cmd(pcr, READ_REG_CMD, (u16)i, 0, 0); 262 } 263 264 rtsx_pci_add_cmd(pcr, READ_REG_CMD, SD_STAT1, 0, 0); 265 266 err = rtsx_pci_send_cmd(pcr, timeout); 267 if (err < 0) { 268 sd_print_debug_regs(host); 269 sd_clear_error(host); 270 dev_dbg(sdmmc_dev(host), 271 "rtsx_pci_send_cmd error (err = %d)\n", err); 272 goto out; 273 } 274 275 if (rsp_type == SD_RSP_TYPE_R0) { 276 err = 0; 277 goto out; 278 } 279 280 /* Eliminate returned value of CHECK_REG_CMD */ 281 ptr = rtsx_pci_get_cmd_data(pcr) + 1; 282 283 /* Check (Start,Transmission) bit of Response */ 284 if ((ptr[0] & 0xC0) != 0) { 285 err = -EILSEQ; 286 dev_dbg(sdmmc_dev(host), "Invalid response bit\n"); 287 goto out; 288 } 289 290 /* Check CRC7 */ 291 if (!(rsp_type & SD_NO_CHECK_CRC7)) { 292 if (ptr[stat_idx] & SD_CRC7_ERR) { 293 err = -EILSEQ; 294 dev_dbg(sdmmc_dev(host), "CRC7 error\n"); 295 goto out; 296 } 297 } 298 299 if (rsp_type == SD_RSP_TYPE_R2) { 300 /* 301 * The controller offloads the last byte {CRC-7, end bit 1'b1} 302 * of response type R2. Assign dummy CRC, 0, and end bit to the 303 * byte(ptr[16], goes into the LSB of resp[3] later). 304 */ 305 ptr[16] = 1; 306 307 for (i = 0; i < 4; i++) { 308 cmd->resp[i] = get_unaligned_be32(ptr + 1 + i * 4); 309 dev_dbg(sdmmc_dev(host), "cmd->resp[%d] = 0x%08x\n", 310 i, cmd->resp[i]); 311 } 312 } else { 313 cmd->resp[0] = get_unaligned_be32(ptr + 1); 314 dev_dbg(sdmmc_dev(host), "cmd->resp[0] = 0x%08x\n", 315 cmd->resp[0]); 316 } 317 318 out: 319 cmd->error = err; 320 321 if (err && clock_toggled) 322 rtsx_pci_write_register(pcr, SD_BUS_STAT, 323 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 324 } 325 326 static int sd_read_data(struct realtek_pci_sdmmc *host, struct mmc_command *cmd, 327 u16 byte_cnt, u8 *buf, int buf_len, int timeout) 328 { 329 struct rtsx_pcr *pcr = host->pcr; 330 int err; 331 u8 trans_mode; 332 333 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 334 __func__, cmd->opcode, cmd->arg); 335 336 if (!buf) 337 buf_len = 0; 338 339 if (cmd->opcode == MMC_SEND_TUNING_BLOCK) 340 trans_mode = SD_TM_AUTO_TUNING; 341 else 342 trans_mode = SD_TM_NORMAL_READ; 343 344 rtsx_pci_init_cmd(pcr); 345 sd_cmd_set_sd_cmd(pcr, cmd); 346 sd_cmd_set_data_len(pcr, 1, byte_cnt); 347 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 348 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 349 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_6); 350 if (trans_mode != SD_TM_AUTO_TUNING) 351 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 352 CARD_DATA_SOURCE, 0x01, PINGPONG_BUFFER); 353 354 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 355 0xFF, trans_mode | SD_TRANSFER_START); 356 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 357 SD_TRANSFER_END, SD_TRANSFER_END); 358 359 err = rtsx_pci_send_cmd(pcr, timeout); 360 if (err < 0) { 361 sd_print_debug_regs(host); 362 dev_dbg(sdmmc_dev(host), 363 "rtsx_pci_send_cmd fail (err = %d)\n", err); 364 return err; 365 } 366 367 if (buf && buf_len) { 368 err = rtsx_pci_read_ppbuf(pcr, buf, buf_len); 369 if (err < 0) { 370 dev_dbg(sdmmc_dev(host), 371 "rtsx_pci_read_ppbuf fail (err = %d)\n", err); 372 return err; 373 } 374 } 375 376 return 0; 377 } 378 379 static int sd_write_data(struct realtek_pci_sdmmc *host, 380 struct mmc_command *cmd, u16 byte_cnt, u8 *buf, int buf_len, 381 int timeout) 382 { 383 struct rtsx_pcr *pcr = host->pcr; 384 int err; 385 386 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 387 __func__, cmd->opcode, cmd->arg); 388 389 if (!buf) 390 buf_len = 0; 391 392 sd_send_cmd_get_rsp(host, cmd); 393 if (cmd->error) 394 return cmd->error; 395 396 if (buf && buf_len) { 397 err = rtsx_pci_write_ppbuf(pcr, buf, buf_len); 398 if (err < 0) { 399 dev_dbg(sdmmc_dev(host), 400 "rtsx_pci_write_ppbuf fail (err = %d)\n", err); 401 return err; 402 } 403 } 404 405 rtsx_pci_init_cmd(pcr); 406 sd_cmd_set_data_len(pcr, 1, byte_cnt); 407 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, 408 SD_CALCULATE_CRC7 | SD_CHECK_CRC16 | 409 SD_NO_WAIT_BUSY_END | SD_CHECK_CRC7 | SD_RSP_LEN_0); 410 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 411 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 412 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 413 SD_TRANSFER_END, SD_TRANSFER_END); 414 415 err = rtsx_pci_send_cmd(pcr, timeout); 416 if (err < 0) { 417 sd_print_debug_regs(host); 418 dev_dbg(sdmmc_dev(host), 419 "rtsx_pci_send_cmd fail (err = %d)\n", err); 420 return err; 421 } 422 423 return 0; 424 } 425 426 static int sd_read_long_data(struct realtek_pci_sdmmc *host, 427 struct mmc_request *mrq) 428 { 429 struct rtsx_pcr *pcr = host->pcr; 430 struct mmc_host *mmc = host->mmc; 431 struct mmc_card *card = mmc->card; 432 struct mmc_command *cmd = mrq->cmd; 433 struct mmc_data *data = mrq->data; 434 int uhs = mmc_card_uhs(card); 435 u8 cfg2 = 0; 436 int err; 437 int resp_type; 438 size_t data_len = data->blksz * data->blocks; 439 440 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 441 __func__, cmd->opcode, cmd->arg); 442 443 resp_type = sd_response_type(cmd); 444 if (resp_type < 0) 445 return resp_type; 446 447 if (!uhs) 448 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 449 450 rtsx_pci_init_cmd(pcr); 451 sd_cmd_set_sd_cmd(pcr, cmd); 452 sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 453 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 454 DMA_DONE_INT, DMA_DONE_INT); 455 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 456 0xFF, (u8)(data_len >> 24)); 457 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 458 0xFF, (u8)(data_len >> 16)); 459 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 460 0xFF, (u8)(data_len >> 8)); 461 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 462 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 463 0x03 | DMA_PACK_SIZE_MASK, 464 DMA_DIR_FROM_CARD | DMA_EN | DMA_512); 465 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 466 0x01, RING_BUFFER); 467 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2 | resp_type); 468 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 469 SD_TRANSFER_START | SD_TM_AUTO_READ_2); 470 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 471 SD_TRANSFER_END, SD_TRANSFER_END); 472 rtsx_pci_send_cmd_no_wait(pcr); 473 474 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 1, 10000); 475 if (err < 0) { 476 sd_print_debug_regs(host); 477 sd_clear_error(host); 478 return err; 479 } 480 481 return 0; 482 } 483 484 static int sd_write_long_data(struct realtek_pci_sdmmc *host, 485 struct mmc_request *mrq) 486 { 487 struct rtsx_pcr *pcr = host->pcr; 488 struct mmc_host *mmc = host->mmc; 489 struct mmc_card *card = mmc->card; 490 struct mmc_command *cmd = mrq->cmd; 491 struct mmc_data *data = mrq->data; 492 int uhs = mmc_card_uhs(card); 493 u8 cfg2; 494 int err; 495 size_t data_len = data->blksz * data->blocks; 496 497 sd_send_cmd_get_rsp(host, cmd); 498 if (cmd->error) 499 return cmd->error; 500 501 dev_dbg(sdmmc_dev(host), "%s: SD/MMC CMD %d, arg = 0x%08x\n", 502 __func__, cmd->opcode, cmd->arg); 503 504 cfg2 = SD_NO_CALCULATE_CRC7 | SD_CHECK_CRC16 | 505 SD_NO_WAIT_BUSY_END | SD_NO_CHECK_CRC7 | SD_RSP_LEN_0; 506 507 if (!uhs) 508 cfg2 |= SD_NO_CHECK_WAIT_CRC_TO; 509 510 rtsx_pci_init_cmd(pcr); 511 sd_cmd_set_data_len(pcr, data->blocks, data->blksz); 512 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, IRQSTAT0, 513 DMA_DONE_INT, DMA_DONE_INT); 514 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC3, 515 0xFF, (u8)(data_len >> 24)); 516 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC2, 517 0xFF, (u8)(data_len >> 16)); 518 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC1, 519 0xFF, (u8)(data_len >> 8)); 520 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMATC0, 0xFF, (u8)data_len); 521 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, DMACTL, 522 0x03 | DMA_PACK_SIZE_MASK, 523 DMA_DIR_TO_CARD | DMA_EN | DMA_512); 524 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_DATA_SOURCE, 525 0x01, RING_BUFFER); 526 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG2, 0xFF, cfg2); 527 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_TRANSFER, 0xFF, 528 SD_TRANSFER_START | SD_TM_AUTO_WRITE_3); 529 rtsx_pci_add_cmd(pcr, CHECK_REG_CMD, SD_TRANSFER, 530 SD_TRANSFER_END, SD_TRANSFER_END); 531 rtsx_pci_send_cmd_no_wait(pcr); 532 err = rtsx_pci_dma_transfer(pcr, data->sg, host->sg_count, 0, 10000); 533 if (err < 0) { 534 sd_clear_error(host); 535 return err; 536 } 537 538 return 0; 539 } 540 541 static inline void sd_enable_initial_mode(struct realtek_pci_sdmmc *host) 542 { 543 rtsx_pci_write_register(host->pcr, SD_CFG1, 544 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_128); 545 } 546 547 static inline void sd_disable_initial_mode(struct realtek_pci_sdmmc *host) 548 { 549 rtsx_pci_write_register(host->pcr, SD_CFG1, 550 SD_CLK_DIVIDE_MASK, SD_CLK_DIVIDE_0); 551 } 552 553 static int sd_rw_multi(struct realtek_pci_sdmmc *host, struct mmc_request *mrq) 554 { 555 struct mmc_data *data = mrq->data; 556 int err; 557 558 if (host->sg_count < 0) { 559 data->error = host->sg_count; 560 dev_dbg(sdmmc_dev(host), "%s: sg_count = %d is invalid\n", 561 __func__, host->sg_count); 562 return data->error; 563 } 564 565 if (data->flags & MMC_DATA_READ) { 566 if (host->initial_mode) 567 sd_disable_initial_mode(host); 568 569 err = sd_read_long_data(host, mrq); 570 571 if (host->initial_mode) 572 sd_enable_initial_mode(host); 573 574 return err; 575 } 576 577 return sd_write_long_data(host, mrq); 578 } 579 580 static void sd_normal_rw(struct realtek_pci_sdmmc *host, 581 struct mmc_request *mrq) 582 { 583 struct mmc_command *cmd = mrq->cmd; 584 struct mmc_data *data = mrq->data; 585 u8 *buf; 586 587 buf = kzalloc(data->blksz, GFP_NOIO); 588 if (!buf) { 589 cmd->error = -ENOMEM; 590 return; 591 } 592 593 if (data->flags & MMC_DATA_READ) { 594 if (host->initial_mode) 595 sd_disable_initial_mode(host); 596 597 cmd->error = sd_read_data(host, cmd, (u16)data->blksz, buf, 598 data->blksz, 200); 599 600 if (host->initial_mode) 601 sd_enable_initial_mode(host); 602 603 sg_copy_from_buffer(data->sg, data->sg_len, buf, data->blksz); 604 } else { 605 sg_copy_to_buffer(data->sg, data->sg_len, buf, data->blksz); 606 607 cmd->error = sd_write_data(host, cmd, (u16)data->blksz, buf, 608 data->blksz, 200); 609 } 610 611 kfree(buf); 612 } 613 614 static int sd_change_phase(struct realtek_pci_sdmmc *host, 615 u8 sample_point, bool rx) 616 { 617 struct rtsx_pcr *pcr = host->pcr; 618 u16 SD_VP_CTL = 0; 619 dev_dbg(sdmmc_dev(host), "%s(%s): sample_point = %d\n", 620 __func__, rx ? "RX" : "TX", sample_point); 621 622 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, CHANGE_CLK); 623 if (rx) { 624 SD_VP_CTL = SD_VPRX_CTL; 625 rtsx_pci_write_register(pcr, SD_VPRX_CTL, 626 PHASE_SELECT_MASK, sample_point); 627 } else { 628 SD_VP_CTL = SD_VPTX_CTL; 629 rtsx_pci_write_register(pcr, SD_VPTX_CTL, 630 PHASE_SELECT_MASK, sample_point); 631 } 632 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 0); 633 rtsx_pci_write_register(pcr, SD_VP_CTL, PHASE_NOT_RESET, 634 PHASE_NOT_RESET); 635 rtsx_pci_write_register(pcr, CLK_CTL, CHANGE_CLK, 0); 636 rtsx_pci_write_register(pcr, SD_CFG1, SD_ASYNC_FIFO_NOT_RST, 0); 637 638 return 0; 639 } 640 641 static inline u32 test_phase_bit(u32 phase_map, unsigned int bit) 642 { 643 bit %= RTSX_PHASE_MAX; 644 return phase_map & (1 << bit); 645 } 646 647 static int sd_get_phase_len(u32 phase_map, unsigned int start_bit) 648 { 649 int i; 650 651 for (i = 0; i < RTSX_PHASE_MAX; i++) { 652 if (test_phase_bit(phase_map, start_bit + i) == 0) 653 return i; 654 } 655 return RTSX_PHASE_MAX; 656 } 657 658 static u8 sd_search_final_phase(struct realtek_pci_sdmmc *host, u32 phase_map) 659 { 660 int start = 0, len = 0; 661 int start_final = 0, len_final = 0; 662 u8 final_phase = 0xFF; 663 664 if (phase_map == 0) { 665 dev_err(sdmmc_dev(host), "phase error: [map:%x]\n", phase_map); 666 return final_phase; 667 } 668 669 while (start < RTSX_PHASE_MAX) { 670 len = sd_get_phase_len(phase_map, start); 671 if (len_final < len) { 672 start_final = start; 673 len_final = len; 674 } 675 start += len ? len : 1; 676 } 677 678 final_phase = (start_final + len_final / 2) % RTSX_PHASE_MAX; 679 dev_dbg(sdmmc_dev(host), "phase: [map:%x] [maxlen:%d] [final:%d]\n", 680 phase_map, len_final, final_phase); 681 682 return final_phase; 683 } 684 685 static void sd_wait_data_idle(struct realtek_pci_sdmmc *host) 686 { 687 int i; 688 u8 val = 0; 689 690 for (i = 0; i < 100; i++) { 691 rtsx_pci_read_register(host->pcr, SD_DATA_STATE, &val); 692 if (val & SD_DATA_IDLE) 693 return; 694 695 udelay(100); 696 } 697 } 698 699 static int sd_tuning_rx_cmd(struct realtek_pci_sdmmc *host, 700 u8 opcode, u8 sample_point) 701 { 702 int err; 703 struct mmc_command cmd = {}; 704 struct rtsx_pcr *pcr = host->pcr; 705 706 sd_change_phase(host, sample_point, true); 707 708 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 709 SD_RSP_80CLK_TIMEOUT_EN); 710 711 cmd.opcode = opcode; 712 err = sd_read_data(host, &cmd, 0x40, NULL, 0, 100); 713 if (err < 0) { 714 /* Wait till SD DATA IDLE */ 715 sd_wait_data_idle(host); 716 sd_clear_error(host); 717 rtsx_pci_write_register(pcr, SD_CFG3, 718 SD_RSP_80CLK_TIMEOUT_EN, 0); 719 return err; 720 } 721 722 rtsx_pci_write_register(pcr, SD_CFG3, SD_RSP_80CLK_TIMEOUT_EN, 0); 723 return 0; 724 } 725 726 static int sd_tuning_phase(struct realtek_pci_sdmmc *host, 727 u8 opcode, u32 *phase_map) 728 { 729 int err, i; 730 u32 raw_phase_map = 0; 731 732 for (i = 0; i < RTSX_PHASE_MAX; i++) { 733 err = sd_tuning_rx_cmd(host, opcode, (u8)i); 734 if (err == 0) 735 raw_phase_map |= 1 << i; 736 } 737 738 if (phase_map) 739 *phase_map = raw_phase_map; 740 741 return 0; 742 } 743 744 static int sd_tuning_rx(struct realtek_pci_sdmmc *host, u8 opcode) 745 { 746 int err, i; 747 u32 raw_phase_map[RX_TUNING_CNT] = {0}, phase_map; 748 u8 final_phase; 749 750 for (i = 0; i < RX_TUNING_CNT; i++) { 751 err = sd_tuning_phase(host, opcode, &(raw_phase_map[i])); 752 if (err < 0) 753 return err; 754 755 if (raw_phase_map[i] == 0) 756 break; 757 } 758 759 phase_map = 0xFFFFFFFF; 760 for (i = 0; i < RX_TUNING_CNT; i++) { 761 dev_dbg(sdmmc_dev(host), "RX raw_phase_map[%d] = 0x%08x\n", 762 i, raw_phase_map[i]); 763 phase_map &= raw_phase_map[i]; 764 } 765 dev_dbg(sdmmc_dev(host), "RX phase_map = 0x%08x\n", phase_map); 766 767 if (phase_map) { 768 final_phase = sd_search_final_phase(host, phase_map); 769 if (final_phase == 0xFF) 770 return -EINVAL; 771 772 err = sd_change_phase(host, final_phase, true); 773 if (err < 0) 774 return err; 775 } else { 776 return -EINVAL; 777 } 778 779 return 0; 780 } 781 782 static inline int sdio_extblock_cmd(struct mmc_command *cmd, 783 struct mmc_data *data) 784 { 785 return (cmd->opcode == SD_IO_RW_EXTENDED) && (data->blksz == 512); 786 } 787 788 static inline int sd_rw_cmd(struct mmc_command *cmd) 789 { 790 return mmc_op_multi(cmd->opcode) || 791 (cmd->opcode == MMC_READ_SINGLE_BLOCK) || 792 (cmd->opcode == MMC_WRITE_BLOCK); 793 } 794 795 static void sd_request(struct work_struct *work) 796 { 797 struct realtek_pci_sdmmc *host = container_of(work, 798 struct realtek_pci_sdmmc, work); 799 struct rtsx_pcr *pcr = host->pcr; 800 801 struct mmc_host *mmc = host->mmc; 802 struct mmc_request *mrq = host->mrq; 803 struct mmc_command *cmd = mrq->cmd; 804 struct mmc_data *data = mrq->data; 805 806 unsigned int data_size = 0; 807 int err; 808 809 if (host->eject || !sd_get_cd_int(host)) { 810 cmd->error = -ENOMEDIUM; 811 goto finish; 812 } 813 814 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 815 if (err) { 816 cmd->error = err; 817 goto finish; 818 } 819 820 mutex_lock(&pcr->pcr_mutex); 821 822 rtsx_pci_start_run(pcr); 823 824 rtsx_pci_switch_clock(pcr, host->clock, host->ssc_depth, 825 host->initial_mode, host->double_clk, host->vpclk); 826 rtsx_pci_write_register(pcr, CARD_SELECT, 0x07, SD_MOD_SEL); 827 rtsx_pci_write_register(pcr, CARD_SHARE_MODE, 828 CARD_SHARE_MASK, CARD_SHARE_48_SD); 829 830 mutex_lock(&host->host_mutex); 831 host->mrq = mrq; 832 mutex_unlock(&host->host_mutex); 833 834 if (mrq->data) 835 data_size = data->blocks * data->blksz; 836 837 if (!data_size) { 838 sd_send_cmd_get_rsp(host, cmd); 839 } else if (sd_rw_cmd(cmd) || sdio_extblock_cmd(cmd, data)) { 840 cmd->error = sd_rw_multi(host, mrq); 841 if (!host->using_cookie) 842 sdmmc_post_req(host->mmc, host->mrq, 0); 843 844 if (mmc_op_multi(cmd->opcode) && mrq->stop) 845 sd_send_cmd_get_rsp(host, mrq->stop); 846 } else { 847 sd_normal_rw(host, mrq); 848 } 849 850 if (mrq->data) { 851 if (cmd->error || data->error) 852 data->bytes_xfered = 0; 853 else 854 data->bytes_xfered = data->blocks * data->blksz; 855 } 856 857 mutex_unlock(&pcr->pcr_mutex); 858 859 finish: 860 if (cmd->error) { 861 dev_dbg(sdmmc_dev(host), "CMD %d 0x%08x error(%d)\n", 862 cmd->opcode, cmd->arg, cmd->error); 863 } 864 865 mutex_lock(&host->host_mutex); 866 host->mrq = NULL; 867 mutex_unlock(&host->host_mutex); 868 869 mmc_request_done(mmc, mrq); 870 } 871 872 static void sdmmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 873 { 874 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 875 struct mmc_data *data = mrq->data; 876 877 mutex_lock(&host->host_mutex); 878 host->mrq = mrq; 879 mutex_unlock(&host->host_mutex); 880 881 if (sd_rw_cmd(mrq->cmd) || sdio_extblock_cmd(mrq->cmd, data)) 882 host->using_cookie = sd_pre_dma_transfer(host, data, false); 883 884 schedule_work(&host->work); 885 } 886 887 static int sd_set_bus_width(struct realtek_pci_sdmmc *host, 888 unsigned char bus_width) 889 { 890 int err = 0; 891 u8 width[] = { 892 [MMC_BUS_WIDTH_1] = SD_BUS_WIDTH_1BIT, 893 [MMC_BUS_WIDTH_4] = SD_BUS_WIDTH_4BIT, 894 [MMC_BUS_WIDTH_8] = SD_BUS_WIDTH_8BIT, 895 }; 896 897 if (bus_width <= MMC_BUS_WIDTH_8) 898 err = rtsx_pci_write_register(host->pcr, SD_CFG1, 899 0x03, width[bus_width]); 900 901 return err; 902 } 903 904 static int sd_power_on(struct realtek_pci_sdmmc *host, unsigned char power_mode) 905 { 906 struct rtsx_pcr *pcr = host->pcr; 907 struct mmc_host *mmc = host->mmc; 908 int err; 909 u32 val; 910 u8 test_mode; 911 912 if (host->prev_power_state == MMC_POWER_ON) 913 return 0; 914 915 if (host->prev_power_state == MMC_POWER_UP) { 916 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, 0); 917 goto finish; 918 } 919 920 msleep(100); 921 922 rtsx_pci_init_cmd(pcr); 923 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SELECT, 0x07, SD_MOD_SEL); 924 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_SHARE_MODE, 925 CARD_SHARE_MASK, CARD_SHARE_48_SD); 926 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, 927 SD_CLK_EN, SD_CLK_EN); 928 err = rtsx_pci_send_cmd(pcr, 100); 929 if (err < 0) 930 return err; 931 932 err = rtsx_pci_card_pull_ctl_enable(pcr, RTSX_SD_CARD); 933 if (err < 0) 934 return err; 935 936 err = rtsx_pci_card_power_on(pcr, RTSX_SD_CARD); 937 if (err < 0) 938 return err; 939 940 mdelay(1); 941 942 err = rtsx_pci_write_register(pcr, CARD_OE, SD_OUTPUT_EN, SD_OUTPUT_EN); 943 if (err < 0) 944 return err; 945 946 /* send at least 74 clocks */ 947 rtsx_pci_write_register(pcr, SD_BUS_STAT, SD_CLK_TOGGLE_EN, SD_CLK_TOGGLE_EN); 948 949 if ((PCI_PID(pcr) == PID_5261) || (PCI_PID(pcr) == PID_5264)) { 950 /* 951 * If test mode is set switch to SD Express mandatorily, 952 * this is only for factory testing. 953 */ 954 rtsx_pci_read_register(pcr, RTS5261_FW_CFG_INFO0, &test_mode); 955 if (test_mode & RTS5261_FW_EXPRESS_TEST_MASK) { 956 sdmmc_init_sd_express(mmc, NULL); 957 return 0; 958 } 959 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 960 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 961 /* 962 * HW read wp status when resuming from S3/S4, 963 * and then picks SD legacy interface if it's set 964 * in read-only mode. 965 */ 966 val = rtsx_pci_readl(pcr, RTSX_BIPR); 967 if (val & SD_WRITE_PROTECT) { 968 pcr->extra_caps &= ~EXTRA_CAPS_SD_EXPRESS; 969 mmc->caps2 &= ~(MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V); 970 } 971 } 972 973 finish: 974 host->prev_power_state = power_mode; 975 return 0; 976 } 977 978 static int sd_power_off(struct realtek_pci_sdmmc *host) 979 { 980 struct rtsx_pcr *pcr = host->pcr; 981 int err; 982 983 host->prev_power_state = MMC_POWER_OFF; 984 985 rtsx_pci_init_cmd(pcr); 986 987 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_EN, SD_CLK_EN, 0); 988 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE, SD_OUTPUT_EN, 0); 989 990 err = rtsx_pci_send_cmd(pcr, 100); 991 if (err < 0) 992 return err; 993 994 err = rtsx_pci_card_power_off(pcr, RTSX_SD_CARD); 995 if (err < 0) 996 return err; 997 998 return rtsx_pci_card_pull_ctl_disable(pcr, RTSX_SD_CARD); 999 } 1000 1001 static int sd_set_power_mode(struct realtek_pci_sdmmc *host, 1002 unsigned char power_mode) 1003 { 1004 int err; 1005 1006 if (power_mode == MMC_POWER_OFF) 1007 err = sd_power_off(host); 1008 else 1009 err = sd_power_on(host, power_mode); 1010 1011 return err; 1012 } 1013 1014 static int sd_set_timing(struct realtek_pci_sdmmc *host, unsigned char timing) 1015 { 1016 struct rtsx_pcr *pcr = host->pcr; 1017 int err = 0; 1018 1019 rtsx_pci_init_cmd(pcr); 1020 1021 switch (timing) { 1022 case MMC_TIMING_UHS_SDR104: 1023 case MMC_TIMING_UHS_SDR50: 1024 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1025 0x0C | SD_ASYNC_FIFO_NOT_RST, 1026 SD_30_MODE | SD_ASYNC_FIFO_NOT_RST); 1027 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1028 CLK_LOW_FREQ, CLK_LOW_FREQ); 1029 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1030 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1031 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1032 break; 1033 1034 case MMC_TIMING_MMC_DDR52: 1035 case MMC_TIMING_UHS_DDR50: 1036 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1037 0x0C | SD_ASYNC_FIFO_NOT_RST, 1038 SD_DDR_MODE | SD_ASYNC_FIFO_NOT_RST); 1039 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1040 CLK_LOW_FREQ, CLK_LOW_FREQ); 1041 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1042 CRC_VAR_CLK0 | SD30_FIX_CLK | SAMPLE_VAR_CLK1); 1043 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1044 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1045 DDR_VAR_TX_CMD_DAT, DDR_VAR_TX_CMD_DAT); 1046 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1047 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD, 1048 DDR_VAR_RX_DAT | DDR_VAR_RX_CMD); 1049 break; 1050 1051 case MMC_TIMING_MMC_HS: 1052 case MMC_TIMING_SD_HS: 1053 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_CFG1, 1054 0x0C, SD_20_MODE); 1055 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1056 CLK_LOW_FREQ, CLK_LOW_FREQ); 1057 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1058 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1059 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1060 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_PUSH_POINT_CTL, 1061 SD20_TX_SEL_MASK, SD20_TX_14_AHEAD); 1062 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1063 SD20_RX_SEL_MASK, SD20_RX_14_DELAY); 1064 break; 1065 1066 default: 1067 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1068 SD_CFG1, 0x0C, SD_20_MODE); 1069 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, 1070 CLK_LOW_FREQ, CLK_LOW_FREQ); 1071 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_CLK_SOURCE, 0xFF, 1072 CRC_FIX_CLK | SD30_VAR_CLK0 | SAMPLE_VAR_CLK1); 1073 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CLK_CTL, CLK_LOW_FREQ, 0); 1074 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, 1075 SD_PUSH_POINT_CTL, 0xFF, 0); 1076 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD_SAMPLE_POINT_CTL, 1077 SD20_RX_SEL_MASK, SD20_RX_POS_EDGE); 1078 break; 1079 } 1080 1081 err = rtsx_pci_send_cmd(pcr, 100); 1082 1083 return err; 1084 } 1085 1086 static void sdmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1087 { 1088 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1089 struct rtsx_pcr *pcr = host->pcr; 1090 1091 if (host->eject) 1092 return; 1093 1094 if (rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD)) 1095 return; 1096 1097 mutex_lock(&pcr->pcr_mutex); 1098 1099 rtsx_pci_start_run(pcr); 1100 1101 sd_set_bus_width(host, ios->bus_width); 1102 sd_set_power_mode(host, ios->power_mode); 1103 sd_set_timing(host, ios->timing); 1104 1105 host->vpclk = false; 1106 host->double_clk = true; 1107 1108 switch (ios->timing) { 1109 case MMC_TIMING_UHS_SDR104: 1110 case MMC_TIMING_UHS_SDR50: 1111 host->ssc_depth = RTSX_SSC_DEPTH_2M; 1112 host->vpclk = true; 1113 host->double_clk = false; 1114 break; 1115 case MMC_TIMING_MMC_DDR52: 1116 case MMC_TIMING_UHS_DDR50: 1117 case MMC_TIMING_UHS_SDR25: 1118 host->ssc_depth = RTSX_SSC_DEPTH_1M; 1119 break; 1120 default: 1121 host->ssc_depth = RTSX_SSC_DEPTH_500K; 1122 break; 1123 } 1124 1125 host->initial_mode = (ios->clock <= 1000000) ? true : false; 1126 1127 host->clock = ios->clock; 1128 rtsx_pci_switch_clock(pcr, ios->clock, host->ssc_depth, 1129 host->initial_mode, host->double_clk, host->vpclk); 1130 1131 mutex_unlock(&pcr->pcr_mutex); 1132 } 1133 1134 static int sdmmc_get_ro(struct mmc_host *mmc) 1135 { 1136 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1137 struct rtsx_pcr *pcr = host->pcr; 1138 int ro = 0; 1139 u32 val; 1140 1141 if (host->eject) 1142 return -ENOMEDIUM; 1143 1144 mutex_lock(&pcr->pcr_mutex); 1145 1146 rtsx_pci_start_run(pcr); 1147 1148 /* Check SD mechanical write-protect switch */ 1149 val = rtsx_pci_readl(pcr, RTSX_BIPR); 1150 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1151 if (val & SD_WRITE_PROTECT) 1152 ro = 1; 1153 1154 mutex_unlock(&pcr->pcr_mutex); 1155 1156 return ro; 1157 } 1158 1159 static int sdmmc_get_cd(struct mmc_host *mmc) 1160 { 1161 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1162 struct rtsx_pcr *pcr = host->pcr; 1163 int cd = 0; 1164 u32 val; 1165 1166 if (host->eject) 1167 return cd; 1168 1169 mutex_lock(&pcr->pcr_mutex); 1170 1171 rtsx_pci_start_run(pcr); 1172 1173 /* Check SD card detect */ 1174 val = rtsx_pci_card_exist(pcr); 1175 dev_dbg(sdmmc_dev(host), "%s: RTSX_BIPR = 0x%08x\n", __func__, val); 1176 if (val & SD_EXIST) 1177 cd = 1; 1178 1179 mutex_unlock(&pcr->pcr_mutex); 1180 1181 return cd; 1182 } 1183 1184 static int sd_wait_voltage_stable_1(struct realtek_pci_sdmmc *host) 1185 { 1186 struct rtsx_pcr *pcr = host->pcr; 1187 int err; 1188 u8 stat; 1189 1190 /* Reference to Signal Voltage Switch Sequence in SD spec. 1191 * Wait for a period of time so that the card can drive SD_CMD and 1192 * SD_DAT[3:0] to low after sending back CMD11 response. 1193 */ 1194 mdelay(1); 1195 1196 /* SD_CMD, SD_DAT[3:0] should be driven to low by card; 1197 * If either one of SD_CMD,SD_DAT[3:0] is not low, 1198 * abort the voltage switch sequence; 1199 */ 1200 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1201 if (err < 0) 1202 return err; 1203 1204 if (stat & (SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1205 SD_DAT1_STATUS | SD_DAT0_STATUS)) 1206 return -EINVAL; 1207 1208 /* Stop toggle SD clock */ 1209 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1210 0xFF, SD_CLK_FORCE_STOP); 1211 if (err < 0) 1212 return err; 1213 1214 return 0; 1215 } 1216 1217 static int sd_wait_voltage_stable_2(struct realtek_pci_sdmmc *host) 1218 { 1219 struct rtsx_pcr *pcr = host->pcr; 1220 int err; 1221 u8 stat, mask, val; 1222 1223 /* Wait 1.8V output of voltage regulator in card stable */ 1224 msleep(50); 1225 1226 /* Toggle SD clock again */ 1227 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 0xFF, SD_CLK_TOGGLE_EN); 1228 if (err < 0) 1229 return err; 1230 1231 /* Wait for a period of time so that the card can drive 1232 * SD_DAT[3:0] to high at 1.8V 1233 */ 1234 msleep(20); 1235 1236 /* SD_CMD, SD_DAT[3:0] should be pulled high by host */ 1237 err = rtsx_pci_read_register(pcr, SD_BUS_STAT, &stat); 1238 if (err < 0) 1239 return err; 1240 1241 mask = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1242 SD_DAT1_STATUS | SD_DAT0_STATUS; 1243 val = SD_CMD_STATUS | SD_DAT3_STATUS | SD_DAT2_STATUS | 1244 SD_DAT1_STATUS | SD_DAT0_STATUS; 1245 if ((stat & mask) != val) { 1246 dev_dbg(sdmmc_dev(host), 1247 "%s: SD_BUS_STAT = 0x%x\n", __func__, stat); 1248 rtsx_pci_write_register(pcr, SD_BUS_STAT, 1249 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1250 rtsx_pci_write_register(pcr, CARD_CLK_EN, 0xFF, 0); 1251 return -EINVAL; 1252 } 1253 1254 return 0; 1255 } 1256 1257 static int sdmmc_switch_voltage(struct mmc_host *mmc, struct mmc_ios *ios) 1258 { 1259 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1260 struct rtsx_pcr *pcr = host->pcr; 1261 int err = 0; 1262 u8 voltage; 1263 1264 dev_dbg(sdmmc_dev(host), "%s: signal_voltage = %d\n", 1265 __func__, ios->signal_voltage); 1266 1267 if (host->eject) 1268 return -ENOMEDIUM; 1269 1270 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1271 if (err) 1272 return err; 1273 1274 mutex_lock(&pcr->pcr_mutex); 1275 1276 rtsx_pci_start_run(pcr); 1277 1278 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) 1279 voltage = OUTPUT_3V3; 1280 else 1281 voltage = OUTPUT_1V8; 1282 1283 if (voltage == OUTPUT_1V8) { 1284 err = sd_wait_voltage_stable_1(host); 1285 if (err < 0) 1286 goto out; 1287 } 1288 1289 err = rtsx_pci_switch_output_voltage(pcr, voltage); 1290 if (err < 0) 1291 goto out; 1292 1293 if (voltage == OUTPUT_1V8) { 1294 err = sd_wait_voltage_stable_2(host); 1295 if (err < 0) 1296 goto out; 1297 } 1298 1299 out: 1300 /* Stop toggle SD clock in idle */ 1301 err = rtsx_pci_write_register(pcr, SD_BUS_STAT, 1302 SD_CLK_TOGGLE_EN | SD_CLK_FORCE_STOP, 0); 1303 1304 mutex_unlock(&pcr->pcr_mutex); 1305 1306 return err; 1307 } 1308 1309 static int sdmmc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1310 { 1311 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1312 struct rtsx_pcr *pcr = host->pcr; 1313 int err = 0; 1314 1315 if (host->eject) 1316 return -ENOMEDIUM; 1317 1318 err = rtsx_pci_card_exclusive_check(host->pcr, RTSX_SD_CARD); 1319 if (err) 1320 return err; 1321 1322 mutex_lock(&pcr->pcr_mutex); 1323 1324 rtsx_pci_start_run(pcr); 1325 1326 /* Set initial TX phase */ 1327 switch (mmc->ios.timing) { 1328 case MMC_TIMING_UHS_SDR104: 1329 err = sd_change_phase(host, SDR104_TX_PHASE(pcr), false); 1330 break; 1331 1332 case MMC_TIMING_UHS_SDR50: 1333 err = sd_change_phase(host, SDR50_TX_PHASE(pcr), false); 1334 break; 1335 1336 case MMC_TIMING_UHS_DDR50: 1337 err = sd_change_phase(host, DDR50_TX_PHASE(pcr), false); 1338 break; 1339 1340 default: 1341 err = 0; 1342 } 1343 1344 if (err) 1345 goto out; 1346 1347 /* Tuning RX phase */ 1348 if ((mmc->ios.timing == MMC_TIMING_UHS_SDR104) || 1349 (mmc->ios.timing == MMC_TIMING_UHS_SDR50)) 1350 err = sd_tuning_rx(host, opcode); 1351 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) 1352 err = sd_change_phase(host, DDR50_RX_PHASE(pcr), true); 1353 1354 out: 1355 mutex_unlock(&pcr->pcr_mutex); 1356 1357 return err; 1358 } 1359 1360 static int sdmmc_init_sd_express(struct mmc_host *mmc, struct mmc_ios *ios) 1361 { 1362 u32 relink_time; 1363 struct realtek_pci_sdmmc *host = mmc_priv(mmc); 1364 struct rtsx_pcr *pcr = host->pcr; 1365 1366 if (PCI_PID(pcr) == PID_5264) { 1367 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL2, 1368 PCI_EXP_LNKCTL2_TLS, PCI_EXP_LNKCTL2_TLS_2_5GT); 1369 pci_write_config_byte(pcr->pci, 0x80e, 0x02); 1370 pcie_capability_clear_and_set_word(pcr->pci, PCI_EXP_LNKCTL2, 1371 PCI_EXP_LNKCTL2_TLS, PCI_EXP_LNKCTL2_TLS_5_0GT); 1372 } 1373 1374 /* Set relink_time for changing to PCIe card */ 1375 relink_time = 0x8FFF; 1376 1377 rtsx_pci_write_register(pcr, 0xFF01, 0xFF, relink_time); 1378 rtsx_pci_write_register(pcr, 0xFF02, 0xFF, relink_time >> 8); 1379 rtsx_pci_write_register(pcr, 0xFF03, 0x01, relink_time >> 16); 1380 1381 rtsx_pci_write_register(pcr, PETXCFG, 0x80, 0x80); 1382 rtsx_pci_write_register(pcr, LDO_VCC_CFG0, 1383 RTS5261_LDO1_OCP_THD_MASK, 1384 pcr->option.sd_800mA_ocp_thd); 1385 1386 if (pcr->ops->disable_auto_blink) 1387 pcr->ops->disable_auto_blink(pcr); 1388 1389 if (PCI_PID(pcr) == PID_5264) { 1390 rtsx_pci_write_register(pcr, RTS5264_AUTOLOAD_CFG2, 1391 RTS5264_CHIP_RST_N_SEL, RTS5264_CHIP_RST_N_SEL); 1392 rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00); 1393 } 1394 1395 /* For PCIe/NVMe mode can't enter delink issue */ 1396 pcr->hw_param.interrupt_en &= ~(SD_INT_EN); 1397 rtsx_pci_writel(pcr, RTSX_BIER, pcr->hw_param.interrupt_en); 1398 1399 rtsx_pci_write_register(pcr, RTS5260_AUTOLOAD_CFG4, 1400 RTS5261_AUX_CLK_16M_EN, RTS5261_AUX_CLK_16M_EN); 1401 rtsx_pci_write_register(pcr, RTS5261_FW_CFG0, 1402 RTS5261_FW_ENTER_EXPRESS, RTS5261_FW_ENTER_EXPRESS); 1403 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 1404 RTS5261_MCU_CLOCK_GATING, RTS5261_MCU_CLOCK_GATING); 1405 rtsx_pci_write_register(pcr, RTS5261_FW_CFG1, 1406 RTS5261_MCU_BUS_SEL_MASK | RTS5261_MCU_CLOCK_SEL_MASK 1407 | RTS5261_DRIVER_ENABLE_FW, 1408 RTS5261_MCU_CLOCK_SEL_16M | RTS5261_DRIVER_ENABLE_FW); 1409 host->eject = true; 1410 return 0; 1411 } 1412 1413 static const struct mmc_host_ops realtek_pci_sdmmc_ops = { 1414 .pre_req = sdmmc_pre_req, 1415 .post_req = sdmmc_post_req, 1416 .request = sdmmc_request, 1417 .set_ios = sdmmc_set_ios, 1418 .get_ro = sdmmc_get_ro, 1419 .get_cd = sdmmc_get_cd, 1420 .start_signal_voltage_switch = sdmmc_switch_voltage, 1421 .execute_tuning = sdmmc_execute_tuning, 1422 .init_sd_express = sdmmc_init_sd_express, 1423 }; 1424 1425 static void init_extra_caps(struct realtek_pci_sdmmc *host) 1426 { 1427 struct mmc_host *mmc = host->mmc; 1428 struct rtsx_pcr *pcr = host->pcr; 1429 1430 dev_dbg(sdmmc_dev(host), "pcr->extra_caps = 0x%x\n", pcr->extra_caps); 1431 1432 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR50) 1433 mmc->caps |= MMC_CAP_UHS_SDR50; 1434 if (pcr->extra_caps & EXTRA_CAPS_SD_SDR104) 1435 mmc->caps |= MMC_CAP_UHS_SDR104; 1436 if (pcr->extra_caps & EXTRA_CAPS_SD_DDR50) 1437 mmc->caps |= MMC_CAP_UHS_DDR50; 1438 if (pcr->extra_caps & EXTRA_CAPS_MMC_HSDDR) 1439 mmc->caps |= MMC_CAP_1_8V_DDR; 1440 if (pcr->extra_caps & EXTRA_CAPS_MMC_8BIT) 1441 mmc->caps |= MMC_CAP_8_BIT_DATA; 1442 if (pcr->extra_caps & EXTRA_CAPS_NO_MMC) 1443 mmc->caps2 |= MMC_CAP2_NO_MMC; 1444 if (pcr->extra_caps & EXTRA_CAPS_SD_EXPRESS) 1445 mmc->caps2 |= MMC_CAP2_SD_EXP | MMC_CAP2_SD_EXP_1_2V; 1446 } 1447 1448 static void realtek_init_host(struct realtek_pci_sdmmc *host) 1449 { 1450 struct mmc_host *mmc = host->mmc; 1451 struct rtsx_pcr *pcr = host->pcr; 1452 1453 mmc->f_min = 250000; 1454 mmc->f_max = 208000000; 1455 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195; 1456 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SD_HIGHSPEED | 1457 MMC_CAP_MMC_HIGHSPEED | MMC_CAP_BUS_WIDTH_TEST | 1458 MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; 1459 if (pcr->rtd3_en) 1460 mmc->caps = mmc->caps | MMC_CAP_AGGRESSIVE_PM; 1461 mmc->caps2 = MMC_CAP2_NO_PRESCAN_POWERUP | MMC_CAP2_FULL_PWR_CYCLE | 1462 MMC_CAP2_NO_SDIO; 1463 mmc->max_current_330 = 400; 1464 mmc->max_current_180 = 800; 1465 mmc->ops = &realtek_pci_sdmmc_ops; 1466 1467 init_extra_caps(host); 1468 1469 mmc->max_segs = 256; 1470 mmc->max_seg_size = 65536; 1471 mmc->max_blk_size = 512; 1472 mmc->max_blk_count = 65535; 1473 mmc->max_req_size = 524288; 1474 } 1475 1476 static void rtsx_pci_sdmmc_card_event(struct platform_device *pdev) 1477 { 1478 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1479 1480 host->cookie = -1; 1481 mmc_detect_change(host->mmc, 0); 1482 } 1483 1484 static int rtsx_pci_sdmmc_drv_probe(struct platform_device *pdev) 1485 { 1486 struct mmc_host *mmc; 1487 struct realtek_pci_sdmmc *host; 1488 struct rtsx_pcr *pcr; 1489 struct pcr_handle *handle = pdev->dev.platform_data; 1490 int ret; 1491 1492 if (!handle) 1493 return -ENXIO; 1494 1495 pcr = handle->pcr; 1496 if (!pcr) 1497 return -ENXIO; 1498 1499 dev_dbg(&(pdev->dev), ": Realtek PCI-E SDMMC controller found\n"); 1500 1501 mmc = mmc_alloc_host(sizeof(*host), &pdev->dev); 1502 if (!mmc) 1503 return -ENOMEM; 1504 1505 host = mmc_priv(mmc); 1506 host->pcr = pcr; 1507 mmc->ios.power_delay_ms = 5; 1508 host->mmc = mmc; 1509 host->pdev = pdev; 1510 host->cookie = -1; 1511 host->prev_power_state = MMC_POWER_OFF; 1512 INIT_WORK(&host->work, sd_request); 1513 platform_set_drvdata(pdev, host); 1514 pcr->slots[RTSX_SD_CARD].p_dev = pdev; 1515 pcr->slots[RTSX_SD_CARD].card_event = rtsx_pci_sdmmc_card_event; 1516 1517 mutex_init(&host->host_mutex); 1518 1519 realtek_init_host(host); 1520 1521 pm_runtime_no_callbacks(&pdev->dev); 1522 pm_runtime_set_active(&pdev->dev); 1523 pm_runtime_enable(&pdev->dev); 1524 pm_runtime_set_autosuspend_delay(&pdev->dev, 200); 1525 pm_runtime_mark_last_busy(&pdev->dev); 1526 pm_runtime_use_autosuspend(&pdev->dev); 1527 1528 ret = mmc_add_host(mmc); 1529 if (ret) { 1530 pm_runtime_dont_use_autosuspend(&pdev->dev); 1531 pm_runtime_disable(&pdev->dev); 1532 mmc_free_host(mmc); 1533 return ret; 1534 } 1535 1536 return 0; 1537 } 1538 1539 static void rtsx_pci_sdmmc_drv_remove(struct platform_device *pdev) 1540 { 1541 struct realtek_pci_sdmmc *host = platform_get_drvdata(pdev); 1542 struct rtsx_pcr *pcr; 1543 struct mmc_host *mmc; 1544 1545 pcr = host->pcr; 1546 pcr->slots[RTSX_SD_CARD].p_dev = NULL; 1547 pcr->slots[RTSX_SD_CARD].card_event = NULL; 1548 mmc = host->mmc; 1549 1550 cancel_work_sync(&host->work); 1551 1552 mutex_lock(&host->host_mutex); 1553 if (host->mrq) { 1554 dev_dbg(&(pdev->dev), 1555 "%s: Controller removed during transfer\n", 1556 mmc_hostname(mmc)); 1557 1558 rtsx_pci_complete_unfinished_transfer(pcr); 1559 1560 host->mrq->cmd->error = -ENOMEDIUM; 1561 if (host->mrq->stop) 1562 host->mrq->stop->error = -ENOMEDIUM; 1563 mmc_request_done(mmc, host->mrq); 1564 } 1565 mutex_unlock(&host->host_mutex); 1566 1567 mmc_remove_host(mmc); 1568 host->eject = true; 1569 1570 flush_work(&host->work); 1571 1572 pm_runtime_dont_use_autosuspend(&pdev->dev); 1573 pm_runtime_disable(&pdev->dev); 1574 1575 mmc_free_host(mmc); 1576 1577 dev_dbg(&(pdev->dev), 1578 ": Realtek PCI-E SDMMC controller has been removed\n"); 1579 } 1580 1581 static const struct platform_device_id rtsx_pci_sdmmc_ids[] = { 1582 { 1583 .name = DRV_NAME_RTSX_PCI_SDMMC, 1584 }, { 1585 /* sentinel */ 1586 } 1587 }; 1588 MODULE_DEVICE_TABLE(platform, rtsx_pci_sdmmc_ids); 1589 1590 static struct platform_driver rtsx_pci_sdmmc_driver = { 1591 .probe = rtsx_pci_sdmmc_drv_probe, 1592 .remove = rtsx_pci_sdmmc_drv_remove, 1593 .id_table = rtsx_pci_sdmmc_ids, 1594 .driver = { 1595 .name = DRV_NAME_RTSX_PCI_SDMMC, 1596 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1597 }, 1598 }; 1599 module_platform_driver(rtsx_pci_sdmmc_driver); 1600 1601 MODULE_LICENSE("GPL"); 1602 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>"); 1603 MODULE_DESCRIPTION("Realtek PCI-E SD/MMC Card Host Driver"); 1604