xref: /linux/drivers/mmc/host/renesas_sdhi_internal_dmac.c (revision 3f374d7972c48bc0824bdabb8f94fe82e54fd07d)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * DMA support for Internal DMAC with SDHI SD/SDIO controller
4  *
5  * Copyright (C) 2016-19 Renesas Electronics Corporation
6  * Copyright (C) 2016-17 Horms Solutions, Simon Horman
7  * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang
8  */
9 
10 #include <linux/bitops.h>
11 #include <linux/device.h>
12 #include <linux/dma-mapping.h>
13 #include <linux/io-64-nonatomic-hi-lo.h>
14 #include <linux/mfd/tmio.h>
15 #include <linux/mmc/host.h>
16 #include <linux/mod_devicetable.h>
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/pagemap.h>
20 #include <linux/scatterlist.h>
21 #include <linux/sys_soc.h>
22 
23 #include "renesas_sdhi.h"
24 #include "tmio_mmc.h"
25 
26 #define DM_CM_DTRAN_MODE	0x820
27 #define DM_CM_DTRAN_CTRL	0x828
28 #define DM_CM_RST		0x830
29 #define DM_CM_INFO1		0x840
30 #define DM_CM_INFO1_MASK	0x848
31 #define DM_CM_INFO2		0x850
32 #define DM_CM_INFO2_MASK	0x858
33 #define DM_DTRAN_ADDR		0x880
34 
35 /* DM_CM_DTRAN_MODE */
36 #define DTRAN_MODE_CH_NUM_CH0	0	/* "downstream" = for write commands */
37 #define DTRAN_MODE_CH_NUM_CH1	BIT(16)	/* "upstream" = for read commands */
38 #define DTRAN_MODE_BUS_WIDTH	(BIT(5) | BIT(4))
39 #define DTRAN_MODE_ADDR_MODE	BIT(0)	/* 1 = Increment address, 0 = Fixed */
40 
41 /* DM_CM_DTRAN_CTRL */
42 #define DTRAN_CTRL_DM_START	BIT(0)
43 
44 /* DM_CM_RST */
45 #define RST_DTRANRST1		BIT(9)
46 #define RST_DTRANRST0		BIT(8)
47 #define RST_RESERVED_BITS	GENMASK_ULL(31, 0)
48 
49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */
50 #define INFO1_CLEAR		0
51 #define INFO1_MASK_CLEAR	GENMASK_ULL(31, 0)
52 #define INFO1_DTRANEND1		BIT(17)
53 #define INFO1_DTRANEND0		BIT(16)
54 
55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */
56 #define INFO2_MASK_CLEAR	GENMASK_ULL(31, 0)
57 #define INFO2_DTRANERR1		BIT(17)
58 #define INFO2_DTRANERR0		BIT(16)
59 
60 enum renesas_sdhi_dma_cookie {
61 	COOKIE_UNMAPPED,
62 	COOKIE_PRE_MAPPED,
63 	COOKIE_MAPPED,
64 };
65 
66 /*
67  * Specification of this driver:
68  * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma
69  * - Since this SDHI DMAC register set has 16 but 32-bit width, we
70  *   need a custom accessor.
71  */
72 
73 static unsigned long global_flags;
74 /*
75  * Workaround for avoiding to use RX DMAC by multiple channels.
76  * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use
77  * RX DMAC simultaneously, sometimes hundreds of bytes data are not
78  * stored into the system memory even if the DMAC interrupt happened.
79  * So, this driver then uses one RX DMAC channel only.
80  */
81 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY	0
82 #define SDHI_INTERNAL_DMAC_RX_IN_USE	1
83 
84 /* RZ/A2 does not have the ADRR_MODE bit */
85 #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2
86 
87 /* Definitions for sampling clocks */
88 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = {
89 	{
90 		.clk_rate = 0,
91 		.tap = 0x00000300,
92 		.tap_hs400_4tap = 0x00000100,
93 	},
94 };
95 
96 static const struct renesas_sdhi_of_data of_data_rza2 = {
97 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
98 			  TMIO_MMC_HAVE_CBSY,
99 	.tmio_ocr_mask	= MMC_VDD_32_33,
100 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
101 			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
102 	.bus_shift	= 2,
103 	.scc_offset	= 0 - 0x1000,
104 	.taps		= rcar_gen3_scc_taps,
105 	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
106 	/* DMAC can handle 32bit blk count but only 1 segment */
107 	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
108 	.max_segs	= 1,
109 };
110 
111 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = {
112 	.of_data	= &of_data_rza2,
113 };
114 
115 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = {
116 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
117 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
118 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
119 			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
120 	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
121 	.bus_shift	= 2,
122 	.scc_offset	= 0x1000,
123 	.taps		= rcar_gen3_scc_taps,
124 	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
125 	/* DMAC can handle 32bit blk count but only 1 segment */
126 	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
127 	.max_segs	= 1,
128 	.sdhi_flags	= SDHI_FLAG_NEED_CLKH_FALLBACK,
129 };
130 
131 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_fallback = {
132 	.tmio_flags	= TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL |
133 			  TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2,
134 	.capabilities	= MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
135 			  MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY,
136 	.capabilities2	= MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE,
137 	.bus_shift	= 2,
138 	.scc_offset	= 0x1000,
139 	.taps		= rcar_gen3_scc_taps,
140 	.taps_num	= ARRAY_SIZE(rcar_gen3_scc_taps),
141 	/* DMAC can handle 32bit blk count but only 1 segment */
142 	.max_blk_count	= UINT_MAX / TMIO_MAX_BLK_SIZE,
143 	.max_segs	= 1,
144 };
145 
146 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
147 	{ 3,  3,  3,  3,  3,  3,  3,  4,  4,  5,  6,  7,  8,  9, 10, 15,
148 	 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 },
149 	{ 5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  5,  6,  7,  8, 11,
150 	 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 }
151 };
152 
153 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
154 	{ 1,  2,  6,  6,  7,  8,  9, 10, 11, 12, 13, 14, 15, 15, 15, 16,
155 	 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 },
156 	{ 2,  3,  4,  4,  5,  6,  7,  9, 10, 11, 12, 13, 14, 15, 16, 17,
157 	 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 }
158 };
159 
160 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = {
161 	{ 0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
162 	  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0 },
163 	{ 0,  0,  0,  1,  2,  3,  3,  4,  4,  4,  5,  5,  6,  8,  9, 10,
164 	 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 }
165 };
166 
167 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = {
168 	.hs400_disabled = true,
169 	.hs400_4taps = true,
170 };
171 
172 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = {
173 	.hs400_4taps = true,
174 	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
175 };
176 
177 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = {
178 	.hs400_disabled = true,
179 };
180 
181 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = {
182 	.hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7),
183 };
184 
185 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = {
186 	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
187 };
188 
189 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = {
190 	.hs400_4taps = true,
191 	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
192 	.hs400_calib_table = r8a7796_es13_calib_table,
193 };
194 
195 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = {
196 	.hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7),
197 	.hs400_calib_table = r8a77965_calib_table,
198 };
199 
200 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = {
201 	.hs400_calib_table = r8a77990_calib_table,
202 };
203 
204 /*
205  * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now.
206  * So, we want to treat them equally and only have a match for ES1.2 to enforce
207  * this if there ever will be a way to distinguish ES1.2.
208  */
209 static const struct soc_device_attribute sdhi_quirks_match[]  = {
210 	{ .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
211 	{ .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 },
212 	{ .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap },
213 	{ .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 },
214 	{ .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 },
215 	{ /* Sentinel. */ }
216 };
217 
218 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = {
219 	.of_data = &of_data_rcar_gen3,
220 	.quirks = &sdhi_quirks_bad_taps2367,
221 };
222 
223 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = {
224 	.of_data = &of_data_rcar_gen3,
225 	.quirks = &sdhi_quirks_bad_taps1357,
226 };
227 
228 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = {
229 	.of_data = &of_data_rcar_gen3,
230 	.quirks = &sdhi_quirks_r8a77965,
231 };
232 
233 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = {
234 	.of_data = &of_data_rcar_gen3_no_fallback,
235 };
236 
237 static const struct renesas_sdhi_of_data_with_quirks of_r8a77980_compatible = {
238 	.of_data = &of_data_rcar_gen3,
239 	.quirks = &sdhi_quirks_nohs400,
240 };
241 
242 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = {
243 	.of_data = &of_data_rcar_gen3,
244 	.quirks = &sdhi_quirks_r8a77990,
245 };
246 
247 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = {
248 	.of_data = &of_data_rcar_gen3,
249 };
250 
251 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = {
252 	{ .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, },
253 	{ .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, },
254 	{ .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, },
255 	{ .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, },
256 	{ .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, },
257 	{ .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, },
258 	{ .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, },
259 	{ .compatible = "renesas,sdhi-r8a77980", .data = &of_r8a77980_compatible, },
260 	{ .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, },
261 	{ .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, },
262 	{},
263 };
264 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match);
265 
266 static void
267 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host,
268 				    int addr, u64 val)
269 {
270 	writeq(val, host->ctl + addr);
271 }
272 
273 static void
274 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable)
275 {
276 	struct renesas_sdhi *priv = host_to_priv(host);
277 
278 	if (!host->chan_tx || !host->chan_rx)
279 		return;
280 
281 	if (!enable)
282 		renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1,
283 						    INFO1_CLEAR);
284 
285 	if (priv->dma_priv.enable)
286 		priv->dma_priv.enable(host, enable);
287 }
288 
289 static void
290 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) {
291 	u64 val = RST_DTRANRST1 | RST_DTRANRST0;
292 
293 	renesas_sdhi_internal_dmac_enable_dma(host, false);
294 
295 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
296 					    RST_RESERVED_BITS & ~val);
297 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST,
298 					    RST_RESERVED_BITS | val);
299 
300 	clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
301 
302 	renesas_sdhi_internal_dmac_enable_dma(host, true);
303 }
304 
305 static void
306 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) {
307 	struct renesas_sdhi *priv = host_to_priv(host);
308 
309 	tasklet_schedule(&priv->dma_priv.dma_complete);
310 }
311 
312 /*
313  * renesas_sdhi_internal_dmac_map() will be called with two difference
314  * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single
315  * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg
316  * pointer in a mmc_data instead of host->sg_ptr.
317  */
318 static void
319 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host,
320 				 struct mmc_data *data,
321 				 enum renesas_sdhi_dma_cookie cookie)
322 {
323 	bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) :
324 						 (data->host_cookie == cookie);
325 
326 	if (unmap) {
327 		dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len,
328 			     mmc_get_dma_dir(data));
329 		data->host_cookie = COOKIE_UNMAPPED;
330 	}
331 }
332 
333 static bool
334 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host,
335 			       struct mmc_data *data,
336 			       enum renesas_sdhi_dma_cookie cookie)
337 {
338 	if (data->host_cookie == COOKIE_PRE_MAPPED)
339 		return true;
340 
341 	if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
342 			    mmc_get_dma_dir(data)))
343 		return false;
344 
345 	data->host_cookie = cookie;
346 
347 	/* This DMAC cannot handle if buffer is not 128-bytes alignment */
348 	if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) {
349 		renesas_sdhi_internal_dmac_unmap(host, data, cookie);
350 		return false;
351 	}
352 
353 	return true;
354 }
355 
356 static void
357 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host,
358 				     struct mmc_data *data)
359 {
360 	struct scatterlist *sg = host->sg_ptr;
361 	u32 dtran_mode = DTRAN_MODE_BUS_WIDTH;
362 
363 	if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags))
364 		dtran_mode |= DTRAN_MODE_ADDR_MODE;
365 
366 	if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED))
367 		goto force_pio;
368 
369 	if (data->flags & MMC_DATA_READ) {
370 		dtran_mode |= DTRAN_MODE_CH_NUM_CH1;
371 		if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) &&
372 		    test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags))
373 			goto force_pio_with_unmap;
374 	} else {
375 		dtran_mode |= DTRAN_MODE_CH_NUM_CH0;
376 	}
377 
378 	renesas_sdhi_internal_dmac_enable_dma(host, true);
379 
380 	/* set dma parameters */
381 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE,
382 					    dtran_mode);
383 	renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR,
384 					    sg_dma_address(sg));
385 
386 	host->dma_on = true;
387 
388 	return;
389 
390 force_pio_with_unmap:
391 	renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
392 
393 force_pio:
394 	renesas_sdhi_internal_dmac_enable_dma(host, false);
395 }
396 
397 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg)
398 {
399 	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
400 
401 	tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND);
402 
403 	/* start the DMAC */
404 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL,
405 					    DTRAN_CTRL_DM_START);
406 }
407 
408 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host)
409 {
410 	enum dma_data_direction dir;
411 
412 	if (!host->dma_on)
413 		return false;
414 
415 	if (!host->data)
416 		return false;
417 
418 	if (host->data->flags & MMC_DATA_READ)
419 		dir = DMA_FROM_DEVICE;
420 	else
421 		dir = DMA_TO_DEVICE;
422 
423 	renesas_sdhi_internal_dmac_enable_dma(host, false);
424 	renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED);
425 
426 	if (dir == DMA_FROM_DEVICE)
427 		clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags);
428 
429 	host->dma_on = false;
430 
431 	return true;
432 }
433 
434 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg)
435 {
436 	struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg;
437 
438 	spin_lock_irq(&host->lock);
439 	if (!renesas_sdhi_internal_dmac_complete(host))
440 		goto out;
441 
442 	tmio_mmc_do_data_irq(host);
443 out:
444 	spin_unlock_irq(&host->lock);
445 }
446 
447 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host)
448 {
449 	if (host->data)
450 		renesas_sdhi_internal_dmac_complete(host);
451 }
452 
453 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc,
454 						struct mmc_request *mrq,
455 						int err)
456 {
457 	struct tmio_mmc_host *host = mmc_priv(mmc);
458 	struct mmc_data *data = mrq->data;
459 
460 	if (!data)
461 		return;
462 
463 	renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED);
464 }
465 
466 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc,
467 					       struct mmc_request *mrq)
468 {
469 	struct tmio_mmc_host *host = mmc_priv(mmc);
470 	struct mmc_data *data = mrq->data;
471 
472 	if (!data)
473 		return;
474 
475 	data->host_cookie = COOKIE_UNMAPPED;
476 	renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED);
477 }
478 
479 static void
480 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host,
481 				       struct tmio_mmc_data *pdata)
482 {
483 	struct renesas_sdhi *priv = host_to_priv(host);
484 
485 	/* Disable DMAC interrupts, we don't use them */
486 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK,
487 					    INFO1_MASK_CLEAR);
488 	renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK,
489 					    INFO2_MASK_CLEAR);
490 
491 	/* Each value is set to non-zero to assume "enabling" each DMA */
492 	host->chan_rx = host->chan_tx = (void *)0xdeadbeaf;
493 
494 	tasklet_init(&priv->dma_priv.dma_complete,
495 		     renesas_sdhi_internal_dmac_complete_tasklet_fn,
496 		     (unsigned long)host);
497 	tasklet_init(&host->dma_issue,
498 		     renesas_sdhi_internal_dmac_issue_tasklet_fn,
499 		     (unsigned long)host);
500 
501 	/* Add pre_req and post_req */
502 	host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req;
503 	host->ops.post_req = renesas_sdhi_internal_dmac_post_req;
504 }
505 
506 static void
507 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host)
508 {
509 	/* Each value is set to zero to assume "disabling" each DMA */
510 	host->chan_rx = host->chan_tx = NULL;
511 }
512 
513 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = {
514 	.start = renesas_sdhi_internal_dmac_start_dma,
515 	.enable = renesas_sdhi_internal_dmac_enable_dma,
516 	.request = renesas_sdhi_internal_dmac_request_dma,
517 	.release = renesas_sdhi_internal_dmac_release_dma,
518 	.abort = renesas_sdhi_internal_dmac_abort_dma,
519 	.dataend = renesas_sdhi_internal_dmac_dataend_dma,
520 	.end = renesas_sdhi_internal_dmac_end_dma,
521 };
522 
523 /*
524  * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC
525  * implementation as others may use a different implementation.
526  */
527 static const struct soc_device_attribute soc_dma_quirks[] = {
528 	{ .soc_id = "r7s9210",
529 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) },
530 	{ .soc_id = "r8a7795", .revision = "ES1.*",
531 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
532 	{ .soc_id = "r8a7796", .revision = "ES1.0",
533 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
534 	{ /* sentinel */ }
535 };
536 
537 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev)
538 {
539 	const struct soc_device_attribute *attr;
540 	const struct renesas_sdhi_of_data_with_quirks *of_data_quirks;
541 	const struct renesas_sdhi_quirks *quirks;
542 	struct device *dev = &pdev->dev;
543 
544 	of_data_quirks = of_device_get_match_data(&pdev->dev);
545 	quirks = of_data_quirks->quirks;
546 
547 	attr = soc_device_match(soc_dma_quirks);
548 	if (attr)
549 		global_flags |= (unsigned long)attr->data;
550 
551 	attr = soc_device_match(sdhi_quirks_match);
552 	if (attr)
553 		quirks = attr->data;
554 
555 	/* value is max of SD_SECCNT. Confirmed by HW engineers */
556 	dma_set_max_seg_size(dev, 0xffffffff);
557 
558 	return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops,
559 				  of_data_quirks->of_data, quirks);
560 }
561 
562 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = {
563 	SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
564 				pm_runtime_force_resume)
565 	SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend,
566 			   tmio_mmc_host_runtime_resume,
567 			   NULL)
568 };
569 
570 static struct platform_driver renesas_internal_dmac_sdhi_driver = {
571 	.driver		= {
572 		.name	= "renesas_sdhi_internal_dmac",
573 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
574 		.pm	= &renesas_sdhi_internal_dmac_dev_pm_ops,
575 		.of_match_table = renesas_sdhi_internal_dmac_of_match,
576 	},
577 	.probe		= renesas_sdhi_internal_dmac_probe,
578 	.remove		= renesas_sdhi_remove,
579 };
580 
581 module_platform_driver(renesas_internal_dmac_sdhi_driver);
582 
583 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC");
584 MODULE_AUTHOR("Yoshihiro Shimoda");
585 MODULE_LICENSE("GPL v2");
586