1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io-64-nonatomic-hi-lo.h> 14 #include <linux/mfd/tmio.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 38 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_CLEAR 0 51 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 52 #define INFO1_DTRANEND1 BIT(17) 53 #define INFO1_DTRANEND0 BIT(16) 54 55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 56 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 57 #define INFO2_DTRANERR1 BIT(17) 58 #define INFO2_DTRANERR0 BIT(16) 59 60 enum renesas_sdhi_dma_cookie { 61 COOKIE_UNMAPPED, 62 COOKIE_PRE_MAPPED, 63 COOKIE_MAPPED, 64 }; 65 66 /* 67 * Specification of this driver: 68 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 69 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 70 * need a custom accessor. 71 */ 72 73 static unsigned long global_flags; 74 /* 75 * Workaround for avoiding to use RX DMAC by multiple channels. 76 * On R-Car H3 ES1.* and M3-W ES1.0, when multiple SDHI channels use 77 * RX DMAC simultaneously, sometimes hundreds of bytes data are not 78 * stored into the system memory even if the DMAC interrupt happened. 79 * So, this driver then uses one RX DMAC channel only. 80 */ 81 #define SDHI_INTERNAL_DMAC_ONE_RX_ONLY 0 82 #define SDHI_INTERNAL_DMAC_RX_IN_USE 1 83 84 /* RZ/A2 does not have the ADRR_MODE bit */ 85 #define SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY 2 86 87 /* Definitions for sampling clocks */ 88 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 89 { 90 .clk_rate = 0, 91 .tap = 0x00000300, 92 .tap_hs400_4tap = 0x00000100, 93 }, 94 }; 95 96 static const struct renesas_sdhi_of_data of_data_rza2 = { 97 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 98 TMIO_MMC_HAVE_CBSY, 99 .tmio_ocr_mask = MMC_VDD_32_33, 100 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 101 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 102 .bus_shift = 2, 103 .scc_offset = 0 - 0x1000, 104 .taps = rcar_gen3_scc_taps, 105 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 106 /* DMAC can handle 32bit blk count but only 1 segment */ 107 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 108 .max_segs = 1, 109 }; 110 111 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 112 .of_data = &of_data_rza2, 113 }; 114 115 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 116 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 117 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 118 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 119 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 120 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 121 .bus_shift = 2, 122 .scc_offset = 0x1000, 123 .taps = rcar_gen3_scc_taps, 124 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 125 /* DMAC can handle 32bit blk count but only 1 segment */ 126 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 127 .max_segs = 1, 128 }; 129 130 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 131 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 132 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 133 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 134 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 135 }; 136 137 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 138 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 139 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 140 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 141 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 142 }; 143 144 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 145 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 146 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 147 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 148 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 149 }; 150 151 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 152 .hs400_disabled = true, 153 .hs400_4taps = true, 154 }; 155 156 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 157 .hs400_4taps = true, 158 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 159 }; 160 161 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 162 .hs400_disabled = true, 163 }; 164 165 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 166 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 167 }; 168 169 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 170 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 171 }; 172 173 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 174 .hs400_4taps = true, 175 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 176 .hs400_calib_table = r8a7796_es13_calib_table, 177 }; 178 179 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 180 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 181 .hs400_calib_table = r8a77965_calib_table, 182 }; 183 184 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 185 .hs400_calib_table = r8a77990_calib_table, 186 }; 187 188 /* 189 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 190 * So, we want to treat them equally and only have a match for ES1.2 to enforce 191 * this if there ever will be a way to distinguish ES1.2. 192 */ 193 static const struct soc_device_attribute sdhi_quirks_match[] = { 194 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 195 { .soc_id = "r8a7795", .revision = "ES1.*", .data = &sdhi_quirks_4tap_nohs400 }, 196 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 197 { .soc_id = "r8a7796", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 198 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 199 { /* Sentinel. */ }, 200 }; 201 202 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 203 .of_data = &of_data_rcar_gen3, 204 .quirks = &sdhi_quirks_bad_taps2367, 205 }; 206 207 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 208 .of_data = &of_data_rcar_gen3, 209 .quirks = &sdhi_quirks_bad_taps1357, 210 }; 211 212 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 213 .of_data = &of_data_rcar_gen3, 214 .quirks = &sdhi_quirks_r8a77965, 215 }; 216 217 static const struct renesas_sdhi_of_data_with_quirks of_r8a77980_compatible = { 218 .of_data = &of_data_rcar_gen3, 219 .quirks = &sdhi_quirks_nohs400, 220 }; 221 222 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 223 .of_data = &of_data_rcar_gen3, 224 .quirks = &sdhi_quirks_r8a77990, 225 }; 226 227 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 228 .of_data = &of_data_rcar_gen3, 229 }; 230 231 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 232 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 233 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 234 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 235 { .compatible = "renesas,sdhi-r8a7796", .data = &of_rcar_gen3_compatible, }, 236 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 237 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 238 { .compatible = "renesas,sdhi-r8a77980", .data = &of_r8a77980_compatible, }, 239 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 240 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 241 {}, 242 }; 243 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 244 245 static void 246 renesas_sdhi_internal_dmac_dm_write(struct tmio_mmc_host *host, 247 int addr, u64 val) 248 { 249 writeq(val, host->ctl + addr); 250 } 251 252 static void 253 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 254 { 255 struct renesas_sdhi *priv = host_to_priv(host); 256 257 if (!host->chan_tx || !host->chan_rx) 258 return; 259 260 if (!enable) 261 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1, 262 INFO1_CLEAR); 263 264 if (priv->dma_priv.enable) 265 priv->dma_priv.enable(host, enable); 266 } 267 268 static void 269 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) { 270 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 271 272 renesas_sdhi_internal_dmac_enable_dma(host, false); 273 274 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 275 RST_RESERVED_BITS & ~val); 276 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_RST, 277 RST_RESERVED_BITS | val); 278 279 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 280 281 renesas_sdhi_internal_dmac_enable_dma(host, true); 282 } 283 284 static void 285 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) { 286 struct renesas_sdhi *priv = host_to_priv(host); 287 288 tasklet_schedule(&priv->dma_priv.dma_complete); 289 } 290 291 /* 292 * renesas_sdhi_internal_dmac_map() will be called with two difference 293 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 294 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 295 * pointer in a mmc_data instead of host->sg_ptr. 296 */ 297 static void 298 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 299 struct mmc_data *data, 300 enum renesas_sdhi_dma_cookie cookie) 301 { 302 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 303 (data->host_cookie == cookie); 304 305 if (unmap) { 306 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 307 mmc_get_dma_dir(data)); 308 data->host_cookie = COOKIE_UNMAPPED; 309 } 310 } 311 312 static bool 313 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 314 struct mmc_data *data, 315 enum renesas_sdhi_dma_cookie cookie) 316 { 317 if (data->host_cookie == COOKIE_PRE_MAPPED) 318 return true; 319 320 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 321 mmc_get_dma_dir(data))) 322 return false; 323 324 data->host_cookie = cookie; 325 326 /* This DMAC cannot handle if buffer is not 128-bytes alignment */ 327 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 328 renesas_sdhi_internal_dmac_unmap(host, data, cookie); 329 return false; 330 } 331 332 return true; 333 } 334 335 static void 336 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 337 struct mmc_data *data) 338 { 339 struct scatterlist *sg = host->sg_ptr; 340 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 341 342 if (!test_bit(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY, &global_flags)) 343 dtran_mode |= DTRAN_MODE_ADDR_MODE; 344 345 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 346 goto force_pio; 347 348 if (data->flags & MMC_DATA_READ) { 349 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 350 if (test_bit(SDHI_INTERNAL_DMAC_ONE_RX_ONLY, &global_flags) && 351 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 352 goto force_pio_with_unmap; 353 } else { 354 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 355 } 356 357 renesas_sdhi_internal_dmac_enable_dma(host, true); 358 359 /* set dma parameters */ 360 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_MODE, 361 dtran_mode); 362 renesas_sdhi_internal_dmac_dm_write(host, DM_DTRAN_ADDR, 363 sg_dma_address(sg)); 364 365 host->dma_on = true; 366 367 return; 368 369 force_pio_with_unmap: 370 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 371 372 force_pio: 373 renesas_sdhi_internal_dmac_enable_dma(host, false); 374 } 375 376 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 377 { 378 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 379 380 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 381 382 /* start the DMAC */ 383 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_DTRAN_CTRL, 384 DTRAN_CTRL_DM_START); 385 } 386 387 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 388 { 389 enum dma_data_direction dir; 390 391 if (!host->dma_on) 392 return false; 393 394 if (!host->data) 395 return false; 396 397 if (host->data->flags & MMC_DATA_READ) 398 dir = DMA_FROM_DEVICE; 399 else 400 dir = DMA_TO_DEVICE; 401 402 renesas_sdhi_internal_dmac_enable_dma(host, false); 403 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 404 405 if (dir == DMA_FROM_DEVICE) 406 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 407 408 host->dma_on = false; 409 410 return true; 411 } 412 413 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 414 { 415 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 416 417 spin_lock_irq(&host->lock); 418 if (!renesas_sdhi_internal_dmac_complete(host)) 419 goto out; 420 421 tmio_mmc_do_data_irq(host); 422 out: 423 spin_unlock_irq(&host->lock); 424 } 425 426 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 427 { 428 if (host->data) 429 renesas_sdhi_internal_dmac_complete(host); 430 } 431 432 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 433 struct mmc_request *mrq, 434 int err) 435 { 436 struct tmio_mmc_host *host = mmc_priv(mmc); 437 struct mmc_data *data = mrq->data; 438 439 if (!data) 440 return; 441 442 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 443 } 444 445 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 446 struct mmc_request *mrq) 447 { 448 struct tmio_mmc_host *host = mmc_priv(mmc); 449 struct mmc_data *data = mrq->data; 450 451 if (!data) 452 return; 453 454 data->host_cookie = COOKIE_UNMAPPED; 455 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 456 } 457 458 static void 459 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 460 struct tmio_mmc_data *pdata) 461 { 462 struct renesas_sdhi *priv = host_to_priv(host); 463 464 /* Disable DMAC interrupts, we don't use them */ 465 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO1_MASK, 466 INFO1_MASK_CLEAR); 467 renesas_sdhi_internal_dmac_dm_write(host, DM_CM_INFO2_MASK, 468 INFO2_MASK_CLEAR); 469 470 /* Each value is set to non-zero to assume "enabling" each DMA */ 471 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 472 473 tasklet_init(&priv->dma_priv.dma_complete, 474 renesas_sdhi_internal_dmac_complete_tasklet_fn, 475 (unsigned long)host); 476 tasklet_init(&host->dma_issue, 477 renesas_sdhi_internal_dmac_issue_tasklet_fn, 478 (unsigned long)host); 479 480 /* Add pre_req and post_req */ 481 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 482 host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 483 } 484 485 static void 486 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 487 { 488 /* Each value is set to zero to assume "disabling" each DMA */ 489 host->chan_rx = host->chan_tx = NULL; 490 } 491 492 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 493 .start = renesas_sdhi_internal_dmac_start_dma, 494 .enable = renesas_sdhi_internal_dmac_enable_dma, 495 .request = renesas_sdhi_internal_dmac_request_dma, 496 .release = renesas_sdhi_internal_dmac_release_dma, 497 .abort = renesas_sdhi_internal_dmac_abort_dma, 498 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 499 .end = renesas_sdhi_internal_dmac_end_dma, 500 }; 501 502 /* 503 * Whitelist of specific R-Car Gen3 SoC ES versions to use this DMAC 504 * implementation as others may use a different implementation. 505 */ 506 static const struct soc_device_attribute soc_dma_quirks[] = { 507 { .soc_id = "r7s9210", 508 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ADDR_MODE_FIXED_ONLY) }, 509 { .soc_id = "r8a7795", .revision = "ES1.*", 510 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 511 { .soc_id = "r8a7796", .revision = "ES1.0", 512 .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) }, 513 { /* sentinel */ } 514 }; 515 516 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 517 { 518 const struct soc_device_attribute *attr; 519 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 520 const struct renesas_sdhi_quirks *quirks; 521 struct device *dev = &pdev->dev; 522 523 of_data_quirks = of_device_get_match_data(&pdev->dev); 524 quirks = of_data_quirks->quirks; 525 526 attr = soc_device_match(soc_dma_quirks); 527 if (attr) 528 global_flags |= (unsigned long)attr->data; 529 530 attr = soc_device_match(sdhi_quirks_match); 531 if (attr) 532 quirks = attr->data; 533 534 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 535 dma_set_max_seg_size(dev, 0xffffffff); 536 537 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 538 of_data_quirks->of_data, quirks); 539 } 540 541 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 542 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 543 pm_runtime_force_resume) 544 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 545 tmio_mmc_host_runtime_resume, 546 NULL) 547 }; 548 549 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 550 .driver = { 551 .name = "renesas_sdhi_internal_dmac", 552 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 553 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 554 .of_match_table = renesas_sdhi_internal_dmac_of_match, 555 }, 556 .probe = renesas_sdhi_internal_dmac_probe, 557 .remove = renesas_sdhi_remove, 558 }; 559 560 module_platform_driver(renesas_internal_dmac_sdhi_driver); 561 562 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 563 MODULE_AUTHOR("Yoshihiro Shimoda"); 564 MODULE_LICENSE("GPL v2"); 565