1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * DMA support for Internal DMAC with SDHI SD/SDIO controller 4 * 5 * Copyright (C) 2016-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 7 * Copyright (C) 2018-19 Sang Engineering, Wolfram Sang 8 */ 9 10 #include <linux/bitops.h> 11 #include <linux/device.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/io-64-nonatomic-hi-lo.h> 14 #include <linux/mfd/tmio.h> 15 #include <linux/mmc/host.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/pagemap.h> 20 #include <linux/scatterlist.h> 21 #include <linux/sys_soc.h> 22 23 #include "renesas_sdhi.h" 24 #include "tmio_mmc.h" 25 26 #define DM_CM_DTRAN_MODE 0x820 27 #define DM_CM_DTRAN_CTRL 0x828 28 #define DM_CM_RST 0x830 29 #define DM_CM_INFO1 0x840 30 #define DM_CM_INFO1_MASK 0x848 31 #define DM_CM_INFO2 0x850 32 #define DM_CM_INFO2_MASK 0x858 33 #define DM_DTRAN_ADDR 0x880 34 35 /* DM_CM_DTRAN_MODE */ 36 #define DTRAN_MODE_CH_NUM_CH0 0 /* "downstream" = for write commands */ 37 #define DTRAN_MODE_CH_NUM_CH1 BIT(16) /* "upstream" = for read commands */ 38 #define DTRAN_MODE_BUS_WIDTH (BIT(5) | BIT(4)) 39 #define DTRAN_MODE_ADDR_MODE BIT(0) /* 1 = Increment address, 0 = Fixed */ 40 41 /* DM_CM_DTRAN_CTRL */ 42 #define DTRAN_CTRL_DM_START BIT(0) 43 44 /* DM_CM_RST */ 45 #define RST_DTRANRST1 BIT(9) 46 #define RST_DTRANRST0 BIT(8) 47 #define RST_RESERVED_BITS GENMASK_ULL(31, 0) 48 49 /* DM_CM_INFO1 and DM_CM_INFO1_MASK */ 50 #define INFO1_MASK_CLEAR GENMASK_ULL(31, 0) 51 #define INFO1_DTRANEND1 BIT(20) 52 #define INFO1_DTRANEND1_OLD BIT(17) 53 #define INFO1_DTRANEND0 BIT(16) 54 55 /* DM_CM_INFO2 and DM_CM_INFO2_MASK */ 56 #define INFO2_MASK_CLEAR GENMASK_ULL(31, 0) 57 #define INFO2_DTRANERR1 BIT(17) 58 #define INFO2_DTRANERR0 BIT(16) 59 60 enum renesas_sdhi_dma_cookie { 61 COOKIE_UNMAPPED, 62 COOKIE_PRE_MAPPED, 63 COOKIE_MAPPED, 64 }; 65 66 /* 67 * Specification of this driver: 68 * - host->chan_{rx,tx} will be used as a flag of enabling/disabling the dma 69 * - Since this SDHI DMAC register set has 16 but 32-bit width, we 70 * need a custom accessor. 71 */ 72 73 static unsigned long global_flags; 74 /* 75 * Workaround for avoiding to use RX DMAC by multiple channels. On R-Car M3-W 76 * ES1.0, when multiple SDHI channels use RX DMAC simultaneously, sometimes 77 * hundreds of data bytes are not stored into the system memory even if the 78 * DMAC interrupt happened. So, this driver then uses one RX DMAC channel only. 79 */ 80 #define SDHI_INTERNAL_DMAC_RX_IN_USE 0 81 82 /* Definitions for sampling clocks */ 83 static struct renesas_sdhi_scc rcar_gen3_scc_taps[] = { 84 { 85 .clk_rate = 0, 86 .tap = 0x00000300, 87 .tap_hs400_4tap = 0x00000100, 88 }, 89 }; 90 91 static const struct renesas_sdhi_of_data of_data_rza2 = { 92 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 93 TMIO_MMC_HAVE_CBSY, 94 .tmio_ocr_mask = MMC_VDD_32_33, 95 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 96 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 97 .bus_shift = 2, 98 .scc_offset = 0 - 0x1000, 99 .taps = rcar_gen3_scc_taps, 100 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 101 /* DMAC can handle 32bit blk count but only 1 segment */ 102 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 103 .max_segs = 1, 104 }; 105 106 static const struct renesas_sdhi_of_data of_data_rcar_gen3 = { 107 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 108 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 109 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 110 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 111 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 112 .bus_shift = 2, 113 .scc_offset = 0x1000, 114 .taps = rcar_gen3_scc_taps, 115 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 116 /* DMAC can handle 32bit blk count but only 1 segment */ 117 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 118 .max_segs = 1, 119 .sdhi_flags = SDHI_FLAG_NEED_CLKH_FALLBACK, 120 }; 121 122 static const struct renesas_sdhi_of_data of_data_rcar_gen3_no_sdh_fallback = { 123 .tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_CLK_ACTUAL | 124 TMIO_MMC_HAVE_CBSY | TMIO_MMC_MIN_RCAR2, 125 .capabilities = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ | 126 MMC_CAP_CMD23 | MMC_CAP_WAIT_WHILE_BUSY, 127 .capabilities2 = MMC_CAP2_NO_WRITE_PROTECT | MMC_CAP2_MERGE_CAPABLE, 128 .bus_shift = 2, 129 .scc_offset = 0x1000, 130 .taps = rcar_gen3_scc_taps, 131 .taps_num = ARRAY_SIZE(rcar_gen3_scc_taps), 132 /* DMAC can handle 32bit blk count but only 1 segment */ 133 .max_blk_count = UINT_MAX / TMIO_MAX_BLK_SIZE, 134 .max_segs = 1, 135 }; 136 137 static const u8 r8a7796_es13_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 138 { 3, 3, 3, 3, 3, 3, 3, 4, 4, 5, 6, 7, 8, 9, 10, 15, 139 16, 16, 16, 16, 16, 16, 17, 18, 18, 19, 20, 21, 22, 23, 24, 25 }, 140 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 6, 7, 8, 11, 141 12, 17, 18, 18, 18, 18, 18, 18, 18, 19, 20, 21, 22, 23, 25, 25 } 142 }; 143 144 static const u8 r8a77965_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 145 { 1, 2, 6, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 15, 15, 16, 146 17, 18, 19, 20, 21, 22, 23, 24, 25, 25, 26, 27, 28, 29, 30, 31 }, 147 { 2, 3, 4, 4, 5, 6, 7, 9, 10, 11, 12, 13, 14, 15, 16, 17, 148 17, 17, 20, 21, 22, 23, 24, 25, 27, 28, 29, 30, 31, 31, 31, 31 } 149 }; 150 151 static const u8 r8a77990_calib_table[2][SDHI_CALIB_TABLE_MAX] = { 152 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 153 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, 154 { 0, 0, 0, 1, 2, 3, 3, 4, 4, 4, 5, 5, 6, 8, 9, 10, 155 11, 12, 13, 15, 16, 17, 17, 18, 18, 19, 20, 22, 24, 25, 26, 26 } 156 }; 157 158 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400 = { 159 .hs400_disabled = true, 160 .hs400_4taps = true, 161 }; 162 163 static const struct renesas_sdhi_quirks sdhi_quirks_4tap_nohs400_one_rx = { 164 .hs400_disabled = true, 165 .hs400_4taps = true, 166 .dma_one_rx_only = true, 167 .old_info1_layout = true, 168 }; 169 170 static const struct renesas_sdhi_quirks sdhi_quirks_4tap = { 171 .hs400_4taps = true, 172 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 173 .manual_tap_correction = true, 174 }; 175 176 static const struct renesas_sdhi_quirks sdhi_quirks_nohs400 = { 177 .hs400_disabled = true, 178 }; 179 180 static const struct renesas_sdhi_quirks sdhi_quirks_fixed_addr = { 181 .fixed_addr_mode = true, 182 }; 183 184 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps1357 = { 185 .hs400_bad_taps = BIT(1) | BIT(3) | BIT(5) | BIT(7), 186 .manual_tap_correction = true, 187 }; 188 189 static const struct renesas_sdhi_quirks sdhi_quirks_bad_taps2367 = { 190 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 191 .manual_tap_correction = true, 192 }; 193 194 static const struct renesas_sdhi_quirks sdhi_quirks_r8a7796_es13 = { 195 .hs400_4taps = true, 196 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 197 .hs400_calib_table = r8a7796_es13_calib_table, 198 .manual_tap_correction = true, 199 }; 200 201 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77965 = { 202 .hs400_bad_taps = BIT(2) | BIT(3) | BIT(6) | BIT(7), 203 .hs400_calib_table = r8a77965_calib_table, 204 .manual_tap_correction = true, 205 }; 206 207 static const struct renesas_sdhi_quirks sdhi_quirks_r8a77990 = { 208 .hs400_calib_table = r8a77990_calib_table, 209 .manual_tap_correction = true, 210 }; 211 212 static const struct renesas_sdhi_quirks sdhi_quirks_r9a09g011 = { 213 .fixed_addr_mode = true, 214 .hs400_disabled = true, 215 }; 216 217 /* 218 * Note for r8a7796 / r8a774a1: we can't distinguish ES1.1 and 1.2 as of now. 219 * So, we want to treat them equally and only have a match for ES1.2 to enforce 220 * this if there ever will be a way to distinguish ES1.2. 221 */ 222 static const struct soc_device_attribute sdhi_quirks_match[] = { 223 { .soc_id = "r8a774a1", .revision = "ES1.[012]", .data = &sdhi_quirks_4tap_nohs400 }, 224 { .soc_id = "r8a7795", .revision = "ES2.0", .data = &sdhi_quirks_4tap }, 225 { .soc_id = "r8a7796", .revision = "ES1.0", .data = &sdhi_quirks_4tap_nohs400_one_rx }, 226 { .soc_id = "r8a7796", .revision = "ES1.[12]", .data = &sdhi_quirks_4tap_nohs400 }, 227 { .soc_id = "r8a7796", .revision = "ES1.*", .data = &sdhi_quirks_r8a7796_es13 }, 228 { .soc_id = "r8a77980", .revision = "ES1.*", .data = &sdhi_quirks_nohs400 }, 229 { /* Sentinel. */ } 230 }; 231 232 static const struct renesas_sdhi_of_data_with_quirks of_r8a7795_compatible = { 233 .of_data = &of_data_rcar_gen3, 234 .quirks = &sdhi_quirks_bad_taps2367, 235 }; 236 237 static const struct renesas_sdhi_of_data_with_quirks of_r8a77961_compatible = { 238 .of_data = &of_data_rcar_gen3, 239 .quirks = &sdhi_quirks_bad_taps1357, 240 }; 241 242 static const struct renesas_sdhi_of_data_with_quirks of_r8a77965_compatible = { 243 .of_data = &of_data_rcar_gen3, 244 .quirks = &sdhi_quirks_r8a77965, 245 }; 246 247 static const struct renesas_sdhi_of_data_with_quirks of_r8a77970_compatible = { 248 .of_data = &of_data_rcar_gen3_no_sdh_fallback, 249 .quirks = &sdhi_quirks_nohs400, 250 }; 251 252 static const struct renesas_sdhi_of_data_with_quirks of_r8a77990_compatible = { 253 .of_data = &of_data_rcar_gen3, 254 .quirks = &sdhi_quirks_r8a77990, 255 }; 256 257 static const struct renesas_sdhi_of_data_with_quirks of_r9a09g011_compatible = { 258 .of_data = &of_data_rcar_gen3, 259 .quirks = &sdhi_quirks_r9a09g011, 260 }; 261 262 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_compatible = { 263 .of_data = &of_data_rcar_gen3, 264 }; 265 266 static const struct renesas_sdhi_of_data_with_quirks of_rcar_gen3_nohs400_compatible = { 267 .of_data = &of_data_rcar_gen3, 268 .quirks = &sdhi_quirks_nohs400, 269 }; 270 271 static const struct renesas_sdhi_of_data_with_quirks of_rza2_compatible = { 272 .of_data = &of_data_rza2, 273 .quirks = &sdhi_quirks_fixed_addr, 274 }; 275 276 static const struct of_device_id renesas_sdhi_internal_dmac_of_match[] = { 277 { .compatible = "renesas,sdhi-r7s9210", .data = &of_rza2_compatible, }, 278 { .compatible = "renesas,sdhi-mmc-r8a77470", .data = &of_rcar_gen3_compatible, }, 279 { .compatible = "renesas,sdhi-r8a7795", .data = &of_r8a7795_compatible, }, 280 { .compatible = "renesas,sdhi-r8a77961", .data = &of_r8a77961_compatible, }, 281 { .compatible = "renesas,sdhi-r8a77965", .data = &of_r8a77965_compatible, }, 282 { .compatible = "renesas,sdhi-r8a77970", .data = &of_r8a77970_compatible, }, 283 { .compatible = "renesas,sdhi-r8a77990", .data = &of_r8a77990_compatible, }, 284 { .compatible = "renesas,sdhi-r8a77995", .data = &of_rcar_gen3_nohs400_compatible, }, 285 { .compatible = "renesas,sdhi-r9a09g011", .data = &of_r9a09g011_compatible, }, 286 { .compatible = "renesas,rcar-gen3-sdhi", .data = &of_rcar_gen3_compatible, }, 287 { .compatible = "renesas,rcar-gen4-sdhi", .data = &of_rcar_gen3_compatible, }, 288 {}, 289 }; 290 MODULE_DEVICE_TABLE(of, renesas_sdhi_internal_dmac_of_match); 291 292 static void 293 renesas_sdhi_internal_dmac_enable_dma(struct tmio_mmc_host *host, bool enable) 294 { 295 struct renesas_sdhi *priv = host_to_priv(host); 296 u32 dma_irqs = INFO1_DTRANEND0 | 297 (sdhi_has_quirk(priv, old_info1_layout) ? 298 INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 299 300 if (!host->chan_tx || !host->chan_rx) 301 return; 302 303 writel(enable ? ~dma_irqs : INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 304 305 if (priv->dma_priv.enable) 306 priv->dma_priv.enable(host, enable); 307 } 308 309 static void 310 renesas_sdhi_internal_dmac_abort_dma(struct tmio_mmc_host *host) 311 { 312 u64 val = RST_DTRANRST1 | RST_DTRANRST0; 313 314 renesas_sdhi_internal_dmac_enable_dma(host, false); 315 316 writel(RST_RESERVED_BITS & ~val, host->ctl + DM_CM_RST); 317 writel(RST_RESERVED_BITS | val, host->ctl + DM_CM_RST); 318 319 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 320 321 renesas_sdhi_internal_dmac_enable_dma(host, true); 322 } 323 324 static bool renesas_sdhi_internal_dmac_dma_irq(struct tmio_mmc_host *host) 325 { 326 struct renesas_sdhi *priv = host_to_priv(host); 327 struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 328 329 u32 dma_irqs = INFO1_DTRANEND0 | 330 (sdhi_has_quirk(priv, old_info1_layout) ? 331 INFO1_DTRANEND1_OLD : INFO1_DTRANEND1); 332 u32 status = readl(host->ctl + DM_CM_INFO1); 333 334 if (status & dma_irqs) { 335 writel(status ^ dma_irqs, host->ctl + DM_CM_INFO1); 336 set_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags); 337 if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags)) 338 tasklet_schedule(&dma_priv->dma_complete); 339 } 340 341 return status & dma_irqs; 342 } 343 344 static void 345 renesas_sdhi_internal_dmac_dataend_dma(struct tmio_mmc_host *host) 346 { 347 struct renesas_sdhi *priv = host_to_priv(host); 348 struct renesas_sdhi_dma *dma_priv = &priv->dma_priv; 349 350 set_bit(SDHI_DMA_END_FLAG_ACCESS, &dma_priv->end_flags); 351 if (test_bit(SDHI_DMA_END_FLAG_DMA, &dma_priv->end_flags) || 352 host->data->error) 353 tasklet_schedule(&dma_priv->dma_complete); 354 } 355 356 /* 357 * renesas_sdhi_internal_dmac_map() will be called with two different 358 * sg pointers in two mmc_data by .pre_req(), but tmio host can have a single 359 * sg_ptr only. So, renesas_sdhi_internal_dmac_{un}map() should use a sg 360 * pointer in a mmc_data instead of host->sg_ptr. 361 */ 362 static void 363 renesas_sdhi_internal_dmac_unmap(struct tmio_mmc_host *host, 364 struct mmc_data *data, 365 enum renesas_sdhi_dma_cookie cookie) 366 { 367 bool unmap = cookie == COOKIE_UNMAPPED ? (data->host_cookie != cookie) : 368 (data->host_cookie == cookie); 369 370 if (unmap) { 371 dma_unmap_sg(&host->pdev->dev, data->sg, data->sg_len, 372 mmc_get_dma_dir(data)); 373 data->host_cookie = COOKIE_UNMAPPED; 374 } 375 } 376 377 static bool 378 renesas_sdhi_internal_dmac_map(struct tmio_mmc_host *host, 379 struct mmc_data *data, 380 enum renesas_sdhi_dma_cookie cookie) 381 { 382 if (data->host_cookie == COOKIE_PRE_MAPPED) 383 return true; 384 385 if (!dma_map_sg(&host->pdev->dev, data->sg, data->sg_len, 386 mmc_get_dma_dir(data))) 387 return false; 388 389 data->host_cookie = cookie; 390 391 /* This DMAC needs buffers to be 128-byte aligned */ 392 if (!IS_ALIGNED(sg_dma_address(data->sg), 128)) { 393 renesas_sdhi_internal_dmac_unmap(host, data, cookie); 394 return false; 395 } 396 397 return true; 398 } 399 400 static void 401 renesas_sdhi_internal_dmac_start_dma(struct tmio_mmc_host *host, 402 struct mmc_data *data) 403 { 404 struct renesas_sdhi *priv = host_to_priv(host); 405 struct scatterlist *sg = host->sg_ptr; 406 u32 dtran_mode = DTRAN_MODE_BUS_WIDTH; 407 408 if (!sdhi_has_quirk(priv, fixed_addr_mode)) 409 dtran_mode |= DTRAN_MODE_ADDR_MODE; 410 411 if (!renesas_sdhi_internal_dmac_map(host, data, COOKIE_MAPPED)) 412 goto force_pio; 413 414 if (data->flags & MMC_DATA_READ) { 415 dtran_mode |= DTRAN_MODE_CH_NUM_CH1; 416 if (sdhi_has_quirk(priv, dma_one_rx_only) && 417 test_and_set_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags)) 418 goto force_pio_with_unmap; 419 } else { 420 dtran_mode |= DTRAN_MODE_CH_NUM_CH0; 421 } 422 423 priv->dma_priv.end_flags = 0; 424 renesas_sdhi_internal_dmac_enable_dma(host, true); 425 426 /* set dma parameters */ 427 writel(dtran_mode, host->ctl + DM_CM_DTRAN_MODE); 428 writel(sg_dma_address(sg), host->ctl + DM_DTRAN_ADDR); 429 430 host->dma_on = true; 431 432 return; 433 434 force_pio_with_unmap: 435 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 436 437 force_pio: 438 renesas_sdhi_internal_dmac_enable_dma(host, false); 439 } 440 441 static void renesas_sdhi_internal_dmac_issue_tasklet_fn(unsigned long arg) 442 { 443 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 444 struct renesas_sdhi *priv = host_to_priv(host); 445 446 tmio_mmc_enable_mmc_irqs(host, TMIO_STAT_DATAEND); 447 448 if (!host->cmd->error) { 449 /* start the DMAC */ 450 writel(DTRAN_CTRL_DM_START, host->ctl + DM_CM_DTRAN_CTRL); 451 } else { 452 /* on CMD errors, simulate DMA end immediately */ 453 set_bit(SDHI_DMA_END_FLAG_DMA, &priv->dma_priv.end_flags); 454 if (test_bit(SDHI_DMA_END_FLAG_ACCESS, &priv->dma_priv.end_flags)) 455 tasklet_schedule(&priv->dma_priv.dma_complete); 456 } 457 } 458 459 static bool renesas_sdhi_internal_dmac_complete(struct tmio_mmc_host *host) 460 { 461 enum dma_data_direction dir; 462 463 if (!host->dma_on) 464 return false; 465 466 if (!host->data) 467 return false; 468 469 if (host->data->flags & MMC_DATA_READ) 470 dir = DMA_FROM_DEVICE; 471 else 472 dir = DMA_TO_DEVICE; 473 474 renesas_sdhi_internal_dmac_enable_dma(host, false); 475 renesas_sdhi_internal_dmac_unmap(host, host->data, COOKIE_MAPPED); 476 477 if (dir == DMA_FROM_DEVICE) 478 clear_bit(SDHI_INTERNAL_DMAC_RX_IN_USE, &global_flags); 479 480 host->dma_on = false; 481 482 return true; 483 } 484 485 static void renesas_sdhi_internal_dmac_complete_tasklet_fn(unsigned long arg) 486 { 487 struct tmio_mmc_host *host = (struct tmio_mmc_host *)arg; 488 489 spin_lock_irq(&host->lock); 490 if (!renesas_sdhi_internal_dmac_complete(host)) 491 goto out; 492 493 tmio_mmc_do_data_irq(host); 494 out: 495 spin_unlock_irq(&host->lock); 496 } 497 498 static void renesas_sdhi_internal_dmac_end_dma(struct tmio_mmc_host *host) 499 { 500 if (host->data) 501 renesas_sdhi_internal_dmac_complete(host); 502 } 503 504 static void renesas_sdhi_internal_dmac_post_req(struct mmc_host *mmc, 505 struct mmc_request *mrq, 506 int err) 507 { 508 struct tmio_mmc_host *host = mmc_priv(mmc); 509 struct mmc_data *data = mrq->data; 510 511 if (!data) 512 return; 513 514 renesas_sdhi_internal_dmac_unmap(host, data, COOKIE_UNMAPPED); 515 } 516 517 static void renesas_sdhi_internal_dmac_pre_req(struct mmc_host *mmc, 518 struct mmc_request *mrq) 519 { 520 struct tmio_mmc_host *host = mmc_priv(mmc); 521 struct mmc_data *data = mrq->data; 522 523 if (!data) 524 return; 525 526 data->host_cookie = COOKIE_UNMAPPED; 527 renesas_sdhi_internal_dmac_map(host, data, COOKIE_PRE_MAPPED); 528 } 529 530 static void 531 renesas_sdhi_internal_dmac_request_dma(struct tmio_mmc_host *host, 532 struct tmio_mmc_data *pdata) 533 { 534 struct renesas_sdhi *priv = host_to_priv(host); 535 536 /* Disable DMAC interrupts initially */ 537 writel(INFO1_MASK_CLEAR, host->ctl + DM_CM_INFO1_MASK); 538 writel(INFO2_MASK_CLEAR, host->ctl + DM_CM_INFO2_MASK); 539 writel(0, host->ctl + DM_CM_INFO1); 540 writel(0, host->ctl + DM_CM_INFO2); 541 542 /* Each value is set to non-zero to assume "enabling" each DMA */ 543 host->chan_rx = host->chan_tx = (void *)0xdeadbeaf; 544 545 tasklet_init(&priv->dma_priv.dma_complete, 546 renesas_sdhi_internal_dmac_complete_tasklet_fn, 547 (unsigned long)host); 548 tasklet_init(&host->dma_issue, 549 renesas_sdhi_internal_dmac_issue_tasklet_fn, 550 (unsigned long)host); 551 552 /* Add pre_req and post_req */ 553 host->ops.pre_req = renesas_sdhi_internal_dmac_pre_req; 554 host->ops.post_req = renesas_sdhi_internal_dmac_post_req; 555 } 556 557 static void 558 renesas_sdhi_internal_dmac_release_dma(struct tmio_mmc_host *host) 559 { 560 /* Each value is set to zero to assume "disabling" each DMA */ 561 host->chan_rx = host->chan_tx = NULL; 562 } 563 564 static const struct tmio_mmc_dma_ops renesas_sdhi_internal_dmac_dma_ops = { 565 .start = renesas_sdhi_internal_dmac_start_dma, 566 .enable = renesas_sdhi_internal_dmac_enable_dma, 567 .request = renesas_sdhi_internal_dmac_request_dma, 568 .release = renesas_sdhi_internal_dmac_release_dma, 569 .abort = renesas_sdhi_internal_dmac_abort_dma, 570 .dataend = renesas_sdhi_internal_dmac_dataend_dma, 571 .end = renesas_sdhi_internal_dmac_end_dma, 572 .dma_irq = renesas_sdhi_internal_dmac_dma_irq, 573 }; 574 575 static int renesas_sdhi_internal_dmac_probe(struct platform_device *pdev) 576 { 577 const struct soc_device_attribute *attr; 578 const struct renesas_sdhi_of_data_with_quirks *of_data_quirks; 579 const struct renesas_sdhi_quirks *quirks; 580 struct device *dev = &pdev->dev; 581 582 of_data_quirks = of_device_get_match_data(&pdev->dev); 583 quirks = of_data_quirks->quirks; 584 585 attr = soc_device_match(sdhi_quirks_match); 586 if (attr) 587 quirks = attr->data; 588 589 /* value is max of SD_SECCNT. Confirmed by HW engineers */ 590 dma_set_max_seg_size(dev, 0xffffffff); 591 592 return renesas_sdhi_probe(pdev, &renesas_sdhi_internal_dmac_dma_ops, 593 of_data_quirks->of_data, quirks); 594 } 595 596 static const struct dev_pm_ops renesas_sdhi_internal_dmac_dev_pm_ops = { 597 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 598 pm_runtime_force_resume) 599 SET_RUNTIME_PM_OPS(tmio_mmc_host_runtime_suspend, 600 tmio_mmc_host_runtime_resume, 601 NULL) 602 }; 603 604 static struct platform_driver renesas_internal_dmac_sdhi_driver = { 605 .driver = { 606 .name = "renesas_sdhi_internal_dmac", 607 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 608 .pm = &renesas_sdhi_internal_dmac_dev_pm_ops, 609 .of_match_table = renesas_sdhi_internal_dmac_of_match, 610 }, 611 .probe = renesas_sdhi_internal_dmac_probe, 612 .remove = renesas_sdhi_remove, 613 }; 614 615 module_platform_driver(renesas_internal_dmac_sdhi_driver); 616 617 MODULE_DESCRIPTION("Renesas SDHI driver for internal DMAC"); 618 MODULE_AUTHOR("Yoshihiro Shimoda"); 619 MODULE_LICENSE("GPL v2"); 620