1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/iopoll.h> 24 #include <linux/kernel.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/mmc.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/module.h> 29 #include <linux/mux/consumer.h> 30 #include <linux/pinctrl/consumer.h> 31 #include <linux/pinctrl/pinctrl-state.h> 32 #include <linux/platform_data/tmio.h> 33 #include <linux/platform_device.h> 34 #include <linux/pm_domain.h> 35 #include <linux/pm_runtime.h> 36 #include <linux/regulator/consumer.h> 37 #include <linux/regulator/driver.h> 38 #include <linux/regulator/of_regulator.h> 39 #include <linux/reset.h> 40 #include <linux/sh_dma.h> 41 #include <linux/slab.h> 42 43 #include "renesas_sdhi.h" 44 #include "tmio_mmc.h" 45 46 #define CTL_HOST_MODE 0xe4 47 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 48 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 49 #define HOST_MODE_GEN3_WMODE BIT(0) 50 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 51 52 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 53 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 54 #define HOST_MODE_GEN3_64BIT 0 55 56 #define SDHI_VER_GEN2_SDR50 0x490c 57 #define SDHI_VER_RZ_A1 0x820b 58 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 59 #define SDHI_VER_GEN2_SDR104 0xcb0d 60 #define SDHI_VER_GEN3_SD 0xcc10 61 #define SDHI_VER_GEN3_SDMMC 0xcd10 62 63 #define SDHI_GEN3_MMC0_ADDR 0xee140000 64 65 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 66 { 67 u32 val; 68 69 /* 70 * see also 71 * renesas_sdhi_of_data :: dma_buswidth 72 */ 73 switch (sd_ctrl_read16(host, CTL_VERSION)) { 74 case SDHI_VER_GEN2_SDR50: 75 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 76 break; 77 case SDHI_VER_GEN2_SDR104: 78 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 79 break; 80 case SDHI_VER_GEN3_SD: 81 case SDHI_VER_GEN3_SDMMC: 82 if (width == 64) 83 val = HOST_MODE_GEN3_64BIT; 84 else if (width == 32) 85 val = HOST_MODE_GEN3_32BIT; 86 else 87 val = HOST_MODE_GEN3_16BIT; 88 break; 89 default: 90 /* nothing to do */ 91 return; 92 } 93 94 sd_ctrl_write16(host, CTL_HOST_MODE, val); 95 } 96 97 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 98 { 99 struct mmc_host *mmc = host->mmc; 100 struct renesas_sdhi *priv = host_to_priv(host); 101 int ret; 102 103 ret = clk_prepare_enable(priv->clk_cd); 104 if (ret < 0) 105 return ret; 106 107 /* 108 * The clock driver may not know what maximum frequency 109 * actually works, so it should be set with the max-frequency 110 * property which will already have been read to f_max. If it 111 * was missing, assume the current frequency is the maximum. 112 */ 113 if (!mmc->f_max) 114 mmc->f_max = clk_get_rate(priv->clk); 115 116 /* 117 * Minimum frequency is the minimum input clock frequency 118 * divided by our maximum divider. 119 */ 120 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 121 122 /* enable 16bit data access on SDBUF as default */ 123 renesas_sdhi_sdbuf_width(host, 16); 124 125 return 0; 126 } 127 128 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 129 unsigned int wanted_clock) 130 { 131 struct renesas_sdhi *priv = host_to_priv(host); 132 struct clk *ref_clk = priv->clk; 133 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 134 unsigned int new_clock, clkh_shift = 0; 135 unsigned int new_upper_limit; 136 int i; 137 138 /* 139 * We simply return the current rate if a) we are not on a R-Car Gen2+ 140 * SoC (may work for others, but untested) or b) if the SCC needs its 141 * clock during tuning, so we don't change the external clock setup. 142 */ 143 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 144 return clk_get_rate(priv->clk); 145 146 if (priv->clkh) { 147 /* HS400 with 4TAP needs different clock settings */ 148 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 149 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 150 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 151 ref_clk = priv->clkh; 152 } 153 154 new_clock = wanted_clock << clkh_shift; 155 156 /* 157 * We want the bus clock to be as close as possible to, but no 158 * greater than, new_clock. As we can divide by 1 << i for 159 * any i in [0, 9] we want the input clock to be as close as 160 * possible, but no greater than, new_clock << i. 161 * 162 * Add an upper limit of 1/1024 rate higher to the clock rate to fix 163 * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has 164 * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request 165 * for 533.333333 MHz will selects a slower 400 MHz due to rounding 166 * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)). 167 */ 168 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 169 freq = clk_round_rate(ref_clk, new_clock << i); 170 new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10); 171 if (freq > new_upper_limit) { 172 /* Too fast; look for a slightly slower option */ 173 freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 174 if (freq > new_upper_limit) 175 continue; 176 } 177 178 diff = new_clock - (freq >> i); 179 if (diff <= diff_min) { 180 best_freq = freq; 181 diff_min = diff; 182 } 183 } 184 185 clk_set_rate(ref_clk, best_freq); 186 187 if (priv->clkh) 188 clk_set_rate(priv->clk, best_freq >> clkh_shift); 189 190 return clk_get_rate(priv->clk); 191 } 192 193 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 194 unsigned int new_clock) 195 { 196 unsigned int clk_margin; 197 u32 clk = 0, clock; 198 199 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 200 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 201 202 if (new_clock == 0) { 203 host->mmc->actual_clock = 0; 204 goto out; 205 } 206 207 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 208 clock = host->mmc->actual_clock / 512; 209 210 /* 211 * Add a margin of 1/1024 rate higher to the clock rate in order 212 * to avoid clk variable setting a value of 0 due to the margin 213 * provided for actual_clock in renesas_sdhi_clk_update(). 214 */ 215 clk_margin = new_clock >> 10; 216 for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1) 217 clock <<= 1; 218 219 /* 1/1 clock is option */ 220 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 221 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 222 clk |= 0xff; 223 else 224 clk &= ~0xff; 225 } 226 227 clock = clk & CLK_CTL_DIV_MASK; 228 if (clock != CLK_CTL_DIV_MASK) 229 host->mmc->actual_clock /= (1 << (ffs(clock) + 1)); 230 231 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); 232 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 233 usleep_range(10000, 11000); 234 235 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 236 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 237 238 out: 239 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 240 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 241 usleep_range(10000, 11000); 242 } 243 244 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 245 { 246 struct renesas_sdhi *priv = host_to_priv(host); 247 248 clk_disable_unprepare(priv->clk_cd); 249 } 250 251 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 252 { 253 struct tmio_mmc_host *host = mmc_priv(mmc); 254 255 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 256 TMIO_STAT_DAT0); 257 } 258 259 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 260 struct mmc_ios *ios) 261 { 262 struct tmio_mmc_host *host = mmc_priv(mmc); 263 struct renesas_sdhi *priv = host_to_priv(host); 264 struct pinctrl_state *pin_state; 265 int ret; 266 267 switch (ios->signal_voltage) { 268 case MMC_SIGNAL_VOLTAGE_330: 269 pin_state = priv->pins_default; 270 break; 271 case MMC_SIGNAL_VOLTAGE_180: 272 pin_state = priv->pins_uhs; 273 break; 274 default: 275 return -EINVAL; 276 } 277 278 /* 279 * If anything is missing, assume signal voltage is fixed at 280 * 3.3V and succeed/fail accordingly. 281 */ 282 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 283 return ios->signal_voltage == 284 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 285 286 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 287 if (ret < 0) 288 return ret; 289 290 return pinctrl_select_state(priv->pinctrl, pin_state); 291 } 292 293 /* SCC registers */ 294 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 295 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 296 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 297 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 298 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 299 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 300 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 301 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 302 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 303 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 304 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 305 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 306 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 307 308 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 309 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 310 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 311 312 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 313 314 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 315 316 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 317 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 318 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 319 320 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 321 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 322 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 323 324 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 325 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 326 327 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 328 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 329 330 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 331 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 332 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 333 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 334 335 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 336 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 337 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 338 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 339 340 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 341 struct renesas_sdhi *priv, int addr) 342 { 343 return readl(priv->scc_ctl + (addr << host->bus_shift)); 344 } 345 346 static inline void sd_scc_write32(struct tmio_mmc_host *host, 347 struct renesas_sdhi *priv, 348 int addr, u32 val) 349 { 350 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 351 } 352 353 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 354 { 355 struct renesas_sdhi *priv; 356 357 priv = host_to_priv(host); 358 359 /* Initialize SCC */ 360 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 361 362 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 363 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 364 365 /* set sampling clock selection range */ 366 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 367 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 368 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 369 370 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 371 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 372 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 373 374 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 375 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 376 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 377 378 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 379 380 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 381 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 382 383 /* Read TAPNUM */ 384 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 385 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 386 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 387 } 388 389 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 390 { 391 struct tmio_mmc_host *host = mmc_priv(mmc); 392 struct renesas_sdhi *priv = host_to_priv(host); 393 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 394 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 395 396 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 397 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 398 399 /* Set HS400 mode */ 400 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 401 sd_ctrl_read16(host, CTL_SDIF_MODE)); 402 403 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 404 priv->scc_tappos_hs400); 405 406 if (sdhi_has_quirk(priv, manual_tap_correction)) 407 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 408 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 409 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 410 411 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 412 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 413 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 414 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 415 416 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 417 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 418 sd_scc_read32(host, priv, 419 SH_MOBILE_SDHI_SCC_DTCNTL)); 420 421 /* Avoid bad TAP */ 422 if (bad_taps & BIT(priv->tap_set)) { 423 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 424 425 if (bad_taps & BIT(new_tap)) 426 new_tap = (priv->tap_set - 1) % priv->tap_num; 427 428 if (bad_taps & BIT(new_tap)) { 429 new_tap = priv->tap_set; 430 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 431 } 432 433 priv->tap_set = new_tap; 434 } 435 436 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 437 priv->tap_set / (use_4tap ? 2 : 1)); 438 439 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 440 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 441 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 442 443 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 444 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 445 446 if (priv->adjust_hs400_calib_table) 447 priv->needs_adjust_hs400 = true; 448 } 449 450 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 451 { 452 struct tmio_mmc_host *host = mmc_priv(mmc); 453 struct renesas_sdhi *priv = host_to_priv(host); 454 455 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 456 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 457 458 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 459 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 460 sd_scc_read32(host, priv, 461 SH_MOBILE_SDHI_SCC_CKSEL)); 462 463 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 464 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 465 sd_scc_read32(host, priv, 466 SH_MOBILE_SDHI_SCC_DTCNTL)); 467 468 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 469 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 470 } 471 472 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 473 struct renesas_sdhi *priv, u32 addr) 474 { 475 /* read mode */ 476 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 477 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 478 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 479 480 /* access start and stop */ 481 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 482 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 483 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 484 485 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 486 } 487 488 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 489 struct renesas_sdhi *priv, u32 addr, u32 val) 490 { 491 /* write mode */ 492 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 493 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 494 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 495 496 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 497 498 /* access start and stop */ 499 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 500 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 501 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 502 } 503 504 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 505 { 506 struct renesas_sdhi *priv = host_to_priv(host); 507 u32 calib_code; 508 509 /* disable write protect */ 510 sd_scc_tmpport_write32(host, priv, 0x00, 511 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 512 /* read calibration code and adjust */ 513 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 514 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 515 516 sd_scc_tmpport_write32(host, priv, 0x22, 517 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 518 priv->adjust_hs400_calib_table[calib_code]); 519 520 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 521 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 522 523 /* adjustment done, clear flag */ 524 priv->needs_adjust_hs400 = false; 525 } 526 527 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 528 { 529 struct renesas_sdhi *priv = host_to_priv(host); 530 531 /* disable write protect */ 532 sd_scc_tmpport_write32(host, priv, 0x00, 533 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 534 /* disable manual calibration */ 535 sd_scc_tmpport_write32(host, priv, 0x22, 0); 536 /* clear offset value of TMPPORT3 */ 537 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 538 } 539 540 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 541 struct renesas_sdhi *priv) 542 { 543 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 544 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 545 546 /* Reset HS400 mode */ 547 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 548 sd_ctrl_read16(host, CTL_SDIF_MODE)); 549 550 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 551 552 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 553 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 554 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 555 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 556 557 if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps)) 558 renesas_sdhi_adjust_hs400_mode_disable(host); 559 560 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 561 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 562 } 563 564 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 565 { 566 struct tmio_mmc_host *host = mmc_priv(mmc); 567 568 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 569 return 0; 570 } 571 572 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 573 { 574 renesas_sdhi_disable_scc(host->mmc); 575 renesas_sdhi_reset_hs400_mode(host, priv); 576 priv->needs_adjust_hs400 = false; 577 578 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 579 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 580 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 581 } 582 583 /* only populated for TMIO_MMC_MIN_RCAR2 */ 584 static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) 585 { 586 struct renesas_sdhi *priv = host_to_priv(host); 587 int ret; 588 u16 val; 589 590 if (!preserve) { 591 if (priv->rstc) { 592 u32 sd_status; 593 /* 594 * HW reset might have toggled the regulator state in 595 * HW which regulator core might be unaware of so save 596 * and restore the regulator state during HW reset. 597 */ 598 if (priv->rdev) 599 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 600 601 reset_control_reset(priv->rstc); 602 /* Unknown why but without polling reset status, it will hang */ 603 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 604 false, priv->rstc); 605 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 606 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 607 if (priv->rdev) 608 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 609 610 priv->needs_adjust_hs400 = false; 611 renesas_sdhi_set_clock(host, host->clk_cache); 612 613 /* Ensure default value for this driver. */ 614 renesas_sdhi_sdbuf_width(host, 16); 615 } else if (priv->scc_ctl) { 616 renesas_sdhi_scc_reset(host, priv); 617 } 618 } 619 620 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 621 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 622 val |= CARD_OPT_EXTOP; 623 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 624 } 625 } 626 627 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 628 { 629 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 630 631 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 632 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 633 634 } 635 636 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 637 638 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 639 { 640 struct renesas_sdhi *priv = host_to_priv(host); 641 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 642 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 643 unsigned long *bitmap; 644 645 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 646 647 /* 648 * When tuning CMD19 is issued twice for each tap, merge the 649 * result requiring the tap to be good in both runs before 650 * considering it for tuning selection. 651 */ 652 for (i = 0; i < taps_size; i++) { 653 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 654 655 if (!test_bit(i, priv->taps)) 656 clear_bit(i + offset, priv->taps); 657 658 if (!test_bit(i, priv->smpcmp)) 659 clear_bit(i + offset, priv->smpcmp); 660 } 661 662 /* 663 * If all TAP are OK, the sampling clock position is selected by 664 * identifying the change point of data. 665 */ 666 if (bitmap_full(priv->taps, taps_size)) { 667 bitmap = priv->smpcmp; 668 min_tap_row = 1; 669 } else { 670 bitmap = priv->taps; 671 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 672 } 673 674 /* 675 * Find the longest consecutive run of successful probes. If that 676 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 677 * center index as the tap, otherwise bail out. 678 */ 679 for_each_set_bitrange(rs, re, bitmap, taps_size) { 680 if (re - rs > tap_cnt) { 681 tap_end = re; 682 tap_start = rs; 683 tap_cnt = tap_end - tap_start; 684 } 685 } 686 687 if (tap_cnt >= min_tap_row) 688 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 689 else 690 return -EIO; 691 692 /* Set SCC */ 693 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 694 695 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 696 (priv->card_is_sdio ? 0 : SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) | 697 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 698 699 return 0; 700 } 701 702 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 703 { 704 struct tmio_mmc_host *host = mmc_priv(mmc); 705 struct renesas_sdhi *priv = host_to_priv(host); 706 int i, ret; 707 708 priv->tap_num = renesas_sdhi_init_tuning(host); 709 if (!priv->tap_num) 710 return 0; /* Tuning is not supported */ 711 712 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 713 dev_err(&host->pdev->dev, 714 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 715 return -EINVAL; 716 } 717 718 bitmap_zero(priv->taps, priv->tap_num * 2); 719 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 720 721 /* Issue CMD19 twice for each tap */ 722 for (i = 0; i < 2 * priv->tap_num; i++) { 723 int cmd_error = 0; 724 725 /* Set sampling clock position */ 726 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 727 728 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 729 set_bit(i, priv->taps); 730 731 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 732 set_bit(i, priv->smpcmp); 733 734 if (cmd_error) 735 mmc_send_abort_tuning(mmc, opcode); 736 } 737 738 ret = renesas_sdhi_select_tuning(host); 739 if (ret < 0) 740 renesas_sdhi_scc_reset(host, priv); 741 return ret; 742 } 743 744 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 745 { 746 struct renesas_sdhi *priv = host_to_priv(host); 747 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 748 u32 val; 749 750 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 751 if (!val) 752 return false; 753 754 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 755 756 /* Change TAP position according to correction status */ 757 if (sdhi_has_quirk(priv, manual_tap_correction) && 758 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 759 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 760 /* 761 * With HS400, the DAT signal is based on DS, not CLK. 762 * Therefore, use only CMD status. 763 */ 764 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 765 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 766 if (!smpcmp) { 767 return false; /* no error in CMD signal */ 768 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 769 new_tap++; 770 error_tap--; 771 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 772 new_tap--; 773 error_tap++; 774 } else { 775 return true; /* need retune */ 776 } 777 778 /* 779 * When new_tap is a bad tap, we cannot change. Then, we compare 780 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 781 * we can at least retune. 782 */ 783 if (bad_taps & BIT(new_tap % priv->tap_num)) 784 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 785 } else { 786 if (!priv->card_is_sdio && 787 !(val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)) { 788 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP); 789 790 /* DAT1 is unmatched because of an SDIO irq */ 791 if (smpcmp & (BIT(17) | BIT(1))) 792 return false; 793 } 794 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 795 return true; /* need retune */ 796 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 797 new_tap++; 798 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 799 new_tap--; 800 else 801 return false; 802 } 803 804 priv->tap_set = (new_tap % priv->tap_num); 805 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 806 priv->tap_set / (use_4tap ? 2 : 1)); 807 808 return false; 809 } 810 811 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 812 { 813 struct renesas_sdhi *priv = host_to_priv(host); 814 815 /* Check SCC error */ 816 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 817 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 818 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 819 return true; 820 } 821 822 return false; 823 } 824 825 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 826 struct mmc_request *mrq) 827 { 828 struct renesas_sdhi *priv = host_to_priv(host); 829 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 830 bool ret = false; 831 832 /* 833 * Skip checking SCC errors when running on 4 taps in HS400 mode as 834 * any retuning would still result in the same 4 taps being used. 835 */ 836 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 837 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 838 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 839 return false; 840 841 if (mmc_doing_tune(host->mmc)) 842 return false; 843 844 /* mrq can be NULL to check SCC error on SDIO irq without any request */ 845 if (mrq) { 846 if (((mrq->cmd->error == -ETIMEDOUT) || 847 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 848 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 849 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 850 ret |= true; 851 } 852 853 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 854 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 855 ret |= renesas_sdhi_auto_correction(host); 856 else 857 ret |= renesas_sdhi_manual_correction(host, use_4tap); 858 859 return ret; 860 } 861 862 static void renesas_sdhi_init_card(struct mmc_host *mmc, struct mmc_card *card) 863 { 864 struct tmio_mmc_host *host = mmc_priv(mmc); 865 struct renesas_sdhi *priv = host_to_priv(host); 866 867 /* 868 * This controller cannot do auto-retune with SDIO irqs, so we 869 * then need to enforce manual correction. However, when tuning, 870 * mmc->card is not populated yet, so we don't know if the card 871 * is SDIO. init_card provides this information earlier, so we 872 * keep a copy of it. 873 */ 874 priv->card_is_sdio = mmc_card_sdio(card); 875 } 876 877 static void renesas_sdhi_sdio_irq(struct tmio_mmc_host *host) 878 { 879 /* This controller requires retune when an SDIO irq occurs */ 880 if (renesas_sdhi_check_scc_error(host, NULL)) 881 mmc_retune_needed(host->mmc); 882 } 883 884 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 885 { 886 int timeout = 1000; 887 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 888 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 889 890 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 891 & bit) == wait_state) 892 udelay(1); 893 894 if (!timeout) { 895 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 896 return -EBUSY; 897 } 898 899 return 0; 900 } 901 902 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 903 { 904 u32 bit = TMIO_STAT_SCLKDIVEN; 905 906 switch (addr) { 907 case CTL_SD_CMD: 908 case CTL_STOP_INTERNAL_ACTION: 909 case CTL_XFER_BLK_COUNT: 910 case CTL_SD_XFER_LEN: 911 case CTL_SD_MEM_CARD_OPT: 912 case CTL_TRANSACTION_CTL: 913 case CTL_DMA_ENABLE: 914 case CTL_HOST_MODE: 915 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 916 bit = TMIO_STAT_CMD_BUSY; 917 fallthrough; 918 case CTL_SD_CARD_CLK_CTL: 919 return renesas_sdhi_wait_idle(host, bit); 920 } 921 922 return 0; 923 } 924 925 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 926 unsigned int direction, int blk_size) 927 { 928 /* 929 * In Renesas controllers, when performing a 930 * multiple block read of one or two blocks, 931 * depending on the timing with which the 932 * response register is read, the response 933 * value may not be read properly. 934 * Use single block read for this HW bug 935 */ 936 if ((direction == MMC_DATA_READ) && 937 blk_size == 2) 938 return 1; 939 940 return blk_size; 941 } 942 943 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 944 { 945 struct renesas_sdhi *priv = host_to_priv(host); 946 947 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 948 renesas_sdhi_adjust_hs400_mode_enable(host); 949 } 950 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 951 { 952 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 953 int width = (host->bus_shift == 2) ? 64 : 32; 954 955 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 956 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 957 } 958 959 static const unsigned int renesas_sdhi_vqmmc_voltages[] = { 960 3300000, 1800000 961 }; 962 963 static int renesas_sdhi_regulator_disable(struct regulator_dev *rdev) 964 { 965 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 966 u32 sd_status; 967 968 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 969 sd_status &= ~SD_STATUS_PWEN; 970 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 971 972 return 0; 973 } 974 975 static int renesas_sdhi_regulator_enable(struct regulator_dev *rdev) 976 { 977 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 978 u32 sd_status; 979 980 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 981 sd_status |= SD_STATUS_PWEN; 982 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 983 984 return 0; 985 } 986 987 static int renesas_sdhi_regulator_is_enabled(struct regulator_dev *rdev) 988 { 989 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 990 u32 sd_status; 991 992 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 993 994 return (sd_status & SD_STATUS_PWEN) ? 1 : 0; 995 } 996 997 static int renesas_sdhi_regulator_get_voltage(struct regulator_dev *rdev) 998 { 999 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 1000 u32 sd_status; 1001 1002 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 1003 1004 return (sd_status & SD_STATUS_IOVS) ? 1800000 : 3300000; 1005 } 1006 1007 static int renesas_sdhi_regulator_set_voltage(struct regulator_dev *rdev, 1008 int min_uV, int max_uV, 1009 unsigned int *selector) 1010 { 1011 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 1012 u32 sd_status; 1013 1014 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 1015 if (min_uV >= 1700000 && max_uV <= 1950000) { 1016 sd_status |= SD_STATUS_IOVS; 1017 *selector = 1; 1018 } else { 1019 sd_status &= ~SD_STATUS_IOVS; 1020 *selector = 0; 1021 } 1022 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 1023 1024 return 0; 1025 } 1026 1027 static int renesas_sdhi_regulator_list_voltage(struct regulator_dev *rdev, 1028 unsigned int selector) 1029 { 1030 if (selector >= ARRAY_SIZE(renesas_sdhi_vqmmc_voltages)) 1031 return -EINVAL; 1032 1033 return renesas_sdhi_vqmmc_voltages[selector]; 1034 } 1035 1036 static const struct regulator_ops renesas_sdhi_regulator_voltage_ops = { 1037 .enable = renesas_sdhi_regulator_enable, 1038 .disable = renesas_sdhi_regulator_disable, 1039 .is_enabled = renesas_sdhi_regulator_is_enabled, 1040 .list_voltage = renesas_sdhi_regulator_list_voltage, 1041 .get_voltage = renesas_sdhi_regulator_get_voltage, 1042 .set_voltage = renesas_sdhi_regulator_set_voltage, 1043 }; 1044 1045 static const struct regulator_desc renesas_sdhi_vqmmc_regulator = { 1046 .name = "sdhi-vqmmc-regulator", 1047 .of_match = of_match_ptr("vqmmc-regulator"), 1048 .type = REGULATOR_VOLTAGE, 1049 .owner = THIS_MODULE, 1050 .ops = &renesas_sdhi_regulator_voltage_ops, 1051 .volt_table = renesas_sdhi_vqmmc_voltages, 1052 .n_voltages = ARRAY_SIZE(renesas_sdhi_vqmmc_voltages), 1053 }; 1054 1055 int renesas_sdhi_probe(struct platform_device *pdev, 1056 const struct tmio_mmc_dma_ops *dma_ops, 1057 const struct renesas_sdhi_of_data *of_data, 1058 const struct renesas_sdhi_quirks *quirks) 1059 { 1060 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 1061 struct tmio_mmc_data *mmc_data; 1062 struct regulator_config rcfg = { .dev = &pdev->dev, }; 1063 struct regulator_dev *rdev; 1064 struct renesas_sdhi_dma *dma_priv; 1065 struct device *dev = &pdev->dev; 1066 struct mux_state *mux_state; 1067 struct tmio_mmc_host *host; 1068 struct renesas_sdhi *priv; 1069 int num_irqs, irq, ret, i; 1070 struct resource *res; 1071 u16 ver; 1072 1073 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1074 if (!res) 1075 return -EINVAL; 1076 1077 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 1078 GFP_KERNEL); 1079 if (!priv) 1080 return -ENOMEM; 1081 1082 priv->quirks = quirks; 1083 mmc_data = &priv->mmc_data; 1084 dma_priv = &priv->dma_priv; 1085 1086 priv->clk = devm_clk_get(&pdev->dev, NULL); 1087 if (IS_ERR(priv->clk)) 1088 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 1089 1090 priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 1091 if (IS_ERR(priv->clkh)) 1092 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 1093 1094 /* 1095 * Some controllers provide a 2nd clock just to run the internal card 1096 * detection logic. Unfortunately, the existing driver architecture does 1097 * not support a separation of clocks for runtime PM usage. When 1098 * native hotplug is used, the tmio driver assumes that the core 1099 * must continue to run for card detect to stay active, so we cannot 1100 * disable it. 1101 * Additionally, it is prohibited to supply a clock to the core but not 1102 * to the card detect circuit. That leaves us with if separate clocks 1103 * are presented, we must treat them both as virtually 1 clock. 1104 */ 1105 priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 1106 if (IS_ERR(priv->clk_cd)) 1107 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 1108 1109 priv->rstc = devm_reset_control_get_optional_exclusive_deasserted(&pdev->dev, NULL); 1110 if (IS_ERR(priv->rstc)) 1111 return PTR_ERR(priv->rstc); 1112 1113 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1114 if (!IS_ERR(priv->pinctrl)) { 1115 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 1116 PINCTRL_STATE_DEFAULT); 1117 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 1118 "state_uhs"); 1119 } 1120 1121 mux_state = devm_mux_state_get_optional_selected(&pdev->dev, NULL); 1122 if (IS_ERR(mux_state)) 1123 return PTR_ERR(mux_state); 1124 1125 host = tmio_mmc_host_alloc(pdev, mmc_data); 1126 if (IS_ERR(host)) 1127 return PTR_ERR(host); 1128 1129 priv->host = host; 1130 1131 if (of_data) { 1132 mmc_data->flags |= of_data->tmio_flags; 1133 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 1134 mmc_data->capabilities |= of_data->capabilities; 1135 mmc_data->capabilities2 |= of_data->capabilities2; 1136 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 1137 mmc_data->max_blk_count = of_data->max_blk_count; 1138 mmc_data->max_segs = of_data->max_segs; 1139 dma_priv->dma_buswidth = of_data->dma_buswidth; 1140 host->bus_shift = of_data->bus_shift; 1141 /* Fallback for old DTs */ 1142 if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 1143 priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 1144 1145 } 1146 1147 host->write16_hook = renesas_sdhi_write16_hook; 1148 host->clk_enable = renesas_sdhi_clk_enable; 1149 host->clk_disable = renesas_sdhi_clk_disable; 1150 host->set_clock = renesas_sdhi_set_clock; 1151 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 1152 host->dma_ops = dma_ops; 1153 1154 if (sdhi_has_quirk(priv, hs400_disabled)) 1155 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1156 1157 /* For some SoC, we disable internal WP. GPIO may override this */ 1158 if (mmc_host_can_gpio_ro(host->mmc)) 1159 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1160 1161 /* SDR speeds are only available on Gen2+ */ 1162 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1163 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 1164 host->ops.card_busy = renesas_sdhi_card_busy; 1165 host->ops.start_signal_voltage_switch = 1166 renesas_sdhi_start_signal_voltage_switch; 1167 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 1168 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 1169 host->reset = renesas_sdhi_reset; 1170 } else { 1171 host->sdcard_irq_mask_all = TMIO_MASK_ALL; 1172 } 1173 1174 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1175 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1176 host->bus_shift = 1; 1177 1178 if (mmd) 1179 *mmc_data = *mmd; 1180 1181 dma_priv->filter = shdma_chan_filter; 1182 dma_priv->enable = renesas_sdhi_enable_dma; 1183 1184 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1185 1186 /* 1187 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1188 * bus width mode. 1189 */ 1190 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1191 1192 /* 1193 * All SDHI blocks support SDIO IRQ signalling. 1194 */ 1195 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1196 1197 /* All SDHI have CMD12 control bit */ 1198 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1199 1200 /* All SDHI have SDIO status bits which must be 1 */ 1201 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1202 1203 /* All SDHI support HW busy detection */ 1204 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1205 1206 dev_pm_domain_start(&pdev->dev); 1207 1208 ret = renesas_sdhi_clk_enable(host); 1209 if (ret) 1210 return ret; 1211 1212 rcfg.of_node = of_get_available_child_by_name(dev->of_node, "vqmmc-regulator"); 1213 if (rcfg.of_node) { 1214 rcfg.driver_data = priv->host; 1215 rdev = devm_regulator_register(dev, &renesas_sdhi_vqmmc_regulator, &rcfg); 1216 of_node_put(rcfg.of_node); 1217 if (IS_ERR(rdev)) { 1218 dev_err(dev, "regulator register failed err=%ld", PTR_ERR(rdev)); 1219 ret = PTR_ERR(rdev); 1220 goto edisclk; 1221 } 1222 priv->rdev = rdev; 1223 } 1224 1225 ver = sd_ctrl_read16(host, CTL_VERSION); 1226 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1227 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1228 mmc_data->max_blk_count = U16_MAX; 1229 1230 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1231 if (ver == SDHI_VER_GEN2_SDR50) 1232 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1233 1234 if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) { 1235 host->fixup_request = renesas_sdhi_fixup_request; 1236 priv->adjust_hs400_calib_table = *( 1237 res->start == SDHI_GEN3_MMC0_ADDR ? 1238 quirks->hs400_calib_table : 1239 quirks->hs400_calib_table + 1); 1240 } 1241 1242 /* these have an EXTOP bit */ 1243 if (ver >= SDHI_VER_GEN3_SD) 1244 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1245 1246 /* Check for SCC so we can reset it if needed */ 1247 if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104) 1248 priv->scc_ctl = host->ctl + of_data->scc_offset; 1249 1250 /* Enable tuning iff we have an SCC and a supported mode */ 1251 if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1252 host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) { 1253 const struct renesas_sdhi_scc *taps = of_data->taps; 1254 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 1255 bool hit = false; 1256 1257 for (i = 0; i < of_data->taps_num; i++) { 1258 if (taps[i].clk_rate == 0 || 1259 taps[i].clk_rate == host->mmc->f_max) { 1260 priv->scc_tappos = taps->tap; 1261 priv->scc_tappos_hs400 = use_4tap ? 1262 taps->tap_hs400_4tap : 1263 taps->tap; 1264 hit = true; 1265 break; 1266 } 1267 } 1268 1269 if (!hit) 1270 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1271 1272 host->check_retune = renesas_sdhi_check_scc_error; 1273 host->sdio_irq = renesas_sdhi_sdio_irq; 1274 host->ops.init_card = renesas_sdhi_init_card; 1275 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1276 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1277 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1278 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1279 } 1280 1281 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all); 1282 1283 /* There must be at least one IRQ source */ 1284 num_irqs = platform_irq_count(pdev); 1285 if (num_irqs <= 0) { 1286 ret = num_irqs ?: -ENOENT; 1287 goto edisclk; 1288 } 1289 1290 for (i = 0; i < num_irqs; i++) { 1291 irq = platform_get_irq(pdev, i); 1292 if (irq < 0) { 1293 ret = irq; 1294 goto edisclk; 1295 } 1296 1297 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1298 dev_name(&pdev->dev), host); 1299 if (ret) 1300 goto edisclk; 1301 } 1302 1303 ret = tmio_mmc_host_probe(host); 1304 if (ret < 0) 1305 goto edisclk; 1306 1307 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1308 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1309 1310 return ret; 1311 1312 edisclk: 1313 renesas_sdhi_clk_disable(host); 1314 return ret; 1315 } 1316 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1317 1318 void renesas_sdhi_remove(struct platform_device *pdev) 1319 { 1320 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1321 1322 tmio_mmc_host_remove(host); 1323 renesas_sdhi_clk_disable(host); 1324 } 1325 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1326 1327 int renesas_sdhi_suspend(struct device *dev) 1328 { 1329 struct tmio_mmc_host *host = dev_get_drvdata(dev); 1330 struct renesas_sdhi *priv = host_to_priv(host); 1331 int ret; 1332 1333 ret = pm_runtime_force_suspend(dev); 1334 if (ret) 1335 return ret; 1336 1337 ret = reset_control_assert(priv->rstc); 1338 if (ret) 1339 pm_runtime_force_resume(dev); 1340 1341 return ret; 1342 } 1343 EXPORT_SYMBOL_GPL(renesas_sdhi_suspend); 1344 1345 int renesas_sdhi_resume(struct device *dev) 1346 { 1347 struct tmio_mmc_host *host = dev_get_drvdata(dev); 1348 struct renesas_sdhi *priv = host_to_priv(host); 1349 int ret; 1350 1351 ret = reset_control_deassert(priv->rstc); 1352 if (ret) 1353 return ret; 1354 1355 ret = pm_runtime_force_resume(dev); 1356 if (ret) 1357 reset_control_assert(priv->rstc); 1358 1359 return ret; 1360 } 1361 EXPORT_SYMBOL_GPL(renesas_sdhi_resume); 1362 1363 MODULE_DESCRIPTION("Renesas SDHI core driver"); 1364 MODULE_LICENSE("GPL v2"); 1365