1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas SDHI 4 * 5 * Copyright (C) 2015-19 Renesas Electronics Corporation 6 * Copyright (C) 2016-19 Sang Engineering, Wolfram Sang 7 * Copyright (C) 2016-17 Horms Solutions, Simon Horman 8 * Copyright (C) 2009 Magnus Damm 9 * 10 * Based on "Compaq ASIC3 support": 11 * 12 * Copyright 2001 Compaq Computer Corporation. 13 * Copyright 2004-2005 Phil Blundell 14 * Copyright 2007-2008 OpenedHand Ltd. 15 * 16 * Authors: Phil Blundell <pb@handhelds.org>, 17 * Samuel Ortiz <sameo@openedhand.com> 18 * 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/iopoll.h> 24 #include <linux/kernel.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/mmc.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/module.h> 29 #include <linux/pinctrl/consumer.h> 30 #include <linux/pinctrl/pinctrl-state.h> 31 #include <linux/platform_data/tmio.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_domain.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/regulator/driver.h> 36 #include <linux/regulator/of_regulator.h> 37 #include <linux/reset.h> 38 #include <linux/sh_dma.h> 39 #include <linux/slab.h> 40 41 #include "renesas_sdhi.h" 42 #include "tmio_mmc.h" 43 44 #define CTL_HOST_MODE 0xe4 45 #define HOST_MODE_GEN2_SDR50_WMODE BIT(0) 46 #define HOST_MODE_GEN2_SDR104_WMODE BIT(0) 47 #define HOST_MODE_GEN3_WMODE BIT(0) 48 #define HOST_MODE_GEN3_BUSWIDTH BIT(8) 49 50 #define HOST_MODE_GEN3_16BIT HOST_MODE_GEN3_WMODE 51 #define HOST_MODE_GEN3_32BIT (HOST_MODE_GEN3_WMODE | HOST_MODE_GEN3_BUSWIDTH) 52 #define HOST_MODE_GEN3_64BIT 0 53 54 #define SDHI_VER_GEN2_SDR50 0x490c 55 #define SDHI_VER_RZ_A1 0x820b 56 /* very old datasheets said 0x490c for SDR104, too. They are wrong! */ 57 #define SDHI_VER_GEN2_SDR104 0xcb0d 58 #define SDHI_VER_GEN3_SD 0xcc10 59 #define SDHI_VER_GEN3_SDMMC 0xcd10 60 61 #define SDHI_GEN3_MMC0_ADDR 0xee140000 62 63 static void renesas_sdhi_sdbuf_width(struct tmio_mmc_host *host, int width) 64 { 65 u32 val; 66 67 /* 68 * see also 69 * renesas_sdhi_of_data :: dma_buswidth 70 */ 71 switch (sd_ctrl_read16(host, CTL_VERSION)) { 72 case SDHI_VER_GEN2_SDR50: 73 val = (width == 32) ? HOST_MODE_GEN2_SDR50_WMODE : 0; 74 break; 75 case SDHI_VER_GEN2_SDR104: 76 val = (width == 32) ? 0 : HOST_MODE_GEN2_SDR104_WMODE; 77 break; 78 case SDHI_VER_GEN3_SD: 79 case SDHI_VER_GEN3_SDMMC: 80 if (width == 64) 81 val = HOST_MODE_GEN3_64BIT; 82 else if (width == 32) 83 val = HOST_MODE_GEN3_32BIT; 84 else 85 val = HOST_MODE_GEN3_16BIT; 86 break; 87 default: 88 /* nothing to do */ 89 return; 90 } 91 92 sd_ctrl_write16(host, CTL_HOST_MODE, val); 93 } 94 95 static int renesas_sdhi_clk_enable(struct tmio_mmc_host *host) 96 { 97 struct mmc_host *mmc = host->mmc; 98 struct renesas_sdhi *priv = host_to_priv(host); 99 int ret; 100 101 ret = clk_prepare_enable(priv->clk_cd); 102 if (ret < 0) 103 return ret; 104 105 /* 106 * The clock driver may not know what maximum frequency 107 * actually works, so it should be set with the max-frequency 108 * property which will already have been read to f_max. If it 109 * was missing, assume the current frequency is the maximum. 110 */ 111 if (!mmc->f_max) 112 mmc->f_max = clk_get_rate(priv->clk); 113 114 /* 115 * Minimum frequency is the minimum input clock frequency 116 * divided by our maximum divider. 117 */ 118 mmc->f_min = max(clk_round_rate(priv->clk, 1) / 512, 1L); 119 120 /* enable 16bit data access on SDBUF as default */ 121 renesas_sdhi_sdbuf_width(host, 16); 122 123 return 0; 124 } 125 126 static unsigned int renesas_sdhi_clk_update(struct tmio_mmc_host *host, 127 unsigned int wanted_clock) 128 { 129 struct renesas_sdhi *priv = host_to_priv(host); 130 struct clk *ref_clk = priv->clk; 131 unsigned int freq, diff, best_freq = 0, diff_min = ~0; 132 unsigned int new_clock, clkh_shift = 0; 133 unsigned int new_upper_limit; 134 int i; 135 136 /* 137 * We simply return the current rate if a) we are not on a R-Car Gen2+ 138 * SoC (may work for others, but untested) or b) if the SCC needs its 139 * clock during tuning, so we don't change the external clock setup. 140 */ 141 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2) || mmc_doing_tune(host->mmc)) 142 return clk_get_rate(priv->clk); 143 144 if (priv->clkh) { 145 /* HS400 with 4TAP needs different clock settings */ 146 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 147 bool need_slow_clkh = host->mmc->ios.timing == MMC_TIMING_MMC_HS400; 148 clkh_shift = use_4tap && need_slow_clkh ? 1 : 2; 149 ref_clk = priv->clkh; 150 } 151 152 new_clock = wanted_clock << clkh_shift; 153 154 /* 155 * We want the bus clock to be as close as possible to, but no 156 * greater than, new_clock. As we can divide by 1 << i for 157 * any i in [0, 9] we want the input clock to be as close as 158 * possible, but no greater than, new_clock << i. 159 * 160 * Add an upper limit of 1/1024 rate higher to the clock rate to fix 161 * clk rate jumping to lower rate due to rounding error (eg: RZ/G2L has 162 * 3 clk sources 533.333333 MHz, 400 MHz and 266.666666 MHz. The request 163 * for 533.333333 MHz will selects a slower 400 MHz due to rounding 164 * error (533333333 Hz / 4 * 4 = 533333332 Hz < 533333333 Hz)). 165 */ 166 for (i = min(9, ilog2(UINT_MAX / new_clock)); i >= 0; i--) { 167 freq = clk_round_rate(ref_clk, new_clock << i); 168 new_upper_limit = (new_clock << i) + ((new_clock << i) >> 10); 169 if (freq > new_upper_limit) { 170 /* Too fast; look for a slightly slower option */ 171 freq = clk_round_rate(ref_clk, (new_clock << i) / 4 * 3); 172 if (freq > new_upper_limit) 173 continue; 174 } 175 176 diff = new_clock - (freq >> i); 177 if (diff <= diff_min) { 178 best_freq = freq; 179 diff_min = diff; 180 } 181 } 182 183 clk_set_rate(ref_clk, best_freq); 184 185 if (priv->clkh) 186 clk_set_rate(priv->clk, best_freq >> clkh_shift); 187 188 return clk_get_rate(priv->clk); 189 } 190 191 static void renesas_sdhi_set_clock(struct tmio_mmc_host *host, 192 unsigned int new_clock) 193 { 194 unsigned int clk_margin; 195 u32 clk = 0, clock; 196 197 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 198 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 199 200 if (new_clock == 0) { 201 host->mmc->actual_clock = 0; 202 goto out; 203 } 204 205 host->mmc->actual_clock = renesas_sdhi_clk_update(host, new_clock); 206 clock = host->mmc->actual_clock / 512; 207 208 /* 209 * Add a margin of 1/1024 rate higher to the clock rate in order 210 * to avoid clk variable setting a value of 0 due to the margin 211 * provided for actual_clock in renesas_sdhi_clk_update(). 212 */ 213 clk_margin = new_clock >> 10; 214 for (clk = 0x80000080; new_clock + clk_margin >= (clock << 1); clk >>= 1) 215 clock <<= 1; 216 217 /* 1/1 clock is option */ 218 if ((host->pdata->flags & TMIO_MMC_CLK_ACTUAL) && ((clk >> 22) & 0x1)) { 219 if (!(host->mmc->ios.timing == MMC_TIMING_MMC_HS400)) 220 clk |= 0xff; 221 else 222 clk &= ~0xff; 223 } 224 225 clock = clk & CLK_CTL_DIV_MASK; 226 if (clock != CLK_CTL_DIV_MASK) 227 host->mmc->actual_clock /= (1 << (ffs(clock) + 1)); 228 229 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, clock); 230 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 231 usleep_range(10000, 11000); 232 233 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 234 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 235 236 out: 237 /* HW engineers overrode docs: no sleep needed on R-Car2+ */ 238 if (!(host->pdata->flags & TMIO_MMC_MIN_RCAR2)) 239 usleep_range(10000, 11000); 240 } 241 242 static void renesas_sdhi_clk_disable(struct tmio_mmc_host *host) 243 { 244 struct renesas_sdhi *priv = host_to_priv(host); 245 246 clk_disable_unprepare(priv->clk_cd); 247 } 248 249 static int renesas_sdhi_card_busy(struct mmc_host *mmc) 250 { 251 struct tmio_mmc_host *host = mmc_priv(mmc); 252 253 return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) & 254 TMIO_STAT_DAT0); 255 } 256 257 static int renesas_sdhi_start_signal_voltage_switch(struct mmc_host *mmc, 258 struct mmc_ios *ios) 259 { 260 struct tmio_mmc_host *host = mmc_priv(mmc); 261 struct renesas_sdhi *priv = host_to_priv(host); 262 struct pinctrl_state *pin_state; 263 int ret; 264 265 switch (ios->signal_voltage) { 266 case MMC_SIGNAL_VOLTAGE_330: 267 pin_state = priv->pins_default; 268 break; 269 case MMC_SIGNAL_VOLTAGE_180: 270 pin_state = priv->pins_uhs; 271 break; 272 default: 273 return -EINVAL; 274 } 275 276 /* 277 * If anything is missing, assume signal voltage is fixed at 278 * 3.3V and succeed/fail accordingly. 279 */ 280 if (IS_ERR(priv->pinctrl) || IS_ERR(pin_state)) 281 return ios->signal_voltage == 282 MMC_SIGNAL_VOLTAGE_330 ? 0 : -EINVAL; 283 284 ret = mmc_regulator_set_vqmmc(host->mmc, ios); 285 if (ret < 0) 286 return ret; 287 288 return pinctrl_select_state(priv->pinctrl, pin_state); 289 } 290 291 /* SCC registers */ 292 #define SH_MOBILE_SDHI_SCC_DTCNTL 0x000 293 #define SH_MOBILE_SDHI_SCC_TAPSET 0x002 294 #define SH_MOBILE_SDHI_SCC_DT2FF 0x004 295 #define SH_MOBILE_SDHI_SCC_CKSEL 0x006 296 #define SH_MOBILE_SDHI_SCC_RVSCNTL 0x008 297 #define SH_MOBILE_SDHI_SCC_RVSREQ 0x00A 298 #define SH_MOBILE_SDHI_SCC_SMPCMP 0x00C 299 #define SH_MOBILE_SDHI_SCC_TMPPORT2 0x00E 300 #define SH_MOBILE_SDHI_SCC_TMPPORT3 0x014 301 #define SH_MOBILE_SDHI_SCC_TMPPORT4 0x016 302 #define SH_MOBILE_SDHI_SCC_TMPPORT5 0x018 303 #define SH_MOBILE_SDHI_SCC_TMPPORT6 0x01A 304 #define SH_MOBILE_SDHI_SCC_TMPPORT7 0x01C 305 306 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN BIT(0) 307 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT 16 308 #define SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK 0xff 309 310 #define SH_MOBILE_SDHI_SCC_CKSEL_DTSEL BIT(0) 311 312 #define SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN BIT(0) 313 314 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN BIT(0) 315 #define SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP BIT(1) 316 #define SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR BIT(2) 317 318 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN BIT(8) 319 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP BIT(24) 320 #define SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR (BIT(8) | BIT(24)) 321 322 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL BIT(4) 323 #define SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN BIT(31) 324 325 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT4 register */ 326 #define SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START BIT(0) 327 328 /* Definitions for values the SH_MOBILE_SDHI_SCC_TMPPORT5 register */ 329 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R BIT(8) 330 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W (0 << 8) 331 #define SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK 0x3F 332 333 /* Definitions for values the SH_MOBILE_SDHI_SCC register */ 334 #define SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE 0xa5000000 335 #define SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK 0x1f 336 #define SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE BIT(7) 337 338 static inline u32 sd_scc_read32(struct tmio_mmc_host *host, 339 struct renesas_sdhi *priv, int addr) 340 { 341 return readl(priv->scc_ctl + (addr << host->bus_shift)); 342 } 343 344 static inline void sd_scc_write32(struct tmio_mmc_host *host, 345 struct renesas_sdhi *priv, 346 int addr, u32 val) 347 { 348 writel(val, priv->scc_ctl + (addr << host->bus_shift)); 349 } 350 351 static unsigned int renesas_sdhi_init_tuning(struct tmio_mmc_host *host) 352 { 353 struct renesas_sdhi *priv; 354 355 priv = host_to_priv(host); 356 357 /* Initialize SCC */ 358 sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, 0x0); 359 360 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 361 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 362 363 /* set sampling clock selection range */ 364 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 365 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 366 0x8 << SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT); 367 368 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 369 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 370 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 371 372 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 373 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 374 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 375 376 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 377 378 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 379 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 380 381 /* Read TAPNUM */ 382 return (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL) >> 383 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_SHIFT) & 384 SH_MOBILE_SDHI_SCC_DTCNTL_TAPNUM_MASK; 385 } 386 387 static void renesas_sdhi_hs400_complete(struct mmc_host *mmc) 388 { 389 struct tmio_mmc_host *host = mmc_priv(mmc); 390 struct renesas_sdhi *priv = host_to_priv(host); 391 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 392 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 393 394 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 395 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 396 397 /* Set HS400 mode */ 398 sd_ctrl_write16(host, CTL_SDIF_MODE, SDIF_MODE_HS400 | 399 sd_ctrl_read16(host, CTL_SDIF_MODE)); 400 401 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, 402 priv->scc_tappos_hs400); 403 404 if (sdhi_has_quirk(priv, manual_tap_correction)) 405 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 406 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 407 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 408 409 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 410 (SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 411 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) | 412 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 413 414 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 415 SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN | 416 sd_scc_read32(host, priv, 417 SH_MOBILE_SDHI_SCC_DTCNTL)); 418 419 /* Avoid bad TAP */ 420 if (bad_taps & BIT(priv->tap_set)) { 421 u32 new_tap = (priv->tap_set + 1) % priv->tap_num; 422 423 if (bad_taps & BIT(new_tap)) 424 new_tap = (priv->tap_set - 1) % priv->tap_num; 425 426 if (bad_taps & BIT(new_tap)) { 427 new_tap = priv->tap_set; 428 dev_dbg(&host->pdev->dev, "Can't handle three bad tap in a row\n"); 429 } 430 431 priv->tap_set = new_tap; 432 } 433 434 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 435 priv->tap_set / (use_4tap ? 2 : 1)); 436 437 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 438 SH_MOBILE_SDHI_SCC_CKSEL_DTSEL | 439 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL)); 440 441 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 442 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 443 444 if (priv->adjust_hs400_calib_table) 445 priv->needs_adjust_hs400 = true; 446 } 447 448 static void renesas_sdhi_disable_scc(struct mmc_host *mmc) 449 { 450 struct tmio_mmc_host *host = mmc_priv(mmc); 451 struct renesas_sdhi *priv = host_to_priv(host); 452 453 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 454 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 455 456 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_CKSEL, 457 ~SH_MOBILE_SDHI_SCC_CKSEL_DTSEL & 458 sd_scc_read32(host, priv, 459 SH_MOBILE_SDHI_SCC_CKSEL)); 460 461 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DTCNTL, 462 ~SH_MOBILE_SDHI_SCC_DTCNTL_TAPEN & 463 sd_scc_read32(host, priv, 464 SH_MOBILE_SDHI_SCC_DTCNTL)); 465 466 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 467 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 468 } 469 470 static u32 sd_scc_tmpport_read32(struct tmio_mmc_host *host, 471 struct renesas_sdhi *priv, u32 addr) 472 { 473 /* read mode */ 474 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 475 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_R | 476 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 477 478 /* access start and stop */ 479 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 480 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 481 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 482 483 return sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT7); 484 } 485 486 static void sd_scc_tmpport_write32(struct tmio_mmc_host *host, 487 struct renesas_sdhi *priv, u32 addr, u32 val) 488 { 489 /* write mode */ 490 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT5, 491 SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_RW_SEL_W | 492 (SH_MOBILE_SDHI_SCC_TMPPORT5_DLL_ADR_MASK & addr)); 493 494 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT6, val); 495 496 /* access start and stop */ 497 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 498 SH_MOBILE_SDHI_SCC_TMPPORT4_DLL_ACC_START); 499 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT4, 0); 500 } 501 502 static void renesas_sdhi_adjust_hs400_mode_enable(struct tmio_mmc_host *host) 503 { 504 struct renesas_sdhi *priv = host_to_priv(host); 505 u32 calib_code; 506 507 /* disable write protect */ 508 sd_scc_tmpport_write32(host, priv, 0x00, 509 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 510 /* read calibration code and adjust */ 511 calib_code = sd_scc_tmpport_read32(host, priv, 0x26); 512 calib_code &= SH_MOBILE_SDHI_SCC_TMPPORT_CALIB_CODE_MASK; 513 514 sd_scc_tmpport_write32(host, priv, 0x22, 515 SH_MOBILE_SDHI_SCC_TMPPORT_MANUAL_MODE | 516 priv->adjust_hs400_calib_table[calib_code]); 517 518 /* set offset value to TMPPORT3, hardcoded to OFFSET0 (= 0x3) for now */ 519 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0x3); 520 521 /* adjustment done, clear flag */ 522 priv->needs_adjust_hs400 = false; 523 } 524 525 static void renesas_sdhi_adjust_hs400_mode_disable(struct tmio_mmc_host *host) 526 { 527 struct renesas_sdhi *priv = host_to_priv(host); 528 529 /* disable write protect */ 530 sd_scc_tmpport_write32(host, priv, 0x00, 531 SH_MOBILE_SDHI_SCC_TMPPORT_DISABLE_WP_CODE); 532 /* disable manual calibration */ 533 sd_scc_tmpport_write32(host, priv, 0x22, 0); 534 /* clear offset value of TMPPORT3 */ 535 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT3, 0); 536 } 537 538 static void renesas_sdhi_reset_hs400_mode(struct tmio_mmc_host *host, 539 struct renesas_sdhi *priv) 540 { 541 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, ~CLK_CTL_SCLKEN & 542 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 543 544 /* Reset HS400 mode */ 545 sd_ctrl_write16(host, CTL_SDIF_MODE, ~SDIF_MODE_HS400 & 546 sd_ctrl_read16(host, CTL_SDIF_MODE)); 547 548 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_DT2FF, priv->scc_tappos); 549 550 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 551 ~(SH_MOBILE_SDHI_SCC_TMPPORT2_HS400EN | 552 SH_MOBILE_SDHI_SCC_TMPPORT2_HS400OSEL) & 553 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2)); 554 555 if (sdhi_has_quirk(priv, hs400_calib_table) || sdhi_has_quirk(priv, hs400_bad_taps)) 556 renesas_sdhi_adjust_hs400_mode_disable(host); 557 558 sd_ctrl_write16(host, CTL_SD_CARD_CLK_CTL, CLK_CTL_SCLKEN | 559 sd_ctrl_read16(host, CTL_SD_CARD_CLK_CTL)); 560 } 561 562 static int renesas_sdhi_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 563 { 564 struct tmio_mmc_host *host = mmc_priv(mmc); 565 566 renesas_sdhi_reset_hs400_mode(host, host_to_priv(host)); 567 return 0; 568 } 569 570 static void renesas_sdhi_scc_reset(struct tmio_mmc_host *host, struct renesas_sdhi *priv) 571 { 572 renesas_sdhi_disable_scc(host->mmc); 573 renesas_sdhi_reset_hs400_mode(host, priv); 574 priv->needs_adjust_hs400 = false; 575 576 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 577 ~SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN & 578 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 579 } 580 581 /* only populated for TMIO_MMC_MIN_RCAR2 */ 582 static void renesas_sdhi_reset(struct tmio_mmc_host *host, bool preserve) 583 { 584 struct renesas_sdhi *priv = host_to_priv(host); 585 int ret; 586 u16 val; 587 588 if (!preserve) { 589 if (priv->rstc) { 590 u32 sd_status; 591 /* 592 * HW reset might have toggled the regulator state in 593 * HW which regulator core might be unaware of so save 594 * and restore the regulator state during HW reset. 595 */ 596 if (priv->rdev) 597 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 598 599 reset_control_reset(priv->rstc); 600 /* Unknown why but without polling reset status, it will hang */ 601 read_poll_timeout(reset_control_status, ret, ret == 0, 1, 100, 602 false, priv->rstc); 603 /* At least SDHI_VER_GEN2_SDR50 needs manual release of reset */ 604 sd_ctrl_write16(host, CTL_RESET_SD, 0x0001); 605 if (priv->rdev) 606 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 607 608 priv->needs_adjust_hs400 = false; 609 renesas_sdhi_set_clock(host, host->clk_cache); 610 611 /* Ensure default value for this driver. */ 612 renesas_sdhi_sdbuf_width(host, 16); 613 } else if (priv->scc_ctl) { 614 renesas_sdhi_scc_reset(host, priv); 615 } 616 } 617 618 if (sd_ctrl_read16(host, CTL_VERSION) >= SDHI_VER_GEN3_SD) { 619 val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 620 val |= CARD_OPT_EXTOP; 621 sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, val); 622 } 623 } 624 625 static unsigned int renesas_sdhi_gen3_get_cycles(struct tmio_mmc_host *host) 626 { 627 u16 num, val = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT); 628 629 num = (val & CARD_OPT_TOP_MASK) >> CARD_OPT_TOP_SHIFT; 630 return 1 << ((val & CARD_OPT_EXTOP ? 14 : 13) + num); 631 632 } 633 634 #define SH_MOBILE_SDHI_MIN_TAP_ROW 3 635 636 static int renesas_sdhi_select_tuning(struct tmio_mmc_host *host) 637 { 638 struct renesas_sdhi *priv = host_to_priv(host); 639 unsigned int tap_start = 0, tap_end = 0, tap_cnt = 0, rs, re, i; 640 unsigned int taps_size = priv->tap_num * 2, min_tap_row; 641 unsigned long *bitmap; 642 643 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 644 645 /* 646 * When tuning CMD19 is issued twice for each tap, merge the 647 * result requiring the tap to be good in both runs before 648 * considering it for tuning selection. 649 */ 650 for (i = 0; i < taps_size; i++) { 651 int offset = priv->tap_num * (i < priv->tap_num ? 1 : -1); 652 653 if (!test_bit(i, priv->taps)) 654 clear_bit(i + offset, priv->taps); 655 656 if (!test_bit(i, priv->smpcmp)) 657 clear_bit(i + offset, priv->smpcmp); 658 } 659 660 /* 661 * If all TAP are OK, the sampling clock position is selected by 662 * identifying the change point of data. 663 */ 664 if (bitmap_full(priv->taps, taps_size)) { 665 bitmap = priv->smpcmp; 666 min_tap_row = 1; 667 } else { 668 bitmap = priv->taps; 669 min_tap_row = SH_MOBILE_SDHI_MIN_TAP_ROW; 670 } 671 672 /* 673 * Find the longest consecutive run of successful probes. If that 674 * is at least SH_MOBILE_SDHI_MIN_TAP_ROW probes long then use the 675 * center index as the tap, otherwise bail out. 676 */ 677 for_each_set_bitrange(rs, re, bitmap, taps_size) { 678 if (re - rs > tap_cnt) { 679 tap_end = re; 680 tap_start = rs; 681 tap_cnt = tap_end - tap_start; 682 } 683 } 684 685 if (tap_cnt >= min_tap_row) 686 priv->tap_set = (tap_start + tap_end) / 2 % priv->tap_num; 687 else 688 return -EIO; 689 690 /* Set SCC */ 691 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, priv->tap_set); 692 693 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL, 694 (priv->card_is_sdio ? 0 : SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) | 695 sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL)); 696 697 return 0; 698 } 699 700 static int renesas_sdhi_execute_tuning(struct mmc_host *mmc, u32 opcode) 701 { 702 struct tmio_mmc_host *host = mmc_priv(mmc); 703 struct renesas_sdhi *priv = host_to_priv(host); 704 int i, ret; 705 706 priv->tap_num = renesas_sdhi_init_tuning(host); 707 if (!priv->tap_num) 708 return 0; /* Tuning is not supported */ 709 710 if (priv->tap_num * 2 >= sizeof(priv->taps) * BITS_PER_BYTE) { 711 dev_err(&host->pdev->dev, 712 "Too many taps, please update 'taps' in tmio_mmc_host!\n"); 713 return -EINVAL; 714 } 715 716 bitmap_zero(priv->taps, priv->tap_num * 2); 717 bitmap_zero(priv->smpcmp, priv->tap_num * 2); 718 719 /* Issue CMD19 twice for each tap */ 720 for (i = 0; i < 2 * priv->tap_num; i++) { 721 int cmd_error = 0; 722 723 /* Set sampling clock position */ 724 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, i % priv->tap_num); 725 726 if (mmc_send_tuning(mmc, opcode, &cmd_error) == 0) 727 set_bit(i, priv->taps); 728 729 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) == 0) 730 set_bit(i, priv->smpcmp); 731 732 if (cmd_error) 733 mmc_send_abort_tuning(mmc, opcode); 734 } 735 736 ret = renesas_sdhi_select_tuning(host); 737 if (ret < 0) 738 renesas_sdhi_scc_reset(host, priv); 739 return ret; 740 } 741 742 static bool renesas_sdhi_manual_correction(struct tmio_mmc_host *host, bool use_4tap) 743 { 744 struct renesas_sdhi *priv = host_to_priv(host); 745 unsigned int new_tap = priv->tap_set, error_tap = priv->tap_set; 746 u32 val; 747 748 val = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ); 749 if (!val) 750 return false; 751 752 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 753 754 /* Change TAP position according to correction status */ 755 if (sdhi_has_quirk(priv, manual_tap_correction) && 756 host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 757 u32 bad_taps = priv->quirks ? priv->quirks->hs400_bad_taps : 0; 758 /* 759 * With HS400, the DAT signal is based on DS, not CLK. 760 * Therefore, use only CMD status. 761 */ 762 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP) & 763 SH_MOBILE_SDHI_SCC_SMPCMP_CMD_ERR; 764 if (!smpcmp) { 765 return false; /* no error in CMD signal */ 766 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQUP) { 767 new_tap++; 768 error_tap--; 769 } else if (smpcmp == SH_MOBILE_SDHI_SCC_SMPCMP_CMD_REQDOWN) { 770 new_tap--; 771 error_tap++; 772 } else { 773 return true; /* need retune */ 774 } 775 776 /* 777 * When new_tap is a bad tap, we cannot change. Then, we compare 778 * with the HS200 tuning result. When smpcmp[error_tap] is OK, 779 * we can at least retune. 780 */ 781 if (bad_taps & BIT(new_tap % priv->tap_num)) 782 return test_bit(error_tap % priv->tap_num, priv->smpcmp); 783 } else { 784 if (!priv->card_is_sdio && 785 !(val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR)) { 786 u32 smpcmp = sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_SMPCMP); 787 788 /* DAT1 is unmatched because of an SDIO irq */ 789 if (smpcmp & (BIT(17) | BIT(1))) 790 return false; 791 } 792 if (val & SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) 793 return true; /* need retune */ 794 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPUP) 795 new_tap++; 796 else if (val & SH_MOBILE_SDHI_SCC_RVSREQ_REQTAPDOWN) 797 new_tap--; 798 else 799 return false; 800 } 801 802 priv->tap_set = (new_tap % priv->tap_num); 803 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TAPSET, 804 priv->tap_set / (use_4tap ? 2 : 1)); 805 806 return false; 807 } 808 809 static bool renesas_sdhi_auto_correction(struct tmio_mmc_host *host) 810 { 811 struct renesas_sdhi *priv = host_to_priv(host); 812 813 /* Check SCC error */ 814 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ) & 815 SH_MOBILE_SDHI_SCC_RVSREQ_RVSERR) { 816 sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_RVSREQ, 0); 817 return true; 818 } 819 820 return false; 821 } 822 823 static bool renesas_sdhi_check_scc_error(struct tmio_mmc_host *host, 824 struct mmc_request *mrq) 825 { 826 struct renesas_sdhi *priv = host_to_priv(host); 827 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 828 bool ret = false; 829 830 /* 831 * Skip checking SCC errors when running on 4 taps in HS400 mode as 832 * any retuning would still result in the same 4 taps being used. 833 */ 834 if (!(host->mmc->ios.timing == MMC_TIMING_UHS_SDR104) && 835 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS200) && 836 !(host->mmc->ios.timing == MMC_TIMING_MMC_HS400 && !use_4tap)) 837 return false; 838 839 if (mmc_doing_tune(host->mmc)) 840 return false; 841 842 /* mrq can be NULL to check SCC error on SDIO irq without any request */ 843 if (mrq) { 844 if (((mrq->cmd->error == -ETIMEDOUT) || 845 (mrq->data && mrq->data->error == -ETIMEDOUT)) && 846 ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 847 (host->ops.get_cd && host->ops.get_cd(host->mmc)))) 848 ret |= true; 849 } 850 851 if (sd_scc_read32(host, priv, SH_MOBILE_SDHI_SCC_RVSCNTL) & 852 SH_MOBILE_SDHI_SCC_RVSCNTL_RVSEN) 853 ret |= renesas_sdhi_auto_correction(host); 854 else 855 ret |= renesas_sdhi_manual_correction(host, use_4tap); 856 857 return ret; 858 } 859 860 static void renesas_sdhi_init_card(struct mmc_host *mmc, struct mmc_card *card) 861 { 862 struct tmio_mmc_host *host = mmc_priv(mmc); 863 struct renesas_sdhi *priv = host_to_priv(host); 864 865 /* 866 * This controller cannot do auto-retune with SDIO irqs, so we 867 * then need to enforce manual correction. However, when tuning, 868 * mmc->card is not populated yet, so we don't know if the card 869 * is SDIO. init_card provides this information earlier, so we 870 * keep a copy of it. 871 */ 872 priv->card_is_sdio = mmc_card_sdio(card); 873 } 874 875 static void renesas_sdhi_sdio_irq(struct tmio_mmc_host *host) 876 { 877 /* This controller requires retune when an SDIO irq occurs */ 878 if (renesas_sdhi_check_scc_error(host, NULL)) 879 mmc_retune_needed(host->mmc); 880 } 881 882 static int renesas_sdhi_wait_idle(struct tmio_mmc_host *host, u32 bit) 883 { 884 int timeout = 1000; 885 /* CBSY is set when busy, SCLKDIVEN is cleared when busy */ 886 u32 wait_state = (bit == TMIO_STAT_CMD_BUSY ? TMIO_STAT_CMD_BUSY : 0); 887 888 while (--timeout && (sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) 889 & bit) == wait_state) 890 udelay(1); 891 892 if (!timeout) { 893 dev_warn(&host->pdev->dev, "timeout waiting for SD bus idle\n"); 894 return -EBUSY; 895 } 896 897 return 0; 898 } 899 900 static int renesas_sdhi_write16_hook(struct tmio_mmc_host *host, int addr) 901 { 902 u32 bit = TMIO_STAT_SCLKDIVEN; 903 904 switch (addr) { 905 case CTL_SD_CMD: 906 case CTL_STOP_INTERNAL_ACTION: 907 case CTL_XFER_BLK_COUNT: 908 case CTL_SD_XFER_LEN: 909 case CTL_SD_MEM_CARD_OPT: 910 case CTL_TRANSACTION_CTL: 911 case CTL_DMA_ENABLE: 912 case CTL_HOST_MODE: 913 if (host->pdata->flags & TMIO_MMC_HAVE_CBSY) 914 bit = TMIO_STAT_CMD_BUSY; 915 fallthrough; 916 case CTL_SD_CARD_CLK_CTL: 917 return renesas_sdhi_wait_idle(host, bit); 918 } 919 920 return 0; 921 } 922 923 static int renesas_sdhi_multi_io_quirk(struct mmc_card *card, 924 unsigned int direction, int blk_size) 925 { 926 /* 927 * In Renesas controllers, when performing a 928 * multiple block read of one or two blocks, 929 * depending on the timing with which the 930 * response register is read, the response 931 * value may not be read properly. 932 * Use single block read for this HW bug 933 */ 934 if ((direction == MMC_DATA_READ) && 935 blk_size == 2) 936 return 1; 937 938 return blk_size; 939 } 940 941 static void renesas_sdhi_fixup_request(struct tmio_mmc_host *host, struct mmc_request *mrq) 942 { 943 struct renesas_sdhi *priv = host_to_priv(host); 944 945 if (priv->needs_adjust_hs400 && mrq->cmd->opcode == MMC_SEND_STATUS) 946 renesas_sdhi_adjust_hs400_mode_enable(host); 947 } 948 static void renesas_sdhi_enable_dma(struct tmio_mmc_host *host, bool enable) 949 { 950 /* Iff regs are 8 byte apart, sdbuf is 64 bit. Otherwise always 32. */ 951 int width = (host->bus_shift == 2) ? 64 : 32; 952 953 sd_ctrl_write16(host, CTL_DMA_ENABLE, enable ? DMA_ENABLE_DMASDRW : 0); 954 renesas_sdhi_sdbuf_width(host, enable ? width : 16); 955 } 956 957 static const unsigned int renesas_sdhi_vqmmc_voltages[] = { 958 3300000, 1800000 959 }; 960 961 static int renesas_sdhi_regulator_disable(struct regulator_dev *rdev) 962 { 963 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 964 u32 sd_status; 965 966 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 967 sd_status &= ~SD_STATUS_PWEN; 968 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 969 970 return 0; 971 } 972 973 static int renesas_sdhi_regulator_enable(struct regulator_dev *rdev) 974 { 975 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 976 u32 sd_status; 977 978 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 979 sd_status |= SD_STATUS_PWEN; 980 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 981 982 return 0; 983 } 984 985 static int renesas_sdhi_regulator_is_enabled(struct regulator_dev *rdev) 986 { 987 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 988 u32 sd_status; 989 990 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 991 992 return (sd_status & SD_STATUS_PWEN) ? 1 : 0; 993 } 994 995 static int renesas_sdhi_regulator_get_voltage(struct regulator_dev *rdev) 996 { 997 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 998 u32 sd_status; 999 1000 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 1001 1002 return (sd_status & SD_STATUS_IOVS) ? 1800000 : 3300000; 1003 } 1004 1005 static int renesas_sdhi_regulator_set_voltage(struct regulator_dev *rdev, 1006 int min_uV, int max_uV, 1007 unsigned int *selector) 1008 { 1009 struct tmio_mmc_host *host = rdev_get_drvdata(rdev); 1010 u32 sd_status; 1011 1012 sd_status = sd_ctrl_read32(host, CTL_SD_STATUS); 1013 if (min_uV >= 1700000 && max_uV <= 1950000) { 1014 sd_status |= SD_STATUS_IOVS; 1015 *selector = 1; 1016 } else { 1017 sd_status &= ~SD_STATUS_IOVS; 1018 *selector = 0; 1019 } 1020 sd_ctrl_write32(host, CTL_SD_STATUS, sd_status); 1021 1022 return 0; 1023 } 1024 1025 static int renesas_sdhi_regulator_list_voltage(struct regulator_dev *rdev, 1026 unsigned int selector) 1027 { 1028 if (selector >= ARRAY_SIZE(renesas_sdhi_vqmmc_voltages)) 1029 return -EINVAL; 1030 1031 return renesas_sdhi_vqmmc_voltages[selector]; 1032 } 1033 1034 static const struct regulator_ops renesas_sdhi_regulator_voltage_ops = { 1035 .enable = renesas_sdhi_regulator_enable, 1036 .disable = renesas_sdhi_regulator_disable, 1037 .is_enabled = renesas_sdhi_regulator_is_enabled, 1038 .list_voltage = renesas_sdhi_regulator_list_voltage, 1039 .get_voltage = renesas_sdhi_regulator_get_voltage, 1040 .set_voltage = renesas_sdhi_regulator_set_voltage, 1041 }; 1042 1043 static const struct regulator_desc renesas_sdhi_vqmmc_regulator = { 1044 .name = "sdhi-vqmmc-regulator", 1045 .of_match = of_match_ptr("vqmmc-regulator"), 1046 .type = REGULATOR_VOLTAGE, 1047 .owner = THIS_MODULE, 1048 .ops = &renesas_sdhi_regulator_voltage_ops, 1049 .volt_table = renesas_sdhi_vqmmc_voltages, 1050 .n_voltages = ARRAY_SIZE(renesas_sdhi_vqmmc_voltages), 1051 }; 1052 1053 int renesas_sdhi_probe(struct platform_device *pdev, 1054 const struct tmio_mmc_dma_ops *dma_ops, 1055 const struct renesas_sdhi_of_data *of_data, 1056 const struct renesas_sdhi_quirks *quirks) 1057 { 1058 struct tmio_mmc_data *mmd = pdev->dev.platform_data; 1059 struct tmio_mmc_data *mmc_data; 1060 struct regulator_config rcfg = { .dev = &pdev->dev, }; 1061 struct regulator_dev *rdev; 1062 struct renesas_sdhi_dma *dma_priv; 1063 struct device *dev = &pdev->dev; 1064 struct tmio_mmc_host *host; 1065 struct renesas_sdhi *priv; 1066 int num_irqs, irq, ret, i; 1067 struct resource *res; 1068 u16 ver; 1069 1070 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1071 if (!res) 1072 return -EINVAL; 1073 1074 priv = devm_kzalloc(&pdev->dev, sizeof(struct renesas_sdhi), 1075 GFP_KERNEL); 1076 if (!priv) 1077 return -ENOMEM; 1078 1079 priv->quirks = quirks; 1080 mmc_data = &priv->mmc_data; 1081 dma_priv = &priv->dma_priv; 1082 1083 priv->clk = devm_clk_get(&pdev->dev, NULL); 1084 if (IS_ERR(priv->clk)) 1085 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk), "cannot get clock"); 1086 1087 priv->clkh = devm_clk_get_optional(&pdev->dev, "clkh"); 1088 if (IS_ERR(priv->clkh)) 1089 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clkh), "cannot get clkh"); 1090 1091 /* 1092 * Some controllers provide a 2nd clock just to run the internal card 1093 * detection logic. Unfortunately, the existing driver architecture does 1094 * not support a separation of clocks for runtime PM usage. When 1095 * native hotplug is used, the tmio driver assumes that the core 1096 * must continue to run for card detect to stay active, so we cannot 1097 * disable it. 1098 * Additionally, it is prohibited to supply a clock to the core but not 1099 * to the card detect circuit. That leaves us with if separate clocks 1100 * are presented, we must treat them both as virtually 1 clock. 1101 */ 1102 priv->clk_cd = devm_clk_get_optional(&pdev->dev, "cd"); 1103 if (IS_ERR(priv->clk_cd)) 1104 return dev_err_probe(&pdev->dev, PTR_ERR(priv->clk_cd), "cannot get cd clock"); 1105 1106 priv->rstc = devm_reset_control_get_optional_exclusive(&pdev->dev, NULL); 1107 if (IS_ERR(priv->rstc)) 1108 return PTR_ERR(priv->rstc); 1109 1110 priv->pinctrl = devm_pinctrl_get(&pdev->dev); 1111 if (!IS_ERR(priv->pinctrl)) { 1112 priv->pins_default = pinctrl_lookup_state(priv->pinctrl, 1113 PINCTRL_STATE_DEFAULT); 1114 priv->pins_uhs = pinctrl_lookup_state(priv->pinctrl, 1115 "state_uhs"); 1116 } 1117 1118 host = tmio_mmc_host_alloc(pdev, mmc_data); 1119 if (IS_ERR(host)) 1120 return PTR_ERR(host); 1121 1122 priv->host = host; 1123 1124 if (of_data) { 1125 mmc_data->flags |= of_data->tmio_flags; 1126 mmc_data->ocr_mask = of_data->tmio_ocr_mask; 1127 mmc_data->capabilities |= of_data->capabilities; 1128 mmc_data->capabilities2 |= of_data->capabilities2; 1129 mmc_data->dma_rx_offset = of_data->dma_rx_offset; 1130 mmc_data->max_blk_count = of_data->max_blk_count; 1131 mmc_data->max_segs = of_data->max_segs; 1132 dma_priv->dma_buswidth = of_data->dma_buswidth; 1133 host->bus_shift = of_data->bus_shift; 1134 /* Fallback for old DTs */ 1135 if (!priv->clkh && of_data->sdhi_flags & SDHI_FLAG_NEED_CLKH_FALLBACK) 1136 priv->clkh = clk_get_parent(clk_get_parent(priv->clk)); 1137 1138 } 1139 1140 host->write16_hook = renesas_sdhi_write16_hook; 1141 host->clk_enable = renesas_sdhi_clk_enable; 1142 host->clk_disable = renesas_sdhi_clk_disable; 1143 host->set_clock = renesas_sdhi_set_clock; 1144 host->multi_io_quirk = renesas_sdhi_multi_io_quirk; 1145 host->dma_ops = dma_ops; 1146 1147 if (sdhi_has_quirk(priv, hs400_disabled)) 1148 host->mmc->caps2 &= ~(MMC_CAP2_HS400 | MMC_CAP2_HS400_ES); 1149 1150 /* For some SoC, we disable internal WP. GPIO may override this */ 1151 if (mmc_host_can_gpio_ro(host->mmc)) 1152 mmc_data->capabilities2 &= ~MMC_CAP2_NO_WRITE_PROTECT; 1153 1154 /* SDR speeds are only available on Gen2+ */ 1155 if (mmc_data->flags & TMIO_MMC_MIN_RCAR2) { 1156 /* card_busy caused issues on r8a73a4 (pre-Gen2) CD-less SDHI */ 1157 host->ops.card_busy = renesas_sdhi_card_busy; 1158 host->ops.start_signal_voltage_switch = 1159 renesas_sdhi_start_signal_voltage_switch; 1160 host->sdcard_irq_setbit_mask = TMIO_STAT_ALWAYS_SET_27; 1161 host->sdcard_irq_mask_all = TMIO_MASK_ALL_RCAR2; 1162 host->reset = renesas_sdhi_reset; 1163 } else { 1164 host->sdcard_irq_mask_all = TMIO_MASK_ALL; 1165 } 1166 1167 /* Orginally registers were 16 bit apart, could be 32 or 64 nowadays */ 1168 if (!host->bus_shift && resource_size(res) > 0x100) /* old way to determine the shift */ 1169 host->bus_shift = 1; 1170 1171 if (mmd) 1172 *mmc_data = *mmd; 1173 1174 dma_priv->filter = shdma_chan_filter; 1175 dma_priv->enable = renesas_sdhi_enable_dma; 1176 1177 mmc_data->capabilities |= MMC_CAP_MMC_HIGHSPEED; 1178 1179 /* 1180 * All SDHI blocks support 2-byte and larger block sizes in 4-bit 1181 * bus width mode. 1182 */ 1183 mmc_data->flags |= TMIO_MMC_BLKSZ_2BYTES; 1184 1185 /* 1186 * All SDHI blocks support SDIO IRQ signalling. 1187 */ 1188 mmc_data->flags |= TMIO_MMC_SDIO_IRQ; 1189 1190 /* All SDHI have CMD12 control bit */ 1191 mmc_data->flags |= TMIO_MMC_HAVE_CMD12_CTRL; 1192 1193 /* All SDHI have SDIO status bits which must be 1 */ 1194 mmc_data->flags |= TMIO_MMC_SDIO_STATUS_SETBITS; 1195 1196 /* All SDHI support HW busy detection */ 1197 mmc_data->flags |= TMIO_MMC_USE_BUSY_TIMEOUT; 1198 1199 dev_pm_domain_start(&pdev->dev); 1200 1201 ret = renesas_sdhi_clk_enable(host); 1202 if (ret) 1203 return ret; 1204 1205 rcfg.of_node = of_get_available_child_by_name(dev->of_node, "vqmmc-regulator"); 1206 if (rcfg.of_node) { 1207 rcfg.driver_data = priv->host; 1208 rdev = devm_regulator_register(dev, &renesas_sdhi_vqmmc_regulator, &rcfg); 1209 of_node_put(rcfg.of_node); 1210 if (IS_ERR(rdev)) { 1211 dev_err(dev, "regulator register failed err=%ld", PTR_ERR(rdev)); 1212 ret = PTR_ERR(rdev); 1213 goto edisclk; 1214 } 1215 priv->rdev = rdev; 1216 } 1217 1218 ver = sd_ctrl_read16(host, CTL_VERSION); 1219 /* GEN2_SDR104 is first known SDHI to use 32bit block count */ 1220 if (ver < SDHI_VER_GEN2_SDR104 && mmc_data->max_blk_count > U16_MAX) 1221 mmc_data->max_blk_count = U16_MAX; 1222 1223 /* One Gen2 SDHI incarnation does NOT have a CBSY bit */ 1224 if (ver == SDHI_VER_GEN2_SDR50) 1225 mmc_data->flags &= ~TMIO_MMC_HAVE_CBSY; 1226 1227 if (ver == SDHI_VER_GEN3_SDMMC && sdhi_has_quirk(priv, hs400_calib_table)) { 1228 host->fixup_request = renesas_sdhi_fixup_request; 1229 priv->adjust_hs400_calib_table = *( 1230 res->start == SDHI_GEN3_MMC0_ADDR ? 1231 quirks->hs400_calib_table : 1232 quirks->hs400_calib_table + 1); 1233 } 1234 1235 /* these have an EXTOP bit */ 1236 if (ver >= SDHI_VER_GEN3_SD) 1237 host->get_timeout_cycles = renesas_sdhi_gen3_get_cycles; 1238 1239 /* Check for SCC so we can reset it if needed */ 1240 if (of_data && of_data->scc_offset && ver >= SDHI_VER_GEN2_SDR104) 1241 priv->scc_ctl = host->ctl + of_data->scc_offset; 1242 1243 /* Enable tuning iff we have an SCC and a supported mode */ 1244 if (priv->scc_ctl && (host->mmc->caps & MMC_CAP_UHS_SDR104 || 1245 host->mmc->caps2 & MMC_CAP2_HSX00_1_8V)) { 1246 const struct renesas_sdhi_scc *taps = of_data->taps; 1247 bool use_4tap = sdhi_has_quirk(priv, hs400_4taps); 1248 bool hit = false; 1249 1250 for (i = 0; i < of_data->taps_num; i++) { 1251 if (taps[i].clk_rate == 0 || 1252 taps[i].clk_rate == host->mmc->f_max) { 1253 priv->scc_tappos = taps->tap; 1254 priv->scc_tappos_hs400 = use_4tap ? 1255 taps->tap_hs400_4tap : 1256 taps->tap; 1257 hit = true; 1258 break; 1259 } 1260 } 1261 1262 if (!hit) 1263 dev_warn(&host->pdev->dev, "Unknown clock rate for tuning\n"); 1264 1265 host->check_retune = renesas_sdhi_check_scc_error; 1266 host->sdio_irq = renesas_sdhi_sdio_irq; 1267 host->ops.init_card = renesas_sdhi_init_card; 1268 host->ops.execute_tuning = renesas_sdhi_execute_tuning; 1269 host->ops.prepare_hs400_tuning = renesas_sdhi_prepare_hs400_tuning; 1270 host->ops.hs400_downgrade = renesas_sdhi_disable_scc; 1271 host->ops.hs400_complete = renesas_sdhi_hs400_complete; 1272 } 1273 1274 sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask_all); 1275 1276 /* There must be at least one IRQ source */ 1277 num_irqs = platform_irq_count(pdev); 1278 if (num_irqs <= 0) { 1279 ret = num_irqs ?: -ENOENT; 1280 goto edisclk; 1281 } 1282 1283 for (i = 0; i < num_irqs; i++) { 1284 irq = platform_get_irq(pdev, i); 1285 if (irq < 0) { 1286 ret = irq; 1287 goto edisclk; 1288 } 1289 1290 ret = devm_request_irq(&pdev->dev, irq, tmio_mmc_irq, 0, 1291 dev_name(&pdev->dev), host); 1292 if (ret) 1293 goto edisclk; 1294 } 1295 1296 ret = tmio_mmc_host_probe(host); 1297 if (ret < 0) 1298 goto edisclk; 1299 1300 dev_info(&pdev->dev, "%s base at %pa, max clock rate %u MHz\n", 1301 mmc_hostname(host->mmc), &res->start, host->mmc->f_max / 1000000); 1302 1303 return ret; 1304 1305 edisclk: 1306 renesas_sdhi_clk_disable(host); 1307 return ret; 1308 } 1309 EXPORT_SYMBOL_GPL(renesas_sdhi_probe); 1310 1311 void renesas_sdhi_remove(struct platform_device *pdev) 1312 { 1313 struct tmio_mmc_host *host = platform_get_drvdata(pdev); 1314 1315 tmio_mmc_host_remove(host); 1316 renesas_sdhi_clk_disable(host); 1317 } 1318 EXPORT_SYMBOL_GPL(renesas_sdhi_remove); 1319 1320 MODULE_DESCRIPTION("Renesas SDHI core driver"); 1321 MODULE_LICENSE("GPL v2"); 1322