1 /* 2 * linux/drivers/mmc/host/pxa.c - PXA MMCI driver 3 * 4 * Copyright (C) 2003 Russell King, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This hardware is really sick: 11 * - No way to clear interrupts. 12 * - Have to turn off the clock whenever we touch the device. 13 * - Doesn't tell you how many data blocks were transferred. 14 * Yuck! 15 * 16 * 1 and 3 byte data transfers not supported 17 * max block length up to 1023 18 */ 19 #include <linux/module.h> 20 #include <linux/init.h> 21 #include <linux/ioport.h> 22 #include <linux/platform_device.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/clk.h> 27 #include <linux/err.h> 28 #include <linux/mmc/host.h> 29 #include <linux/io.h> 30 31 #include <asm/sizes.h> 32 33 #include <mach/hardware.h> 34 #include <mach/dma.h> 35 #include <mach/mmc.h> 36 37 #include "pxamci.h" 38 39 #define DRIVER_NAME "pxa2xx-mci" 40 41 #define NR_SG 1 42 #define CLKRT_OFF (~0) 43 44 struct pxamci_host { 45 struct mmc_host *mmc; 46 spinlock_t lock; 47 struct resource *res; 48 void __iomem *base; 49 struct clk *clk; 50 unsigned long clkrate; 51 int irq; 52 int dma; 53 unsigned int clkrt; 54 unsigned int cmdat; 55 unsigned int imask; 56 unsigned int power_mode; 57 struct pxamci_platform_data *pdata; 58 59 struct mmc_request *mrq; 60 struct mmc_command *cmd; 61 struct mmc_data *data; 62 63 dma_addr_t sg_dma; 64 struct pxa_dma_desc *sg_cpu; 65 unsigned int dma_len; 66 67 unsigned int dma_dir; 68 unsigned int dma_drcmrrx; 69 unsigned int dma_drcmrtx; 70 }; 71 72 static void pxamci_stop_clock(struct pxamci_host *host) 73 { 74 if (readl(host->base + MMC_STAT) & STAT_CLK_EN) { 75 unsigned long timeout = 10000; 76 unsigned int v; 77 78 writel(STOP_CLOCK, host->base + MMC_STRPCL); 79 80 do { 81 v = readl(host->base + MMC_STAT); 82 if (!(v & STAT_CLK_EN)) 83 break; 84 udelay(1); 85 } while (timeout--); 86 87 if (v & STAT_CLK_EN) 88 dev_err(mmc_dev(host->mmc), "unable to stop clock\n"); 89 } 90 } 91 92 static void pxamci_enable_irq(struct pxamci_host *host, unsigned int mask) 93 { 94 unsigned long flags; 95 96 spin_lock_irqsave(&host->lock, flags); 97 host->imask &= ~mask; 98 writel(host->imask, host->base + MMC_I_MASK); 99 spin_unlock_irqrestore(&host->lock, flags); 100 } 101 102 static void pxamci_disable_irq(struct pxamci_host *host, unsigned int mask) 103 { 104 unsigned long flags; 105 106 spin_lock_irqsave(&host->lock, flags); 107 host->imask |= mask; 108 writel(host->imask, host->base + MMC_I_MASK); 109 spin_unlock_irqrestore(&host->lock, flags); 110 } 111 112 static void pxamci_setup_data(struct pxamci_host *host, struct mmc_data *data) 113 { 114 unsigned int nob = data->blocks; 115 unsigned long long clks; 116 unsigned int timeout; 117 bool dalgn = 0; 118 u32 dcmd; 119 int i; 120 121 host->data = data; 122 123 if (data->flags & MMC_DATA_STREAM) 124 nob = 0xffff; 125 126 writel(nob, host->base + MMC_NOB); 127 writel(data->blksz, host->base + MMC_BLKLEN); 128 129 clks = (unsigned long long)data->timeout_ns * host->clkrate; 130 do_div(clks, 1000000000UL); 131 timeout = (unsigned int)clks + (data->timeout_clks << host->clkrt); 132 writel((timeout + 255) / 256, host->base + MMC_RDTO); 133 134 if (data->flags & MMC_DATA_READ) { 135 host->dma_dir = DMA_FROM_DEVICE; 136 dcmd = DCMD_INCTRGADDR | DCMD_FLOWTRG; 137 DRCMR(host->dma_drcmrtx) = 0; 138 DRCMR(host->dma_drcmrrx) = host->dma | DRCMR_MAPVLD; 139 } else { 140 host->dma_dir = DMA_TO_DEVICE; 141 dcmd = DCMD_INCSRCADDR | DCMD_FLOWSRC; 142 DRCMR(host->dma_drcmrrx) = 0; 143 DRCMR(host->dma_drcmrtx) = host->dma | DRCMR_MAPVLD; 144 } 145 146 dcmd |= DCMD_BURST32 | DCMD_WIDTH1; 147 148 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 149 host->dma_dir); 150 151 for (i = 0; i < host->dma_len; i++) { 152 unsigned int length = sg_dma_len(&data->sg[i]); 153 host->sg_cpu[i].dcmd = dcmd | length; 154 if (length & 31 && !(data->flags & MMC_DATA_READ)) 155 host->sg_cpu[i].dcmd |= DCMD_ENDIRQEN; 156 /* Not aligned to 8-byte boundary? */ 157 if (sg_dma_address(&data->sg[i]) & 0x7) 158 dalgn = 1; 159 if (data->flags & MMC_DATA_READ) { 160 host->sg_cpu[i].dsadr = host->res->start + MMC_RXFIFO; 161 host->sg_cpu[i].dtadr = sg_dma_address(&data->sg[i]); 162 } else { 163 host->sg_cpu[i].dsadr = sg_dma_address(&data->sg[i]); 164 host->sg_cpu[i].dtadr = host->res->start + MMC_TXFIFO; 165 } 166 host->sg_cpu[i].ddadr = host->sg_dma + (i + 1) * 167 sizeof(struct pxa_dma_desc); 168 } 169 host->sg_cpu[host->dma_len - 1].ddadr = DDADR_STOP; 170 wmb(); 171 172 /* 173 * The PXA27x DMA controller encounters overhead when working with 174 * unaligned (to 8-byte boundaries) data, so switch on byte alignment 175 * mode only if we have unaligned data. 176 */ 177 if (dalgn) 178 DALGN |= (1 << host->dma); 179 else 180 DALGN &= ~(1 << host->dma); 181 DDADR(host->dma) = host->sg_dma; 182 183 /* 184 * workaround for erratum #91: 185 * only start DMA now if we are doing a read, 186 * otherwise we wait until CMD/RESP has finished 187 * before starting DMA. 188 */ 189 if (!cpu_is_pxa27x() || data->flags & MMC_DATA_READ) 190 DCSR(host->dma) = DCSR_RUN; 191 } 192 193 static void pxamci_start_cmd(struct pxamci_host *host, struct mmc_command *cmd, unsigned int cmdat) 194 { 195 WARN_ON(host->cmd != NULL); 196 host->cmd = cmd; 197 198 if (cmd->flags & MMC_RSP_BUSY) 199 cmdat |= CMDAT_BUSY; 200 201 #define RSP_TYPE(x) ((x) & ~(MMC_RSP_BUSY|MMC_RSP_OPCODE)) 202 switch (RSP_TYPE(mmc_resp_type(cmd))) { 203 case RSP_TYPE(MMC_RSP_R1): /* r1, r1b, r6, r7 */ 204 cmdat |= CMDAT_RESP_SHORT; 205 break; 206 case RSP_TYPE(MMC_RSP_R3): 207 cmdat |= CMDAT_RESP_R3; 208 break; 209 case RSP_TYPE(MMC_RSP_R2): 210 cmdat |= CMDAT_RESP_R2; 211 break; 212 default: 213 break; 214 } 215 216 writel(cmd->opcode, host->base + MMC_CMD); 217 writel(cmd->arg >> 16, host->base + MMC_ARGH); 218 writel(cmd->arg & 0xffff, host->base + MMC_ARGL); 219 writel(cmdat, host->base + MMC_CMDAT); 220 writel(host->clkrt, host->base + MMC_CLKRT); 221 222 writel(START_CLOCK, host->base + MMC_STRPCL); 223 224 pxamci_enable_irq(host, END_CMD_RES); 225 } 226 227 static void pxamci_finish_request(struct pxamci_host *host, struct mmc_request *mrq) 228 { 229 host->mrq = NULL; 230 host->cmd = NULL; 231 host->data = NULL; 232 mmc_request_done(host->mmc, mrq); 233 } 234 235 static int pxamci_cmd_done(struct pxamci_host *host, unsigned int stat) 236 { 237 struct mmc_command *cmd = host->cmd; 238 int i; 239 u32 v; 240 241 if (!cmd) 242 return 0; 243 244 host->cmd = NULL; 245 246 /* 247 * Did I mention this is Sick. We always need to 248 * discard the upper 8 bits of the first 16-bit word. 249 */ 250 v = readl(host->base + MMC_RES) & 0xffff; 251 for (i = 0; i < 4; i++) { 252 u32 w1 = readl(host->base + MMC_RES) & 0xffff; 253 u32 w2 = readl(host->base + MMC_RES) & 0xffff; 254 cmd->resp[i] = v << 24 | w1 << 8 | w2 >> 8; 255 v = w2; 256 } 257 258 if (stat & STAT_TIME_OUT_RESPONSE) { 259 cmd->error = -ETIMEDOUT; 260 } else if (stat & STAT_RES_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 261 /* 262 * workaround for erratum #42: 263 * Intel PXA27x Family Processor Specification Update Rev 001 264 * A bogus CRC error can appear if the msb of a 136 bit 265 * response is a one. 266 */ 267 if (cpu_is_pxa27x() && 268 (cmd->flags & MMC_RSP_136 && cmd->resp[0] & 0x80000000)) 269 pr_debug("ignoring CRC from command %d - *risky*\n", cmd->opcode); 270 else 271 cmd->error = -EILSEQ; 272 } 273 274 pxamci_disable_irq(host, END_CMD_RES); 275 if (host->data && !cmd->error) { 276 pxamci_enable_irq(host, DATA_TRAN_DONE); 277 /* 278 * workaround for erratum #91, if doing write 279 * enable DMA late 280 */ 281 if (cpu_is_pxa27x() && host->data->flags & MMC_DATA_WRITE) 282 DCSR(host->dma) = DCSR_RUN; 283 } else { 284 pxamci_finish_request(host, host->mrq); 285 } 286 287 return 1; 288 } 289 290 static int pxamci_data_done(struct pxamci_host *host, unsigned int stat) 291 { 292 struct mmc_data *data = host->data; 293 294 if (!data) 295 return 0; 296 297 DCSR(host->dma) = 0; 298 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 299 host->dma_dir); 300 301 if (stat & STAT_READ_TIME_OUT) 302 data->error = -ETIMEDOUT; 303 else if (stat & (STAT_CRC_READ_ERROR|STAT_CRC_WRITE_ERROR)) 304 data->error = -EILSEQ; 305 306 /* 307 * There appears to be a hardware design bug here. There seems to 308 * be no way to find out how much data was transferred to the card. 309 * This means that if there was an error on any block, we mark all 310 * data blocks as being in error. 311 */ 312 if (!data->error) 313 data->bytes_xfered = data->blocks * data->blksz; 314 else 315 data->bytes_xfered = 0; 316 317 pxamci_disable_irq(host, DATA_TRAN_DONE); 318 319 host->data = NULL; 320 if (host->mrq->stop) { 321 pxamci_stop_clock(host); 322 pxamci_start_cmd(host, host->mrq->stop, host->cmdat); 323 } else { 324 pxamci_finish_request(host, host->mrq); 325 } 326 327 return 1; 328 } 329 330 static irqreturn_t pxamci_irq(int irq, void *devid) 331 { 332 struct pxamci_host *host = devid; 333 unsigned int ireg; 334 int handled = 0; 335 336 ireg = readl(host->base + MMC_I_REG) & ~readl(host->base + MMC_I_MASK); 337 338 if (ireg) { 339 unsigned stat = readl(host->base + MMC_STAT); 340 341 pr_debug("PXAMCI: irq %08x stat %08x\n", ireg, stat); 342 343 if (ireg & END_CMD_RES) 344 handled |= pxamci_cmd_done(host, stat); 345 if (ireg & DATA_TRAN_DONE) 346 handled |= pxamci_data_done(host, stat); 347 if (ireg & SDIO_INT) { 348 mmc_signal_sdio_irq(host->mmc); 349 handled = 1; 350 } 351 } 352 353 return IRQ_RETVAL(handled); 354 } 355 356 static void pxamci_request(struct mmc_host *mmc, struct mmc_request *mrq) 357 { 358 struct pxamci_host *host = mmc_priv(mmc); 359 unsigned int cmdat; 360 361 WARN_ON(host->mrq != NULL); 362 363 host->mrq = mrq; 364 365 pxamci_stop_clock(host); 366 367 cmdat = host->cmdat; 368 host->cmdat &= ~CMDAT_INIT; 369 370 if (mrq->data) { 371 pxamci_setup_data(host, mrq->data); 372 373 cmdat &= ~CMDAT_BUSY; 374 cmdat |= CMDAT_DATAEN | CMDAT_DMAEN; 375 if (mrq->data->flags & MMC_DATA_WRITE) 376 cmdat |= CMDAT_WRITE; 377 378 if (mrq->data->flags & MMC_DATA_STREAM) 379 cmdat |= CMDAT_STREAM; 380 } 381 382 pxamci_start_cmd(host, mrq->cmd, cmdat); 383 } 384 385 static int pxamci_get_ro(struct mmc_host *mmc) 386 { 387 struct pxamci_host *host = mmc_priv(mmc); 388 389 if (host->pdata && host->pdata->get_ro) 390 return !!host->pdata->get_ro(mmc_dev(mmc)); 391 /* 392 * Board doesn't support read only detection; let the mmc core 393 * decide what to do. 394 */ 395 return -ENOSYS; 396 } 397 398 static void pxamci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 399 { 400 struct pxamci_host *host = mmc_priv(mmc); 401 402 if (ios->clock) { 403 unsigned long rate = host->clkrate; 404 unsigned int clk = rate / ios->clock; 405 406 if (host->clkrt == CLKRT_OFF) 407 clk_enable(host->clk); 408 409 if (ios->clock == 26000000) { 410 /* to support 26MHz on pxa300/pxa310 */ 411 host->clkrt = 7; 412 } else { 413 /* to handle (19.5MHz, 26MHz) */ 414 if (!clk) 415 clk = 1; 416 417 /* 418 * clk might result in a lower divisor than we 419 * desire. check for that condition and adjust 420 * as appropriate. 421 */ 422 if (rate / clk > ios->clock) 423 clk <<= 1; 424 host->clkrt = fls(clk) - 1; 425 } 426 427 /* 428 * we write clkrt on the next command 429 */ 430 } else { 431 pxamci_stop_clock(host); 432 if (host->clkrt != CLKRT_OFF) { 433 host->clkrt = CLKRT_OFF; 434 clk_disable(host->clk); 435 } 436 } 437 438 if (host->power_mode != ios->power_mode) { 439 host->power_mode = ios->power_mode; 440 441 if (host->pdata && host->pdata->setpower) 442 host->pdata->setpower(mmc_dev(mmc), ios->vdd); 443 444 if (ios->power_mode == MMC_POWER_ON) 445 host->cmdat |= CMDAT_INIT; 446 } 447 448 if (ios->bus_width == MMC_BUS_WIDTH_4) 449 host->cmdat |= CMDAT_SD_4DAT; 450 else 451 host->cmdat &= ~CMDAT_SD_4DAT; 452 453 pr_debug("PXAMCI: clkrt = %x cmdat = %x\n", 454 host->clkrt, host->cmdat); 455 } 456 457 static void pxamci_enable_sdio_irq(struct mmc_host *host, int enable) 458 { 459 struct pxamci_host *pxa_host = mmc_priv(host); 460 461 if (enable) 462 pxamci_enable_irq(pxa_host, SDIO_INT); 463 else 464 pxamci_disable_irq(pxa_host, SDIO_INT); 465 } 466 467 static const struct mmc_host_ops pxamci_ops = { 468 .request = pxamci_request, 469 .get_ro = pxamci_get_ro, 470 .set_ios = pxamci_set_ios, 471 .enable_sdio_irq = pxamci_enable_sdio_irq, 472 }; 473 474 static void pxamci_dma_irq(int dma, void *devid) 475 { 476 struct pxamci_host *host = devid; 477 int dcsr = DCSR(dma); 478 DCSR(dma) = dcsr & ~DCSR_STOPIRQEN; 479 480 if (dcsr & DCSR_ENDINTR) { 481 writel(BUF_PART_FULL, host->base + MMC_PRTBUF); 482 } else { 483 printk(KERN_ERR "%s: DMA error on channel %d (DCSR=%#x)\n", 484 mmc_hostname(host->mmc), dma, dcsr); 485 host->data->error = -EIO; 486 pxamci_data_done(host, 0); 487 } 488 } 489 490 static irqreturn_t pxamci_detect_irq(int irq, void *devid) 491 { 492 struct pxamci_host *host = mmc_priv(devid); 493 494 mmc_detect_change(devid, host->pdata->detect_delay); 495 return IRQ_HANDLED; 496 } 497 498 static int pxamci_probe(struct platform_device *pdev) 499 { 500 struct mmc_host *mmc; 501 struct pxamci_host *host = NULL; 502 struct resource *r, *dmarx, *dmatx; 503 int ret, irq; 504 505 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 506 irq = platform_get_irq(pdev, 0); 507 if (!r || irq < 0) 508 return -ENXIO; 509 510 r = request_mem_region(r->start, SZ_4K, DRIVER_NAME); 511 if (!r) 512 return -EBUSY; 513 514 mmc = mmc_alloc_host(sizeof(struct pxamci_host), &pdev->dev); 515 if (!mmc) { 516 ret = -ENOMEM; 517 goto out; 518 } 519 520 mmc->ops = &pxamci_ops; 521 522 /* 523 * We can do SG-DMA, but we don't because we never know how much 524 * data we successfully wrote to the card. 525 */ 526 mmc->max_phys_segs = NR_SG; 527 528 /* 529 * Our hardware DMA can handle a maximum of one page per SG entry. 530 */ 531 mmc->max_seg_size = PAGE_SIZE; 532 533 /* 534 * Block length register is only 10 bits before PXA27x. 535 */ 536 mmc->max_blk_size = cpu_is_pxa25x() ? 1023 : 2048; 537 538 /* 539 * Block count register is 16 bits. 540 */ 541 mmc->max_blk_count = 65535; 542 543 host = mmc_priv(mmc); 544 host->mmc = mmc; 545 host->dma = -1; 546 host->pdata = pdev->dev.platform_data; 547 host->clkrt = CLKRT_OFF; 548 549 host->clk = clk_get(&pdev->dev, NULL); 550 if (IS_ERR(host->clk)) { 551 ret = PTR_ERR(host->clk); 552 host->clk = NULL; 553 goto out; 554 } 555 556 host->clkrate = clk_get_rate(host->clk); 557 558 /* 559 * Calculate minimum clock rate, rounding up. 560 */ 561 mmc->f_min = (host->clkrate + 63) / 64; 562 mmc->f_max = (cpu_is_pxa300() || cpu_is_pxa310()) ? 26000000 563 : host->clkrate; 564 565 mmc->ocr_avail = host->pdata ? 566 host->pdata->ocr_mask : 567 MMC_VDD_32_33|MMC_VDD_33_34; 568 mmc->caps = 0; 569 host->cmdat = 0; 570 if (!cpu_is_pxa25x()) { 571 mmc->caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 572 host->cmdat |= CMDAT_SDIO_INT_EN; 573 if (cpu_is_pxa300() || cpu_is_pxa310()) 574 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | 575 MMC_CAP_SD_HIGHSPEED; 576 } 577 578 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, &host->sg_dma, GFP_KERNEL); 579 if (!host->sg_cpu) { 580 ret = -ENOMEM; 581 goto out; 582 } 583 584 spin_lock_init(&host->lock); 585 host->res = r; 586 host->irq = irq; 587 host->imask = MMC_I_MASK_ALL; 588 589 host->base = ioremap(r->start, SZ_4K); 590 if (!host->base) { 591 ret = -ENOMEM; 592 goto out; 593 } 594 595 /* 596 * Ensure that the host controller is shut down, and setup 597 * with our defaults. 598 */ 599 pxamci_stop_clock(host); 600 writel(0, host->base + MMC_SPI); 601 writel(64, host->base + MMC_RESTO); 602 writel(host->imask, host->base + MMC_I_MASK); 603 604 host->dma = pxa_request_dma(DRIVER_NAME, DMA_PRIO_LOW, 605 pxamci_dma_irq, host); 606 if (host->dma < 0) { 607 ret = -EBUSY; 608 goto out; 609 } 610 611 ret = request_irq(host->irq, pxamci_irq, 0, DRIVER_NAME, host); 612 if (ret) 613 goto out; 614 615 platform_set_drvdata(pdev, mmc); 616 617 dmarx = platform_get_resource(pdev, IORESOURCE_DMA, 0); 618 if (!dmarx) { 619 ret = -ENXIO; 620 goto out; 621 } 622 host->dma_drcmrrx = dmarx->start; 623 624 dmatx = platform_get_resource(pdev, IORESOURCE_DMA, 1); 625 if (!dmatx) { 626 ret = -ENXIO; 627 goto out; 628 } 629 host->dma_drcmrtx = dmatx->start; 630 631 if (host->pdata && host->pdata->init) 632 host->pdata->init(&pdev->dev, pxamci_detect_irq, mmc); 633 634 mmc_add_host(mmc); 635 636 return 0; 637 638 out: 639 if (host) { 640 if (host->dma >= 0) 641 pxa_free_dma(host->dma); 642 if (host->base) 643 iounmap(host->base); 644 if (host->sg_cpu) 645 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 646 if (host->clk) 647 clk_put(host->clk); 648 } 649 if (mmc) 650 mmc_free_host(mmc); 651 release_resource(r); 652 return ret; 653 } 654 655 static int pxamci_remove(struct platform_device *pdev) 656 { 657 struct mmc_host *mmc = platform_get_drvdata(pdev); 658 659 platform_set_drvdata(pdev, NULL); 660 661 if (mmc) { 662 struct pxamci_host *host = mmc_priv(mmc); 663 664 if (host->pdata && host->pdata->exit) 665 host->pdata->exit(&pdev->dev, mmc); 666 667 mmc_remove_host(mmc); 668 669 pxamci_stop_clock(host); 670 writel(TXFIFO_WR_REQ|RXFIFO_RD_REQ|CLK_IS_OFF|STOP_CMD| 671 END_CMD_RES|PRG_DONE|DATA_TRAN_DONE, 672 host->base + MMC_I_MASK); 673 674 DRCMR(host->dma_drcmrrx) = 0; 675 DRCMR(host->dma_drcmrtx) = 0; 676 677 free_irq(host->irq, host); 678 pxa_free_dma(host->dma); 679 iounmap(host->base); 680 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 681 682 clk_put(host->clk); 683 684 release_resource(host->res); 685 686 mmc_free_host(mmc); 687 } 688 return 0; 689 } 690 691 #ifdef CONFIG_PM 692 static int pxamci_suspend(struct platform_device *dev, pm_message_t state) 693 { 694 struct mmc_host *mmc = platform_get_drvdata(dev); 695 int ret = 0; 696 697 if (mmc) 698 ret = mmc_suspend_host(mmc, state); 699 700 return ret; 701 } 702 703 static int pxamci_resume(struct platform_device *dev) 704 { 705 struct mmc_host *mmc = platform_get_drvdata(dev); 706 int ret = 0; 707 708 if (mmc) 709 ret = mmc_resume_host(mmc); 710 711 return ret; 712 } 713 #else 714 #define pxamci_suspend NULL 715 #define pxamci_resume NULL 716 #endif 717 718 static struct platform_driver pxamci_driver = { 719 .probe = pxamci_probe, 720 .remove = pxamci_remove, 721 .suspend = pxamci_suspend, 722 .resume = pxamci_resume, 723 .driver = { 724 .name = DRIVER_NAME, 725 .owner = THIS_MODULE, 726 }, 727 }; 728 729 static int __init pxamci_init(void) 730 { 731 return platform_driver_register(&pxamci_driver); 732 } 733 734 static void __exit pxamci_exit(void) 735 { 736 platform_driver_unregister(&pxamci_driver); 737 } 738 739 module_init(pxamci_init); 740 module_exit(pxamci_exit); 741 742 MODULE_DESCRIPTION("PXA Multimedia Card Interface Driver"); 743 MODULE_LICENSE("GPL"); 744 MODULE_ALIAS("platform:pxa2xx-mci"); 745