1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/kernel.h> 21 #include <linux/debugfs.h> 22 #include <linux/dmaengine.h> 23 #include <linux/seq_file.h> 24 #include <linux/interrupt.h> 25 #include <linux/delay.h> 26 #include <linux/dma-mapping.h> 27 #include <linux/platform_device.h> 28 #include <linux/timer.h> 29 #include <linux/clk.h> 30 #include <linux/of.h> 31 #include <linux/of_gpio.h> 32 #include <linux/of_device.h> 33 #include <linux/omap-dma.h> 34 #include <linux/mmc/host.h> 35 #include <linux/mmc/core.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/io.h> 38 #include <linux/gpio.h> 39 #include <linux/regulator/consumer.h> 40 #include <linux/pinctrl/consumer.h> 41 #include <linux/pm_runtime.h> 42 #include <linux/platform_data/mmc-omap.h> 43 44 /* OMAP HSMMC Host Controller Registers */ 45 #define OMAP_HSMMC_SYSSTATUS 0x0014 46 #define OMAP_HSMMC_CON 0x002C 47 #define OMAP_HSMMC_BLK 0x0104 48 #define OMAP_HSMMC_ARG 0x0108 49 #define OMAP_HSMMC_CMD 0x010C 50 #define OMAP_HSMMC_RSP10 0x0110 51 #define OMAP_HSMMC_RSP32 0x0114 52 #define OMAP_HSMMC_RSP54 0x0118 53 #define OMAP_HSMMC_RSP76 0x011C 54 #define OMAP_HSMMC_DATA 0x0120 55 #define OMAP_HSMMC_HCTL 0x0128 56 #define OMAP_HSMMC_SYSCTL 0x012C 57 #define OMAP_HSMMC_STAT 0x0130 58 #define OMAP_HSMMC_IE 0x0134 59 #define OMAP_HSMMC_ISE 0x0138 60 #define OMAP_HSMMC_CAPA 0x0140 61 62 #define VS18 (1 << 26) 63 #define VS30 (1 << 25) 64 #define HSS (1 << 21) 65 #define SDVS18 (0x5 << 9) 66 #define SDVS30 (0x6 << 9) 67 #define SDVS33 (0x7 << 9) 68 #define SDVS_MASK 0x00000E00 69 #define SDVSCLR 0xFFFFF1FF 70 #define SDVSDET 0x00000400 71 #define AUTOIDLE 0x1 72 #define SDBP (1 << 8) 73 #define DTO 0xe 74 #define ICE 0x1 75 #define ICS 0x2 76 #define CEN (1 << 2) 77 #define CLKD_MASK 0x0000FFC0 78 #define CLKD_SHIFT 6 79 #define DTO_MASK 0x000F0000 80 #define DTO_SHIFT 16 81 #define INIT_STREAM (1 << 1) 82 #define DP_SELECT (1 << 21) 83 #define DDIR (1 << 4) 84 #define DMAE 0x1 85 #define MSBS (1 << 5) 86 #define BCE (1 << 1) 87 #define FOUR_BIT (1 << 1) 88 #define HSPE (1 << 2) 89 #define DDR (1 << 19) 90 #define DW8 (1 << 5) 91 #define OD 0x1 92 #define STAT_CLEAR 0xFFFFFFFF 93 #define INIT_STREAM_CMD 0x00000000 94 #define DUAL_VOLT_OCR_BIT 7 95 #define SRC (1 << 25) 96 #define SRD (1 << 26) 97 #define SOFTRESET (1 << 1) 98 #define RESETDONE (1 << 0) 99 100 /* Interrupt masks for IE and ISE register */ 101 #define CC_EN (1 << 0) 102 #define TC_EN (1 << 1) 103 #define BWR_EN (1 << 4) 104 #define BRR_EN (1 << 5) 105 #define ERR_EN (1 << 15) 106 #define CTO_EN (1 << 16) 107 #define CCRC_EN (1 << 17) 108 #define CEB_EN (1 << 18) 109 #define CIE_EN (1 << 19) 110 #define DTO_EN (1 << 20) 111 #define DCRC_EN (1 << 21) 112 #define DEB_EN (1 << 22) 113 #define CERR_EN (1 << 28) 114 #define BADA_EN (1 << 29) 115 116 #define INT_EN_MASK (BADA_EN | CERR_EN | DEB_EN | DCRC_EN |\ 117 DTO_EN | CIE_EN | CEB_EN | CCRC_EN | CTO_EN | \ 118 BRR_EN | BWR_EN | TC_EN | CC_EN) 119 120 #define MMC_AUTOSUSPEND_DELAY 100 121 #define MMC_TIMEOUT_MS 20 122 #define OMAP_MMC_MIN_CLOCK 400000 123 #define OMAP_MMC_MAX_CLOCK 52000000 124 #define DRIVER_NAME "omap_hsmmc" 125 126 /* 127 * One controller can have multiple slots, like on some omap boards using 128 * omap.c controller driver. Luckily this is not currently done on any known 129 * omap_hsmmc.c device. 130 */ 131 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 132 133 /* 134 * MMC Host controller read/write API's 135 */ 136 #define OMAP_HSMMC_READ(base, reg) \ 137 __raw_readl((base) + OMAP_HSMMC_##reg) 138 139 #define OMAP_HSMMC_WRITE(base, reg, val) \ 140 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 141 142 struct omap_hsmmc_next { 143 unsigned int dma_len; 144 s32 cookie; 145 }; 146 147 struct omap_hsmmc_host { 148 struct device *dev; 149 struct mmc_host *mmc; 150 struct mmc_request *mrq; 151 struct mmc_command *cmd; 152 struct mmc_data *data; 153 struct clk *fclk; 154 struct clk *dbclk; 155 /* 156 * vcc == configured supply 157 * vcc_aux == optional 158 * - MMC1, supply for DAT4..DAT7 159 * - MMC2/MMC2, external level shifter voltage supply, for 160 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 161 */ 162 struct regulator *vcc; 163 struct regulator *vcc_aux; 164 void __iomem *base; 165 resource_size_t mapbase; 166 spinlock_t irq_lock; /* Prevent races with irq handler */ 167 unsigned int dma_len; 168 unsigned int dma_sg_idx; 169 unsigned char bus_mode; 170 unsigned char power_mode; 171 int suspended; 172 int irq; 173 int use_dma, dma_ch; 174 struct dma_chan *tx_chan; 175 struct dma_chan *rx_chan; 176 int slot_id; 177 int response_busy; 178 int context_loss; 179 int protect_card; 180 int reqs_blocked; 181 int use_reg; 182 int req_in_progress; 183 struct omap_hsmmc_next next_data; 184 185 struct omap_mmc_platform_data *pdata; 186 }; 187 188 static int omap_hsmmc_card_detect(struct device *dev, int slot) 189 { 190 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 191 struct omap_mmc_platform_data *mmc = host->pdata; 192 193 /* NOTE: assumes card detect signal is active-low */ 194 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 195 } 196 197 static int omap_hsmmc_get_wp(struct device *dev, int slot) 198 { 199 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 200 struct omap_mmc_platform_data *mmc = host->pdata; 201 202 /* NOTE: assumes write protect signal is active-high */ 203 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 204 } 205 206 static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 207 { 208 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 209 struct omap_mmc_platform_data *mmc = host->pdata; 210 211 /* NOTE: assumes card detect signal is active-low */ 212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 213 } 214 215 #ifdef CONFIG_PM 216 217 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 218 { 219 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 220 struct omap_mmc_platform_data *mmc = host->pdata; 221 222 disable_irq(mmc->slots[0].card_detect_irq); 223 return 0; 224 } 225 226 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 227 { 228 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 229 struct omap_mmc_platform_data *mmc = host->pdata; 230 231 enable_irq(mmc->slots[0].card_detect_irq); 232 return 0; 233 } 234 235 #else 236 237 #define omap_hsmmc_suspend_cdirq NULL 238 #define omap_hsmmc_resume_cdirq NULL 239 240 #endif 241 242 #ifdef CONFIG_REGULATOR 243 244 static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on, 245 int vdd) 246 { 247 struct omap_hsmmc_host *host = 248 platform_get_drvdata(to_platform_device(dev)); 249 int ret = 0; 250 251 /* 252 * If we don't see a Vcc regulator, assume it's a fixed 253 * voltage always-on regulator. 254 */ 255 if (!host->vcc) 256 return 0; 257 /* 258 * With DT, never turn OFF the regulator. This is because 259 * the pbias cell programming support is still missing when 260 * booting with Device tree 261 */ 262 if (dev->of_node && !vdd) 263 return 0; 264 265 if (mmc_slot(host).before_set_reg) 266 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 267 268 /* 269 * Assume Vcc regulator is used only to power the card ... OMAP 270 * VDDS is used to power the pins, optionally with a transceiver to 271 * support cards using voltages other than VDDS (1.8V nominal). When a 272 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 273 * 274 * In some cases this regulator won't support enable/disable; 275 * e.g. it's a fixed rail for a WLAN chip. 276 * 277 * In other cases vcc_aux switches interface power. Example, for 278 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 279 * chips/cards need an interface voltage rail too. 280 */ 281 if (power_on) { 282 ret = mmc_regulator_set_ocr(host->mmc, host->vcc, vdd); 283 /* Enable interface voltage rail, if needed */ 284 if (ret == 0 && host->vcc_aux) { 285 ret = regulator_enable(host->vcc_aux); 286 if (ret < 0) 287 ret = mmc_regulator_set_ocr(host->mmc, 288 host->vcc, 0); 289 } 290 } else { 291 /* Shut down the rail */ 292 if (host->vcc_aux) 293 ret = regulator_disable(host->vcc_aux); 294 if (!ret) { 295 /* Then proceed to shut down the local regulator */ 296 ret = mmc_regulator_set_ocr(host->mmc, 297 host->vcc, 0); 298 } 299 } 300 301 if (mmc_slot(host).after_set_reg) 302 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 303 304 return ret; 305 } 306 307 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 308 { 309 struct regulator *reg; 310 int ocr_value = 0; 311 312 reg = regulator_get(host->dev, "vmmc"); 313 if (IS_ERR(reg)) { 314 dev_err(host->dev, "vmmc regulator missing\n"); 315 return PTR_ERR(reg); 316 } else { 317 mmc_slot(host).set_power = omap_hsmmc_set_power; 318 host->vcc = reg; 319 ocr_value = mmc_regulator_get_ocrmask(reg); 320 if (!mmc_slot(host).ocr_mask) { 321 mmc_slot(host).ocr_mask = ocr_value; 322 } else { 323 if (!(mmc_slot(host).ocr_mask & ocr_value)) { 324 dev_err(host->dev, "ocrmask %x is not supported\n", 325 mmc_slot(host).ocr_mask); 326 mmc_slot(host).ocr_mask = 0; 327 return -EINVAL; 328 } 329 } 330 331 /* Allow an aux regulator */ 332 reg = regulator_get(host->dev, "vmmc_aux"); 333 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 334 335 /* For eMMC do not power off when not in sleep state */ 336 if (mmc_slot(host).no_regulator_off_init) 337 return 0; 338 /* 339 * UGLY HACK: workaround regulator framework bugs. 340 * When the bootloader leaves a supply active, it's 341 * initialized with zero usecount ... and we can't 342 * disable it without first enabling it. Until the 343 * framework is fixed, we need a workaround like this 344 * (which is safe for MMC, but not in general). 345 */ 346 if (regulator_is_enabled(host->vcc) > 0 || 347 (host->vcc_aux && regulator_is_enabled(host->vcc_aux))) { 348 int vdd = ffs(mmc_slot(host).ocr_mask) - 1; 349 350 mmc_slot(host).set_power(host->dev, host->slot_id, 351 1, vdd); 352 mmc_slot(host).set_power(host->dev, host->slot_id, 353 0, 0); 354 } 355 } 356 357 return 0; 358 } 359 360 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 361 { 362 regulator_put(host->vcc); 363 regulator_put(host->vcc_aux); 364 mmc_slot(host).set_power = NULL; 365 } 366 367 static inline int omap_hsmmc_have_reg(void) 368 { 369 return 1; 370 } 371 372 #else 373 374 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 375 { 376 return -EINVAL; 377 } 378 379 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 380 { 381 } 382 383 static inline int omap_hsmmc_have_reg(void) 384 { 385 return 0; 386 } 387 388 #endif 389 390 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 391 { 392 int ret; 393 394 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 395 if (pdata->slots[0].cover) 396 pdata->slots[0].get_cover_state = 397 omap_hsmmc_get_cover_state; 398 else 399 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 400 pdata->slots[0].card_detect_irq = 401 gpio_to_irq(pdata->slots[0].switch_pin); 402 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 403 if (ret) 404 return ret; 405 ret = gpio_direction_input(pdata->slots[0].switch_pin); 406 if (ret) 407 goto err_free_sp; 408 } else 409 pdata->slots[0].switch_pin = -EINVAL; 410 411 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 412 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 413 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 414 if (ret) 415 goto err_free_cd; 416 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 417 if (ret) 418 goto err_free_wp; 419 } else 420 pdata->slots[0].gpio_wp = -EINVAL; 421 422 return 0; 423 424 err_free_wp: 425 gpio_free(pdata->slots[0].gpio_wp); 426 err_free_cd: 427 if (gpio_is_valid(pdata->slots[0].switch_pin)) 428 err_free_sp: 429 gpio_free(pdata->slots[0].switch_pin); 430 return ret; 431 } 432 433 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 434 { 435 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 436 gpio_free(pdata->slots[0].gpio_wp); 437 if (gpio_is_valid(pdata->slots[0].switch_pin)) 438 gpio_free(pdata->slots[0].switch_pin); 439 } 440 441 /* 442 * Start clock to the card 443 */ 444 static void omap_hsmmc_start_clock(struct omap_hsmmc_host *host) 445 { 446 OMAP_HSMMC_WRITE(host->base, SYSCTL, 447 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 448 } 449 450 /* 451 * Stop clock to the card 452 */ 453 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 454 { 455 OMAP_HSMMC_WRITE(host->base, SYSCTL, 456 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 457 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 458 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stopped\n"); 459 } 460 461 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 462 struct mmc_command *cmd) 463 { 464 unsigned int irq_mask; 465 466 if (host->use_dma) 467 irq_mask = INT_EN_MASK & ~(BRR_EN | BWR_EN); 468 else 469 irq_mask = INT_EN_MASK; 470 471 /* Disable timeout for erases */ 472 if (cmd->opcode == MMC_ERASE) 473 irq_mask &= ~DTO_EN; 474 475 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 476 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 477 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 478 } 479 480 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 481 { 482 OMAP_HSMMC_WRITE(host->base, ISE, 0); 483 OMAP_HSMMC_WRITE(host->base, IE, 0); 484 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 485 } 486 487 /* Calculate divisor for the given clock frequency */ 488 static u16 calc_divisor(struct omap_hsmmc_host *host, struct mmc_ios *ios) 489 { 490 u16 dsor = 0; 491 492 if (ios->clock) { 493 dsor = DIV_ROUND_UP(clk_get_rate(host->fclk), ios->clock); 494 if (dsor > 250) 495 dsor = 250; 496 } 497 498 return dsor; 499 } 500 501 static void omap_hsmmc_set_clock(struct omap_hsmmc_host *host) 502 { 503 struct mmc_ios *ios = &host->mmc->ios; 504 unsigned long regval; 505 unsigned long timeout; 506 unsigned long clkdiv; 507 508 dev_vdbg(mmc_dev(host->mmc), "Set clock to %uHz\n", ios->clock); 509 510 omap_hsmmc_stop_clock(host); 511 512 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 513 regval = regval & ~(CLKD_MASK | DTO_MASK); 514 clkdiv = calc_divisor(host, ios); 515 regval = regval | (clkdiv << 6) | (DTO << 16); 516 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 517 OMAP_HSMMC_WRITE(host->base, SYSCTL, 518 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 519 520 /* Wait till the ICS bit is set */ 521 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 522 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 523 && time_before(jiffies, timeout)) 524 cpu_relax(); 525 526 /* 527 * Enable High-Speed Support 528 * Pre-Requisites 529 * - Controller should support High-Speed-Enable Bit 530 * - Controller should not be using DDR Mode 531 * - Controller should advertise that it supports High Speed 532 * in capabilities register 533 * - MMC/SD clock coming out of controller > 25MHz 534 */ 535 if ((mmc_slot(host).features & HSMMC_HAS_HSPE_SUPPORT) && 536 (ios->timing != MMC_TIMING_UHS_DDR50) && 537 ((OMAP_HSMMC_READ(host->base, CAPA) & HSS) == HSS)) { 538 regval = OMAP_HSMMC_READ(host->base, HCTL); 539 if (clkdiv && (clk_get_rate(host->fclk)/clkdiv) > 25000000) 540 regval |= HSPE; 541 else 542 regval &= ~HSPE; 543 544 OMAP_HSMMC_WRITE(host->base, HCTL, regval); 545 } 546 547 omap_hsmmc_start_clock(host); 548 } 549 550 static void omap_hsmmc_set_bus_width(struct omap_hsmmc_host *host) 551 { 552 struct mmc_ios *ios = &host->mmc->ios; 553 u32 con; 554 555 con = OMAP_HSMMC_READ(host->base, CON); 556 if (ios->timing == MMC_TIMING_UHS_DDR50) 557 con |= DDR; /* configure in DDR mode */ 558 else 559 con &= ~DDR; 560 switch (ios->bus_width) { 561 case MMC_BUS_WIDTH_8: 562 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 563 break; 564 case MMC_BUS_WIDTH_4: 565 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 566 OMAP_HSMMC_WRITE(host->base, HCTL, 567 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 568 break; 569 case MMC_BUS_WIDTH_1: 570 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 571 OMAP_HSMMC_WRITE(host->base, HCTL, 572 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 573 break; 574 } 575 } 576 577 static void omap_hsmmc_set_bus_mode(struct omap_hsmmc_host *host) 578 { 579 struct mmc_ios *ios = &host->mmc->ios; 580 u32 con; 581 582 con = OMAP_HSMMC_READ(host->base, CON); 583 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 584 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 585 else 586 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 587 } 588 589 #ifdef CONFIG_PM 590 591 /* 592 * Restore the MMC host context, if it was lost as result of a 593 * power state change. 594 */ 595 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 596 { 597 struct mmc_ios *ios = &host->mmc->ios; 598 struct omap_mmc_platform_data *pdata = host->pdata; 599 int context_loss = 0; 600 u32 hctl, capa; 601 unsigned long timeout; 602 603 if (pdata->get_context_loss_count) { 604 context_loss = pdata->get_context_loss_count(host->dev); 605 if (context_loss < 0) 606 return 1; 607 } 608 609 dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 610 context_loss == host->context_loss ? "not " : ""); 611 if (host->context_loss == context_loss) 612 return 1; 613 614 if (!OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) 615 return 1; 616 617 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 618 if (host->power_mode != MMC_POWER_OFF && 619 (1 << ios->vdd) <= MMC_VDD_23_24) 620 hctl = SDVS18; 621 else 622 hctl = SDVS30; 623 capa = VS30 | VS18; 624 } else { 625 hctl = SDVS18; 626 capa = VS18; 627 } 628 629 OMAP_HSMMC_WRITE(host->base, HCTL, 630 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 631 632 OMAP_HSMMC_WRITE(host->base, CAPA, 633 OMAP_HSMMC_READ(host->base, CAPA) | capa); 634 635 OMAP_HSMMC_WRITE(host->base, HCTL, 636 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 637 638 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 639 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 640 && time_before(jiffies, timeout)) 641 ; 642 643 omap_hsmmc_disable_irq(host); 644 645 /* Do not initialize card-specific things if the power is off */ 646 if (host->power_mode == MMC_POWER_OFF) 647 goto out; 648 649 omap_hsmmc_set_bus_width(host); 650 651 omap_hsmmc_set_clock(host); 652 653 omap_hsmmc_set_bus_mode(host); 654 655 out: 656 host->context_loss = context_loss; 657 658 dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 659 return 0; 660 } 661 662 /* 663 * Save the MMC host context (store the number of power state changes so far). 664 */ 665 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 666 { 667 struct omap_mmc_platform_data *pdata = host->pdata; 668 int context_loss; 669 670 if (pdata->get_context_loss_count) { 671 context_loss = pdata->get_context_loss_count(host->dev); 672 if (context_loss < 0) 673 return; 674 host->context_loss = context_loss; 675 } 676 } 677 678 #else 679 680 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 681 { 682 return 0; 683 } 684 685 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 686 { 687 } 688 689 #endif 690 691 /* 692 * Send init stream sequence to card 693 * before sending IDLE command 694 */ 695 static void send_init_stream(struct omap_hsmmc_host *host) 696 { 697 int reg = 0; 698 unsigned long timeout; 699 700 if (host->protect_card) 701 return; 702 703 disable_irq(host->irq); 704 705 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 706 OMAP_HSMMC_WRITE(host->base, CON, 707 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 708 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 709 710 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 711 while ((reg != CC_EN) && time_before(jiffies, timeout)) 712 reg = OMAP_HSMMC_READ(host->base, STAT) & CC_EN; 713 714 OMAP_HSMMC_WRITE(host->base, CON, 715 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 716 717 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 718 OMAP_HSMMC_READ(host->base, STAT); 719 720 enable_irq(host->irq); 721 } 722 723 static inline 724 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 725 { 726 int r = 1; 727 728 if (mmc_slot(host).get_cover_state) 729 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 730 return r; 731 } 732 733 static ssize_t 734 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 735 char *buf) 736 { 737 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 738 struct omap_hsmmc_host *host = mmc_priv(mmc); 739 740 return sprintf(buf, "%s\n", 741 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 742 } 743 744 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 745 746 static ssize_t 747 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 748 char *buf) 749 { 750 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 751 struct omap_hsmmc_host *host = mmc_priv(mmc); 752 753 return sprintf(buf, "%s\n", mmc_slot(host).name); 754 } 755 756 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 757 758 /* 759 * Configure the response type and send the cmd. 760 */ 761 static void 762 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 763 struct mmc_data *data) 764 { 765 int cmdreg = 0, resptype = 0, cmdtype = 0; 766 767 dev_vdbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 768 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 769 host->cmd = cmd; 770 771 omap_hsmmc_enable_irq(host, cmd); 772 773 host->response_busy = 0; 774 if (cmd->flags & MMC_RSP_PRESENT) { 775 if (cmd->flags & MMC_RSP_136) 776 resptype = 1; 777 else if (cmd->flags & MMC_RSP_BUSY) { 778 resptype = 3; 779 host->response_busy = 1; 780 } else 781 resptype = 2; 782 } 783 784 /* 785 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 786 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 787 * a val of 0x3, rest 0x0. 788 */ 789 if (cmd == host->mrq->stop) 790 cmdtype = 0x3; 791 792 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 793 794 if (data) { 795 cmdreg |= DP_SELECT | MSBS | BCE; 796 if (data->flags & MMC_DATA_READ) 797 cmdreg |= DDIR; 798 else 799 cmdreg &= ~(DDIR); 800 } 801 802 if (host->use_dma) 803 cmdreg |= DMAE; 804 805 host->req_in_progress = 1; 806 807 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 808 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 809 } 810 811 static int 812 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 813 { 814 if (data->flags & MMC_DATA_WRITE) 815 return DMA_TO_DEVICE; 816 else 817 return DMA_FROM_DEVICE; 818 } 819 820 static struct dma_chan *omap_hsmmc_get_dma_chan(struct omap_hsmmc_host *host, 821 struct mmc_data *data) 822 { 823 return data->flags & MMC_DATA_WRITE ? host->tx_chan : host->rx_chan; 824 } 825 826 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 827 { 828 int dma_ch; 829 unsigned long flags; 830 831 spin_lock_irqsave(&host->irq_lock, flags); 832 host->req_in_progress = 0; 833 dma_ch = host->dma_ch; 834 spin_unlock_irqrestore(&host->irq_lock, flags); 835 836 omap_hsmmc_disable_irq(host); 837 /* Do not complete the request if DMA is still in progress */ 838 if (mrq->data && host->use_dma && dma_ch != -1) 839 return; 840 host->mrq = NULL; 841 mmc_request_done(host->mmc, mrq); 842 } 843 844 /* 845 * Notify the transfer complete to MMC core 846 */ 847 static void 848 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 849 { 850 if (!data) { 851 struct mmc_request *mrq = host->mrq; 852 853 /* TC before CC from CMD6 - don't know why, but it happens */ 854 if (host->cmd && host->cmd->opcode == 6 && 855 host->response_busy) { 856 host->response_busy = 0; 857 return; 858 } 859 860 omap_hsmmc_request_done(host, mrq); 861 return; 862 } 863 864 host->data = NULL; 865 866 if (!data->error) 867 data->bytes_xfered += data->blocks * (data->blksz); 868 else 869 data->bytes_xfered = 0; 870 871 if (!data->stop) { 872 omap_hsmmc_request_done(host, data->mrq); 873 return; 874 } 875 omap_hsmmc_start_command(host, data->stop, NULL); 876 } 877 878 /* 879 * Notify the core about command completion 880 */ 881 static void 882 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 883 { 884 host->cmd = NULL; 885 886 if (cmd->flags & MMC_RSP_PRESENT) { 887 if (cmd->flags & MMC_RSP_136) { 888 /* response type 2 */ 889 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 890 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 891 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 892 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 893 } else { 894 /* response types 1, 1b, 3, 4, 5, 6 */ 895 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 896 } 897 } 898 if ((host->data == NULL && !host->response_busy) || cmd->error) 899 omap_hsmmc_request_done(host, cmd->mrq); 900 } 901 902 /* 903 * DMA clean up for command errors 904 */ 905 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 906 { 907 int dma_ch; 908 unsigned long flags; 909 910 host->data->error = errno; 911 912 spin_lock_irqsave(&host->irq_lock, flags); 913 dma_ch = host->dma_ch; 914 host->dma_ch = -1; 915 spin_unlock_irqrestore(&host->irq_lock, flags); 916 917 if (host->use_dma && dma_ch != -1) { 918 struct dma_chan *chan = omap_hsmmc_get_dma_chan(host, host->data); 919 920 dmaengine_terminate_all(chan); 921 dma_unmap_sg(chan->device->dev, 922 host->data->sg, host->data->sg_len, 923 omap_hsmmc_get_dma_dir(host, host->data)); 924 925 host->data->host_cookie = 0; 926 } 927 host->data = NULL; 928 } 929 930 /* 931 * Readable error output 932 */ 933 #ifdef CONFIG_MMC_DEBUG 934 static void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, u32 status) 935 { 936 /* --- means reserved bit without definition at documentation */ 937 static const char *omap_hsmmc_status_bits[] = { 938 "CC" , "TC" , "BGE", "---", "BWR" , "BRR" , "---" , "---" , 939 "CIRQ", "OBI" , "---", "---", "---" , "---" , "---" , "ERRI", 940 "CTO" , "CCRC", "CEB", "CIE", "DTO" , "DCRC", "DEB" , "---" , 941 "ACE" , "---" , "---", "---", "CERR", "BADA", "---" , "---" 942 }; 943 char res[256]; 944 char *buf = res; 945 int len, i; 946 947 len = sprintf(buf, "MMC IRQ 0x%x :", status); 948 buf += len; 949 950 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 951 if (status & (1 << i)) { 952 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 953 buf += len; 954 } 955 956 dev_vdbg(mmc_dev(host->mmc), "%s\n", res); 957 } 958 #else 959 static inline void omap_hsmmc_dbg_report_irq(struct omap_hsmmc_host *host, 960 u32 status) 961 { 962 } 963 #endif /* CONFIG_MMC_DEBUG */ 964 965 /* 966 * MMC controller internal state machines reset 967 * 968 * Used to reset command or data internal state machines, using respectively 969 * SRC or SRD bit of SYSCTL register 970 * Can be called from interrupt context 971 */ 972 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 973 unsigned long bit) 974 { 975 unsigned long i = 0; 976 unsigned long limit = (loops_per_jiffy * 977 msecs_to_jiffies(MMC_TIMEOUT_MS)); 978 979 OMAP_HSMMC_WRITE(host->base, SYSCTL, 980 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 981 982 /* 983 * OMAP4 ES2 and greater has an updated reset logic. 984 * Monitor a 0->1 transition first 985 */ 986 if (mmc_slot(host).features & HSMMC_HAS_UPDATED_RESET) { 987 while ((!(OMAP_HSMMC_READ(host->base, SYSCTL) & bit)) 988 && (i++ < limit)) 989 cpu_relax(); 990 } 991 i = 0; 992 993 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 994 (i++ < limit)) 995 cpu_relax(); 996 997 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 998 dev_err(mmc_dev(host->mmc), 999 "Timeout waiting on controller reset in %s\n", 1000 __func__); 1001 } 1002 1003 static void hsmmc_command_incomplete(struct omap_hsmmc_host *host, 1004 int err, int end_cmd) 1005 { 1006 if (end_cmd) { 1007 omap_hsmmc_reset_controller_fsm(host, SRC); 1008 if (host->cmd) 1009 host->cmd->error = err; 1010 } 1011 1012 if (host->data) { 1013 omap_hsmmc_reset_controller_fsm(host, SRD); 1014 omap_hsmmc_dma_cleanup(host, err); 1015 } else if (host->mrq && host->mrq->cmd) 1016 host->mrq->cmd->error = err; 1017 } 1018 1019 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 1020 { 1021 struct mmc_data *data; 1022 int end_cmd = 0, end_trans = 0; 1023 1024 data = host->data; 1025 dev_vdbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1026 1027 if (status & ERR_EN) { 1028 omap_hsmmc_dbg_report_irq(host, status); 1029 1030 if (status & (CTO_EN | CCRC_EN)) 1031 end_cmd = 1; 1032 if (status & (CTO_EN | DTO_EN)) 1033 hsmmc_command_incomplete(host, -ETIMEDOUT, end_cmd); 1034 else if (status & (CCRC_EN | DCRC_EN)) 1035 hsmmc_command_incomplete(host, -EILSEQ, end_cmd); 1036 1037 if (host->data || host->response_busy) { 1038 end_trans = !end_cmd; 1039 host->response_busy = 0; 1040 } 1041 } 1042 1043 if (end_cmd || ((status & CC_EN) && host->cmd)) 1044 omap_hsmmc_cmd_done(host, host->cmd); 1045 if ((end_trans || (status & TC_EN)) && host->mrq) 1046 omap_hsmmc_xfer_done(host, data); 1047 } 1048 1049 /* 1050 * MMC controller IRQ handler 1051 */ 1052 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1053 { 1054 struct omap_hsmmc_host *host = dev_id; 1055 int status; 1056 1057 status = OMAP_HSMMC_READ(host->base, STAT); 1058 while (status & INT_EN_MASK && host->req_in_progress) { 1059 omap_hsmmc_do_irq(host, status); 1060 1061 /* Flush posted write */ 1062 OMAP_HSMMC_WRITE(host->base, STAT, status); 1063 status = OMAP_HSMMC_READ(host->base, STAT); 1064 } 1065 1066 return IRQ_HANDLED; 1067 } 1068 1069 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1070 { 1071 unsigned long i; 1072 1073 OMAP_HSMMC_WRITE(host->base, HCTL, 1074 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1075 for (i = 0; i < loops_per_jiffy; i++) { 1076 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1077 break; 1078 cpu_relax(); 1079 } 1080 } 1081 1082 /* 1083 * Switch MMC interface voltage ... only relevant for MMC1. 1084 * 1085 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1086 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1087 * Some chips, like eMMC ones, use internal transceivers. 1088 */ 1089 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1090 { 1091 u32 reg_val = 0; 1092 int ret; 1093 1094 /* Disable the clocks */ 1095 pm_runtime_put_sync(host->dev); 1096 if (host->dbclk) 1097 clk_disable_unprepare(host->dbclk); 1098 1099 /* Turn the power off */ 1100 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1101 1102 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1103 if (!ret) 1104 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1105 vdd); 1106 pm_runtime_get_sync(host->dev); 1107 if (host->dbclk) 1108 clk_prepare_enable(host->dbclk); 1109 1110 if (ret != 0) 1111 goto err; 1112 1113 OMAP_HSMMC_WRITE(host->base, HCTL, 1114 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1115 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1116 1117 /* 1118 * If a MMC dual voltage card is detected, the set_ios fn calls 1119 * this fn with VDD bit set for 1.8V. Upon card removal from the 1120 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1121 * 1122 * Cope with a bit of slop in the range ... per data sheets: 1123 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1124 * but recommended values are 1.71V to 1.89V 1125 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1126 * but recommended values are 2.7V to 3.3V 1127 * 1128 * Board setup code shouldn't permit anything very out-of-range. 1129 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1130 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1131 */ 1132 if ((1 << vdd) <= MMC_VDD_23_24) 1133 reg_val |= SDVS18; 1134 else 1135 reg_val |= SDVS30; 1136 1137 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1138 set_sd_bus_power(host); 1139 1140 return 0; 1141 err: 1142 dev_err(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1143 return ret; 1144 } 1145 1146 /* Protect the card while the cover is open */ 1147 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1148 { 1149 if (!mmc_slot(host).get_cover_state) 1150 return; 1151 1152 host->reqs_blocked = 0; 1153 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1154 if (host->protect_card) { 1155 dev_info(host->dev, "%s: cover is closed, " 1156 "card is now accessible\n", 1157 mmc_hostname(host->mmc)); 1158 host->protect_card = 0; 1159 } 1160 } else { 1161 if (!host->protect_card) { 1162 dev_info(host->dev, "%s: cover is open, " 1163 "card is now inaccessible\n", 1164 mmc_hostname(host->mmc)); 1165 host->protect_card = 1; 1166 } 1167 } 1168 } 1169 1170 /* 1171 * irq handler to notify the core about card insertion/removal 1172 */ 1173 static irqreturn_t omap_hsmmc_detect(int irq, void *dev_id) 1174 { 1175 struct omap_hsmmc_host *host = dev_id; 1176 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1177 int carddetect; 1178 1179 if (host->suspended) 1180 return IRQ_HANDLED; 1181 1182 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1183 1184 if (slot->card_detect) 1185 carddetect = slot->card_detect(host->dev, host->slot_id); 1186 else { 1187 omap_hsmmc_protect_card(host); 1188 carddetect = -ENOSYS; 1189 } 1190 1191 if (carddetect) 1192 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1193 else 1194 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1195 return IRQ_HANDLED; 1196 } 1197 1198 static void omap_hsmmc_dma_callback(void *param) 1199 { 1200 struct omap_hsmmc_host *host = param; 1201 struct dma_chan *chan; 1202 struct mmc_data *data; 1203 int req_in_progress; 1204 1205 spin_lock_irq(&host->irq_lock); 1206 if (host->dma_ch < 0) { 1207 spin_unlock_irq(&host->irq_lock); 1208 return; 1209 } 1210 1211 data = host->mrq->data; 1212 chan = omap_hsmmc_get_dma_chan(host, data); 1213 if (!data->host_cookie) 1214 dma_unmap_sg(chan->device->dev, 1215 data->sg, data->sg_len, 1216 omap_hsmmc_get_dma_dir(host, data)); 1217 1218 req_in_progress = host->req_in_progress; 1219 host->dma_ch = -1; 1220 spin_unlock_irq(&host->irq_lock); 1221 1222 /* If DMA has finished after TC, complete the request */ 1223 if (!req_in_progress) { 1224 struct mmc_request *mrq = host->mrq; 1225 1226 host->mrq = NULL; 1227 mmc_request_done(host->mmc, mrq); 1228 } 1229 } 1230 1231 static int omap_hsmmc_pre_dma_transfer(struct omap_hsmmc_host *host, 1232 struct mmc_data *data, 1233 struct omap_hsmmc_next *next, 1234 struct dma_chan *chan) 1235 { 1236 int dma_len; 1237 1238 if (!next && data->host_cookie && 1239 data->host_cookie != host->next_data.cookie) { 1240 dev_warn(host->dev, "[%s] invalid cookie: data->host_cookie %d" 1241 " host->next_data.cookie %d\n", 1242 __func__, data->host_cookie, host->next_data.cookie); 1243 data->host_cookie = 0; 1244 } 1245 1246 /* Check if next job is already prepared */ 1247 if (next || 1248 (!next && data->host_cookie != host->next_data.cookie)) { 1249 dma_len = dma_map_sg(chan->device->dev, data->sg, data->sg_len, 1250 omap_hsmmc_get_dma_dir(host, data)); 1251 1252 } else { 1253 dma_len = host->next_data.dma_len; 1254 host->next_data.dma_len = 0; 1255 } 1256 1257 1258 if (dma_len == 0) 1259 return -EINVAL; 1260 1261 if (next) { 1262 next->dma_len = dma_len; 1263 data->host_cookie = ++next->cookie < 0 ? 1 : next->cookie; 1264 } else 1265 host->dma_len = dma_len; 1266 1267 return 0; 1268 } 1269 1270 /* 1271 * Routine to configure and start DMA for the MMC card 1272 */ 1273 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 1274 struct mmc_request *req) 1275 { 1276 struct dma_slave_config cfg; 1277 struct dma_async_tx_descriptor *tx; 1278 int ret = 0, i; 1279 struct mmc_data *data = req->data; 1280 struct dma_chan *chan; 1281 1282 /* Sanity check: all the SG entries must be aligned by block size. */ 1283 for (i = 0; i < data->sg_len; i++) { 1284 struct scatterlist *sgl; 1285 1286 sgl = data->sg + i; 1287 if (sgl->length % data->blksz) 1288 return -EINVAL; 1289 } 1290 if ((data->blksz % 4) != 0) 1291 /* REVISIT: The MMC buffer increments only when MSB is written. 1292 * Return error for blksz which is non multiple of four. 1293 */ 1294 return -EINVAL; 1295 1296 BUG_ON(host->dma_ch != -1); 1297 1298 chan = omap_hsmmc_get_dma_chan(host, data); 1299 1300 cfg.src_addr = host->mapbase + OMAP_HSMMC_DATA; 1301 cfg.dst_addr = host->mapbase + OMAP_HSMMC_DATA; 1302 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1303 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1304 cfg.src_maxburst = data->blksz / 4; 1305 cfg.dst_maxburst = data->blksz / 4; 1306 1307 ret = dmaengine_slave_config(chan, &cfg); 1308 if (ret) 1309 return ret; 1310 1311 ret = omap_hsmmc_pre_dma_transfer(host, data, NULL, chan); 1312 if (ret) 1313 return ret; 1314 1315 tx = dmaengine_prep_slave_sg(chan, data->sg, data->sg_len, 1316 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1317 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1318 if (!tx) { 1319 dev_err(mmc_dev(host->mmc), "prep_slave_sg() failed\n"); 1320 /* FIXME: cleanup */ 1321 return -1; 1322 } 1323 1324 tx->callback = omap_hsmmc_dma_callback; 1325 tx->callback_param = host; 1326 1327 /* Does not fail */ 1328 dmaengine_submit(tx); 1329 1330 host->dma_ch = 1; 1331 1332 dma_async_issue_pending(chan); 1333 1334 return 0; 1335 } 1336 1337 static void set_data_timeout(struct omap_hsmmc_host *host, 1338 unsigned int timeout_ns, 1339 unsigned int timeout_clks) 1340 { 1341 unsigned int timeout, cycle_ns; 1342 uint32_t reg, clkd, dto = 0; 1343 1344 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1345 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1346 if (clkd == 0) 1347 clkd = 1; 1348 1349 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1350 timeout = timeout_ns / cycle_ns; 1351 timeout += timeout_clks; 1352 if (timeout) { 1353 while ((timeout & 0x80000000) == 0) { 1354 dto += 1; 1355 timeout <<= 1; 1356 } 1357 dto = 31 - dto; 1358 timeout <<= 1; 1359 if (timeout && dto) 1360 dto += 1; 1361 if (dto >= 13) 1362 dto -= 13; 1363 else 1364 dto = 0; 1365 if (dto > 14) 1366 dto = 14; 1367 } 1368 1369 reg &= ~DTO_MASK; 1370 reg |= dto << DTO_SHIFT; 1371 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1372 } 1373 1374 /* 1375 * Configure block length for MMC/SD cards and initiate the transfer. 1376 */ 1377 static int 1378 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1379 { 1380 int ret; 1381 host->data = req->data; 1382 1383 if (req->data == NULL) { 1384 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1385 /* 1386 * Set an arbitrary 100ms data timeout for commands with 1387 * busy signal. 1388 */ 1389 if (req->cmd->flags & MMC_RSP_BUSY) 1390 set_data_timeout(host, 100000000U, 0); 1391 return 0; 1392 } 1393 1394 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1395 | (req->data->blocks << 16)); 1396 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1397 1398 if (host->use_dma) { 1399 ret = omap_hsmmc_start_dma_transfer(host, req); 1400 if (ret != 0) { 1401 dev_err(mmc_dev(host->mmc), "MMC start dma failure\n"); 1402 return ret; 1403 } 1404 } 1405 return 0; 1406 } 1407 1408 static void omap_hsmmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1409 int err) 1410 { 1411 struct omap_hsmmc_host *host = mmc_priv(mmc); 1412 struct mmc_data *data = mrq->data; 1413 1414 if (host->use_dma && data->host_cookie) { 1415 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, data); 1416 1417 dma_unmap_sg(c->device->dev, data->sg, data->sg_len, 1418 omap_hsmmc_get_dma_dir(host, data)); 1419 data->host_cookie = 0; 1420 } 1421 } 1422 1423 static void omap_hsmmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, 1424 bool is_first_req) 1425 { 1426 struct omap_hsmmc_host *host = mmc_priv(mmc); 1427 1428 if (mrq->data->host_cookie) { 1429 mrq->data->host_cookie = 0; 1430 return ; 1431 } 1432 1433 if (host->use_dma) { 1434 struct dma_chan *c = omap_hsmmc_get_dma_chan(host, mrq->data); 1435 1436 if (omap_hsmmc_pre_dma_transfer(host, mrq->data, 1437 &host->next_data, c)) 1438 mrq->data->host_cookie = 0; 1439 } 1440 } 1441 1442 /* 1443 * Request function. for read/write operation 1444 */ 1445 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1446 { 1447 struct omap_hsmmc_host *host = mmc_priv(mmc); 1448 int err; 1449 1450 BUG_ON(host->req_in_progress); 1451 BUG_ON(host->dma_ch != -1); 1452 if (host->protect_card) { 1453 if (host->reqs_blocked < 3) { 1454 /* 1455 * Ensure the controller is left in a consistent 1456 * state by resetting the command and data state 1457 * machines. 1458 */ 1459 omap_hsmmc_reset_controller_fsm(host, SRD); 1460 omap_hsmmc_reset_controller_fsm(host, SRC); 1461 host->reqs_blocked += 1; 1462 } 1463 req->cmd->error = -EBADF; 1464 if (req->data) 1465 req->data->error = -EBADF; 1466 req->cmd->retries = 0; 1467 mmc_request_done(mmc, req); 1468 return; 1469 } else if (host->reqs_blocked) 1470 host->reqs_blocked = 0; 1471 WARN_ON(host->mrq != NULL); 1472 host->mrq = req; 1473 err = omap_hsmmc_prepare_data(host, req); 1474 if (err) { 1475 req->cmd->error = err; 1476 if (req->data) 1477 req->data->error = err; 1478 host->mrq = NULL; 1479 mmc_request_done(mmc, req); 1480 return; 1481 } 1482 1483 omap_hsmmc_start_command(host, req->cmd, req->data); 1484 } 1485 1486 /* Routine to configure clock values. Exposed API to core */ 1487 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1488 { 1489 struct omap_hsmmc_host *host = mmc_priv(mmc); 1490 int do_send_init_stream = 0; 1491 1492 pm_runtime_get_sync(host->dev); 1493 1494 if (ios->power_mode != host->power_mode) { 1495 switch (ios->power_mode) { 1496 case MMC_POWER_OFF: 1497 mmc_slot(host).set_power(host->dev, host->slot_id, 1498 0, 0); 1499 break; 1500 case MMC_POWER_UP: 1501 mmc_slot(host).set_power(host->dev, host->slot_id, 1502 1, ios->vdd); 1503 break; 1504 case MMC_POWER_ON: 1505 do_send_init_stream = 1; 1506 break; 1507 } 1508 host->power_mode = ios->power_mode; 1509 } 1510 1511 /* FIXME: set registers based only on changes to ios */ 1512 1513 omap_hsmmc_set_bus_width(host); 1514 1515 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1516 /* Only MMC1 can interface at 3V without some flavor 1517 * of external transceiver; but they all handle 1.8V. 1518 */ 1519 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1520 (ios->vdd == DUAL_VOLT_OCR_BIT) && 1521 /* 1522 * With pbias cell programming missing, this 1523 * can't be allowed when booting with device 1524 * tree. 1525 */ 1526 !host->dev->of_node) { 1527 /* 1528 * The mmc_select_voltage fn of the core does 1529 * not seem to set the power_mode to 1530 * MMC_POWER_UP upon recalculating the voltage. 1531 * vdd 1.8v. 1532 */ 1533 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1534 dev_dbg(mmc_dev(host->mmc), 1535 "Switch operation failed\n"); 1536 } 1537 } 1538 1539 omap_hsmmc_set_clock(host); 1540 1541 if (do_send_init_stream) 1542 send_init_stream(host); 1543 1544 omap_hsmmc_set_bus_mode(host); 1545 1546 pm_runtime_put_autosuspend(host->dev); 1547 } 1548 1549 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1550 { 1551 struct omap_hsmmc_host *host = mmc_priv(mmc); 1552 1553 if (!mmc_slot(host).card_detect) 1554 return -ENOSYS; 1555 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1556 } 1557 1558 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1559 { 1560 struct omap_hsmmc_host *host = mmc_priv(mmc); 1561 1562 if (!mmc_slot(host).get_ro) 1563 return -ENOSYS; 1564 return mmc_slot(host).get_ro(host->dev, 0); 1565 } 1566 1567 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1568 { 1569 struct omap_hsmmc_host *host = mmc_priv(mmc); 1570 1571 if (mmc_slot(host).init_card) 1572 mmc_slot(host).init_card(card); 1573 } 1574 1575 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1576 { 1577 u32 hctl, capa, value; 1578 1579 /* Only MMC1 supports 3.0V */ 1580 if (host->pdata->controller_flags & OMAP_HSMMC_SUPPORTS_DUAL_VOLT) { 1581 hctl = SDVS30; 1582 capa = VS30 | VS18; 1583 } else { 1584 hctl = SDVS18; 1585 capa = VS18; 1586 } 1587 1588 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1589 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1590 1591 value = OMAP_HSMMC_READ(host->base, CAPA); 1592 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1593 1594 /* Set SD bus power bit */ 1595 set_sd_bus_power(host); 1596 } 1597 1598 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1599 { 1600 struct omap_hsmmc_host *host = mmc_priv(mmc); 1601 1602 pm_runtime_get_sync(host->dev); 1603 1604 return 0; 1605 } 1606 1607 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc) 1608 { 1609 struct omap_hsmmc_host *host = mmc_priv(mmc); 1610 1611 pm_runtime_mark_last_busy(host->dev); 1612 pm_runtime_put_autosuspend(host->dev); 1613 1614 return 0; 1615 } 1616 1617 static const struct mmc_host_ops omap_hsmmc_ops = { 1618 .enable = omap_hsmmc_enable_fclk, 1619 .disable = omap_hsmmc_disable_fclk, 1620 .post_req = omap_hsmmc_post_req, 1621 .pre_req = omap_hsmmc_pre_req, 1622 .request = omap_hsmmc_request, 1623 .set_ios = omap_hsmmc_set_ios, 1624 .get_cd = omap_hsmmc_get_cd, 1625 .get_ro = omap_hsmmc_get_ro, 1626 .init_card = omap_hsmmc_init_card, 1627 /* NYET -- enable_sdio_irq */ 1628 }; 1629 1630 #ifdef CONFIG_DEBUG_FS 1631 1632 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1633 { 1634 struct mmc_host *mmc = s->private; 1635 struct omap_hsmmc_host *host = mmc_priv(mmc); 1636 int context_loss = 0; 1637 1638 if (host->pdata->get_context_loss_count) 1639 context_loss = host->pdata->get_context_loss_count(host->dev); 1640 1641 seq_printf(s, "mmc%d:\n ctx_loss:\t%d:%d\n\nregs:\n", 1642 mmc->index, host->context_loss, context_loss); 1643 1644 if (host->suspended) { 1645 seq_printf(s, "host suspended, can't read registers\n"); 1646 return 0; 1647 } 1648 1649 pm_runtime_get_sync(host->dev); 1650 1651 seq_printf(s, "CON:\t\t0x%08x\n", 1652 OMAP_HSMMC_READ(host->base, CON)); 1653 seq_printf(s, "HCTL:\t\t0x%08x\n", 1654 OMAP_HSMMC_READ(host->base, HCTL)); 1655 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1656 OMAP_HSMMC_READ(host->base, SYSCTL)); 1657 seq_printf(s, "IE:\t\t0x%08x\n", 1658 OMAP_HSMMC_READ(host->base, IE)); 1659 seq_printf(s, "ISE:\t\t0x%08x\n", 1660 OMAP_HSMMC_READ(host->base, ISE)); 1661 seq_printf(s, "CAPA:\t\t0x%08x\n", 1662 OMAP_HSMMC_READ(host->base, CAPA)); 1663 1664 pm_runtime_mark_last_busy(host->dev); 1665 pm_runtime_put_autosuspend(host->dev); 1666 1667 return 0; 1668 } 1669 1670 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1671 { 1672 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1673 } 1674 1675 static const struct file_operations mmc_regs_fops = { 1676 .open = omap_hsmmc_regs_open, 1677 .read = seq_read, 1678 .llseek = seq_lseek, 1679 .release = single_release, 1680 }; 1681 1682 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1683 { 1684 if (mmc->debugfs_root) 1685 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1686 mmc, &mmc_regs_fops); 1687 } 1688 1689 #else 1690 1691 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1692 { 1693 } 1694 1695 #endif 1696 1697 #ifdef CONFIG_OF 1698 static u16 omap4_reg_offset = 0x100; 1699 1700 static const struct of_device_id omap_mmc_of_match[] = { 1701 { 1702 .compatible = "ti,omap2-hsmmc", 1703 }, 1704 { 1705 .compatible = "ti,omap3-hsmmc", 1706 }, 1707 { 1708 .compatible = "ti,omap4-hsmmc", 1709 .data = &omap4_reg_offset, 1710 }, 1711 {}, 1712 }; 1713 MODULE_DEVICE_TABLE(of, omap_mmc_of_match); 1714 1715 static struct omap_mmc_platform_data *of_get_hsmmc_pdata(struct device *dev) 1716 { 1717 struct omap_mmc_platform_data *pdata; 1718 struct device_node *np = dev->of_node; 1719 u32 bus_width, max_freq; 1720 1721 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL); 1722 if (!pdata) 1723 return NULL; /* out of memory */ 1724 1725 if (of_find_property(np, "ti,dual-volt", NULL)) 1726 pdata->controller_flags |= OMAP_HSMMC_SUPPORTS_DUAL_VOLT; 1727 1728 /* This driver only supports 1 slot */ 1729 pdata->nr_slots = 1; 1730 pdata->slots[0].switch_pin = of_get_named_gpio(np, "cd-gpios", 0); 1731 pdata->slots[0].gpio_wp = of_get_named_gpio(np, "wp-gpios", 0); 1732 1733 if (of_find_property(np, "ti,non-removable", NULL)) { 1734 pdata->slots[0].nonremovable = true; 1735 pdata->slots[0].no_regulator_off_init = true; 1736 } 1737 of_property_read_u32(np, "bus-width", &bus_width); 1738 if (bus_width == 4) 1739 pdata->slots[0].caps |= MMC_CAP_4_BIT_DATA; 1740 else if (bus_width == 8) 1741 pdata->slots[0].caps |= MMC_CAP_8_BIT_DATA; 1742 1743 if (of_find_property(np, "ti,needs-special-reset", NULL)) 1744 pdata->slots[0].features |= HSMMC_HAS_UPDATED_RESET; 1745 1746 if (!of_property_read_u32(np, "max-frequency", &max_freq)) 1747 pdata->max_freq = max_freq; 1748 1749 if (of_find_property(np, "ti,needs-special-hs-handling", NULL)) 1750 pdata->slots[0].features |= HSMMC_HAS_HSPE_SUPPORT; 1751 1752 return pdata; 1753 } 1754 #else 1755 static inline struct omap_mmc_platform_data 1756 *of_get_hsmmc_pdata(struct device *dev) 1757 { 1758 return NULL; 1759 } 1760 #endif 1761 1762 static int omap_hsmmc_probe(struct platform_device *pdev) 1763 { 1764 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1765 struct mmc_host *mmc; 1766 struct omap_hsmmc_host *host = NULL; 1767 struct resource *res; 1768 int ret, irq; 1769 const struct of_device_id *match; 1770 dma_cap_mask_t mask; 1771 unsigned tx_req, rx_req; 1772 struct pinctrl *pinctrl; 1773 1774 match = of_match_device(of_match_ptr(omap_mmc_of_match), &pdev->dev); 1775 if (match) { 1776 pdata = of_get_hsmmc_pdata(&pdev->dev); 1777 if (match->data) { 1778 const u16 *offsetp = match->data; 1779 pdata->reg_offset = *offsetp; 1780 } 1781 } 1782 1783 if (pdata == NULL) { 1784 dev_err(&pdev->dev, "Platform Data is missing\n"); 1785 return -ENXIO; 1786 } 1787 1788 if (pdata->nr_slots == 0) { 1789 dev_err(&pdev->dev, "No Slots\n"); 1790 return -ENXIO; 1791 } 1792 1793 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1794 irq = platform_get_irq(pdev, 0); 1795 if (res == NULL || irq < 0) 1796 return -ENXIO; 1797 1798 res = request_mem_region(res->start, resource_size(res), pdev->name); 1799 if (res == NULL) 1800 return -EBUSY; 1801 1802 ret = omap_hsmmc_gpio_init(pdata); 1803 if (ret) 1804 goto err; 1805 1806 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 1807 if (!mmc) { 1808 ret = -ENOMEM; 1809 goto err_alloc; 1810 } 1811 1812 host = mmc_priv(mmc); 1813 host->mmc = mmc; 1814 host->pdata = pdata; 1815 host->dev = &pdev->dev; 1816 host->use_dma = 1; 1817 host->dma_ch = -1; 1818 host->irq = irq; 1819 host->slot_id = 0; 1820 host->mapbase = res->start + pdata->reg_offset; 1821 host->base = ioremap(host->mapbase, SZ_4K); 1822 host->power_mode = MMC_POWER_OFF; 1823 host->next_data.cookie = 1; 1824 1825 platform_set_drvdata(pdev, host); 1826 1827 mmc->ops = &omap_hsmmc_ops; 1828 1829 /* 1830 * If regulator_disable can only put vcc_aux to sleep then there is 1831 * no off state. 1832 */ 1833 if (mmc_slot(host).vcc_aux_disable_is_sleep) 1834 mmc_slot(host).no_off = 1; 1835 1836 mmc->f_min = OMAP_MMC_MIN_CLOCK; 1837 1838 if (pdata->max_freq > 0) 1839 mmc->f_max = pdata->max_freq; 1840 else 1841 mmc->f_max = OMAP_MMC_MAX_CLOCK; 1842 1843 spin_lock_init(&host->irq_lock); 1844 1845 host->fclk = clk_get(&pdev->dev, "fck"); 1846 if (IS_ERR(host->fclk)) { 1847 ret = PTR_ERR(host->fclk); 1848 host->fclk = NULL; 1849 goto err1; 1850 } 1851 1852 if (host->pdata->controller_flags & OMAP_HSMMC_BROKEN_MULTIBLOCK_READ) { 1853 dev_info(&pdev->dev, "multiblock reads disabled due to 35xx erratum 2.1.1.128; MMC read performance may suffer\n"); 1854 mmc->caps2 |= MMC_CAP2_NO_MULTI_READ; 1855 } 1856 1857 pm_runtime_enable(host->dev); 1858 pm_runtime_get_sync(host->dev); 1859 pm_runtime_set_autosuspend_delay(host->dev, MMC_AUTOSUSPEND_DELAY); 1860 pm_runtime_use_autosuspend(host->dev); 1861 1862 omap_hsmmc_context_save(host); 1863 1864 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 1865 /* 1866 * MMC can still work without debounce clock. 1867 */ 1868 if (IS_ERR(host->dbclk)) { 1869 host->dbclk = NULL; 1870 } else if (clk_prepare_enable(host->dbclk) != 0) { 1871 dev_warn(mmc_dev(host->mmc), "Failed to enable debounce clk\n"); 1872 clk_put(host->dbclk); 1873 host->dbclk = NULL; 1874 } 1875 1876 /* Since we do only SG emulation, we can have as many segs 1877 * as we want. */ 1878 mmc->max_segs = 1024; 1879 1880 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 1881 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 1882 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1883 mmc->max_seg_size = mmc->max_req_size; 1884 1885 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1886 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 1887 1888 mmc->caps |= mmc_slot(host).caps; 1889 if (mmc->caps & MMC_CAP_8_BIT_DATA) 1890 mmc->caps |= MMC_CAP_4_BIT_DATA; 1891 1892 if (mmc_slot(host).nonremovable) 1893 mmc->caps |= MMC_CAP_NONREMOVABLE; 1894 1895 mmc->pm_caps = mmc_slot(host).pm_caps; 1896 1897 omap_hsmmc_conf_bus_power(host); 1898 1899 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx"); 1900 if (!res) { 1901 dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n"); 1902 ret = -ENXIO; 1903 goto err_irq; 1904 } 1905 tx_req = res->start; 1906 1907 res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx"); 1908 if (!res) { 1909 dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n"); 1910 ret = -ENXIO; 1911 goto err_irq; 1912 } 1913 rx_req = res->start; 1914 1915 dma_cap_zero(mask); 1916 dma_cap_set(DMA_SLAVE, mask); 1917 1918 host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req); 1919 if (!host->rx_chan) { 1920 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req); 1921 ret = -ENXIO; 1922 goto err_irq; 1923 } 1924 1925 host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req); 1926 if (!host->tx_chan) { 1927 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req); 1928 ret = -ENXIO; 1929 goto err_irq; 1930 } 1931 1932 /* Request IRQ for MMC operations */ 1933 ret = request_irq(host->irq, omap_hsmmc_irq, 0, 1934 mmc_hostname(mmc), host); 1935 if (ret) { 1936 dev_err(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 1937 goto err_irq; 1938 } 1939 1940 if (pdata->init != NULL) { 1941 if (pdata->init(&pdev->dev) != 0) { 1942 dev_err(mmc_dev(host->mmc), 1943 "Unable to configure MMC IRQs\n"); 1944 goto err_irq_cd_init; 1945 } 1946 } 1947 1948 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 1949 ret = omap_hsmmc_reg_get(host); 1950 if (ret) 1951 goto err_reg; 1952 host->use_reg = 1; 1953 } 1954 1955 mmc->ocr_avail = mmc_slot(host).ocr_mask; 1956 1957 /* Request IRQ for card detect */ 1958 if ((mmc_slot(host).card_detect_irq)) { 1959 ret = request_threaded_irq(mmc_slot(host).card_detect_irq, 1960 NULL, 1961 omap_hsmmc_detect, 1962 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 1963 mmc_hostname(mmc), host); 1964 if (ret) { 1965 dev_err(mmc_dev(host->mmc), 1966 "Unable to grab MMC CD IRQ\n"); 1967 goto err_irq_cd; 1968 } 1969 pdata->suspend = omap_hsmmc_suspend_cdirq; 1970 pdata->resume = omap_hsmmc_resume_cdirq; 1971 } 1972 1973 omap_hsmmc_disable_irq(host); 1974 1975 pinctrl = devm_pinctrl_get_select_default(&pdev->dev); 1976 if (IS_ERR(pinctrl)) 1977 dev_warn(&pdev->dev, 1978 "pins are not configured from the driver\n"); 1979 1980 omap_hsmmc_protect_card(host); 1981 1982 mmc_add_host(mmc); 1983 1984 if (mmc_slot(host).name != NULL) { 1985 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 1986 if (ret < 0) 1987 goto err_slot_name; 1988 } 1989 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 1990 ret = device_create_file(&mmc->class_dev, 1991 &dev_attr_cover_switch); 1992 if (ret < 0) 1993 goto err_slot_name; 1994 } 1995 1996 omap_hsmmc_debugfs(mmc); 1997 pm_runtime_mark_last_busy(host->dev); 1998 pm_runtime_put_autosuspend(host->dev); 1999 2000 return 0; 2001 2002 err_slot_name: 2003 mmc_remove_host(mmc); 2004 free_irq(mmc_slot(host).card_detect_irq, host); 2005 err_irq_cd: 2006 if (host->use_reg) 2007 omap_hsmmc_reg_put(host); 2008 err_reg: 2009 if (host->pdata->cleanup) 2010 host->pdata->cleanup(&pdev->dev); 2011 err_irq_cd_init: 2012 free_irq(host->irq, host); 2013 err_irq: 2014 if (host->tx_chan) 2015 dma_release_channel(host->tx_chan); 2016 if (host->rx_chan) 2017 dma_release_channel(host->rx_chan); 2018 pm_runtime_put_sync(host->dev); 2019 pm_runtime_disable(host->dev); 2020 clk_put(host->fclk); 2021 if (host->dbclk) { 2022 clk_disable_unprepare(host->dbclk); 2023 clk_put(host->dbclk); 2024 } 2025 err1: 2026 iounmap(host->base); 2027 platform_set_drvdata(pdev, NULL); 2028 mmc_free_host(mmc); 2029 err_alloc: 2030 omap_hsmmc_gpio_free(pdata); 2031 err: 2032 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2033 if (res) 2034 release_mem_region(res->start, resource_size(res)); 2035 return ret; 2036 } 2037 2038 static int omap_hsmmc_remove(struct platform_device *pdev) 2039 { 2040 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2041 struct resource *res; 2042 2043 pm_runtime_get_sync(host->dev); 2044 mmc_remove_host(host->mmc); 2045 if (host->use_reg) 2046 omap_hsmmc_reg_put(host); 2047 if (host->pdata->cleanup) 2048 host->pdata->cleanup(&pdev->dev); 2049 free_irq(host->irq, host); 2050 if (mmc_slot(host).card_detect_irq) 2051 free_irq(mmc_slot(host).card_detect_irq, host); 2052 2053 if (host->tx_chan) 2054 dma_release_channel(host->tx_chan); 2055 if (host->rx_chan) 2056 dma_release_channel(host->rx_chan); 2057 2058 pm_runtime_put_sync(host->dev); 2059 pm_runtime_disable(host->dev); 2060 clk_put(host->fclk); 2061 if (host->dbclk) { 2062 clk_disable_unprepare(host->dbclk); 2063 clk_put(host->dbclk); 2064 } 2065 2066 omap_hsmmc_gpio_free(host->pdata); 2067 iounmap(host->base); 2068 mmc_free_host(host->mmc); 2069 2070 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2071 if (res) 2072 release_mem_region(res->start, resource_size(res)); 2073 platform_set_drvdata(pdev, NULL); 2074 2075 return 0; 2076 } 2077 2078 #ifdef CONFIG_PM 2079 static int omap_hsmmc_prepare(struct device *dev) 2080 { 2081 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2082 2083 if (host->pdata->suspend) 2084 return host->pdata->suspend(dev, host->slot_id); 2085 2086 return 0; 2087 } 2088 2089 static void omap_hsmmc_complete(struct device *dev) 2090 { 2091 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2092 2093 if (host->pdata->resume) 2094 host->pdata->resume(dev, host->slot_id); 2095 2096 } 2097 2098 static int omap_hsmmc_suspend(struct device *dev) 2099 { 2100 int ret = 0; 2101 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2102 2103 if (!host) 2104 return 0; 2105 2106 if (host && host->suspended) 2107 return 0; 2108 2109 pm_runtime_get_sync(host->dev); 2110 host->suspended = 1; 2111 ret = mmc_suspend_host(host->mmc); 2112 2113 if (ret) { 2114 host->suspended = 0; 2115 goto err; 2116 } 2117 2118 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) { 2119 omap_hsmmc_disable_irq(host); 2120 OMAP_HSMMC_WRITE(host->base, HCTL, 2121 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2122 } 2123 2124 if (host->dbclk) 2125 clk_disable_unprepare(host->dbclk); 2126 err: 2127 pm_runtime_put_sync(host->dev); 2128 return ret; 2129 } 2130 2131 /* Routine to resume the MMC device */ 2132 static int omap_hsmmc_resume(struct device *dev) 2133 { 2134 int ret = 0; 2135 struct omap_hsmmc_host *host = dev_get_drvdata(dev); 2136 2137 if (!host) 2138 return 0; 2139 2140 if (host && !host->suspended) 2141 return 0; 2142 2143 pm_runtime_get_sync(host->dev); 2144 2145 if (host->dbclk) 2146 clk_prepare_enable(host->dbclk); 2147 2148 if (!(host->mmc->pm_flags & MMC_PM_KEEP_POWER)) 2149 omap_hsmmc_conf_bus_power(host); 2150 2151 omap_hsmmc_protect_card(host); 2152 2153 /* Notify the core to resume the host */ 2154 ret = mmc_resume_host(host->mmc); 2155 if (ret == 0) 2156 host->suspended = 0; 2157 2158 pm_runtime_mark_last_busy(host->dev); 2159 pm_runtime_put_autosuspend(host->dev); 2160 2161 return ret; 2162 2163 } 2164 2165 #else 2166 #define omap_hsmmc_prepare NULL 2167 #define omap_hsmmc_complete NULL 2168 #define omap_hsmmc_suspend NULL 2169 #define omap_hsmmc_resume NULL 2170 #endif 2171 2172 static int omap_hsmmc_runtime_suspend(struct device *dev) 2173 { 2174 struct omap_hsmmc_host *host; 2175 2176 host = platform_get_drvdata(to_platform_device(dev)); 2177 omap_hsmmc_context_save(host); 2178 dev_dbg(dev, "disabled\n"); 2179 2180 return 0; 2181 } 2182 2183 static int omap_hsmmc_runtime_resume(struct device *dev) 2184 { 2185 struct omap_hsmmc_host *host; 2186 2187 host = platform_get_drvdata(to_platform_device(dev)); 2188 omap_hsmmc_context_restore(host); 2189 dev_dbg(dev, "enabled\n"); 2190 2191 return 0; 2192 } 2193 2194 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2195 .suspend = omap_hsmmc_suspend, 2196 .resume = omap_hsmmc_resume, 2197 .prepare = omap_hsmmc_prepare, 2198 .complete = omap_hsmmc_complete, 2199 .runtime_suspend = omap_hsmmc_runtime_suspend, 2200 .runtime_resume = omap_hsmmc_runtime_resume, 2201 }; 2202 2203 static struct platform_driver omap_hsmmc_driver = { 2204 .probe = omap_hsmmc_probe, 2205 .remove = omap_hsmmc_remove, 2206 .driver = { 2207 .name = DRIVER_NAME, 2208 .owner = THIS_MODULE, 2209 .pm = &omap_hsmmc_dev_pm_ops, 2210 .of_match_table = of_match_ptr(omap_mmc_of_match), 2211 }, 2212 }; 2213 2214 module_platform_driver(omap_hsmmc_driver); 2215 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2216 MODULE_LICENSE("GPL"); 2217 MODULE_ALIAS("platform:" DRIVER_NAME); 2218 MODULE_AUTHOR("Texas Instruments Inc"); 2219