1 /* 2 * drivers/mmc/host/omap_hsmmc.c 3 * 4 * Driver for OMAP2430/3430 MMC controller. 5 * 6 * Copyright (C) 2007 Texas Instruments. 7 * 8 * Authors: 9 * Syed Mohammed Khasim <x0khasim@ti.com> 10 * Madhusudhan <madhu.cr@ti.com> 11 * Mohit Jalori <mjalori@ti.com> 12 * 13 * This file is licensed under the terms of the GNU General Public License 14 * version 2. This program is licensed "as is" without any warranty of any 15 * kind, whether express or implied. 16 */ 17 18 #include <linux/module.h> 19 #include <linux/init.h> 20 #include <linux/debugfs.h> 21 #include <linux/seq_file.h> 22 #include <linux/interrupt.h> 23 #include <linux/delay.h> 24 #include <linux/dma-mapping.h> 25 #include <linux/platform_device.h> 26 #include <linux/workqueue.h> 27 #include <linux/timer.h> 28 #include <linux/clk.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/core.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/io.h> 33 #include <linux/semaphore.h> 34 #include <linux/gpio.h> 35 #include <linux/regulator/consumer.h> 36 #include <plat/dma.h> 37 #include <mach/hardware.h> 38 #include <plat/board.h> 39 #include <plat/mmc.h> 40 #include <plat/cpu.h> 41 42 /* OMAP HSMMC Host Controller Registers */ 43 #define OMAP_HSMMC_SYSCONFIG 0x0010 44 #define OMAP_HSMMC_SYSSTATUS 0x0014 45 #define OMAP_HSMMC_CON 0x002C 46 #define OMAP_HSMMC_BLK 0x0104 47 #define OMAP_HSMMC_ARG 0x0108 48 #define OMAP_HSMMC_CMD 0x010C 49 #define OMAP_HSMMC_RSP10 0x0110 50 #define OMAP_HSMMC_RSP32 0x0114 51 #define OMAP_HSMMC_RSP54 0x0118 52 #define OMAP_HSMMC_RSP76 0x011C 53 #define OMAP_HSMMC_DATA 0x0120 54 #define OMAP_HSMMC_HCTL 0x0128 55 #define OMAP_HSMMC_SYSCTL 0x012C 56 #define OMAP_HSMMC_STAT 0x0130 57 #define OMAP_HSMMC_IE 0x0134 58 #define OMAP_HSMMC_ISE 0x0138 59 #define OMAP_HSMMC_CAPA 0x0140 60 61 #define VS18 (1 << 26) 62 #define VS30 (1 << 25) 63 #define SDVS18 (0x5 << 9) 64 #define SDVS30 (0x6 << 9) 65 #define SDVS33 (0x7 << 9) 66 #define SDVS_MASK 0x00000E00 67 #define SDVSCLR 0xFFFFF1FF 68 #define SDVSDET 0x00000400 69 #define AUTOIDLE 0x1 70 #define SDBP (1 << 8) 71 #define DTO 0xe 72 #define ICE 0x1 73 #define ICS 0x2 74 #define CEN (1 << 2) 75 #define CLKD_MASK 0x0000FFC0 76 #define CLKD_SHIFT 6 77 #define DTO_MASK 0x000F0000 78 #define DTO_SHIFT 16 79 #define INT_EN_MASK 0x307F0033 80 #define BWR_ENABLE (1 << 4) 81 #define BRR_ENABLE (1 << 5) 82 #define DTO_ENABLE (1 << 20) 83 #define INIT_STREAM (1 << 1) 84 #define DP_SELECT (1 << 21) 85 #define DDIR (1 << 4) 86 #define DMA_EN 0x1 87 #define MSBS (1 << 5) 88 #define BCE (1 << 1) 89 #define FOUR_BIT (1 << 1) 90 #define DW8 (1 << 5) 91 #define CC 0x1 92 #define TC 0x02 93 #define OD 0x1 94 #define ERR (1 << 15) 95 #define CMD_TIMEOUT (1 << 16) 96 #define DATA_TIMEOUT (1 << 20) 97 #define CMD_CRC (1 << 17) 98 #define DATA_CRC (1 << 21) 99 #define CARD_ERR (1 << 28) 100 #define STAT_CLEAR 0xFFFFFFFF 101 #define INIT_STREAM_CMD 0x00000000 102 #define DUAL_VOLT_OCR_BIT 7 103 #define SRC (1 << 25) 104 #define SRD (1 << 26) 105 #define SOFTRESET (1 << 1) 106 #define RESETDONE (1 << 0) 107 108 /* 109 * FIXME: Most likely all the data using these _DEVID defines should come 110 * from the platform_data, or implemented in controller and slot specific 111 * functions. 112 */ 113 #define OMAP_MMC1_DEVID 0 114 #define OMAP_MMC2_DEVID 1 115 #define OMAP_MMC3_DEVID 2 116 #define OMAP_MMC4_DEVID 3 117 #define OMAP_MMC5_DEVID 4 118 119 #define MMC_TIMEOUT_MS 20 120 #define OMAP_MMC_MASTER_CLOCK 96000000 121 #define DRIVER_NAME "mmci-omap-hs" 122 123 /* Timeouts for entering power saving states on inactivity, msec */ 124 #define OMAP_MMC_DISABLED_TIMEOUT 100 125 #define OMAP_MMC_SLEEP_TIMEOUT 1000 126 #define OMAP_MMC_OFF_TIMEOUT 8000 127 128 /* 129 * One controller can have multiple slots, like on some omap boards using 130 * omap.c controller driver. Luckily this is not currently done on any known 131 * omap_hsmmc.c device. 132 */ 133 #define mmc_slot(host) (host->pdata->slots[host->slot_id]) 134 135 /* 136 * MMC Host controller read/write API's 137 */ 138 #define OMAP_HSMMC_READ(base, reg) \ 139 __raw_readl((base) + OMAP_HSMMC_##reg) 140 141 #define OMAP_HSMMC_WRITE(base, reg, val) \ 142 __raw_writel((val), (base) + OMAP_HSMMC_##reg) 143 144 struct omap_hsmmc_host { 145 struct device *dev; 146 struct mmc_host *mmc; 147 struct mmc_request *mrq; 148 struct mmc_command *cmd; 149 struct mmc_data *data; 150 struct clk *fclk; 151 struct clk *iclk; 152 struct clk *dbclk; 153 /* 154 * vcc == configured supply 155 * vcc_aux == optional 156 * - MMC1, supply for DAT4..DAT7 157 * - MMC2/MMC2, external level shifter voltage supply, for 158 * chip (SDIO, eMMC, etc) or transceiver (MMC2 only) 159 */ 160 struct regulator *vcc; 161 struct regulator *vcc_aux; 162 struct work_struct mmc_carddetect_work; 163 void __iomem *base; 164 resource_size_t mapbase; 165 spinlock_t irq_lock; /* Prevent races with irq handler */ 166 unsigned int id; 167 unsigned int dma_len; 168 unsigned int dma_sg_idx; 169 unsigned char bus_mode; 170 unsigned char power_mode; 171 u32 *buffer; 172 u32 bytesleft; 173 int suspended; 174 int irq; 175 int use_dma, dma_ch; 176 int dma_line_tx, dma_line_rx; 177 int slot_id; 178 int got_dbclk; 179 int response_busy; 180 int context_loss; 181 int dpm_state; 182 int vdd; 183 int protect_card; 184 int reqs_blocked; 185 int use_reg; 186 int req_in_progress; 187 188 struct omap_mmc_platform_data *pdata; 189 }; 190 191 static int omap_hsmmc_card_detect(struct device *dev, int slot) 192 { 193 struct omap_mmc_platform_data *mmc = dev->platform_data; 194 195 /* NOTE: assumes card detect signal is active-low */ 196 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 197 } 198 199 static int omap_hsmmc_get_wp(struct device *dev, int slot) 200 { 201 struct omap_mmc_platform_data *mmc = dev->platform_data; 202 203 /* NOTE: assumes write protect signal is active-high */ 204 return gpio_get_value_cansleep(mmc->slots[0].gpio_wp); 205 } 206 207 static int omap_hsmmc_get_cover_state(struct device *dev, int slot) 208 { 209 struct omap_mmc_platform_data *mmc = dev->platform_data; 210 211 /* NOTE: assumes card detect signal is active-low */ 212 return !gpio_get_value_cansleep(mmc->slots[0].switch_pin); 213 } 214 215 #ifdef CONFIG_PM 216 217 static int omap_hsmmc_suspend_cdirq(struct device *dev, int slot) 218 { 219 struct omap_mmc_platform_data *mmc = dev->platform_data; 220 221 disable_irq(mmc->slots[0].card_detect_irq); 222 return 0; 223 } 224 225 static int omap_hsmmc_resume_cdirq(struct device *dev, int slot) 226 { 227 struct omap_mmc_platform_data *mmc = dev->platform_data; 228 229 enable_irq(mmc->slots[0].card_detect_irq); 230 return 0; 231 } 232 233 #else 234 235 #define omap_hsmmc_suspend_cdirq NULL 236 #define omap_hsmmc_resume_cdirq NULL 237 238 #endif 239 240 #ifdef CONFIG_REGULATOR 241 242 static int omap_hsmmc_1_set_power(struct device *dev, int slot, int power_on, 243 int vdd) 244 { 245 struct omap_hsmmc_host *host = 246 platform_get_drvdata(to_platform_device(dev)); 247 int ret; 248 249 if (mmc_slot(host).before_set_reg) 250 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 251 252 if (power_on) 253 ret = mmc_regulator_set_ocr(host->vcc, vdd); 254 else 255 ret = mmc_regulator_set_ocr(host->vcc, 0); 256 257 if (mmc_slot(host).after_set_reg) 258 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 259 260 return ret; 261 } 262 263 static int omap_hsmmc_23_set_power(struct device *dev, int slot, int power_on, 264 int vdd) 265 { 266 struct omap_hsmmc_host *host = 267 platform_get_drvdata(to_platform_device(dev)); 268 int ret = 0; 269 270 /* 271 * If we don't see a Vcc regulator, assume it's a fixed 272 * voltage always-on regulator. 273 */ 274 if (!host->vcc) 275 return 0; 276 277 if (mmc_slot(host).before_set_reg) 278 mmc_slot(host).before_set_reg(dev, slot, power_on, vdd); 279 280 /* 281 * Assume Vcc regulator is used only to power the card ... OMAP 282 * VDDS is used to power the pins, optionally with a transceiver to 283 * support cards using voltages other than VDDS (1.8V nominal). When a 284 * transceiver is used, DAT3..7 are muxed as transceiver control pins. 285 * 286 * In some cases this regulator won't support enable/disable; 287 * e.g. it's a fixed rail for a WLAN chip. 288 * 289 * In other cases vcc_aux switches interface power. Example, for 290 * eMMC cards it represents VccQ. Sometimes transceivers or SDIO 291 * chips/cards need an interface voltage rail too. 292 */ 293 if (power_on) { 294 ret = mmc_regulator_set_ocr(host->vcc, vdd); 295 /* Enable interface voltage rail, if needed */ 296 if (ret == 0 && host->vcc_aux) { 297 ret = regulator_enable(host->vcc_aux); 298 if (ret < 0) 299 ret = mmc_regulator_set_ocr(host->vcc, 0); 300 } 301 } else { 302 if (host->vcc_aux) 303 ret = regulator_disable(host->vcc_aux); 304 if (ret == 0) 305 ret = mmc_regulator_set_ocr(host->vcc, 0); 306 } 307 308 if (mmc_slot(host).after_set_reg) 309 mmc_slot(host).after_set_reg(dev, slot, power_on, vdd); 310 311 return ret; 312 } 313 314 static int omap_hsmmc_1_set_sleep(struct device *dev, int slot, int sleep, 315 int vdd, int cardsleep) 316 { 317 struct omap_hsmmc_host *host = 318 platform_get_drvdata(to_platform_device(dev)); 319 int mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 320 321 return regulator_set_mode(host->vcc, mode); 322 } 323 324 static int omap_hsmmc_23_set_sleep(struct device *dev, int slot, int sleep, 325 int vdd, int cardsleep) 326 { 327 struct omap_hsmmc_host *host = 328 platform_get_drvdata(to_platform_device(dev)); 329 int err, mode; 330 331 /* 332 * If we don't see a Vcc regulator, assume it's a fixed 333 * voltage always-on regulator. 334 */ 335 if (!host->vcc) 336 return 0; 337 338 mode = sleep ? REGULATOR_MODE_STANDBY : REGULATOR_MODE_NORMAL; 339 340 if (!host->vcc_aux) 341 return regulator_set_mode(host->vcc, mode); 342 343 if (cardsleep) { 344 /* VCC can be turned off if card is asleep */ 345 if (sleep) 346 err = mmc_regulator_set_ocr(host->vcc, 0); 347 else 348 err = mmc_regulator_set_ocr(host->vcc, vdd); 349 } else 350 err = regulator_set_mode(host->vcc, mode); 351 if (err) 352 return err; 353 354 if (!mmc_slot(host).vcc_aux_disable_is_sleep) 355 return regulator_set_mode(host->vcc_aux, mode); 356 357 if (sleep) 358 return regulator_disable(host->vcc_aux); 359 else 360 return regulator_enable(host->vcc_aux); 361 } 362 363 static int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 364 { 365 struct regulator *reg; 366 int ret = 0; 367 368 switch (host->id) { 369 case OMAP_MMC1_DEVID: 370 /* On-chip level shifting via PBIAS0/PBIAS1 */ 371 mmc_slot(host).set_power = omap_hsmmc_1_set_power; 372 mmc_slot(host).set_sleep = omap_hsmmc_1_set_sleep; 373 break; 374 case OMAP_MMC2_DEVID: 375 case OMAP_MMC3_DEVID: 376 /* Off-chip level shifting, or none */ 377 mmc_slot(host).set_power = omap_hsmmc_23_set_power; 378 mmc_slot(host).set_sleep = omap_hsmmc_23_set_sleep; 379 break; 380 default: 381 pr_err("MMC%d configuration not supported!\n", host->id); 382 return -EINVAL; 383 } 384 385 reg = regulator_get(host->dev, "vmmc"); 386 if (IS_ERR(reg)) { 387 dev_dbg(host->dev, "vmmc regulator missing\n"); 388 /* 389 * HACK: until fixed.c regulator is usable, 390 * we don't require a main regulator 391 * for MMC2 or MMC3 392 */ 393 if (host->id == OMAP_MMC1_DEVID) { 394 ret = PTR_ERR(reg); 395 goto err; 396 } 397 } else { 398 host->vcc = reg; 399 mmc_slot(host).ocr_mask = mmc_regulator_get_ocrmask(reg); 400 401 /* Allow an aux regulator */ 402 reg = regulator_get(host->dev, "vmmc_aux"); 403 host->vcc_aux = IS_ERR(reg) ? NULL : reg; 404 405 /* 406 * UGLY HACK: workaround regulator framework bugs. 407 * When the bootloader leaves a supply active, it's 408 * initialized with zero usecount ... and we can't 409 * disable it without first enabling it. Until the 410 * framework is fixed, we need a workaround like this 411 * (which is safe for MMC, but not in general). 412 */ 413 if (regulator_is_enabled(host->vcc) > 0) { 414 regulator_enable(host->vcc); 415 regulator_disable(host->vcc); 416 } 417 if (host->vcc_aux) { 418 if (regulator_is_enabled(reg) > 0) { 419 regulator_enable(reg); 420 regulator_disable(reg); 421 } 422 } 423 } 424 425 return 0; 426 427 err: 428 mmc_slot(host).set_power = NULL; 429 mmc_slot(host).set_sleep = NULL; 430 return ret; 431 } 432 433 static void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 434 { 435 regulator_put(host->vcc); 436 regulator_put(host->vcc_aux); 437 mmc_slot(host).set_power = NULL; 438 mmc_slot(host).set_sleep = NULL; 439 } 440 441 static inline int omap_hsmmc_have_reg(void) 442 { 443 return 1; 444 } 445 446 #else 447 448 static inline int omap_hsmmc_reg_get(struct omap_hsmmc_host *host) 449 { 450 return -EINVAL; 451 } 452 453 static inline void omap_hsmmc_reg_put(struct omap_hsmmc_host *host) 454 { 455 } 456 457 static inline int omap_hsmmc_have_reg(void) 458 { 459 return 0; 460 } 461 462 #endif 463 464 static int omap_hsmmc_gpio_init(struct omap_mmc_platform_data *pdata) 465 { 466 int ret; 467 468 if (gpio_is_valid(pdata->slots[0].switch_pin)) { 469 pdata->suspend = omap_hsmmc_suspend_cdirq; 470 pdata->resume = omap_hsmmc_resume_cdirq; 471 if (pdata->slots[0].cover) 472 pdata->slots[0].get_cover_state = 473 omap_hsmmc_get_cover_state; 474 else 475 pdata->slots[0].card_detect = omap_hsmmc_card_detect; 476 pdata->slots[0].card_detect_irq = 477 gpio_to_irq(pdata->slots[0].switch_pin); 478 ret = gpio_request(pdata->slots[0].switch_pin, "mmc_cd"); 479 if (ret) 480 return ret; 481 ret = gpio_direction_input(pdata->slots[0].switch_pin); 482 if (ret) 483 goto err_free_sp; 484 } else 485 pdata->slots[0].switch_pin = -EINVAL; 486 487 if (gpio_is_valid(pdata->slots[0].gpio_wp)) { 488 pdata->slots[0].get_ro = omap_hsmmc_get_wp; 489 ret = gpio_request(pdata->slots[0].gpio_wp, "mmc_wp"); 490 if (ret) 491 goto err_free_cd; 492 ret = gpio_direction_input(pdata->slots[0].gpio_wp); 493 if (ret) 494 goto err_free_wp; 495 } else 496 pdata->slots[0].gpio_wp = -EINVAL; 497 498 return 0; 499 500 err_free_wp: 501 gpio_free(pdata->slots[0].gpio_wp); 502 err_free_cd: 503 if (gpio_is_valid(pdata->slots[0].switch_pin)) 504 err_free_sp: 505 gpio_free(pdata->slots[0].switch_pin); 506 return ret; 507 } 508 509 static void omap_hsmmc_gpio_free(struct omap_mmc_platform_data *pdata) 510 { 511 if (gpio_is_valid(pdata->slots[0].gpio_wp)) 512 gpio_free(pdata->slots[0].gpio_wp); 513 if (gpio_is_valid(pdata->slots[0].switch_pin)) 514 gpio_free(pdata->slots[0].switch_pin); 515 } 516 517 /* 518 * Stop clock to the card 519 */ 520 static void omap_hsmmc_stop_clock(struct omap_hsmmc_host *host) 521 { 522 OMAP_HSMMC_WRITE(host->base, SYSCTL, 523 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 524 if ((OMAP_HSMMC_READ(host->base, SYSCTL) & CEN) != 0x0) 525 dev_dbg(mmc_dev(host->mmc), "MMC Clock is not stoped\n"); 526 } 527 528 static void omap_hsmmc_enable_irq(struct omap_hsmmc_host *host, 529 struct mmc_command *cmd) 530 { 531 unsigned int irq_mask; 532 533 if (host->use_dma) 534 irq_mask = INT_EN_MASK & ~(BRR_ENABLE | BWR_ENABLE); 535 else 536 irq_mask = INT_EN_MASK; 537 538 /* Disable timeout for erases */ 539 if (cmd->opcode == MMC_ERASE) 540 irq_mask &= ~DTO_ENABLE; 541 542 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 543 OMAP_HSMMC_WRITE(host->base, ISE, irq_mask); 544 OMAP_HSMMC_WRITE(host->base, IE, irq_mask); 545 } 546 547 static void omap_hsmmc_disable_irq(struct omap_hsmmc_host *host) 548 { 549 OMAP_HSMMC_WRITE(host->base, ISE, 0); 550 OMAP_HSMMC_WRITE(host->base, IE, 0); 551 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 552 } 553 554 #ifdef CONFIG_PM 555 556 /* 557 * Restore the MMC host context, if it was lost as result of a 558 * power state change. 559 */ 560 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 561 { 562 struct mmc_ios *ios = &host->mmc->ios; 563 struct omap_mmc_platform_data *pdata = host->pdata; 564 int context_loss = 0; 565 u32 hctl, capa, con; 566 u16 dsor = 0; 567 unsigned long timeout; 568 569 if (pdata->get_context_loss_count) { 570 context_loss = pdata->get_context_loss_count(host->dev); 571 if (context_loss < 0) 572 return 1; 573 } 574 575 dev_dbg(mmc_dev(host->mmc), "context was %slost\n", 576 context_loss == host->context_loss ? "not " : ""); 577 if (host->context_loss == context_loss) 578 return 1; 579 580 /* Wait for hardware reset */ 581 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 582 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 583 && time_before(jiffies, timeout)) 584 ; 585 586 /* Do software reset */ 587 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, SOFTRESET); 588 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 589 while ((OMAP_HSMMC_READ(host->base, SYSSTATUS) & RESETDONE) != RESETDONE 590 && time_before(jiffies, timeout)) 591 ; 592 593 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, 594 OMAP_HSMMC_READ(host->base, SYSCONFIG) | AUTOIDLE); 595 596 if (host->id == OMAP_MMC1_DEVID) { 597 if (host->power_mode != MMC_POWER_OFF && 598 (1 << ios->vdd) <= MMC_VDD_23_24) 599 hctl = SDVS18; 600 else 601 hctl = SDVS30; 602 capa = VS30 | VS18; 603 } else { 604 hctl = SDVS18; 605 capa = VS18; 606 } 607 608 OMAP_HSMMC_WRITE(host->base, HCTL, 609 OMAP_HSMMC_READ(host->base, HCTL) | hctl); 610 611 OMAP_HSMMC_WRITE(host->base, CAPA, 612 OMAP_HSMMC_READ(host->base, CAPA) | capa); 613 614 OMAP_HSMMC_WRITE(host->base, HCTL, 615 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 616 617 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 618 while ((OMAP_HSMMC_READ(host->base, HCTL) & SDBP) != SDBP 619 && time_before(jiffies, timeout)) 620 ; 621 622 omap_hsmmc_disable_irq(host); 623 624 /* Do not initialize card-specific things if the power is off */ 625 if (host->power_mode == MMC_POWER_OFF) 626 goto out; 627 628 con = OMAP_HSMMC_READ(host->base, CON); 629 switch (ios->bus_width) { 630 case MMC_BUS_WIDTH_8: 631 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 632 break; 633 case MMC_BUS_WIDTH_4: 634 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 635 OMAP_HSMMC_WRITE(host->base, HCTL, 636 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 637 break; 638 case MMC_BUS_WIDTH_1: 639 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 640 OMAP_HSMMC_WRITE(host->base, HCTL, 641 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 642 break; 643 } 644 645 if (ios->clock) { 646 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 647 if (dsor < 1) 648 dsor = 1; 649 650 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 651 dsor++; 652 653 if (dsor > 250) 654 dsor = 250; 655 } 656 657 OMAP_HSMMC_WRITE(host->base, SYSCTL, 658 OMAP_HSMMC_READ(host->base, SYSCTL) & ~CEN); 659 OMAP_HSMMC_WRITE(host->base, SYSCTL, (dsor << 6) | (DTO << 16)); 660 OMAP_HSMMC_WRITE(host->base, SYSCTL, 661 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 662 663 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 664 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 665 && time_before(jiffies, timeout)) 666 ; 667 668 OMAP_HSMMC_WRITE(host->base, SYSCTL, 669 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 670 671 con = OMAP_HSMMC_READ(host->base, CON); 672 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 673 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 674 else 675 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 676 out: 677 host->context_loss = context_loss; 678 679 dev_dbg(mmc_dev(host->mmc), "context is restored\n"); 680 return 0; 681 } 682 683 /* 684 * Save the MMC host context (store the number of power state changes so far). 685 */ 686 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 687 { 688 struct omap_mmc_platform_data *pdata = host->pdata; 689 int context_loss; 690 691 if (pdata->get_context_loss_count) { 692 context_loss = pdata->get_context_loss_count(host->dev); 693 if (context_loss < 0) 694 return; 695 host->context_loss = context_loss; 696 } 697 } 698 699 #else 700 701 static int omap_hsmmc_context_restore(struct omap_hsmmc_host *host) 702 { 703 return 0; 704 } 705 706 static void omap_hsmmc_context_save(struct omap_hsmmc_host *host) 707 { 708 } 709 710 #endif 711 712 /* 713 * Send init stream sequence to card 714 * before sending IDLE command 715 */ 716 static void send_init_stream(struct omap_hsmmc_host *host) 717 { 718 int reg = 0; 719 unsigned long timeout; 720 721 if (host->protect_card) 722 return; 723 724 disable_irq(host->irq); 725 726 OMAP_HSMMC_WRITE(host->base, IE, INT_EN_MASK); 727 OMAP_HSMMC_WRITE(host->base, CON, 728 OMAP_HSMMC_READ(host->base, CON) | INIT_STREAM); 729 OMAP_HSMMC_WRITE(host->base, CMD, INIT_STREAM_CMD); 730 731 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 732 while ((reg != CC) && time_before(jiffies, timeout)) 733 reg = OMAP_HSMMC_READ(host->base, STAT) & CC; 734 735 OMAP_HSMMC_WRITE(host->base, CON, 736 OMAP_HSMMC_READ(host->base, CON) & ~INIT_STREAM); 737 738 OMAP_HSMMC_WRITE(host->base, STAT, STAT_CLEAR); 739 OMAP_HSMMC_READ(host->base, STAT); 740 741 enable_irq(host->irq); 742 } 743 744 static inline 745 int omap_hsmmc_cover_is_closed(struct omap_hsmmc_host *host) 746 { 747 int r = 1; 748 749 if (mmc_slot(host).get_cover_state) 750 r = mmc_slot(host).get_cover_state(host->dev, host->slot_id); 751 return r; 752 } 753 754 static ssize_t 755 omap_hsmmc_show_cover_switch(struct device *dev, struct device_attribute *attr, 756 char *buf) 757 { 758 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 759 struct omap_hsmmc_host *host = mmc_priv(mmc); 760 761 return sprintf(buf, "%s\n", 762 omap_hsmmc_cover_is_closed(host) ? "closed" : "open"); 763 } 764 765 static DEVICE_ATTR(cover_switch, S_IRUGO, omap_hsmmc_show_cover_switch, NULL); 766 767 static ssize_t 768 omap_hsmmc_show_slot_name(struct device *dev, struct device_attribute *attr, 769 char *buf) 770 { 771 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 772 struct omap_hsmmc_host *host = mmc_priv(mmc); 773 774 return sprintf(buf, "%s\n", mmc_slot(host).name); 775 } 776 777 static DEVICE_ATTR(slot_name, S_IRUGO, omap_hsmmc_show_slot_name, NULL); 778 779 /* 780 * Configure the response type and send the cmd. 781 */ 782 static void 783 omap_hsmmc_start_command(struct omap_hsmmc_host *host, struct mmc_command *cmd, 784 struct mmc_data *data) 785 { 786 int cmdreg = 0, resptype = 0, cmdtype = 0; 787 788 dev_dbg(mmc_dev(host->mmc), "%s: CMD%d, argument 0x%08x\n", 789 mmc_hostname(host->mmc), cmd->opcode, cmd->arg); 790 host->cmd = cmd; 791 792 omap_hsmmc_enable_irq(host, cmd); 793 794 host->response_busy = 0; 795 if (cmd->flags & MMC_RSP_PRESENT) { 796 if (cmd->flags & MMC_RSP_136) 797 resptype = 1; 798 else if (cmd->flags & MMC_RSP_BUSY) { 799 resptype = 3; 800 host->response_busy = 1; 801 } else 802 resptype = 2; 803 } 804 805 /* 806 * Unlike OMAP1 controller, the cmdtype does not seem to be based on 807 * ac, bc, adtc, bcr. Only commands ending an open ended transfer need 808 * a val of 0x3, rest 0x0. 809 */ 810 if (cmd == host->mrq->stop) 811 cmdtype = 0x3; 812 813 cmdreg = (cmd->opcode << 24) | (resptype << 16) | (cmdtype << 22); 814 815 if (data) { 816 cmdreg |= DP_SELECT | MSBS | BCE; 817 if (data->flags & MMC_DATA_READ) 818 cmdreg |= DDIR; 819 else 820 cmdreg &= ~(DDIR); 821 } 822 823 if (host->use_dma) 824 cmdreg |= DMA_EN; 825 826 host->req_in_progress = 1; 827 828 OMAP_HSMMC_WRITE(host->base, ARG, cmd->arg); 829 OMAP_HSMMC_WRITE(host->base, CMD, cmdreg); 830 } 831 832 static int 833 omap_hsmmc_get_dma_dir(struct omap_hsmmc_host *host, struct mmc_data *data) 834 { 835 if (data->flags & MMC_DATA_WRITE) 836 return DMA_TO_DEVICE; 837 else 838 return DMA_FROM_DEVICE; 839 } 840 841 static void omap_hsmmc_request_done(struct omap_hsmmc_host *host, struct mmc_request *mrq) 842 { 843 int dma_ch; 844 845 spin_lock(&host->irq_lock); 846 host->req_in_progress = 0; 847 dma_ch = host->dma_ch; 848 spin_unlock(&host->irq_lock); 849 850 omap_hsmmc_disable_irq(host); 851 /* Do not complete the request if DMA is still in progress */ 852 if (mrq->data && host->use_dma && dma_ch != -1) 853 return; 854 host->mrq = NULL; 855 mmc_request_done(host->mmc, mrq); 856 } 857 858 /* 859 * Notify the transfer complete to MMC core 860 */ 861 static void 862 omap_hsmmc_xfer_done(struct omap_hsmmc_host *host, struct mmc_data *data) 863 { 864 if (!data) { 865 struct mmc_request *mrq = host->mrq; 866 867 /* TC before CC from CMD6 - don't know why, but it happens */ 868 if (host->cmd && host->cmd->opcode == 6 && 869 host->response_busy) { 870 host->response_busy = 0; 871 return; 872 } 873 874 omap_hsmmc_request_done(host, mrq); 875 return; 876 } 877 878 host->data = NULL; 879 880 if (!data->error) 881 data->bytes_xfered += data->blocks * (data->blksz); 882 else 883 data->bytes_xfered = 0; 884 885 if (!data->stop) { 886 omap_hsmmc_request_done(host, data->mrq); 887 return; 888 } 889 omap_hsmmc_start_command(host, data->stop, NULL); 890 } 891 892 /* 893 * Notify the core about command completion 894 */ 895 static void 896 omap_hsmmc_cmd_done(struct omap_hsmmc_host *host, struct mmc_command *cmd) 897 { 898 host->cmd = NULL; 899 900 if (cmd->flags & MMC_RSP_PRESENT) { 901 if (cmd->flags & MMC_RSP_136) { 902 /* response type 2 */ 903 cmd->resp[3] = OMAP_HSMMC_READ(host->base, RSP10); 904 cmd->resp[2] = OMAP_HSMMC_READ(host->base, RSP32); 905 cmd->resp[1] = OMAP_HSMMC_READ(host->base, RSP54); 906 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP76); 907 } else { 908 /* response types 1, 1b, 3, 4, 5, 6 */ 909 cmd->resp[0] = OMAP_HSMMC_READ(host->base, RSP10); 910 } 911 } 912 if ((host->data == NULL && !host->response_busy) || cmd->error) 913 omap_hsmmc_request_done(host, cmd->mrq); 914 } 915 916 /* 917 * DMA clean up for command errors 918 */ 919 static void omap_hsmmc_dma_cleanup(struct omap_hsmmc_host *host, int errno) 920 { 921 int dma_ch; 922 923 host->data->error = errno; 924 925 spin_lock(&host->irq_lock); 926 dma_ch = host->dma_ch; 927 host->dma_ch = -1; 928 spin_unlock(&host->irq_lock); 929 930 if (host->use_dma && dma_ch != -1) { 931 dma_unmap_sg(mmc_dev(host->mmc), host->data->sg, host->dma_len, 932 omap_hsmmc_get_dma_dir(host, host->data)); 933 omap_free_dma(dma_ch); 934 } 935 host->data = NULL; 936 } 937 938 /* 939 * Readable error output 940 */ 941 #ifdef CONFIG_MMC_DEBUG 942 static void omap_hsmmc_report_irq(struct omap_hsmmc_host *host, u32 status) 943 { 944 /* --- means reserved bit without definition at documentation */ 945 static const char *omap_hsmmc_status_bits[] = { 946 "CC", "TC", "BGE", "---", "BWR", "BRR", "---", "---", "CIRQ", 947 "OBI", "---", "---", "---", "---", "---", "ERRI", "CTO", "CCRC", 948 "CEB", "CIE", "DTO", "DCRC", "DEB", "---", "ACE", "---", 949 "---", "---", "---", "CERR", "CERR", "BADA", "---", "---", "---" 950 }; 951 char res[256]; 952 char *buf = res; 953 int len, i; 954 955 len = sprintf(buf, "MMC IRQ 0x%x :", status); 956 buf += len; 957 958 for (i = 0; i < ARRAY_SIZE(omap_hsmmc_status_bits); i++) 959 if (status & (1 << i)) { 960 len = sprintf(buf, " %s", omap_hsmmc_status_bits[i]); 961 buf += len; 962 } 963 964 dev_dbg(mmc_dev(host->mmc), "%s\n", res); 965 } 966 #endif /* CONFIG_MMC_DEBUG */ 967 968 /* 969 * MMC controller internal state machines reset 970 * 971 * Used to reset command or data internal state machines, using respectively 972 * SRC or SRD bit of SYSCTL register 973 * Can be called from interrupt context 974 */ 975 static inline void omap_hsmmc_reset_controller_fsm(struct omap_hsmmc_host *host, 976 unsigned long bit) 977 { 978 unsigned long i = 0; 979 unsigned long limit = (loops_per_jiffy * 980 msecs_to_jiffies(MMC_TIMEOUT_MS)); 981 982 OMAP_HSMMC_WRITE(host->base, SYSCTL, 983 OMAP_HSMMC_READ(host->base, SYSCTL) | bit); 984 985 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & bit) && 986 (i++ < limit)) 987 cpu_relax(); 988 989 if (OMAP_HSMMC_READ(host->base, SYSCTL) & bit) 990 dev_err(mmc_dev(host->mmc), 991 "Timeout waiting on controller reset in %s\n", 992 __func__); 993 } 994 995 static void omap_hsmmc_do_irq(struct omap_hsmmc_host *host, int status) 996 { 997 struct mmc_data *data; 998 int end_cmd = 0, end_trans = 0; 999 1000 if (!host->req_in_progress) { 1001 do { 1002 OMAP_HSMMC_WRITE(host->base, STAT, status); 1003 /* Flush posted write */ 1004 status = OMAP_HSMMC_READ(host->base, STAT); 1005 } while (status & INT_EN_MASK); 1006 return; 1007 } 1008 1009 data = host->data; 1010 dev_dbg(mmc_dev(host->mmc), "IRQ Status is %x\n", status); 1011 1012 if (status & ERR) { 1013 #ifdef CONFIG_MMC_DEBUG 1014 omap_hsmmc_report_irq(host, status); 1015 #endif 1016 if ((status & CMD_TIMEOUT) || 1017 (status & CMD_CRC)) { 1018 if (host->cmd) { 1019 if (status & CMD_TIMEOUT) { 1020 omap_hsmmc_reset_controller_fsm(host, 1021 SRC); 1022 host->cmd->error = -ETIMEDOUT; 1023 } else { 1024 host->cmd->error = -EILSEQ; 1025 } 1026 end_cmd = 1; 1027 } 1028 if (host->data || host->response_busy) { 1029 if (host->data) 1030 omap_hsmmc_dma_cleanup(host, 1031 -ETIMEDOUT); 1032 host->response_busy = 0; 1033 omap_hsmmc_reset_controller_fsm(host, SRD); 1034 } 1035 } 1036 if ((status & DATA_TIMEOUT) || 1037 (status & DATA_CRC)) { 1038 if (host->data || host->response_busy) { 1039 int err = (status & DATA_TIMEOUT) ? 1040 -ETIMEDOUT : -EILSEQ; 1041 1042 if (host->data) 1043 omap_hsmmc_dma_cleanup(host, err); 1044 else 1045 host->mrq->cmd->error = err; 1046 host->response_busy = 0; 1047 omap_hsmmc_reset_controller_fsm(host, SRD); 1048 end_trans = 1; 1049 } 1050 } 1051 if (status & CARD_ERR) { 1052 dev_dbg(mmc_dev(host->mmc), 1053 "Ignoring card err CMD%d\n", host->cmd->opcode); 1054 if (host->cmd) 1055 end_cmd = 1; 1056 if (host->data) 1057 end_trans = 1; 1058 } 1059 } 1060 1061 OMAP_HSMMC_WRITE(host->base, STAT, status); 1062 1063 if (end_cmd || ((status & CC) && host->cmd)) 1064 omap_hsmmc_cmd_done(host, host->cmd); 1065 if ((end_trans || (status & TC)) && host->mrq) 1066 omap_hsmmc_xfer_done(host, data); 1067 } 1068 1069 /* 1070 * MMC controller IRQ handler 1071 */ 1072 static irqreturn_t omap_hsmmc_irq(int irq, void *dev_id) 1073 { 1074 struct omap_hsmmc_host *host = dev_id; 1075 int status; 1076 1077 status = OMAP_HSMMC_READ(host->base, STAT); 1078 do { 1079 omap_hsmmc_do_irq(host, status); 1080 /* Flush posted write */ 1081 status = OMAP_HSMMC_READ(host->base, STAT); 1082 } while (status & INT_EN_MASK); 1083 1084 return IRQ_HANDLED; 1085 } 1086 1087 static void set_sd_bus_power(struct omap_hsmmc_host *host) 1088 { 1089 unsigned long i; 1090 1091 OMAP_HSMMC_WRITE(host->base, HCTL, 1092 OMAP_HSMMC_READ(host->base, HCTL) | SDBP); 1093 for (i = 0; i < loops_per_jiffy; i++) { 1094 if (OMAP_HSMMC_READ(host->base, HCTL) & SDBP) 1095 break; 1096 cpu_relax(); 1097 } 1098 } 1099 1100 /* 1101 * Switch MMC interface voltage ... only relevant for MMC1. 1102 * 1103 * MMC2 and MMC3 use fixed 1.8V levels, and maybe a transceiver. 1104 * The MMC2 transceiver controls are used instead of DAT4..DAT7. 1105 * Some chips, like eMMC ones, use internal transceivers. 1106 */ 1107 static int omap_hsmmc_switch_opcond(struct omap_hsmmc_host *host, int vdd) 1108 { 1109 u32 reg_val = 0; 1110 int ret; 1111 1112 /* Disable the clocks */ 1113 clk_disable(host->fclk); 1114 clk_disable(host->iclk); 1115 if (host->got_dbclk) 1116 clk_disable(host->dbclk); 1117 1118 /* Turn the power off */ 1119 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1120 1121 /* Turn the power ON with given VDD 1.8 or 3.0v */ 1122 if (!ret) 1123 ret = mmc_slot(host).set_power(host->dev, host->slot_id, 1, 1124 vdd); 1125 clk_enable(host->iclk); 1126 clk_enable(host->fclk); 1127 if (host->got_dbclk) 1128 clk_enable(host->dbclk); 1129 1130 if (ret != 0) 1131 goto err; 1132 1133 OMAP_HSMMC_WRITE(host->base, HCTL, 1134 OMAP_HSMMC_READ(host->base, HCTL) & SDVSCLR); 1135 reg_val = OMAP_HSMMC_READ(host->base, HCTL); 1136 1137 /* 1138 * If a MMC dual voltage card is detected, the set_ios fn calls 1139 * this fn with VDD bit set for 1.8V. Upon card removal from the 1140 * slot, omap_hsmmc_set_ios sets the VDD back to 3V on MMC_POWER_OFF. 1141 * 1142 * Cope with a bit of slop in the range ... per data sheets: 1143 * - "1.8V" for vdds_mmc1/vdds_mmc1a can be up to 2.45V max, 1144 * but recommended values are 1.71V to 1.89V 1145 * - "3.0V" for vdds_mmc1/vdds_mmc1a can be up to 3.5V max, 1146 * but recommended values are 2.7V to 3.3V 1147 * 1148 * Board setup code shouldn't permit anything very out-of-range. 1149 * TWL4030-family VMMC1 and VSIM regulators are fine (avoiding the 1150 * middle range) but VSIM can't power DAT4..DAT7 at more than 3V. 1151 */ 1152 if ((1 << vdd) <= MMC_VDD_23_24) 1153 reg_val |= SDVS18; 1154 else 1155 reg_val |= SDVS30; 1156 1157 OMAP_HSMMC_WRITE(host->base, HCTL, reg_val); 1158 set_sd_bus_power(host); 1159 1160 return 0; 1161 err: 1162 dev_dbg(mmc_dev(host->mmc), "Unable to switch operating voltage\n"); 1163 return ret; 1164 } 1165 1166 /* Protect the card while the cover is open */ 1167 static void omap_hsmmc_protect_card(struct omap_hsmmc_host *host) 1168 { 1169 if (!mmc_slot(host).get_cover_state) 1170 return; 1171 1172 host->reqs_blocked = 0; 1173 if (mmc_slot(host).get_cover_state(host->dev, host->slot_id)) { 1174 if (host->protect_card) { 1175 printk(KERN_INFO "%s: cover is closed, " 1176 "card is now accessible\n", 1177 mmc_hostname(host->mmc)); 1178 host->protect_card = 0; 1179 } 1180 } else { 1181 if (!host->protect_card) { 1182 printk(KERN_INFO "%s: cover is open, " 1183 "card is now inaccessible\n", 1184 mmc_hostname(host->mmc)); 1185 host->protect_card = 1; 1186 } 1187 } 1188 } 1189 1190 /* 1191 * Work Item to notify the core about card insertion/removal 1192 */ 1193 static void omap_hsmmc_detect(struct work_struct *work) 1194 { 1195 struct omap_hsmmc_host *host = 1196 container_of(work, struct omap_hsmmc_host, mmc_carddetect_work); 1197 struct omap_mmc_slot_data *slot = &mmc_slot(host); 1198 int carddetect; 1199 1200 if (host->suspended) 1201 return; 1202 1203 sysfs_notify(&host->mmc->class_dev.kobj, NULL, "cover_switch"); 1204 1205 if (slot->card_detect) 1206 carddetect = slot->card_detect(host->dev, host->slot_id); 1207 else { 1208 omap_hsmmc_protect_card(host); 1209 carddetect = -ENOSYS; 1210 } 1211 1212 if (carddetect) 1213 mmc_detect_change(host->mmc, (HZ * 200) / 1000); 1214 else 1215 mmc_detect_change(host->mmc, (HZ * 50) / 1000); 1216 } 1217 1218 /* 1219 * ISR for handling card insertion and removal 1220 */ 1221 static irqreturn_t omap_hsmmc_cd_handler(int irq, void *dev_id) 1222 { 1223 struct omap_hsmmc_host *host = (struct omap_hsmmc_host *)dev_id; 1224 1225 if (host->suspended) 1226 return IRQ_HANDLED; 1227 schedule_work(&host->mmc_carddetect_work); 1228 1229 return IRQ_HANDLED; 1230 } 1231 1232 static int omap_hsmmc_get_dma_sync_dev(struct omap_hsmmc_host *host, 1233 struct mmc_data *data) 1234 { 1235 int sync_dev; 1236 1237 if (data->flags & MMC_DATA_WRITE) 1238 sync_dev = host->dma_line_tx; 1239 else 1240 sync_dev = host->dma_line_rx; 1241 return sync_dev; 1242 } 1243 1244 static void omap_hsmmc_config_dma_params(struct omap_hsmmc_host *host, 1245 struct mmc_data *data, 1246 struct scatterlist *sgl) 1247 { 1248 int blksz, nblk, dma_ch; 1249 1250 dma_ch = host->dma_ch; 1251 if (data->flags & MMC_DATA_WRITE) { 1252 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1253 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1254 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1255 sg_dma_address(sgl), 0, 0); 1256 } else { 1257 omap_set_dma_src_params(dma_ch, 0, OMAP_DMA_AMODE_CONSTANT, 1258 (host->mapbase + OMAP_HSMMC_DATA), 0, 0); 1259 omap_set_dma_dest_params(dma_ch, 0, OMAP_DMA_AMODE_POST_INC, 1260 sg_dma_address(sgl), 0, 0); 1261 } 1262 1263 blksz = host->data->blksz; 1264 nblk = sg_dma_len(sgl) / blksz; 1265 1266 omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S32, 1267 blksz / 4, nblk, OMAP_DMA_SYNC_FRAME, 1268 omap_hsmmc_get_dma_sync_dev(host, data), 1269 !(data->flags & MMC_DATA_WRITE)); 1270 1271 omap_start_dma(dma_ch); 1272 } 1273 1274 /* 1275 * DMA call back function 1276 */ 1277 static void omap_hsmmc_dma_cb(int lch, u16 ch_status, void *cb_data) 1278 { 1279 struct omap_hsmmc_host *host = cb_data; 1280 struct mmc_data *data = host->mrq->data; 1281 int dma_ch, req_in_progress; 1282 1283 if (!(ch_status & OMAP_DMA_BLOCK_IRQ)) { 1284 dev_warn(mmc_dev(host->mmc), "unexpected dma status %x\n", 1285 ch_status); 1286 return; 1287 } 1288 1289 spin_lock(&host->irq_lock); 1290 if (host->dma_ch < 0) { 1291 spin_unlock(&host->irq_lock); 1292 return; 1293 } 1294 1295 host->dma_sg_idx++; 1296 if (host->dma_sg_idx < host->dma_len) { 1297 /* Fire up the next transfer. */ 1298 omap_hsmmc_config_dma_params(host, data, 1299 data->sg + host->dma_sg_idx); 1300 spin_unlock(&host->irq_lock); 1301 return; 1302 } 1303 1304 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_len, 1305 omap_hsmmc_get_dma_dir(host, data)); 1306 1307 req_in_progress = host->req_in_progress; 1308 dma_ch = host->dma_ch; 1309 host->dma_ch = -1; 1310 spin_unlock(&host->irq_lock); 1311 1312 omap_free_dma(dma_ch); 1313 1314 /* If DMA has finished after TC, complete the request */ 1315 if (!req_in_progress) { 1316 struct mmc_request *mrq = host->mrq; 1317 1318 host->mrq = NULL; 1319 mmc_request_done(host->mmc, mrq); 1320 } 1321 } 1322 1323 /* 1324 * Routine to configure and start DMA for the MMC card 1325 */ 1326 static int omap_hsmmc_start_dma_transfer(struct omap_hsmmc_host *host, 1327 struct mmc_request *req) 1328 { 1329 int dma_ch = 0, ret = 0, i; 1330 struct mmc_data *data = req->data; 1331 1332 /* Sanity check: all the SG entries must be aligned by block size. */ 1333 for (i = 0; i < data->sg_len; i++) { 1334 struct scatterlist *sgl; 1335 1336 sgl = data->sg + i; 1337 if (sgl->length % data->blksz) 1338 return -EINVAL; 1339 } 1340 if ((data->blksz % 4) != 0) 1341 /* REVISIT: The MMC buffer increments only when MSB is written. 1342 * Return error for blksz which is non multiple of four. 1343 */ 1344 return -EINVAL; 1345 1346 BUG_ON(host->dma_ch != -1); 1347 1348 ret = omap_request_dma(omap_hsmmc_get_dma_sync_dev(host, data), 1349 "MMC/SD", omap_hsmmc_dma_cb, host, &dma_ch); 1350 if (ret != 0) { 1351 dev_err(mmc_dev(host->mmc), 1352 "%s: omap_request_dma() failed with %d\n", 1353 mmc_hostname(host->mmc), ret); 1354 return ret; 1355 } 1356 1357 host->dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, 1358 data->sg_len, omap_hsmmc_get_dma_dir(host, data)); 1359 host->dma_ch = dma_ch; 1360 host->dma_sg_idx = 0; 1361 1362 omap_hsmmc_config_dma_params(host, data, data->sg); 1363 1364 return 0; 1365 } 1366 1367 static void set_data_timeout(struct omap_hsmmc_host *host, 1368 unsigned int timeout_ns, 1369 unsigned int timeout_clks) 1370 { 1371 unsigned int timeout, cycle_ns; 1372 uint32_t reg, clkd, dto = 0; 1373 1374 reg = OMAP_HSMMC_READ(host->base, SYSCTL); 1375 clkd = (reg & CLKD_MASK) >> CLKD_SHIFT; 1376 if (clkd == 0) 1377 clkd = 1; 1378 1379 cycle_ns = 1000000000 / (clk_get_rate(host->fclk) / clkd); 1380 timeout = timeout_ns / cycle_ns; 1381 timeout += timeout_clks; 1382 if (timeout) { 1383 while ((timeout & 0x80000000) == 0) { 1384 dto += 1; 1385 timeout <<= 1; 1386 } 1387 dto = 31 - dto; 1388 timeout <<= 1; 1389 if (timeout && dto) 1390 dto += 1; 1391 if (dto >= 13) 1392 dto -= 13; 1393 else 1394 dto = 0; 1395 if (dto > 14) 1396 dto = 14; 1397 } 1398 1399 reg &= ~DTO_MASK; 1400 reg |= dto << DTO_SHIFT; 1401 OMAP_HSMMC_WRITE(host->base, SYSCTL, reg); 1402 } 1403 1404 /* 1405 * Configure block length for MMC/SD cards and initiate the transfer. 1406 */ 1407 static int 1408 omap_hsmmc_prepare_data(struct omap_hsmmc_host *host, struct mmc_request *req) 1409 { 1410 int ret; 1411 host->data = req->data; 1412 1413 if (req->data == NULL) { 1414 OMAP_HSMMC_WRITE(host->base, BLK, 0); 1415 /* 1416 * Set an arbitrary 100ms data timeout for commands with 1417 * busy signal. 1418 */ 1419 if (req->cmd->flags & MMC_RSP_BUSY) 1420 set_data_timeout(host, 100000000U, 0); 1421 return 0; 1422 } 1423 1424 OMAP_HSMMC_WRITE(host->base, BLK, (req->data->blksz) 1425 | (req->data->blocks << 16)); 1426 set_data_timeout(host, req->data->timeout_ns, req->data->timeout_clks); 1427 1428 if (host->use_dma) { 1429 ret = omap_hsmmc_start_dma_transfer(host, req); 1430 if (ret != 0) { 1431 dev_dbg(mmc_dev(host->mmc), "MMC start dma failure\n"); 1432 return ret; 1433 } 1434 } 1435 return 0; 1436 } 1437 1438 /* 1439 * Request function. for read/write operation 1440 */ 1441 static void omap_hsmmc_request(struct mmc_host *mmc, struct mmc_request *req) 1442 { 1443 struct omap_hsmmc_host *host = mmc_priv(mmc); 1444 int err; 1445 1446 BUG_ON(host->req_in_progress); 1447 BUG_ON(host->dma_ch != -1); 1448 if (host->protect_card) { 1449 if (host->reqs_blocked < 3) { 1450 /* 1451 * Ensure the controller is left in a consistent 1452 * state by resetting the command and data state 1453 * machines. 1454 */ 1455 omap_hsmmc_reset_controller_fsm(host, SRD); 1456 omap_hsmmc_reset_controller_fsm(host, SRC); 1457 host->reqs_blocked += 1; 1458 } 1459 req->cmd->error = -EBADF; 1460 if (req->data) 1461 req->data->error = -EBADF; 1462 req->cmd->retries = 0; 1463 mmc_request_done(mmc, req); 1464 return; 1465 } else if (host->reqs_blocked) 1466 host->reqs_blocked = 0; 1467 WARN_ON(host->mrq != NULL); 1468 host->mrq = req; 1469 err = omap_hsmmc_prepare_data(host, req); 1470 if (err) { 1471 req->cmd->error = err; 1472 if (req->data) 1473 req->data->error = err; 1474 host->mrq = NULL; 1475 mmc_request_done(mmc, req); 1476 return; 1477 } 1478 1479 omap_hsmmc_start_command(host, req->cmd, req->data); 1480 } 1481 1482 /* Routine to configure clock values. Exposed API to core */ 1483 static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1484 { 1485 struct omap_hsmmc_host *host = mmc_priv(mmc); 1486 u16 dsor = 0; 1487 unsigned long regval; 1488 unsigned long timeout; 1489 u32 con; 1490 int do_send_init_stream = 0; 1491 1492 mmc_host_enable(host->mmc); 1493 1494 if (ios->power_mode != host->power_mode) { 1495 switch (ios->power_mode) { 1496 case MMC_POWER_OFF: 1497 mmc_slot(host).set_power(host->dev, host->slot_id, 1498 0, 0); 1499 host->vdd = 0; 1500 break; 1501 case MMC_POWER_UP: 1502 mmc_slot(host).set_power(host->dev, host->slot_id, 1503 1, ios->vdd); 1504 host->vdd = ios->vdd; 1505 break; 1506 case MMC_POWER_ON: 1507 do_send_init_stream = 1; 1508 break; 1509 } 1510 host->power_mode = ios->power_mode; 1511 } 1512 1513 /* FIXME: set registers based only on changes to ios */ 1514 1515 con = OMAP_HSMMC_READ(host->base, CON); 1516 switch (mmc->ios.bus_width) { 1517 case MMC_BUS_WIDTH_8: 1518 OMAP_HSMMC_WRITE(host->base, CON, con | DW8); 1519 break; 1520 case MMC_BUS_WIDTH_4: 1521 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1522 OMAP_HSMMC_WRITE(host->base, HCTL, 1523 OMAP_HSMMC_READ(host->base, HCTL) | FOUR_BIT); 1524 break; 1525 case MMC_BUS_WIDTH_1: 1526 OMAP_HSMMC_WRITE(host->base, CON, con & ~DW8); 1527 OMAP_HSMMC_WRITE(host->base, HCTL, 1528 OMAP_HSMMC_READ(host->base, HCTL) & ~FOUR_BIT); 1529 break; 1530 } 1531 1532 if (host->id == OMAP_MMC1_DEVID) { 1533 /* Only MMC1 can interface at 3V without some flavor 1534 * of external transceiver; but they all handle 1.8V. 1535 */ 1536 if ((OMAP_HSMMC_READ(host->base, HCTL) & SDVSDET) && 1537 (ios->vdd == DUAL_VOLT_OCR_BIT)) { 1538 /* 1539 * The mmc_select_voltage fn of the core does 1540 * not seem to set the power_mode to 1541 * MMC_POWER_UP upon recalculating the voltage. 1542 * vdd 1.8v. 1543 */ 1544 if (omap_hsmmc_switch_opcond(host, ios->vdd) != 0) 1545 dev_dbg(mmc_dev(host->mmc), 1546 "Switch operation failed\n"); 1547 } 1548 } 1549 1550 if (ios->clock) { 1551 dsor = OMAP_MMC_MASTER_CLOCK / ios->clock; 1552 if (dsor < 1) 1553 dsor = 1; 1554 1555 if (OMAP_MMC_MASTER_CLOCK / dsor > ios->clock) 1556 dsor++; 1557 1558 if (dsor > 250) 1559 dsor = 250; 1560 } 1561 omap_hsmmc_stop_clock(host); 1562 regval = OMAP_HSMMC_READ(host->base, SYSCTL); 1563 regval = regval & ~(CLKD_MASK); 1564 regval = regval | (dsor << 6) | (DTO << 16); 1565 OMAP_HSMMC_WRITE(host->base, SYSCTL, regval); 1566 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1567 OMAP_HSMMC_READ(host->base, SYSCTL) | ICE); 1568 1569 /* Wait till the ICS bit is set */ 1570 timeout = jiffies + msecs_to_jiffies(MMC_TIMEOUT_MS); 1571 while ((OMAP_HSMMC_READ(host->base, SYSCTL) & ICS) != ICS 1572 && time_before(jiffies, timeout)) 1573 msleep(1); 1574 1575 OMAP_HSMMC_WRITE(host->base, SYSCTL, 1576 OMAP_HSMMC_READ(host->base, SYSCTL) | CEN); 1577 1578 if (do_send_init_stream) 1579 send_init_stream(host); 1580 1581 con = OMAP_HSMMC_READ(host->base, CON); 1582 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN) 1583 OMAP_HSMMC_WRITE(host->base, CON, con | OD); 1584 else 1585 OMAP_HSMMC_WRITE(host->base, CON, con & ~OD); 1586 1587 if (host->power_mode == MMC_POWER_OFF) 1588 mmc_host_disable(host->mmc); 1589 else 1590 mmc_host_lazy_disable(host->mmc); 1591 } 1592 1593 static int omap_hsmmc_get_cd(struct mmc_host *mmc) 1594 { 1595 struct omap_hsmmc_host *host = mmc_priv(mmc); 1596 1597 if (!mmc_slot(host).card_detect) 1598 return -ENOSYS; 1599 return mmc_slot(host).card_detect(host->dev, host->slot_id); 1600 } 1601 1602 static int omap_hsmmc_get_ro(struct mmc_host *mmc) 1603 { 1604 struct omap_hsmmc_host *host = mmc_priv(mmc); 1605 1606 if (!mmc_slot(host).get_ro) 1607 return -ENOSYS; 1608 return mmc_slot(host).get_ro(host->dev, 0); 1609 } 1610 1611 static void omap_hsmmc_init_card(struct mmc_host *mmc, struct mmc_card *card) 1612 { 1613 struct omap_hsmmc_host *host = mmc_priv(mmc); 1614 1615 if (mmc_slot(host).init_card) 1616 mmc_slot(host).init_card(card); 1617 } 1618 1619 static void omap_hsmmc_conf_bus_power(struct omap_hsmmc_host *host) 1620 { 1621 u32 hctl, capa, value; 1622 1623 /* Only MMC1 supports 3.0V */ 1624 if (host->id == OMAP_MMC1_DEVID) { 1625 hctl = SDVS30; 1626 capa = VS30 | VS18; 1627 } else { 1628 hctl = SDVS18; 1629 capa = VS18; 1630 } 1631 1632 value = OMAP_HSMMC_READ(host->base, HCTL) & ~SDVS_MASK; 1633 OMAP_HSMMC_WRITE(host->base, HCTL, value | hctl); 1634 1635 value = OMAP_HSMMC_READ(host->base, CAPA); 1636 OMAP_HSMMC_WRITE(host->base, CAPA, value | capa); 1637 1638 /* Set the controller to AUTO IDLE mode */ 1639 value = OMAP_HSMMC_READ(host->base, SYSCONFIG); 1640 OMAP_HSMMC_WRITE(host->base, SYSCONFIG, value | AUTOIDLE); 1641 1642 /* Set SD bus power bit */ 1643 set_sd_bus_power(host); 1644 } 1645 1646 /* 1647 * Dynamic power saving handling, FSM: 1648 * ENABLED -> DISABLED -> CARDSLEEP / REGSLEEP -> OFF 1649 * ^___________| | | 1650 * |______________________|______________________| 1651 * 1652 * ENABLED: mmc host is fully functional 1653 * DISABLED: fclk is off 1654 * CARDSLEEP: fclk is off, card is asleep, voltage regulator is asleep 1655 * REGSLEEP: fclk is off, voltage regulator is asleep 1656 * OFF: fclk is off, voltage regulator is off 1657 * 1658 * Transition handlers return the timeout for the next state transition 1659 * or negative error. 1660 */ 1661 1662 enum {ENABLED = 0, DISABLED, CARDSLEEP, REGSLEEP, OFF}; 1663 1664 /* Handler for [ENABLED -> DISABLED] transition */ 1665 static int omap_hsmmc_enabled_to_disabled(struct omap_hsmmc_host *host) 1666 { 1667 omap_hsmmc_context_save(host); 1668 clk_disable(host->fclk); 1669 host->dpm_state = DISABLED; 1670 1671 dev_dbg(mmc_dev(host->mmc), "ENABLED -> DISABLED\n"); 1672 1673 if (host->power_mode == MMC_POWER_OFF) 1674 return 0; 1675 1676 return OMAP_MMC_SLEEP_TIMEOUT; 1677 } 1678 1679 /* Handler for [DISABLED -> REGSLEEP / CARDSLEEP] transition */ 1680 static int omap_hsmmc_disabled_to_sleep(struct omap_hsmmc_host *host) 1681 { 1682 int err, new_state; 1683 1684 if (!mmc_try_claim_host(host->mmc)) 1685 return 0; 1686 1687 clk_enable(host->fclk); 1688 omap_hsmmc_context_restore(host); 1689 if (mmc_card_can_sleep(host->mmc)) { 1690 err = mmc_card_sleep(host->mmc); 1691 if (err < 0) { 1692 clk_disable(host->fclk); 1693 mmc_release_host(host->mmc); 1694 return err; 1695 } 1696 new_state = CARDSLEEP; 1697 } else { 1698 new_state = REGSLEEP; 1699 } 1700 if (mmc_slot(host).set_sleep) 1701 mmc_slot(host).set_sleep(host->dev, host->slot_id, 1, 0, 1702 new_state == CARDSLEEP); 1703 /* FIXME: turn off bus power and perhaps interrupts too */ 1704 clk_disable(host->fclk); 1705 host->dpm_state = new_state; 1706 1707 mmc_release_host(host->mmc); 1708 1709 dev_dbg(mmc_dev(host->mmc), "DISABLED -> %s\n", 1710 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1711 1712 if (mmc_slot(host).no_off) 1713 return 0; 1714 1715 if ((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1716 mmc_slot(host).card_detect || 1717 (mmc_slot(host).get_cover_state && 1718 mmc_slot(host).get_cover_state(host->dev, host->slot_id))) 1719 return OMAP_MMC_OFF_TIMEOUT; 1720 1721 return 0; 1722 } 1723 1724 /* Handler for [REGSLEEP / CARDSLEEP -> OFF] transition */ 1725 static int omap_hsmmc_sleep_to_off(struct omap_hsmmc_host *host) 1726 { 1727 if (!mmc_try_claim_host(host->mmc)) 1728 return 0; 1729 1730 if (mmc_slot(host).no_off) 1731 return 0; 1732 1733 if (!((host->mmc->caps & MMC_CAP_NONREMOVABLE) || 1734 mmc_slot(host).card_detect || 1735 (mmc_slot(host).get_cover_state && 1736 mmc_slot(host).get_cover_state(host->dev, host->slot_id)))) { 1737 mmc_release_host(host->mmc); 1738 return 0; 1739 } 1740 1741 mmc_slot(host).set_power(host->dev, host->slot_id, 0, 0); 1742 host->vdd = 0; 1743 host->power_mode = MMC_POWER_OFF; 1744 1745 dev_dbg(mmc_dev(host->mmc), "%s -> OFF\n", 1746 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1747 1748 host->dpm_state = OFF; 1749 1750 mmc_release_host(host->mmc); 1751 1752 return 0; 1753 } 1754 1755 /* Handler for [DISABLED -> ENABLED] transition */ 1756 static int omap_hsmmc_disabled_to_enabled(struct omap_hsmmc_host *host) 1757 { 1758 int err; 1759 1760 err = clk_enable(host->fclk); 1761 if (err < 0) 1762 return err; 1763 1764 omap_hsmmc_context_restore(host); 1765 host->dpm_state = ENABLED; 1766 1767 dev_dbg(mmc_dev(host->mmc), "DISABLED -> ENABLED\n"); 1768 1769 return 0; 1770 } 1771 1772 /* Handler for [SLEEP -> ENABLED] transition */ 1773 static int omap_hsmmc_sleep_to_enabled(struct omap_hsmmc_host *host) 1774 { 1775 if (!mmc_try_claim_host(host->mmc)) 1776 return 0; 1777 1778 clk_enable(host->fclk); 1779 omap_hsmmc_context_restore(host); 1780 if (mmc_slot(host).set_sleep) 1781 mmc_slot(host).set_sleep(host->dev, host->slot_id, 0, 1782 host->vdd, host->dpm_state == CARDSLEEP); 1783 if (mmc_card_can_sleep(host->mmc)) 1784 mmc_card_awake(host->mmc); 1785 1786 dev_dbg(mmc_dev(host->mmc), "%s -> ENABLED\n", 1787 host->dpm_state == CARDSLEEP ? "CARDSLEEP" : "REGSLEEP"); 1788 1789 host->dpm_state = ENABLED; 1790 1791 mmc_release_host(host->mmc); 1792 1793 return 0; 1794 } 1795 1796 /* Handler for [OFF -> ENABLED] transition */ 1797 static int omap_hsmmc_off_to_enabled(struct omap_hsmmc_host *host) 1798 { 1799 clk_enable(host->fclk); 1800 1801 omap_hsmmc_context_restore(host); 1802 omap_hsmmc_conf_bus_power(host); 1803 mmc_power_restore_host(host->mmc); 1804 1805 host->dpm_state = ENABLED; 1806 1807 dev_dbg(mmc_dev(host->mmc), "OFF -> ENABLED\n"); 1808 1809 return 0; 1810 } 1811 1812 /* 1813 * Bring MMC host to ENABLED from any other PM state. 1814 */ 1815 static int omap_hsmmc_enable(struct mmc_host *mmc) 1816 { 1817 struct omap_hsmmc_host *host = mmc_priv(mmc); 1818 1819 switch (host->dpm_state) { 1820 case DISABLED: 1821 return omap_hsmmc_disabled_to_enabled(host); 1822 case CARDSLEEP: 1823 case REGSLEEP: 1824 return omap_hsmmc_sleep_to_enabled(host); 1825 case OFF: 1826 return omap_hsmmc_off_to_enabled(host); 1827 default: 1828 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1829 return -EINVAL; 1830 } 1831 } 1832 1833 /* 1834 * Bring MMC host in PM state (one level deeper). 1835 */ 1836 static int omap_hsmmc_disable(struct mmc_host *mmc, int lazy) 1837 { 1838 struct omap_hsmmc_host *host = mmc_priv(mmc); 1839 1840 switch (host->dpm_state) { 1841 case ENABLED: { 1842 int delay; 1843 1844 delay = omap_hsmmc_enabled_to_disabled(host); 1845 if (lazy || delay < 0) 1846 return delay; 1847 return 0; 1848 } 1849 case DISABLED: 1850 return omap_hsmmc_disabled_to_sleep(host); 1851 case CARDSLEEP: 1852 case REGSLEEP: 1853 return omap_hsmmc_sleep_to_off(host); 1854 default: 1855 dev_dbg(mmc_dev(host->mmc), "UNKNOWN state\n"); 1856 return -EINVAL; 1857 } 1858 } 1859 1860 static int omap_hsmmc_enable_fclk(struct mmc_host *mmc) 1861 { 1862 struct omap_hsmmc_host *host = mmc_priv(mmc); 1863 int err; 1864 1865 err = clk_enable(host->fclk); 1866 if (err) 1867 return err; 1868 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: enabled\n"); 1869 omap_hsmmc_context_restore(host); 1870 return 0; 1871 } 1872 1873 static int omap_hsmmc_disable_fclk(struct mmc_host *mmc, int lazy) 1874 { 1875 struct omap_hsmmc_host *host = mmc_priv(mmc); 1876 1877 omap_hsmmc_context_save(host); 1878 clk_disable(host->fclk); 1879 dev_dbg(mmc_dev(host->mmc), "mmc_fclk: disabled\n"); 1880 return 0; 1881 } 1882 1883 static const struct mmc_host_ops omap_hsmmc_ops = { 1884 .enable = omap_hsmmc_enable_fclk, 1885 .disable = omap_hsmmc_disable_fclk, 1886 .request = omap_hsmmc_request, 1887 .set_ios = omap_hsmmc_set_ios, 1888 .get_cd = omap_hsmmc_get_cd, 1889 .get_ro = omap_hsmmc_get_ro, 1890 .init_card = omap_hsmmc_init_card, 1891 /* NYET -- enable_sdio_irq */ 1892 }; 1893 1894 static const struct mmc_host_ops omap_hsmmc_ps_ops = { 1895 .enable = omap_hsmmc_enable, 1896 .disable = omap_hsmmc_disable, 1897 .request = omap_hsmmc_request, 1898 .set_ios = omap_hsmmc_set_ios, 1899 .get_cd = omap_hsmmc_get_cd, 1900 .get_ro = omap_hsmmc_get_ro, 1901 .init_card = omap_hsmmc_init_card, 1902 /* NYET -- enable_sdio_irq */ 1903 }; 1904 1905 #ifdef CONFIG_DEBUG_FS 1906 1907 static int omap_hsmmc_regs_show(struct seq_file *s, void *data) 1908 { 1909 struct mmc_host *mmc = s->private; 1910 struct omap_hsmmc_host *host = mmc_priv(mmc); 1911 int context_loss = 0; 1912 1913 if (host->pdata->get_context_loss_count) 1914 context_loss = host->pdata->get_context_loss_count(host->dev); 1915 1916 seq_printf(s, "mmc%d:\n" 1917 " enabled:\t%d\n" 1918 " dpm_state:\t%d\n" 1919 " nesting_cnt:\t%d\n" 1920 " ctx_loss:\t%d:%d\n" 1921 "\nregs:\n", 1922 mmc->index, mmc->enabled ? 1 : 0, 1923 host->dpm_state, mmc->nesting_cnt, 1924 host->context_loss, context_loss); 1925 1926 if (host->suspended || host->dpm_state == OFF) { 1927 seq_printf(s, "host suspended, can't read registers\n"); 1928 return 0; 1929 } 1930 1931 if (clk_enable(host->fclk) != 0) { 1932 seq_printf(s, "can't read the regs\n"); 1933 return 0; 1934 } 1935 1936 seq_printf(s, "SYSCONFIG:\t0x%08x\n", 1937 OMAP_HSMMC_READ(host->base, SYSCONFIG)); 1938 seq_printf(s, "CON:\t\t0x%08x\n", 1939 OMAP_HSMMC_READ(host->base, CON)); 1940 seq_printf(s, "HCTL:\t\t0x%08x\n", 1941 OMAP_HSMMC_READ(host->base, HCTL)); 1942 seq_printf(s, "SYSCTL:\t\t0x%08x\n", 1943 OMAP_HSMMC_READ(host->base, SYSCTL)); 1944 seq_printf(s, "IE:\t\t0x%08x\n", 1945 OMAP_HSMMC_READ(host->base, IE)); 1946 seq_printf(s, "ISE:\t\t0x%08x\n", 1947 OMAP_HSMMC_READ(host->base, ISE)); 1948 seq_printf(s, "CAPA:\t\t0x%08x\n", 1949 OMAP_HSMMC_READ(host->base, CAPA)); 1950 1951 clk_disable(host->fclk); 1952 1953 return 0; 1954 } 1955 1956 static int omap_hsmmc_regs_open(struct inode *inode, struct file *file) 1957 { 1958 return single_open(file, omap_hsmmc_regs_show, inode->i_private); 1959 } 1960 1961 static const struct file_operations mmc_regs_fops = { 1962 .open = omap_hsmmc_regs_open, 1963 .read = seq_read, 1964 .llseek = seq_lseek, 1965 .release = single_release, 1966 }; 1967 1968 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1969 { 1970 if (mmc->debugfs_root) 1971 debugfs_create_file("regs", S_IRUSR, mmc->debugfs_root, 1972 mmc, &mmc_regs_fops); 1973 } 1974 1975 #else 1976 1977 static void omap_hsmmc_debugfs(struct mmc_host *mmc) 1978 { 1979 } 1980 1981 #endif 1982 1983 static int __init omap_hsmmc_probe(struct platform_device *pdev) 1984 { 1985 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1986 struct mmc_host *mmc; 1987 struct omap_hsmmc_host *host = NULL; 1988 struct resource *res; 1989 int ret, irq; 1990 1991 if (pdata == NULL) { 1992 dev_err(&pdev->dev, "Platform Data is missing\n"); 1993 return -ENXIO; 1994 } 1995 1996 if (pdata->nr_slots == 0) { 1997 dev_err(&pdev->dev, "No Slots\n"); 1998 return -ENXIO; 1999 } 2000 2001 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2002 irq = platform_get_irq(pdev, 0); 2003 if (res == NULL || irq < 0) 2004 return -ENXIO; 2005 2006 res = request_mem_region(res->start, res->end - res->start + 1, 2007 pdev->name); 2008 if (res == NULL) 2009 return -EBUSY; 2010 2011 ret = omap_hsmmc_gpio_init(pdata); 2012 if (ret) 2013 goto err; 2014 2015 mmc = mmc_alloc_host(sizeof(struct omap_hsmmc_host), &pdev->dev); 2016 if (!mmc) { 2017 ret = -ENOMEM; 2018 goto err_alloc; 2019 } 2020 2021 host = mmc_priv(mmc); 2022 host->mmc = mmc; 2023 host->pdata = pdata; 2024 host->dev = &pdev->dev; 2025 host->use_dma = 1; 2026 host->dev->dma_mask = &pdata->dma_mask; 2027 host->dma_ch = -1; 2028 host->irq = irq; 2029 host->id = pdev->id; 2030 host->slot_id = 0; 2031 host->mapbase = res->start; 2032 host->base = ioremap(host->mapbase, SZ_4K); 2033 host->power_mode = MMC_POWER_OFF; 2034 2035 platform_set_drvdata(pdev, host); 2036 INIT_WORK(&host->mmc_carddetect_work, omap_hsmmc_detect); 2037 2038 if (mmc_slot(host).power_saving) 2039 mmc->ops = &omap_hsmmc_ps_ops; 2040 else 2041 mmc->ops = &omap_hsmmc_ops; 2042 2043 /* 2044 * If regulator_disable can only put vcc_aux to sleep then there is 2045 * no off state. 2046 */ 2047 if (mmc_slot(host).vcc_aux_disable_is_sleep) 2048 mmc_slot(host).no_off = 1; 2049 2050 mmc->f_min = 400000; 2051 mmc->f_max = 52000000; 2052 2053 spin_lock_init(&host->irq_lock); 2054 2055 host->iclk = clk_get(&pdev->dev, "ick"); 2056 if (IS_ERR(host->iclk)) { 2057 ret = PTR_ERR(host->iclk); 2058 host->iclk = NULL; 2059 goto err1; 2060 } 2061 host->fclk = clk_get(&pdev->dev, "fck"); 2062 if (IS_ERR(host->fclk)) { 2063 ret = PTR_ERR(host->fclk); 2064 host->fclk = NULL; 2065 clk_put(host->iclk); 2066 goto err1; 2067 } 2068 2069 omap_hsmmc_context_save(host); 2070 2071 mmc->caps |= MMC_CAP_DISABLE; 2072 mmc_set_disable_delay(mmc, OMAP_MMC_DISABLED_TIMEOUT); 2073 /* we start off in DISABLED state */ 2074 host->dpm_state = DISABLED; 2075 2076 if (mmc_host_enable(host->mmc) != 0) { 2077 clk_put(host->iclk); 2078 clk_put(host->fclk); 2079 goto err1; 2080 } 2081 2082 if (clk_enable(host->iclk) != 0) { 2083 mmc_host_disable(host->mmc); 2084 clk_put(host->iclk); 2085 clk_put(host->fclk); 2086 goto err1; 2087 } 2088 2089 if (cpu_is_omap2430()) { 2090 host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck"); 2091 /* 2092 * MMC can still work without debounce clock. 2093 */ 2094 if (IS_ERR(host->dbclk)) 2095 dev_warn(mmc_dev(host->mmc), 2096 "Failed to get debounce clock\n"); 2097 else 2098 host->got_dbclk = 1; 2099 2100 if (host->got_dbclk) 2101 if (clk_enable(host->dbclk) != 0) 2102 dev_dbg(mmc_dev(host->mmc), "Enabling debounce" 2103 " clk failed\n"); 2104 } 2105 2106 /* Since we do only SG emulation, we can have as many segs 2107 * as we want. */ 2108 mmc->max_phys_segs = 1024; 2109 mmc->max_hw_segs = 1024; 2110 2111 mmc->max_blk_size = 512; /* Block Length at max can be 1024 */ 2112 mmc->max_blk_count = 0xFFFF; /* No. of Blocks is 16 bits */ 2113 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 2114 mmc->max_seg_size = mmc->max_req_size; 2115 2116 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 2117 MMC_CAP_WAIT_WHILE_BUSY | MMC_CAP_ERASE; 2118 2119 switch (mmc_slot(host).wires) { 2120 case 8: 2121 mmc->caps |= MMC_CAP_8_BIT_DATA; 2122 /* Fall through */ 2123 case 4: 2124 mmc->caps |= MMC_CAP_4_BIT_DATA; 2125 break; 2126 case 1: 2127 /* Nothing to crib here */ 2128 case 0: 2129 /* Assuming nothing was given by board, Core use's 1-Bit */ 2130 break; 2131 default: 2132 /* Completely unexpected.. Core goes with 1-Bit Width */ 2133 dev_crit(mmc_dev(host->mmc), "Invalid width %d\n used!" 2134 "using 1 instead\n", mmc_slot(host).wires); 2135 } 2136 2137 if (mmc_slot(host).nonremovable) 2138 mmc->caps |= MMC_CAP_NONREMOVABLE; 2139 2140 omap_hsmmc_conf_bus_power(host); 2141 2142 /* Select DMA lines */ 2143 switch (host->id) { 2144 case OMAP_MMC1_DEVID: 2145 host->dma_line_tx = OMAP24XX_DMA_MMC1_TX; 2146 host->dma_line_rx = OMAP24XX_DMA_MMC1_RX; 2147 break; 2148 case OMAP_MMC2_DEVID: 2149 host->dma_line_tx = OMAP24XX_DMA_MMC2_TX; 2150 host->dma_line_rx = OMAP24XX_DMA_MMC2_RX; 2151 break; 2152 case OMAP_MMC3_DEVID: 2153 host->dma_line_tx = OMAP34XX_DMA_MMC3_TX; 2154 host->dma_line_rx = OMAP34XX_DMA_MMC3_RX; 2155 break; 2156 case OMAP_MMC4_DEVID: 2157 host->dma_line_tx = OMAP44XX_DMA_MMC4_TX; 2158 host->dma_line_rx = OMAP44XX_DMA_MMC4_RX; 2159 break; 2160 case OMAP_MMC5_DEVID: 2161 host->dma_line_tx = OMAP44XX_DMA_MMC5_TX; 2162 host->dma_line_rx = OMAP44XX_DMA_MMC5_RX; 2163 break; 2164 default: 2165 dev_err(mmc_dev(host->mmc), "Invalid MMC id\n"); 2166 goto err_irq; 2167 } 2168 2169 /* Request IRQ for MMC operations */ 2170 ret = request_irq(host->irq, omap_hsmmc_irq, IRQF_DISABLED, 2171 mmc_hostname(mmc), host); 2172 if (ret) { 2173 dev_dbg(mmc_dev(host->mmc), "Unable to grab HSMMC IRQ\n"); 2174 goto err_irq; 2175 } 2176 2177 if (pdata->init != NULL) { 2178 if (pdata->init(&pdev->dev) != 0) { 2179 dev_dbg(mmc_dev(host->mmc), 2180 "Unable to configure MMC IRQs\n"); 2181 goto err_irq_cd_init; 2182 } 2183 } 2184 2185 if (omap_hsmmc_have_reg() && !mmc_slot(host).set_power) { 2186 ret = omap_hsmmc_reg_get(host); 2187 if (ret) 2188 goto err_reg; 2189 host->use_reg = 1; 2190 } 2191 2192 mmc->ocr_avail = mmc_slot(host).ocr_mask; 2193 2194 /* Request IRQ for card detect */ 2195 if ((mmc_slot(host).card_detect_irq)) { 2196 ret = request_irq(mmc_slot(host).card_detect_irq, 2197 omap_hsmmc_cd_handler, 2198 IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING 2199 | IRQF_DISABLED, 2200 mmc_hostname(mmc), host); 2201 if (ret) { 2202 dev_dbg(mmc_dev(host->mmc), 2203 "Unable to grab MMC CD IRQ\n"); 2204 goto err_irq_cd; 2205 } 2206 } 2207 2208 omap_hsmmc_disable_irq(host); 2209 2210 mmc_host_lazy_disable(host->mmc); 2211 2212 omap_hsmmc_protect_card(host); 2213 2214 mmc_add_host(mmc); 2215 2216 if (mmc_slot(host).name != NULL) { 2217 ret = device_create_file(&mmc->class_dev, &dev_attr_slot_name); 2218 if (ret < 0) 2219 goto err_slot_name; 2220 } 2221 if (mmc_slot(host).card_detect_irq && mmc_slot(host).get_cover_state) { 2222 ret = device_create_file(&mmc->class_dev, 2223 &dev_attr_cover_switch); 2224 if (ret < 0) 2225 goto err_slot_name; 2226 } 2227 2228 omap_hsmmc_debugfs(mmc); 2229 2230 return 0; 2231 2232 err_slot_name: 2233 mmc_remove_host(mmc); 2234 free_irq(mmc_slot(host).card_detect_irq, host); 2235 err_irq_cd: 2236 if (host->use_reg) 2237 omap_hsmmc_reg_put(host); 2238 err_reg: 2239 if (host->pdata->cleanup) 2240 host->pdata->cleanup(&pdev->dev); 2241 err_irq_cd_init: 2242 free_irq(host->irq, host); 2243 err_irq: 2244 mmc_host_disable(host->mmc); 2245 clk_disable(host->iclk); 2246 clk_put(host->fclk); 2247 clk_put(host->iclk); 2248 if (host->got_dbclk) { 2249 clk_disable(host->dbclk); 2250 clk_put(host->dbclk); 2251 } 2252 err1: 2253 iounmap(host->base); 2254 platform_set_drvdata(pdev, NULL); 2255 mmc_free_host(mmc); 2256 err_alloc: 2257 omap_hsmmc_gpio_free(pdata); 2258 err: 2259 release_mem_region(res->start, res->end - res->start + 1); 2260 return ret; 2261 } 2262 2263 static int omap_hsmmc_remove(struct platform_device *pdev) 2264 { 2265 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2266 struct resource *res; 2267 2268 if (host) { 2269 mmc_host_enable(host->mmc); 2270 mmc_remove_host(host->mmc); 2271 if (host->use_reg) 2272 omap_hsmmc_reg_put(host); 2273 if (host->pdata->cleanup) 2274 host->pdata->cleanup(&pdev->dev); 2275 free_irq(host->irq, host); 2276 if (mmc_slot(host).card_detect_irq) 2277 free_irq(mmc_slot(host).card_detect_irq, host); 2278 flush_scheduled_work(); 2279 2280 mmc_host_disable(host->mmc); 2281 clk_disable(host->iclk); 2282 clk_put(host->fclk); 2283 clk_put(host->iclk); 2284 if (host->got_dbclk) { 2285 clk_disable(host->dbclk); 2286 clk_put(host->dbclk); 2287 } 2288 2289 mmc_free_host(host->mmc); 2290 iounmap(host->base); 2291 omap_hsmmc_gpio_free(pdev->dev.platform_data); 2292 } 2293 2294 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2295 if (res) 2296 release_mem_region(res->start, res->end - res->start + 1); 2297 platform_set_drvdata(pdev, NULL); 2298 2299 return 0; 2300 } 2301 2302 #ifdef CONFIG_PM 2303 static int omap_hsmmc_suspend(struct device *dev) 2304 { 2305 int ret = 0; 2306 struct platform_device *pdev = to_platform_device(dev); 2307 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2308 pm_message_t state = PMSG_SUSPEND; /* unused by MMC core */ 2309 2310 if (host && host->suspended) 2311 return 0; 2312 2313 if (host) { 2314 host->suspended = 1; 2315 if (host->pdata->suspend) { 2316 ret = host->pdata->suspend(&pdev->dev, 2317 host->slot_id); 2318 if (ret) { 2319 dev_dbg(mmc_dev(host->mmc), 2320 "Unable to handle MMC board" 2321 " level suspend\n"); 2322 host->suspended = 0; 2323 return ret; 2324 } 2325 } 2326 cancel_work_sync(&host->mmc_carddetect_work); 2327 mmc_host_enable(host->mmc); 2328 ret = mmc_suspend_host(host->mmc); 2329 if (ret == 0) { 2330 omap_hsmmc_disable_irq(host); 2331 OMAP_HSMMC_WRITE(host->base, HCTL, 2332 OMAP_HSMMC_READ(host->base, HCTL) & ~SDBP); 2333 mmc_host_disable(host->mmc); 2334 clk_disable(host->iclk); 2335 if (host->got_dbclk) 2336 clk_disable(host->dbclk); 2337 } else { 2338 host->suspended = 0; 2339 if (host->pdata->resume) { 2340 ret = host->pdata->resume(&pdev->dev, 2341 host->slot_id); 2342 if (ret) 2343 dev_dbg(mmc_dev(host->mmc), 2344 "Unmask interrupt failed\n"); 2345 } 2346 mmc_host_disable(host->mmc); 2347 } 2348 2349 } 2350 return ret; 2351 } 2352 2353 /* Routine to resume the MMC device */ 2354 static int omap_hsmmc_resume(struct device *dev) 2355 { 2356 int ret = 0; 2357 struct platform_device *pdev = to_platform_device(dev); 2358 struct omap_hsmmc_host *host = platform_get_drvdata(pdev); 2359 2360 if (host && !host->suspended) 2361 return 0; 2362 2363 if (host) { 2364 ret = clk_enable(host->iclk); 2365 if (ret) 2366 goto clk_en_err; 2367 2368 if (mmc_host_enable(host->mmc) != 0) { 2369 clk_disable(host->iclk); 2370 goto clk_en_err; 2371 } 2372 2373 if (host->got_dbclk) 2374 clk_enable(host->dbclk); 2375 2376 omap_hsmmc_conf_bus_power(host); 2377 2378 if (host->pdata->resume) { 2379 ret = host->pdata->resume(&pdev->dev, host->slot_id); 2380 if (ret) 2381 dev_dbg(mmc_dev(host->mmc), 2382 "Unmask interrupt failed\n"); 2383 } 2384 2385 omap_hsmmc_protect_card(host); 2386 2387 /* Notify the core to resume the host */ 2388 ret = mmc_resume_host(host->mmc); 2389 if (ret == 0) 2390 host->suspended = 0; 2391 2392 mmc_host_lazy_disable(host->mmc); 2393 } 2394 2395 return ret; 2396 2397 clk_en_err: 2398 dev_dbg(mmc_dev(host->mmc), 2399 "Failed to enable MMC clocks during resume\n"); 2400 return ret; 2401 } 2402 2403 #else 2404 #define omap_hsmmc_suspend NULL 2405 #define omap_hsmmc_resume NULL 2406 #endif 2407 2408 static struct dev_pm_ops omap_hsmmc_dev_pm_ops = { 2409 .suspend = omap_hsmmc_suspend, 2410 .resume = omap_hsmmc_resume, 2411 }; 2412 2413 static struct platform_driver omap_hsmmc_driver = { 2414 .remove = omap_hsmmc_remove, 2415 .driver = { 2416 .name = DRIVER_NAME, 2417 .owner = THIS_MODULE, 2418 .pm = &omap_hsmmc_dev_pm_ops, 2419 }, 2420 }; 2421 2422 static int __init omap_hsmmc_init(void) 2423 { 2424 /* Register the MMC driver */ 2425 return platform_driver_probe(&omap_hsmmc_driver, omap_hsmmc_probe); 2426 } 2427 2428 static void __exit omap_hsmmc_cleanup(void) 2429 { 2430 /* Unregister MMC driver */ 2431 platform_driver_unregister(&omap_hsmmc_driver); 2432 } 2433 2434 module_init(omap_hsmmc_init); 2435 module_exit(omap_hsmmc_cleanup); 2436 2437 MODULE_DESCRIPTION("OMAP High Speed Multimedia Card driver"); 2438 MODULE_LICENSE("GPL"); 2439 MODULE_ALIAS("platform:" DRIVER_NAME); 2440 MODULE_AUTHOR("Texas Instruments Inc"); 2441