1 /* 2 * linux/drivers/mmc/host/omap.c 3 * 4 * Copyright (C) 2004 Nokia Corporation 5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com> 6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com> 7 * Other hacks (DMA, SD, etc) by David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/ioport.h> 18 #include <linux/platform_device.h> 19 #include <linux/interrupt.h> 20 #include <linux/dmaengine.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/delay.h> 23 #include <linux/spinlock.h> 24 #include <linux/timer.h> 25 #include <linux/omap-dma.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/card.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/i2c/tps65010.h> 31 #include <linux/slab.h> 32 33 #include <asm/io.h> 34 #include <asm/irq.h> 35 36 #include <plat/board.h> 37 #include <plat/mmc.h> 38 #include <asm/gpio.h> 39 #include <plat/dma.h> 40 #include <plat/mux.h> 41 #include <plat/fpga.h> 42 43 #define OMAP_MMC_REG_CMD 0x00 44 #define OMAP_MMC_REG_ARGL 0x01 45 #define OMAP_MMC_REG_ARGH 0x02 46 #define OMAP_MMC_REG_CON 0x03 47 #define OMAP_MMC_REG_STAT 0x04 48 #define OMAP_MMC_REG_IE 0x05 49 #define OMAP_MMC_REG_CTO 0x06 50 #define OMAP_MMC_REG_DTO 0x07 51 #define OMAP_MMC_REG_DATA 0x08 52 #define OMAP_MMC_REG_BLEN 0x09 53 #define OMAP_MMC_REG_NBLK 0x0a 54 #define OMAP_MMC_REG_BUF 0x0b 55 #define OMAP_MMC_REG_SDIO 0x0d 56 #define OMAP_MMC_REG_REV 0x0f 57 #define OMAP_MMC_REG_RSP0 0x10 58 #define OMAP_MMC_REG_RSP1 0x11 59 #define OMAP_MMC_REG_RSP2 0x12 60 #define OMAP_MMC_REG_RSP3 0x13 61 #define OMAP_MMC_REG_RSP4 0x14 62 #define OMAP_MMC_REG_RSP5 0x15 63 #define OMAP_MMC_REG_RSP6 0x16 64 #define OMAP_MMC_REG_RSP7 0x17 65 #define OMAP_MMC_REG_IOSR 0x18 66 #define OMAP_MMC_REG_SYSC 0x19 67 #define OMAP_MMC_REG_SYSS 0x1a 68 69 #define OMAP_MMC_STAT_CARD_ERR (1 << 14) 70 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13) 71 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12) 72 #define OMAP_MMC_STAT_A_EMPTY (1 << 11) 73 #define OMAP_MMC_STAT_A_FULL (1 << 10) 74 #define OMAP_MMC_STAT_CMD_CRC (1 << 8) 75 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7) 76 #define OMAP_MMC_STAT_DATA_CRC (1 << 6) 77 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5) 78 #define OMAP_MMC_STAT_END_BUSY (1 << 4) 79 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3) 80 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2) 81 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0) 82 83 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift) 84 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg)) 85 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) 86 87 /* 88 * Command types 89 */ 90 #define OMAP_MMC_CMDTYPE_BC 0 91 #define OMAP_MMC_CMDTYPE_BCR 1 92 #define OMAP_MMC_CMDTYPE_AC 2 93 #define OMAP_MMC_CMDTYPE_ADTC 3 94 95 96 #define DRIVER_NAME "mmci-omap" 97 98 /* Specifies how often in millisecs to poll for card status changes 99 * when the cover switch is open */ 100 #define OMAP_MMC_COVER_POLL_DELAY 500 101 102 struct mmc_omap_host; 103 104 struct mmc_omap_slot { 105 int id; 106 unsigned int vdd; 107 u16 saved_con; 108 u16 bus_mode; 109 unsigned int fclk_freq; 110 unsigned powered:1; 111 112 struct tasklet_struct cover_tasklet; 113 struct timer_list cover_timer; 114 unsigned cover_open; 115 116 struct mmc_request *mrq; 117 struct mmc_omap_host *host; 118 struct mmc_host *mmc; 119 struct omap_mmc_slot_data *pdata; 120 }; 121 122 struct mmc_omap_host { 123 int initialized; 124 int suspended; 125 struct mmc_request * mrq; 126 struct mmc_command * cmd; 127 struct mmc_data * data; 128 struct mmc_host * mmc; 129 struct device * dev; 130 unsigned char id; /* 16xx chips have 2 MMC blocks */ 131 struct clk * iclk; 132 struct clk * fclk; 133 struct dma_chan *dma_rx; 134 u32 dma_rx_burst; 135 struct dma_chan *dma_tx; 136 u32 dma_tx_burst; 137 struct resource *mem_res; 138 void __iomem *virt_base; 139 unsigned int phys_base; 140 int irq; 141 unsigned char bus_mode; 142 unsigned char hw_bus_mode; 143 unsigned int reg_shift; 144 145 struct work_struct cmd_abort_work; 146 unsigned abort:1; 147 struct timer_list cmd_abort_timer; 148 149 struct work_struct slot_release_work; 150 struct mmc_omap_slot *next_slot; 151 struct work_struct send_stop_work; 152 struct mmc_data *stop_data; 153 154 unsigned int sg_len; 155 int sg_idx; 156 u16 * buffer; 157 u32 buffer_bytes_left; 158 u32 total_bytes_left; 159 160 unsigned use_dma:1; 161 unsigned brs_received:1, dma_done:1; 162 unsigned dma_in_use:1; 163 spinlock_t dma_lock; 164 165 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS]; 166 struct mmc_omap_slot *current_slot; 167 spinlock_t slot_lock; 168 wait_queue_head_t slot_wq; 169 int nr_slots; 170 171 struct timer_list clk_timer; 172 spinlock_t clk_lock; /* for changing enabled state */ 173 unsigned int fclk_enabled:1; 174 struct workqueue_struct *mmc_omap_wq; 175 176 struct omap_mmc_platform_data *pdata; 177 }; 178 179 180 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) 181 { 182 unsigned long tick_ns; 183 184 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { 185 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq; 186 ndelay(8 * tick_ns); 187 } 188 } 189 190 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable) 191 { 192 unsigned long flags; 193 194 spin_lock_irqsave(&host->clk_lock, flags); 195 if (host->fclk_enabled != enable) { 196 host->fclk_enabled = enable; 197 if (enable) 198 clk_enable(host->fclk); 199 else 200 clk_disable(host->fclk); 201 } 202 spin_unlock_irqrestore(&host->clk_lock, flags); 203 } 204 205 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed) 206 { 207 struct mmc_omap_host *host = slot->host; 208 unsigned long flags; 209 210 if (claimed) 211 goto no_claim; 212 spin_lock_irqsave(&host->slot_lock, flags); 213 while (host->mmc != NULL) { 214 spin_unlock_irqrestore(&host->slot_lock, flags); 215 wait_event(host->slot_wq, host->mmc == NULL); 216 spin_lock_irqsave(&host->slot_lock, flags); 217 } 218 host->mmc = slot->mmc; 219 spin_unlock_irqrestore(&host->slot_lock, flags); 220 no_claim: 221 del_timer(&host->clk_timer); 222 if (host->current_slot != slot || !claimed) 223 mmc_omap_fclk_offdelay(host->current_slot); 224 225 if (host->current_slot != slot) { 226 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00); 227 if (host->pdata->switch_slot != NULL) 228 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id); 229 host->current_slot = slot; 230 } 231 232 if (claimed) { 233 mmc_omap_fclk_enable(host, 1); 234 235 /* Doing the dummy read here seems to work around some bug 236 * at least in OMAP24xx silicon where the command would not 237 * start after writing the CMD register. Sigh. */ 238 OMAP_MMC_READ(host, CON); 239 240 OMAP_MMC_WRITE(host, CON, slot->saved_con); 241 } else 242 mmc_omap_fclk_enable(host, 0); 243 } 244 245 static void mmc_omap_start_request(struct mmc_omap_host *host, 246 struct mmc_request *req); 247 248 static void mmc_omap_slot_release_work(struct work_struct *work) 249 { 250 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 251 slot_release_work); 252 struct mmc_omap_slot *next_slot = host->next_slot; 253 struct mmc_request *rq; 254 255 host->next_slot = NULL; 256 mmc_omap_select_slot(next_slot, 1); 257 258 rq = next_slot->mrq; 259 next_slot->mrq = NULL; 260 mmc_omap_start_request(host, rq); 261 } 262 263 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled) 264 { 265 struct mmc_omap_host *host = slot->host; 266 unsigned long flags; 267 int i; 268 269 BUG_ON(slot == NULL || host->mmc == NULL); 270 271 if (clk_enabled) 272 /* Keeps clock running for at least 8 cycles on valid freq */ 273 mod_timer(&host->clk_timer, jiffies + HZ/10); 274 else { 275 del_timer(&host->clk_timer); 276 mmc_omap_fclk_offdelay(slot); 277 mmc_omap_fclk_enable(host, 0); 278 } 279 280 spin_lock_irqsave(&host->slot_lock, flags); 281 /* Check for any pending requests */ 282 for (i = 0; i < host->nr_slots; i++) { 283 struct mmc_omap_slot *new_slot; 284 285 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL) 286 continue; 287 288 BUG_ON(host->next_slot != NULL); 289 new_slot = host->slots[i]; 290 /* The current slot should not have a request in queue */ 291 BUG_ON(new_slot == host->current_slot); 292 293 host->next_slot = new_slot; 294 host->mmc = new_slot->mmc; 295 spin_unlock_irqrestore(&host->slot_lock, flags); 296 queue_work(host->mmc_omap_wq, &host->slot_release_work); 297 return; 298 } 299 300 host->mmc = NULL; 301 wake_up(&host->slot_wq); 302 spin_unlock_irqrestore(&host->slot_lock, flags); 303 } 304 305 static inline 306 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot) 307 { 308 if (slot->pdata->get_cover_state) 309 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), 310 slot->id); 311 return 0; 312 } 313 314 static ssize_t 315 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, 316 char *buf) 317 { 318 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 319 struct mmc_omap_slot *slot = mmc_priv(mmc); 320 321 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" : 322 "closed"); 323 } 324 325 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); 326 327 static ssize_t 328 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, 329 char *buf) 330 { 331 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 332 struct mmc_omap_slot *slot = mmc_priv(mmc); 333 334 return sprintf(buf, "%s\n", slot->pdata->name); 335 } 336 337 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); 338 339 static void 340 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) 341 { 342 u32 cmdreg; 343 u32 resptype; 344 u32 cmdtype; 345 346 host->cmd = cmd; 347 348 resptype = 0; 349 cmdtype = 0; 350 351 /* Our hardware needs to know exact type */ 352 switch (mmc_resp_type(cmd)) { 353 case MMC_RSP_NONE: 354 break; 355 case MMC_RSP_R1: 356 case MMC_RSP_R1B: 357 /* resp 1, 1b, 6, 7 */ 358 resptype = 1; 359 break; 360 case MMC_RSP_R2: 361 resptype = 2; 362 break; 363 case MMC_RSP_R3: 364 resptype = 3; 365 break; 366 default: 367 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd)); 368 break; 369 } 370 371 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { 372 cmdtype = OMAP_MMC_CMDTYPE_ADTC; 373 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) { 374 cmdtype = OMAP_MMC_CMDTYPE_BC; 375 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) { 376 cmdtype = OMAP_MMC_CMDTYPE_BCR; 377 } else { 378 cmdtype = OMAP_MMC_CMDTYPE_AC; 379 } 380 381 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12); 382 383 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN) 384 cmdreg |= 1 << 6; 385 386 if (cmd->flags & MMC_RSP_BUSY) 387 cmdreg |= 1 << 11; 388 389 if (host->data && !(host->data->flags & MMC_DATA_WRITE)) 390 cmdreg |= 1 << 15; 391 392 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2); 393 394 OMAP_MMC_WRITE(host, CTO, 200); 395 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); 396 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); 397 OMAP_MMC_WRITE(host, IE, 398 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | 399 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | 400 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | 401 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | 402 OMAP_MMC_STAT_END_OF_DATA); 403 OMAP_MMC_WRITE(host, CMD, cmdreg); 404 } 405 406 static void 407 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data, 408 int abort) 409 { 410 enum dma_data_direction dma_data_dir; 411 struct device *dev = mmc_dev(host->mmc); 412 struct dma_chan *c; 413 414 if (data->flags & MMC_DATA_WRITE) { 415 dma_data_dir = DMA_TO_DEVICE; 416 c = host->dma_tx; 417 } else { 418 dma_data_dir = DMA_FROM_DEVICE; 419 c = host->dma_rx; 420 } 421 if (c) { 422 if (data->error) { 423 dmaengine_terminate_all(c); 424 /* Claim nothing transferred on error... */ 425 data->bytes_xfered = 0; 426 } 427 dev = c->device->dev; 428 } 429 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir); 430 } 431 432 static void mmc_omap_send_stop_work(struct work_struct *work) 433 { 434 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 435 send_stop_work); 436 struct mmc_omap_slot *slot = host->current_slot; 437 struct mmc_data *data = host->stop_data; 438 unsigned long tick_ns; 439 440 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq; 441 ndelay(8*tick_ns); 442 443 mmc_omap_start_command(host, data->stop); 444 } 445 446 static void 447 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) 448 { 449 if (host->dma_in_use) 450 mmc_omap_release_dma(host, data, data->error); 451 452 host->data = NULL; 453 host->sg_len = 0; 454 455 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing 456 * dozens of requests until the card finishes writing data. 457 * It'd be cheaper to just wait till an EOFB interrupt arrives... 458 */ 459 460 if (!data->stop) { 461 struct mmc_host *mmc; 462 463 host->mrq = NULL; 464 mmc = host->mmc; 465 mmc_omap_release_slot(host->current_slot, 1); 466 mmc_request_done(mmc, data->mrq); 467 return; 468 } 469 470 host->stop_data = data; 471 queue_work(host->mmc_omap_wq, &host->send_stop_work); 472 } 473 474 static void 475 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops) 476 { 477 struct mmc_omap_slot *slot = host->current_slot; 478 unsigned int restarts, passes, timeout; 479 u16 stat = 0; 480 481 /* Sending abort takes 80 clocks. Have some extra and round up */ 482 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq; 483 restarts = 0; 484 while (restarts < maxloops) { 485 OMAP_MMC_WRITE(host, STAT, 0xFFFF); 486 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7)); 487 488 passes = 0; 489 while (passes < timeout) { 490 stat = OMAP_MMC_READ(host, STAT); 491 if (stat & OMAP_MMC_STAT_END_OF_CMD) 492 goto out; 493 udelay(1); 494 passes++; 495 } 496 497 restarts++; 498 } 499 out: 500 OMAP_MMC_WRITE(host, STAT, stat); 501 } 502 503 static void 504 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data) 505 { 506 if (host->dma_in_use) 507 mmc_omap_release_dma(host, data, 1); 508 509 host->data = NULL; 510 host->sg_len = 0; 511 512 mmc_omap_send_abort(host, 10000); 513 } 514 515 static void 516 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data) 517 { 518 unsigned long flags; 519 int done; 520 521 if (!host->dma_in_use) { 522 mmc_omap_xfer_done(host, data); 523 return; 524 } 525 done = 0; 526 spin_lock_irqsave(&host->dma_lock, flags); 527 if (host->dma_done) 528 done = 1; 529 else 530 host->brs_received = 1; 531 spin_unlock_irqrestore(&host->dma_lock, flags); 532 if (done) 533 mmc_omap_xfer_done(host, data); 534 } 535 536 static void 537 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data) 538 { 539 unsigned long flags; 540 int done; 541 542 done = 0; 543 spin_lock_irqsave(&host->dma_lock, flags); 544 if (host->brs_received) 545 done = 1; 546 else 547 host->dma_done = 1; 548 spin_unlock_irqrestore(&host->dma_lock, flags); 549 if (done) 550 mmc_omap_xfer_done(host, data); 551 } 552 553 static void 554 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) 555 { 556 host->cmd = NULL; 557 558 del_timer(&host->cmd_abort_timer); 559 560 if (cmd->flags & MMC_RSP_PRESENT) { 561 if (cmd->flags & MMC_RSP_136) { 562 /* response type 2 */ 563 cmd->resp[3] = 564 OMAP_MMC_READ(host, RSP0) | 565 (OMAP_MMC_READ(host, RSP1) << 16); 566 cmd->resp[2] = 567 OMAP_MMC_READ(host, RSP2) | 568 (OMAP_MMC_READ(host, RSP3) << 16); 569 cmd->resp[1] = 570 OMAP_MMC_READ(host, RSP4) | 571 (OMAP_MMC_READ(host, RSP5) << 16); 572 cmd->resp[0] = 573 OMAP_MMC_READ(host, RSP6) | 574 (OMAP_MMC_READ(host, RSP7) << 16); 575 } else { 576 /* response types 1, 1b, 3, 4, 5, 6 */ 577 cmd->resp[0] = 578 OMAP_MMC_READ(host, RSP6) | 579 (OMAP_MMC_READ(host, RSP7) << 16); 580 } 581 } 582 583 if (host->data == NULL || cmd->error) { 584 struct mmc_host *mmc; 585 586 if (host->data != NULL) 587 mmc_omap_abort_xfer(host, host->data); 588 host->mrq = NULL; 589 mmc = host->mmc; 590 mmc_omap_release_slot(host->current_slot, 1); 591 mmc_request_done(mmc, cmd->mrq); 592 } 593 } 594 595 /* 596 * Abort stuck command. Can occur when card is removed while it is being 597 * read. 598 */ 599 static void mmc_omap_abort_command(struct work_struct *work) 600 { 601 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 602 cmd_abort_work); 603 BUG_ON(!host->cmd); 604 605 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n", 606 host->cmd->opcode); 607 608 if (host->cmd->error == 0) 609 host->cmd->error = -ETIMEDOUT; 610 611 if (host->data == NULL) { 612 struct mmc_command *cmd; 613 struct mmc_host *mmc; 614 615 cmd = host->cmd; 616 host->cmd = NULL; 617 mmc_omap_send_abort(host, 10000); 618 619 host->mrq = NULL; 620 mmc = host->mmc; 621 mmc_omap_release_slot(host->current_slot, 1); 622 mmc_request_done(mmc, cmd->mrq); 623 } else 624 mmc_omap_cmd_done(host, host->cmd); 625 626 host->abort = 0; 627 enable_irq(host->irq); 628 } 629 630 static void 631 mmc_omap_cmd_timer(unsigned long data) 632 { 633 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 634 unsigned long flags; 635 636 spin_lock_irqsave(&host->slot_lock, flags); 637 if (host->cmd != NULL && !host->abort) { 638 OMAP_MMC_WRITE(host, IE, 0); 639 disable_irq(host->irq); 640 host->abort = 1; 641 queue_work(host->mmc_omap_wq, &host->cmd_abort_work); 642 } 643 spin_unlock_irqrestore(&host->slot_lock, flags); 644 } 645 646 /* PIO only */ 647 static void 648 mmc_omap_sg_to_buf(struct mmc_omap_host *host) 649 { 650 struct scatterlist *sg; 651 652 sg = host->data->sg + host->sg_idx; 653 host->buffer_bytes_left = sg->length; 654 host->buffer = sg_virt(sg); 655 if (host->buffer_bytes_left > host->total_bytes_left) 656 host->buffer_bytes_left = host->total_bytes_left; 657 } 658 659 static void 660 mmc_omap_clk_timer(unsigned long data) 661 { 662 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 663 664 mmc_omap_fclk_enable(host, 0); 665 } 666 667 /* PIO only */ 668 static void 669 mmc_omap_xfer_data(struct mmc_omap_host *host, int write) 670 { 671 int n, nwords; 672 673 if (host->buffer_bytes_left == 0) { 674 host->sg_idx++; 675 BUG_ON(host->sg_idx == host->sg_len); 676 mmc_omap_sg_to_buf(host); 677 } 678 n = 64; 679 if (n > host->buffer_bytes_left) 680 n = host->buffer_bytes_left; 681 682 nwords = n / 2; 683 nwords += n & 1; /* handle odd number of bytes to transfer */ 684 685 host->buffer_bytes_left -= n; 686 host->total_bytes_left -= n; 687 host->data->bytes_xfered += n; 688 689 if (write) { 690 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), 691 host->buffer, nwords); 692 } else { 693 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), 694 host->buffer, nwords); 695 } 696 697 host->buffer += nwords; 698 } 699 700 static inline void mmc_omap_report_irq(u16 status) 701 { 702 static const char *mmc_omap_status_bits[] = { 703 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", 704 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR" 705 }; 706 int i, c = 0; 707 708 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) 709 if (status & (1 << i)) { 710 if (c) 711 printk(" "); 712 printk("%s", mmc_omap_status_bits[i]); 713 c++; 714 } 715 } 716 717 static irqreturn_t mmc_omap_irq(int irq, void *dev_id) 718 { 719 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id; 720 u16 status; 721 int end_command; 722 int end_transfer; 723 int transfer_error, cmd_error; 724 725 if (host->cmd == NULL && host->data == NULL) { 726 status = OMAP_MMC_READ(host, STAT); 727 dev_info(mmc_dev(host->slots[0]->mmc), 728 "Spurious IRQ 0x%04x\n", status); 729 if (status != 0) { 730 OMAP_MMC_WRITE(host, STAT, status); 731 OMAP_MMC_WRITE(host, IE, 0); 732 } 733 return IRQ_HANDLED; 734 } 735 736 end_command = 0; 737 end_transfer = 0; 738 transfer_error = 0; 739 cmd_error = 0; 740 741 while ((status = OMAP_MMC_READ(host, STAT)) != 0) { 742 int cmd; 743 744 OMAP_MMC_WRITE(host, STAT, status); 745 if (host->cmd != NULL) 746 cmd = host->cmd->opcode; 747 else 748 cmd = -1; 749 #ifdef CONFIG_MMC_DEBUG 750 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", 751 status, cmd); 752 mmc_omap_report_irq(status); 753 printk("\n"); 754 #endif 755 if (host->total_bytes_left) { 756 if ((status & OMAP_MMC_STAT_A_FULL) || 757 (status & OMAP_MMC_STAT_END_OF_DATA)) 758 mmc_omap_xfer_data(host, 0); 759 if (status & OMAP_MMC_STAT_A_EMPTY) 760 mmc_omap_xfer_data(host, 1); 761 } 762 763 if (status & OMAP_MMC_STAT_END_OF_DATA) 764 end_transfer = 1; 765 766 if (status & OMAP_MMC_STAT_DATA_TOUT) { 767 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n", 768 cmd); 769 if (host->data) { 770 host->data->error = -ETIMEDOUT; 771 transfer_error = 1; 772 } 773 } 774 775 if (status & OMAP_MMC_STAT_DATA_CRC) { 776 if (host->data) { 777 host->data->error = -EILSEQ; 778 dev_dbg(mmc_dev(host->mmc), 779 "data CRC error, bytes left %d\n", 780 host->total_bytes_left); 781 transfer_error = 1; 782 } else { 783 dev_dbg(mmc_dev(host->mmc), "data CRC error\n"); 784 } 785 } 786 787 if (status & OMAP_MMC_STAT_CMD_TOUT) { 788 /* Timeouts are routine with some commands */ 789 if (host->cmd) { 790 struct mmc_omap_slot *slot = 791 host->current_slot; 792 if (slot == NULL || 793 !mmc_omap_cover_is_open(slot)) 794 dev_err(mmc_dev(host->mmc), 795 "command timeout (CMD%d)\n", 796 cmd); 797 host->cmd->error = -ETIMEDOUT; 798 end_command = 1; 799 cmd_error = 1; 800 } 801 } 802 803 if (status & OMAP_MMC_STAT_CMD_CRC) { 804 if (host->cmd) { 805 dev_err(mmc_dev(host->mmc), 806 "command CRC error (CMD%d, arg 0x%08x)\n", 807 cmd, host->cmd->arg); 808 host->cmd->error = -EILSEQ; 809 end_command = 1; 810 cmd_error = 1; 811 } else 812 dev_err(mmc_dev(host->mmc), 813 "command CRC error without cmd?\n"); 814 } 815 816 if (status & OMAP_MMC_STAT_CARD_ERR) { 817 dev_dbg(mmc_dev(host->mmc), 818 "ignoring card status error (CMD%d)\n", 819 cmd); 820 end_command = 1; 821 } 822 823 /* 824 * NOTE: On 1610 the END_OF_CMD may come too early when 825 * starting a write 826 */ 827 if ((status & OMAP_MMC_STAT_END_OF_CMD) && 828 (!(status & OMAP_MMC_STAT_A_EMPTY))) { 829 end_command = 1; 830 } 831 } 832 833 if (cmd_error && host->data) { 834 del_timer(&host->cmd_abort_timer); 835 host->abort = 1; 836 OMAP_MMC_WRITE(host, IE, 0); 837 disable_irq_nosync(host->irq); 838 queue_work(host->mmc_omap_wq, &host->cmd_abort_work); 839 return IRQ_HANDLED; 840 } 841 842 if (end_command && host->cmd) 843 mmc_omap_cmd_done(host, host->cmd); 844 if (host->data != NULL) { 845 if (transfer_error) 846 mmc_omap_xfer_done(host, host->data); 847 else if (end_transfer) 848 mmc_omap_end_of_data(host, host->data); 849 } 850 851 return IRQ_HANDLED; 852 } 853 854 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed) 855 { 856 int cover_open; 857 struct mmc_omap_host *host = dev_get_drvdata(dev); 858 struct mmc_omap_slot *slot = host->slots[num]; 859 860 BUG_ON(num >= host->nr_slots); 861 862 /* Other subsystems can call in here before we're initialised. */ 863 if (host->nr_slots == 0 || !host->slots[num]) 864 return; 865 866 cover_open = mmc_omap_cover_is_open(slot); 867 if (cover_open != slot->cover_open) { 868 slot->cover_open = cover_open; 869 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch"); 870 } 871 872 tasklet_hi_schedule(&slot->cover_tasklet); 873 } 874 875 static void mmc_omap_cover_timer(unsigned long arg) 876 { 877 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg; 878 tasklet_schedule(&slot->cover_tasklet); 879 } 880 881 static void mmc_omap_cover_handler(unsigned long param) 882 { 883 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param; 884 int cover_open = mmc_omap_cover_is_open(slot); 885 886 mmc_detect_change(slot->mmc, 0); 887 if (!cover_open) 888 return; 889 890 /* 891 * If no card is inserted, we postpone polling until 892 * the cover has been closed. 893 */ 894 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card)) 895 return; 896 897 mod_timer(&slot->cover_timer, 898 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY)); 899 } 900 901 static void mmc_omap_dma_callback(void *priv) 902 { 903 struct mmc_omap_host *host = priv; 904 struct mmc_data *data = host->data; 905 906 /* If we got to the end of DMA, assume everything went well */ 907 data->bytes_xfered += data->blocks * data->blksz; 908 909 mmc_omap_dma_done(host, data); 910 } 911 912 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req) 913 { 914 u16 reg; 915 916 reg = OMAP_MMC_READ(host, SDIO); 917 reg &= ~(1 << 5); 918 OMAP_MMC_WRITE(host, SDIO, reg); 919 /* Set maximum timeout */ 920 OMAP_MMC_WRITE(host, CTO, 0xff); 921 } 922 923 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) 924 { 925 unsigned int timeout, cycle_ns; 926 u16 reg; 927 928 cycle_ns = 1000000000 / host->current_slot->fclk_freq; 929 timeout = req->data->timeout_ns / cycle_ns; 930 timeout += req->data->timeout_clks; 931 932 /* Check if we need to use timeout multiplier register */ 933 reg = OMAP_MMC_READ(host, SDIO); 934 if (timeout > 0xffff) { 935 reg |= (1 << 5); 936 timeout /= 1024; 937 } else 938 reg &= ~(1 << 5); 939 OMAP_MMC_WRITE(host, SDIO, reg); 940 OMAP_MMC_WRITE(host, DTO, timeout); 941 } 942 943 static void 944 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) 945 { 946 struct mmc_data *data = req->data; 947 int i, use_dma, block_size; 948 unsigned sg_len; 949 950 host->data = data; 951 if (data == NULL) { 952 OMAP_MMC_WRITE(host, BLEN, 0); 953 OMAP_MMC_WRITE(host, NBLK, 0); 954 OMAP_MMC_WRITE(host, BUF, 0); 955 host->dma_in_use = 0; 956 set_cmd_timeout(host, req); 957 return; 958 } 959 960 block_size = data->blksz; 961 962 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); 963 OMAP_MMC_WRITE(host, BLEN, block_size - 1); 964 set_data_timeout(host, req); 965 966 /* cope with calling layer confusion; it issues "single 967 * block" writes using multi-block scatterlists. 968 */ 969 sg_len = (data->blocks == 1) ? 1 : data->sg_len; 970 971 /* Only do DMA for entire blocks */ 972 use_dma = host->use_dma; 973 if (use_dma) { 974 for (i = 0; i < sg_len; i++) { 975 if ((data->sg[i].length % block_size) != 0) { 976 use_dma = 0; 977 break; 978 } 979 } 980 } 981 982 host->sg_idx = 0; 983 if (use_dma) { 984 enum dma_data_direction dma_data_dir; 985 struct dma_async_tx_descriptor *tx; 986 struct dma_chan *c; 987 u32 burst, *bp; 988 u16 buf; 989 990 /* 991 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx 992 * and 24xx. Use 16 or 32 word frames when the 993 * blocksize is at least that large. Blocksize is 994 * usually 512 bytes; but not for some SD reads. 995 */ 996 burst = cpu_is_omap15xx() ? 32 : 64; 997 if (burst > data->blksz) 998 burst = data->blksz; 999 1000 burst >>= 1; 1001 1002 if (data->flags & MMC_DATA_WRITE) { 1003 c = host->dma_tx; 1004 bp = &host->dma_tx_burst; 1005 buf = 0x0f80 | (burst - 1) << 0; 1006 dma_data_dir = DMA_TO_DEVICE; 1007 } else { 1008 c = host->dma_rx; 1009 bp = &host->dma_rx_burst; 1010 buf = 0x800f | (burst - 1) << 8; 1011 dma_data_dir = DMA_FROM_DEVICE; 1012 } 1013 1014 if (!c) 1015 goto use_pio; 1016 1017 /* Only reconfigure if we have a different burst size */ 1018 if (*bp != burst) { 1019 struct dma_slave_config cfg; 1020 1021 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA); 1022 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA); 1023 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1024 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1025 cfg.src_maxburst = burst; 1026 cfg.dst_maxburst = burst; 1027 1028 if (dmaengine_slave_config(c, &cfg)) 1029 goto use_pio; 1030 1031 *bp = burst; 1032 } 1033 1034 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len, 1035 dma_data_dir); 1036 if (host->sg_len == 0) 1037 goto use_pio; 1038 1039 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len, 1040 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1041 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1042 if (!tx) 1043 goto use_pio; 1044 1045 OMAP_MMC_WRITE(host, BUF, buf); 1046 1047 tx->callback = mmc_omap_dma_callback; 1048 tx->callback_param = host; 1049 dmaengine_submit(tx); 1050 host->brs_received = 0; 1051 host->dma_done = 0; 1052 host->dma_in_use = 1; 1053 return; 1054 } 1055 use_pio: 1056 1057 /* Revert to PIO? */ 1058 OMAP_MMC_WRITE(host, BUF, 0x1f1f); 1059 host->total_bytes_left = data->blocks * block_size; 1060 host->sg_len = sg_len; 1061 mmc_omap_sg_to_buf(host); 1062 host->dma_in_use = 0; 1063 } 1064 1065 static void mmc_omap_start_request(struct mmc_omap_host *host, 1066 struct mmc_request *req) 1067 { 1068 BUG_ON(host->mrq != NULL); 1069 1070 host->mrq = req; 1071 1072 /* only touch fifo AFTER the controller readies it */ 1073 mmc_omap_prepare_data(host, req); 1074 mmc_omap_start_command(host, req->cmd); 1075 if (host->dma_in_use) { 1076 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ? 1077 host->dma_tx : host->dma_rx; 1078 1079 dma_async_issue_pending(c); 1080 } 1081 } 1082 1083 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) 1084 { 1085 struct mmc_omap_slot *slot = mmc_priv(mmc); 1086 struct mmc_omap_host *host = slot->host; 1087 unsigned long flags; 1088 1089 spin_lock_irqsave(&host->slot_lock, flags); 1090 if (host->mmc != NULL) { 1091 BUG_ON(slot->mrq != NULL); 1092 slot->mrq = req; 1093 spin_unlock_irqrestore(&host->slot_lock, flags); 1094 return; 1095 } else 1096 host->mmc = mmc; 1097 spin_unlock_irqrestore(&host->slot_lock, flags); 1098 mmc_omap_select_slot(slot, 1); 1099 mmc_omap_start_request(host, req); 1100 } 1101 1102 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on, 1103 int vdd) 1104 { 1105 struct mmc_omap_host *host; 1106 1107 host = slot->host; 1108 1109 if (slot->pdata->set_power != NULL) 1110 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on, 1111 vdd); 1112 1113 if (cpu_is_omap24xx()) { 1114 u16 w; 1115 1116 if (power_on) { 1117 w = OMAP_MMC_READ(host, CON); 1118 OMAP_MMC_WRITE(host, CON, w | (1 << 11)); 1119 } else { 1120 w = OMAP_MMC_READ(host, CON); 1121 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11)); 1122 } 1123 } 1124 } 1125 1126 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios) 1127 { 1128 struct mmc_omap_slot *slot = mmc_priv(mmc); 1129 struct mmc_omap_host *host = slot->host; 1130 int func_clk_rate = clk_get_rate(host->fclk); 1131 int dsor; 1132 1133 if (ios->clock == 0) 1134 return 0; 1135 1136 dsor = func_clk_rate / ios->clock; 1137 if (dsor < 1) 1138 dsor = 1; 1139 1140 if (func_clk_rate / dsor > ios->clock) 1141 dsor++; 1142 1143 if (dsor > 250) 1144 dsor = 250; 1145 1146 slot->fclk_freq = func_clk_rate / dsor; 1147 1148 if (ios->bus_width == MMC_BUS_WIDTH_4) 1149 dsor |= 1 << 15; 1150 1151 return dsor; 1152 } 1153 1154 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1155 { 1156 struct mmc_omap_slot *slot = mmc_priv(mmc); 1157 struct mmc_omap_host *host = slot->host; 1158 int i, dsor; 1159 int clk_enabled; 1160 1161 mmc_omap_select_slot(slot, 0); 1162 1163 dsor = mmc_omap_calc_divisor(mmc, ios); 1164 1165 if (ios->vdd != slot->vdd) 1166 slot->vdd = ios->vdd; 1167 1168 clk_enabled = 0; 1169 switch (ios->power_mode) { 1170 case MMC_POWER_OFF: 1171 mmc_omap_set_power(slot, 0, ios->vdd); 1172 break; 1173 case MMC_POWER_UP: 1174 /* Cannot touch dsor yet, just power up MMC */ 1175 mmc_omap_set_power(slot, 1, ios->vdd); 1176 goto exit; 1177 case MMC_POWER_ON: 1178 mmc_omap_fclk_enable(host, 1); 1179 clk_enabled = 1; 1180 dsor |= 1 << 11; 1181 break; 1182 } 1183 1184 if (slot->bus_mode != ios->bus_mode) { 1185 if (slot->pdata->set_bus_mode != NULL) 1186 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id, 1187 ios->bus_mode); 1188 slot->bus_mode = ios->bus_mode; 1189 } 1190 1191 /* On insanely high arm_per frequencies something sometimes 1192 * goes somehow out of sync, and the POW bit is not being set, 1193 * which results in the while loop below getting stuck. 1194 * Writing to the CON register twice seems to do the trick. */ 1195 for (i = 0; i < 2; i++) 1196 OMAP_MMC_WRITE(host, CON, dsor); 1197 slot->saved_con = dsor; 1198 if (ios->power_mode == MMC_POWER_ON) { 1199 /* worst case at 400kHz, 80 cycles makes 200 microsecs */ 1200 int usecs = 250; 1201 1202 /* Send clock cycles, poll completion */ 1203 OMAP_MMC_WRITE(host, IE, 0); 1204 OMAP_MMC_WRITE(host, STAT, 0xffff); 1205 OMAP_MMC_WRITE(host, CMD, 1 << 7); 1206 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) { 1207 udelay(1); 1208 usecs--; 1209 } 1210 OMAP_MMC_WRITE(host, STAT, 1); 1211 } 1212 1213 exit: 1214 mmc_omap_release_slot(slot, clk_enabled); 1215 } 1216 1217 static const struct mmc_host_ops mmc_omap_ops = { 1218 .request = mmc_omap_request, 1219 .set_ios = mmc_omap_set_ios, 1220 }; 1221 1222 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id) 1223 { 1224 struct mmc_omap_slot *slot = NULL; 1225 struct mmc_host *mmc; 1226 int r; 1227 1228 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev); 1229 if (mmc == NULL) 1230 return -ENOMEM; 1231 1232 slot = mmc_priv(mmc); 1233 slot->host = host; 1234 slot->mmc = mmc; 1235 slot->id = id; 1236 slot->pdata = &host->pdata->slots[id]; 1237 1238 host->slots[id] = slot; 1239 1240 mmc->caps = 0; 1241 if (host->pdata->slots[id].wires >= 4) 1242 mmc->caps |= MMC_CAP_4_BIT_DATA; 1243 1244 mmc->ops = &mmc_omap_ops; 1245 mmc->f_min = 400000; 1246 1247 if (cpu_class_is_omap2()) 1248 mmc->f_max = 48000000; 1249 else 1250 mmc->f_max = 24000000; 1251 if (host->pdata->max_freq) 1252 mmc->f_max = min(host->pdata->max_freq, mmc->f_max); 1253 mmc->ocr_avail = slot->pdata->ocr_mask; 1254 1255 /* Use scatterlist DMA to reduce per-transfer costs. 1256 * NOTE max_seg_size assumption that small blocks aren't 1257 * normally used (except e.g. for reading SD registers). 1258 */ 1259 mmc->max_segs = 32; 1260 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */ 1261 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */ 1262 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1263 mmc->max_seg_size = mmc->max_req_size; 1264 1265 r = mmc_add_host(mmc); 1266 if (r < 0) 1267 goto err_remove_host; 1268 1269 if (slot->pdata->name != NULL) { 1270 r = device_create_file(&mmc->class_dev, 1271 &dev_attr_slot_name); 1272 if (r < 0) 1273 goto err_remove_host; 1274 } 1275 1276 if (slot->pdata->get_cover_state != NULL) { 1277 r = device_create_file(&mmc->class_dev, 1278 &dev_attr_cover_switch); 1279 if (r < 0) 1280 goto err_remove_slot_name; 1281 1282 setup_timer(&slot->cover_timer, mmc_omap_cover_timer, 1283 (unsigned long)slot); 1284 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler, 1285 (unsigned long)slot); 1286 tasklet_schedule(&slot->cover_tasklet); 1287 } 1288 1289 return 0; 1290 1291 err_remove_slot_name: 1292 if (slot->pdata->name != NULL) 1293 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1294 err_remove_host: 1295 mmc_remove_host(mmc); 1296 mmc_free_host(mmc); 1297 return r; 1298 } 1299 1300 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot) 1301 { 1302 struct mmc_host *mmc = slot->mmc; 1303 1304 if (slot->pdata->name != NULL) 1305 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1306 if (slot->pdata->get_cover_state != NULL) 1307 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); 1308 1309 tasklet_kill(&slot->cover_tasklet); 1310 del_timer_sync(&slot->cover_timer); 1311 flush_workqueue(slot->host->mmc_omap_wq); 1312 1313 mmc_remove_host(mmc); 1314 mmc_free_host(mmc); 1315 } 1316 1317 static int __devinit mmc_omap_probe(struct platform_device *pdev) 1318 { 1319 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1320 struct mmc_omap_host *host = NULL; 1321 struct resource *res; 1322 dma_cap_mask_t mask; 1323 unsigned sig; 1324 int i, ret = 0; 1325 int irq; 1326 1327 if (pdata == NULL) { 1328 dev_err(&pdev->dev, "platform data missing\n"); 1329 return -ENXIO; 1330 } 1331 if (pdata->nr_slots == 0) { 1332 dev_err(&pdev->dev, "no slots\n"); 1333 return -ENXIO; 1334 } 1335 1336 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1337 irq = platform_get_irq(pdev, 0); 1338 if (res == NULL || irq < 0) 1339 return -ENXIO; 1340 1341 res = request_mem_region(res->start, resource_size(res), 1342 pdev->name); 1343 if (res == NULL) 1344 return -EBUSY; 1345 1346 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL); 1347 if (host == NULL) { 1348 ret = -ENOMEM; 1349 goto err_free_mem_region; 1350 } 1351 1352 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); 1353 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); 1354 1355 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); 1356 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, 1357 (unsigned long) host); 1358 1359 spin_lock_init(&host->clk_lock); 1360 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); 1361 1362 spin_lock_init(&host->dma_lock); 1363 spin_lock_init(&host->slot_lock); 1364 init_waitqueue_head(&host->slot_wq); 1365 1366 host->pdata = pdata; 1367 host->dev = &pdev->dev; 1368 platform_set_drvdata(pdev, host); 1369 1370 host->id = pdev->id; 1371 host->mem_res = res; 1372 host->irq = irq; 1373 host->use_dma = 1; 1374 host->irq = irq; 1375 host->phys_base = host->mem_res->start; 1376 host->virt_base = ioremap(res->start, resource_size(res)); 1377 if (!host->virt_base) 1378 goto err_ioremap; 1379 1380 host->iclk = clk_get(&pdev->dev, "ick"); 1381 if (IS_ERR(host->iclk)) { 1382 ret = PTR_ERR(host->iclk); 1383 goto err_free_mmc_host; 1384 } 1385 clk_enable(host->iclk); 1386 1387 host->fclk = clk_get(&pdev->dev, "fck"); 1388 if (IS_ERR(host->fclk)) { 1389 ret = PTR_ERR(host->fclk); 1390 goto err_free_iclk; 1391 } 1392 1393 dma_cap_zero(mask); 1394 dma_cap_set(DMA_SLAVE, mask); 1395 1396 host->dma_tx_burst = -1; 1397 host->dma_rx_burst = -1; 1398 1399 if (cpu_is_omap24xx()) 1400 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX; 1401 else 1402 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX; 1403 host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 1404 #if 0 1405 if (!host->dma_tx) { 1406 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n", 1407 sig); 1408 goto err_dma; 1409 } 1410 #else 1411 if (!host->dma_tx) 1412 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n", 1413 sig); 1414 #endif 1415 if (cpu_is_omap24xx()) 1416 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX; 1417 else 1418 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX; 1419 host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 1420 #if 0 1421 if (!host->dma_rx) { 1422 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n", 1423 sig); 1424 goto err_dma; 1425 } 1426 #else 1427 if (!host->dma_rx) 1428 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n", 1429 sig); 1430 #endif 1431 1432 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); 1433 if (ret) 1434 goto err_free_dma; 1435 1436 if (pdata->init != NULL) { 1437 ret = pdata->init(&pdev->dev); 1438 if (ret < 0) 1439 goto err_free_irq; 1440 } 1441 1442 host->nr_slots = pdata->nr_slots; 1443 host->reg_shift = (cpu_is_omap7xx() ? 1 : 2); 1444 1445 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0); 1446 if (!host->mmc_omap_wq) 1447 goto err_plat_cleanup; 1448 1449 for (i = 0; i < pdata->nr_slots; i++) { 1450 ret = mmc_omap_new_slot(host, i); 1451 if (ret < 0) { 1452 while (--i >= 0) 1453 mmc_omap_remove_slot(host->slots[i]); 1454 1455 goto err_destroy_wq; 1456 } 1457 } 1458 1459 return 0; 1460 1461 err_destroy_wq: 1462 destroy_workqueue(host->mmc_omap_wq); 1463 err_plat_cleanup: 1464 if (pdata->cleanup) 1465 pdata->cleanup(&pdev->dev); 1466 err_free_irq: 1467 free_irq(host->irq, host); 1468 err_free_dma: 1469 if (host->dma_tx) 1470 dma_release_channel(host->dma_tx); 1471 if (host->dma_rx) 1472 dma_release_channel(host->dma_rx); 1473 clk_put(host->fclk); 1474 err_free_iclk: 1475 clk_disable(host->iclk); 1476 clk_put(host->iclk); 1477 err_free_mmc_host: 1478 iounmap(host->virt_base); 1479 err_ioremap: 1480 kfree(host); 1481 err_free_mem_region: 1482 release_mem_region(res->start, resource_size(res)); 1483 return ret; 1484 } 1485 1486 static int __devexit mmc_omap_remove(struct platform_device *pdev) 1487 { 1488 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1489 int i; 1490 1491 platform_set_drvdata(pdev, NULL); 1492 1493 BUG_ON(host == NULL); 1494 1495 for (i = 0; i < host->nr_slots; i++) 1496 mmc_omap_remove_slot(host->slots[i]); 1497 1498 if (host->pdata->cleanup) 1499 host->pdata->cleanup(&pdev->dev); 1500 1501 mmc_omap_fclk_enable(host, 0); 1502 free_irq(host->irq, host); 1503 clk_put(host->fclk); 1504 clk_disable(host->iclk); 1505 clk_put(host->iclk); 1506 1507 if (host->dma_tx) 1508 dma_release_channel(host->dma_tx); 1509 if (host->dma_rx) 1510 dma_release_channel(host->dma_rx); 1511 1512 iounmap(host->virt_base); 1513 release_mem_region(pdev->resource[0].start, 1514 pdev->resource[0].end - pdev->resource[0].start + 1); 1515 destroy_workqueue(host->mmc_omap_wq); 1516 1517 kfree(host); 1518 1519 return 0; 1520 } 1521 1522 #ifdef CONFIG_PM 1523 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg) 1524 { 1525 int i, ret = 0; 1526 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1527 1528 if (host == NULL || host->suspended) 1529 return 0; 1530 1531 for (i = 0; i < host->nr_slots; i++) { 1532 struct mmc_omap_slot *slot; 1533 1534 slot = host->slots[i]; 1535 ret = mmc_suspend_host(slot->mmc); 1536 if (ret < 0) { 1537 while (--i >= 0) { 1538 slot = host->slots[i]; 1539 mmc_resume_host(slot->mmc); 1540 } 1541 return ret; 1542 } 1543 } 1544 host->suspended = 1; 1545 return 0; 1546 } 1547 1548 static int mmc_omap_resume(struct platform_device *pdev) 1549 { 1550 int i, ret = 0; 1551 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1552 1553 if (host == NULL || !host->suspended) 1554 return 0; 1555 1556 for (i = 0; i < host->nr_slots; i++) { 1557 struct mmc_omap_slot *slot; 1558 slot = host->slots[i]; 1559 ret = mmc_resume_host(slot->mmc); 1560 if (ret < 0) 1561 return ret; 1562 1563 host->suspended = 0; 1564 } 1565 return 0; 1566 } 1567 #else 1568 #define mmc_omap_suspend NULL 1569 #define mmc_omap_resume NULL 1570 #endif 1571 1572 static struct platform_driver mmc_omap_driver = { 1573 .probe = mmc_omap_probe, 1574 .remove = __devexit_p(mmc_omap_remove), 1575 .suspend = mmc_omap_suspend, 1576 .resume = mmc_omap_resume, 1577 .driver = { 1578 .name = DRIVER_NAME, 1579 .owner = THIS_MODULE, 1580 }, 1581 }; 1582 1583 module_platform_driver(mmc_omap_driver); 1584 MODULE_DESCRIPTION("OMAP Multimedia Card driver"); 1585 MODULE_LICENSE("GPL"); 1586 MODULE_ALIAS("platform:" DRIVER_NAME); 1587 MODULE_AUTHOR("Juha Yrjölä"); 1588