1 /* 2 * linux/drivers/mmc/host/omap.c 3 * 4 * Copyright (C) 2004 Nokia Corporation 5 * Written by Tuukka Tikkanen and Juha Yrjölä<juha.yrjola@nokia.com> 6 * Misc hacks here and there by Tony Lindgren <tony@atomide.com> 7 * Other hacks (DMA, SD, etc) by David Brownell 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License version 2 as 11 * published by the Free Software Foundation. 12 */ 13 14 #include <linux/module.h> 15 #include <linux/moduleparam.h> 16 #include <linux/init.h> 17 #include <linux/ioport.h> 18 #include <linux/platform_device.h> 19 #include <linux/interrupt.h> 20 #include <linux/dmaengine.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/delay.h> 23 #include <linux/spinlock.h> 24 #include <linux/timer.h> 25 #include <linux/omap-dma.h> 26 #include <linux/mmc/host.h> 27 #include <linux/mmc/card.h> 28 #include <linux/clk.h> 29 #include <linux/scatterlist.h> 30 #include <linux/i2c/tps65010.h> 31 #include <linux/slab.h> 32 33 #include <asm/io.h> 34 #include <asm/irq.h> 35 36 #include <plat/mmc.h> 37 #include <asm/gpio.h> 38 #include <plat/dma.h> 39 #include <plat/fpga.h> 40 41 #define OMAP_MMC_REG_CMD 0x00 42 #define OMAP_MMC_REG_ARGL 0x01 43 #define OMAP_MMC_REG_ARGH 0x02 44 #define OMAP_MMC_REG_CON 0x03 45 #define OMAP_MMC_REG_STAT 0x04 46 #define OMAP_MMC_REG_IE 0x05 47 #define OMAP_MMC_REG_CTO 0x06 48 #define OMAP_MMC_REG_DTO 0x07 49 #define OMAP_MMC_REG_DATA 0x08 50 #define OMAP_MMC_REG_BLEN 0x09 51 #define OMAP_MMC_REG_NBLK 0x0a 52 #define OMAP_MMC_REG_BUF 0x0b 53 #define OMAP_MMC_REG_SDIO 0x0d 54 #define OMAP_MMC_REG_REV 0x0f 55 #define OMAP_MMC_REG_RSP0 0x10 56 #define OMAP_MMC_REG_RSP1 0x11 57 #define OMAP_MMC_REG_RSP2 0x12 58 #define OMAP_MMC_REG_RSP3 0x13 59 #define OMAP_MMC_REG_RSP4 0x14 60 #define OMAP_MMC_REG_RSP5 0x15 61 #define OMAP_MMC_REG_RSP6 0x16 62 #define OMAP_MMC_REG_RSP7 0x17 63 #define OMAP_MMC_REG_IOSR 0x18 64 #define OMAP_MMC_REG_SYSC 0x19 65 #define OMAP_MMC_REG_SYSS 0x1a 66 67 #define OMAP_MMC_STAT_CARD_ERR (1 << 14) 68 #define OMAP_MMC_STAT_CARD_IRQ (1 << 13) 69 #define OMAP_MMC_STAT_OCR_BUSY (1 << 12) 70 #define OMAP_MMC_STAT_A_EMPTY (1 << 11) 71 #define OMAP_MMC_STAT_A_FULL (1 << 10) 72 #define OMAP_MMC_STAT_CMD_CRC (1 << 8) 73 #define OMAP_MMC_STAT_CMD_TOUT (1 << 7) 74 #define OMAP_MMC_STAT_DATA_CRC (1 << 6) 75 #define OMAP_MMC_STAT_DATA_TOUT (1 << 5) 76 #define OMAP_MMC_STAT_END_BUSY (1 << 4) 77 #define OMAP_MMC_STAT_END_OF_DATA (1 << 3) 78 #define OMAP_MMC_STAT_CARD_BUSY (1 << 2) 79 #define OMAP_MMC_STAT_END_OF_CMD (1 << 0) 80 81 #define OMAP_MMC_REG(host, reg) (OMAP_MMC_REG_##reg << (host)->reg_shift) 82 #define OMAP_MMC_READ(host, reg) __raw_readw((host)->virt_base + OMAP_MMC_REG(host, reg)) 83 #define OMAP_MMC_WRITE(host, reg, val) __raw_writew((val), (host)->virt_base + OMAP_MMC_REG(host, reg)) 84 85 /* 86 * Command types 87 */ 88 #define OMAP_MMC_CMDTYPE_BC 0 89 #define OMAP_MMC_CMDTYPE_BCR 1 90 #define OMAP_MMC_CMDTYPE_AC 2 91 #define OMAP_MMC_CMDTYPE_ADTC 3 92 93 94 #define DRIVER_NAME "mmci-omap" 95 96 /* Specifies how often in millisecs to poll for card status changes 97 * when the cover switch is open */ 98 #define OMAP_MMC_COVER_POLL_DELAY 500 99 100 struct mmc_omap_host; 101 102 struct mmc_omap_slot { 103 int id; 104 unsigned int vdd; 105 u16 saved_con; 106 u16 bus_mode; 107 unsigned int fclk_freq; 108 unsigned powered:1; 109 110 struct tasklet_struct cover_tasklet; 111 struct timer_list cover_timer; 112 unsigned cover_open; 113 114 struct mmc_request *mrq; 115 struct mmc_omap_host *host; 116 struct mmc_host *mmc; 117 struct omap_mmc_slot_data *pdata; 118 }; 119 120 struct mmc_omap_host { 121 int initialized; 122 int suspended; 123 struct mmc_request * mrq; 124 struct mmc_command * cmd; 125 struct mmc_data * data; 126 struct mmc_host * mmc; 127 struct device * dev; 128 unsigned char id; /* 16xx chips have 2 MMC blocks */ 129 struct clk * iclk; 130 struct clk * fclk; 131 struct dma_chan *dma_rx; 132 u32 dma_rx_burst; 133 struct dma_chan *dma_tx; 134 u32 dma_tx_burst; 135 struct resource *mem_res; 136 void __iomem *virt_base; 137 unsigned int phys_base; 138 int irq; 139 unsigned char bus_mode; 140 unsigned char hw_bus_mode; 141 unsigned int reg_shift; 142 143 struct work_struct cmd_abort_work; 144 unsigned abort:1; 145 struct timer_list cmd_abort_timer; 146 147 struct work_struct slot_release_work; 148 struct mmc_omap_slot *next_slot; 149 struct work_struct send_stop_work; 150 struct mmc_data *stop_data; 151 152 unsigned int sg_len; 153 int sg_idx; 154 u16 * buffer; 155 u32 buffer_bytes_left; 156 u32 total_bytes_left; 157 158 unsigned use_dma:1; 159 unsigned brs_received:1, dma_done:1; 160 unsigned dma_in_use:1; 161 spinlock_t dma_lock; 162 163 struct mmc_omap_slot *slots[OMAP_MMC_MAX_SLOTS]; 164 struct mmc_omap_slot *current_slot; 165 spinlock_t slot_lock; 166 wait_queue_head_t slot_wq; 167 int nr_slots; 168 169 struct timer_list clk_timer; 170 spinlock_t clk_lock; /* for changing enabled state */ 171 unsigned int fclk_enabled:1; 172 struct workqueue_struct *mmc_omap_wq; 173 174 struct omap_mmc_platform_data *pdata; 175 }; 176 177 178 static void mmc_omap_fclk_offdelay(struct mmc_omap_slot *slot) 179 { 180 unsigned long tick_ns; 181 182 if (slot != NULL && slot->host->fclk_enabled && slot->fclk_freq > 0) { 183 tick_ns = (1000000000 + slot->fclk_freq - 1) / slot->fclk_freq; 184 ndelay(8 * tick_ns); 185 } 186 } 187 188 static void mmc_omap_fclk_enable(struct mmc_omap_host *host, unsigned int enable) 189 { 190 unsigned long flags; 191 192 spin_lock_irqsave(&host->clk_lock, flags); 193 if (host->fclk_enabled != enable) { 194 host->fclk_enabled = enable; 195 if (enable) 196 clk_enable(host->fclk); 197 else 198 clk_disable(host->fclk); 199 } 200 spin_unlock_irqrestore(&host->clk_lock, flags); 201 } 202 203 static void mmc_omap_select_slot(struct mmc_omap_slot *slot, int claimed) 204 { 205 struct mmc_omap_host *host = slot->host; 206 unsigned long flags; 207 208 if (claimed) 209 goto no_claim; 210 spin_lock_irqsave(&host->slot_lock, flags); 211 while (host->mmc != NULL) { 212 spin_unlock_irqrestore(&host->slot_lock, flags); 213 wait_event(host->slot_wq, host->mmc == NULL); 214 spin_lock_irqsave(&host->slot_lock, flags); 215 } 216 host->mmc = slot->mmc; 217 spin_unlock_irqrestore(&host->slot_lock, flags); 218 no_claim: 219 del_timer(&host->clk_timer); 220 if (host->current_slot != slot || !claimed) 221 mmc_omap_fclk_offdelay(host->current_slot); 222 223 if (host->current_slot != slot) { 224 OMAP_MMC_WRITE(host, CON, slot->saved_con & 0xFC00); 225 if (host->pdata->switch_slot != NULL) 226 host->pdata->switch_slot(mmc_dev(slot->mmc), slot->id); 227 host->current_slot = slot; 228 } 229 230 if (claimed) { 231 mmc_omap_fclk_enable(host, 1); 232 233 /* Doing the dummy read here seems to work around some bug 234 * at least in OMAP24xx silicon where the command would not 235 * start after writing the CMD register. Sigh. */ 236 OMAP_MMC_READ(host, CON); 237 238 OMAP_MMC_WRITE(host, CON, slot->saved_con); 239 } else 240 mmc_omap_fclk_enable(host, 0); 241 } 242 243 static void mmc_omap_start_request(struct mmc_omap_host *host, 244 struct mmc_request *req); 245 246 static void mmc_omap_slot_release_work(struct work_struct *work) 247 { 248 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 249 slot_release_work); 250 struct mmc_omap_slot *next_slot = host->next_slot; 251 struct mmc_request *rq; 252 253 host->next_slot = NULL; 254 mmc_omap_select_slot(next_slot, 1); 255 256 rq = next_slot->mrq; 257 next_slot->mrq = NULL; 258 mmc_omap_start_request(host, rq); 259 } 260 261 static void mmc_omap_release_slot(struct mmc_omap_slot *slot, int clk_enabled) 262 { 263 struct mmc_omap_host *host = slot->host; 264 unsigned long flags; 265 int i; 266 267 BUG_ON(slot == NULL || host->mmc == NULL); 268 269 if (clk_enabled) 270 /* Keeps clock running for at least 8 cycles on valid freq */ 271 mod_timer(&host->clk_timer, jiffies + HZ/10); 272 else { 273 del_timer(&host->clk_timer); 274 mmc_omap_fclk_offdelay(slot); 275 mmc_omap_fclk_enable(host, 0); 276 } 277 278 spin_lock_irqsave(&host->slot_lock, flags); 279 /* Check for any pending requests */ 280 for (i = 0; i < host->nr_slots; i++) { 281 struct mmc_omap_slot *new_slot; 282 283 if (host->slots[i] == NULL || host->slots[i]->mrq == NULL) 284 continue; 285 286 BUG_ON(host->next_slot != NULL); 287 new_slot = host->slots[i]; 288 /* The current slot should not have a request in queue */ 289 BUG_ON(new_slot == host->current_slot); 290 291 host->next_slot = new_slot; 292 host->mmc = new_slot->mmc; 293 spin_unlock_irqrestore(&host->slot_lock, flags); 294 queue_work(host->mmc_omap_wq, &host->slot_release_work); 295 return; 296 } 297 298 host->mmc = NULL; 299 wake_up(&host->slot_wq); 300 spin_unlock_irqrestore(&host->slot_lock, flags); 301 } 302 303 static inline 304 int mmc_omap_cover_is_open(struct mmc_omap_slot *slot) 305 { 306 if (slot->pdata->get_cover_state) 307 return slot->pdata->get_cover_state(mmc_dev(slot->mmc), 308 slot->id); 309 return 0; 310 } 311 312 static ssize_t 313 mmc_omap_show_cover_switch(struct device *dev, struct device_attribute *attr, 314 char *buf) 315 { 316 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 317 struct mmc_omap_slot *slot = mmc_priv(mmc); 318 319 return sprintf(buf, "%s\n", mmc_omap_cover_is_open(slot) ? "open" : 320 "closed"); 321 } 322 323 static DEVICE_ATTR(cover_switch, S_IRUGO, mmc_omap_show_cover_switch, NULL); 324 325 static ssize_t 326 mmc_omap_show_slot_name(struct device *dev, struct device_attribute *attr, 327 char *buf) 328 { 329 struct mmc_host *mmc = container_of(dev, struct mmc_host, class_dev); 330 struct mmc_omap_slot *slot = mmc_priv(mmc); 331 332 return sprintf(buf, "%s\n", slot->pdata->name); 333 } 334 335 static DEVICE_ATTR(slot_name, S_IRUGO, mmc_omap_show_slot_name, NULL); 336 337 static void 338 mmc_omap_start_command(struct mmc_omap_host *host, struct mmc_command *cmd) 339 { 340 u32 cmdreg; 341 u32 resptype; 342 u32 cmdtype; 343 344 host->cmd = cmd; 345 346 resptype = 0; 347 cmdtype = 0; 348 349 /* Our hardware needs to know exact type */ 350 switch (mmc_resp_type(cmd)) { 351 case MMC_RSP_NONE: 352 break; 353 case MMC_RSP_R1: 354 case MMC_RSP_R1B: 355 /* resp 1, 1b, 6, 7 */ 356 resptype = 1; 357 break; 358 case MMC_RSP_R2: 359 resptype = 2; 360 break; 361 case MMC_RSP_R3: 362 resptype = 3; 363 break; 364 default: 365 dev_err(mmc_dev(host->mmc), "Invalid response type: %04x\n", mmc_resp_type(cmd)); 366 break; 367 } 368 369 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC) { 370 cmdtype = OMAP_MMC_CMDTYPE_ADTC; 371 } else if (mmc_cmd_type(cmd) == MMC_CMD_BC) { 372 cmdtype = OMAP_MMC_CMDTYPE_BC; 373 } else if (mmc_cmd_type(cmd) == MMC_CMD_BCR) { 374 cmdtype = OMAP_MMC_CMDTYPE_BCR; 375 } else { 376 cmdtype = OMAP_MMC_CMDTYPE_AC; 377 } 378 379 cmdreg = cmd->opcode | (resptype << 8) | (cmdtype << 12); 380 381 if (host->current_slot->bus_mode == MMC_BUSMODE_OPENDRAIN) 382 cmdreg |= 1 << 6; 383 384 if (cmd->flags & MMC_RSP_BUSY) 385 cmdreg |= 1 << 11; 386 387 if (host->data && !(host->data->flags & MMC_DATA_WRITE)) 388 cmdreg |= 1 << 15; 389 390 mod_timer(&host->cmd_abort_timer, jiffies + HZ/2); 391 392 OMAP_MMC_WRITE(host, CTO, 200); 393 OMAP_MMC_WRITE(host, ARGL, cmd->arg & 0xffff); 394 OMAP_MMC_WRITE(host, ARGH, cmd->arg >> 16); 395 OMAP_MMC_WRITE(host, IE, 396 OMAP_MMC_STAT_A_EMPTY | OMAP_MMC_STAT_A_FULL | 397 OMAP_MMC_STAT_CMD_CRC | OMAP_MMC_STAT_CMD_TOUT | 398 OMAP_MMC_STAT_DATA_CRC | OMAP_MMC_STAT_DATA_TOUT | 399 OMAP_MMC_STAT_END_OF_CMD | OMAP_MMC_STAT_CARD_ERR | 400 OMAP_MMC_STAT_END_OF_DATA); 401 OMAP_MMC_WRITE(host, CMD, cmdreg); 402 } 403 404 static void 405 mmc_omap_release_dma(struct mmc_omap_host *host, struct mmc_data *data, 406 int abort) 407 { 408 enum dma_data_direction dma_data_dir; 409 struct device *dev = mmc_dev(host->mmc); 410 struct dma_chan *c; 411 412 if (data->flags & MMC_DATA_WRITE) { 413 dma_data_dir = DMA_TO_DEVICE; 414 c = host->dma_tx; 415 } else { 416 dma_data_dir = DMA_FROM_DEVICE; 417 c = host->dma_rx; 418 } 419 if (c) { 420 if (data->error) { 421 dmaengine_terminate_all(c); 422 /* Claim nothing transferred on error... */ 423 data->bytes_xfered = 0; 424 } 425 dev = c->device->dev; 426 } 427 dma_unmap_sg(dev, data->sg, host->sg_len, dma_data_dir); 428 } 429 430 static void mmc_omap_send_stop_work(struct work_struct *work) 431 { 432 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 433 send_stop_work); 434 struct mmc_omap_slot *slot = host->current_slot; 435 struct mmc_data *data = host->stop_data; 436 unsigned long tick_ns; 437 438 tick_ns = (1000000000 + slot->fclk_freq - 1)/slot->fclk_freq; 439 ndelay(8*tick_ns); 440 441 mmc_omap_start_command(host, data->stop); 442 } 443 444 static void 445 mmc_omap_xfer_done(struct mmc_omap_host *host, struct mmc_data *data) 446 { 447 if (host->dma_in_use) 448 mmc_omap_release_dma(host, data, data->error); 449 450 host->data = NULL; 451 host->sg_len = 0; 452 453 /* NOTE: MMC layer will sometimes poll-wait CMD13 next, issuing 454 * dozens of requests until the card finishes writing data. 455 * It'd be cheaper to just wait till an EOFB interrupt arrives... 456 */ 457 458 if (!data->stop) { 459 struct mmc_host *mmc; 460 461 host->mrq = NULL; 462 mmc = host->mmc; 463 mmc_omap_release_slot(host->current_slot, 1); 464 mmc_request_done(mmc, data->mrq); 465 return; 466 } 467 468 host->stop_data = data; 469 queue_work(host->mmc_omap_wq, &host->send_stop_work); 470 } 471 472 static void 473 mmc_omap_send_abort(struct mmc_omap_host *host, int maxloops) 474 { 475 struct mmc_omap_slot *slot = host->current_slot; 476 unsigned int restarts, passes, timeout; 477 u16 stat = 0; 478 479 /* Sending abort takes 80 clocks. Have some extra and round up */ 480 timeout = (120*1000000 + slot->fclk_freq - 1)/slot->fclk_freq; 481 restarts = 0; 482 while (restarts < maxloops) { 483 OMAP_MMC_WRITE(host, STAT, 0xFFFF); 484 OMAP_MMC_WRITE(host, CMD, (3 << 12) | (1 << 7)); 485 486 passes = 0; 487 while (passes < timeout) { 488 stat = OMAP_MMC_READ(host, STAT); 489 if (stat & OMAP_MMC_STAT_END_OF_CMD) 490 goto out; 491 udelay(1); 492 passes++; 493 } 494 495 restarts++; 496 } 497 out: 498 OMAP_MMC_WRITE(host, STAT, stat); 499 } 500 501 static void 502 mmc_omap_abort_xfer(struct mmc_omap_host *host, struct mmc_data *data) 503 { 504 if (host->dma_in_use) 505 mmc_omap_release_dma(host, data, 1); 506 507 host->data = NULL; 508 host->sg_len = 0; 509 510 mmc_omap_send_abort(host, 10000); 511 } 512 513 static void 514 mmc_omap_end_of_data(struct mmc_omap_host *host, struct mmc_data *data) 515 { 516 unsigned long flags; 517 int done; 518 519 if (!host->dma_in_use) { 520 mmc_omap_xfer_done(host, data); 521 return; 522 } 523 done = 0; 524 spin_lock_irqsave(&host->dma_lock, flags); 525 if (host->dma_done) 526 done = 1; 527 else 528 host->brs_received = 1; 529 spin_unlock_irqrestore(&host->dma_lock, flags); 530 if (done) 531 mmc_omap_xfer_done(host, data); 532 } 533 534 static void 535 mmc_omap_dma_done(struct mmc_omap_host *host, struct mmc_data *data) 536 { 537 unsigned long flags; 538 int done; 539 540 done = 0; 541 spin_lock_irqsave(&host->dma_lock, flags); 542 if (host->brs_received) 543 done = 1; 544 else 545 host->dma_done = 1; 546 spin_unlock_irqrestore(&host->dma_lock, flags); 547 if (done) 548 mmc_omap_xfer_done(host, data); 549 } 550 551 static void 552 mmc_omap_cmd_done(struct mmc_omap_host *host, struct mmc_command *cmd) 553 { 554 host->cmd = NULL; 555 556 del_timer(&host->cmd_abort_timer); 557 558 if (cmd->flags & MMC_RSP_PRESENT) { 559 if (cmd->flags & MMC_RSP_136) { 560 /* response type 2 */ 561 cmd->resp[3] = 562 OMAP_MMC_READ(host, RSP0) | 563 (OMAP_MMC_READ(host, RSP1) << 16); 564 cmd->resp[2] = 565 OMAP_MMC_READ(host, RSP2) | 566 (OMAP_MMC_READ(host, RSP3) << 16); 567 cmd->resp[1] = 568 OMAP_MMC_READ(host, RSP4) | 569 (OMAP_MMC_READ(host, RSP5) << 16); 570 cmd->resp[0] = 571 OMAP_MMC_READ(host, RSP6) | 572 (OMAP_MMC_READ(host, RSP7) << 16); 573 } else { 574 /* response types 1, 1b, 3, 4, 5, 6 */ 575 cmd->resp[0] = 576 OMAP_MMC_READ(host, RSP6) | 577 (OMAP_MMC_READ(host, RSP7) << 16); 578 } 579 } 580 581 if (host->data == NULL || cmd->error) { 582 struct mmc_host *mmc; 583 584 if (host->data != NULL) 585 mmc_omap_abort_xfer(host, host->data); 586 host->mrq = NULL; 587 mmc = host->mmc; 588 mmc_omap_release_slot(host->current_slot, 1); 589 mmc_request_done(mmc, cmd->mrq); 590 } 591 } 592 593 /* 594 * Abort stuck command. Can occur when card is removed while it is being 595 * read. 596 */ 597 static void mmc_omap_abort_command(struct work_struct *work) 598 { 599 struct mmc_omap_host *host = container_of(work, struct mmc_omap_host, 600 cmd_abort_work); 601 BUG_ON(!host->cmd); 602 603 dev_dbg(mmc_dev(host->mmc), "Aborting stuck command CMD%d\n", 604 host->cmd->opcode); 605 606 if (host->cmd->error == 0) 607 host->cmd->error = -ETIMEDOUT; 608 609 if (host->data == NULL) { 610 struct mmc_command *cmd; 611 struct mmc_host *mmc; 612 613 cmd = host->cmd; 614 host->cmd = NULL; 615 mmc_omap_send_abort(host, 10000); 616 617 host->mrq = NULL; 618 mmc = host->mmc; 619 mmc_omap_release_slot(host->current_slot, 1); 620 mmc_request_done(mmc, cmd->mrq); 621 } else 622 mmc_omap_cmd_done(host, host->cmd); 623 624 host->abort = 0; 625 enable_irq(host->irq); 626 } 627 628 static void 629 mmc_omap_cmd_timer(unsigned long data) 630 { 631 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 632 unsigned long flags; 633 634 spin_lock_irqsave(&host->slot_lock, flags); 635 if (host->cmd != NULL && !host->abort) { 636 OMAP_MMC_WRITE(host, IE, 0); 637 disable_irq(host->irq); 638 host->abort = 1; 639 queue_work(host->mmc_omap_wq, &host->cmd_abort_work); 640 } 641 spin_unlock_irqrestore(&host->slot_lock, flags); 642 } 643 644 /* PIO only */ 645 static void 646 mmc_omap_sg_to_buf(struct mmc_omap_host *host) 647 { 648 struct scatterlist *sg; 649 650 sg = host->data->sg + host->sg_idx; 651 host->buffer_bytes_left = sg->length; 652 host->buffer = sg_virt(sg); 653 if (host->buffer_bytes_left > host->total_bytes_left) 654 host->buffer_bytes_left = host->total_bytes_left; 655 } 656 657 static void 658 mmc_omap_clk_timer(unsigned long data) 659 { 660 struct mmc_omap_host *host = (struct mmc_omap_host *) data; 661 662 mmc_omap_fclk_enable(host, 0); 663 } 664 665 /* PIO only */ 666 static void 667 mmc_omap_xfer_data(struct mmc_omap_host *host, int write) 668 { 669 int n, nwords; 670 671 if (host->buffer_bytes_left == 0) { 672 host->sg_idx++; 673 BUG_ON(host->sg_idx == host->sg_len); 674 mmc_omap_sg_to_buf(host); 675 } 676 n = 64; 677 if (n > host->buffer_bytes_left) 678 n = host->buffer_bytes_left; 679 680 nwords = n / 2; 681 nwords += n & 1; /* handle odd number of bytes to transfer */ 682 683 host->buffer_bytes_left -= n; 684 host->total_bytes_left -= n; 685 host->data->bytes_xfered += n; 686 687 if (write) { 688 __raw_writesw(host->virt_base + OMAP_MMC_REG(host, DATA), 689 host->buffer, nwords); 690 } else { 691 __raw_readsw(host->virt_base + OMAP_MMC_REG(host, DATA), 692 host->buffer, nwords); 693 } 694 695 host->buffer += nwords; 696 } 697 698 static inline void mmc_omap_report_irq(u16 status) 699 { 700 static const char *mmc_omap_status_bits[] = { 701 "EOC", "CD", "CB", "BRS", "EOFB", "DTO", "DCRC", "CTO", 702 "CCRC", "CRW", "AF", "AE", "OCRB", "CIRQ", "CERR" 703 }; 704 int i, c = 0; 705 706 for (i = 0; i < ARRAY_SIZE(mmc_omap_status_bits); i++) 707 if (status & (1 << i)) { 708 if (c) 709 printk(" "); 710 printk("%s", mmc_omap_status_bits[i]); 711 c++; 712 } 713 } 714 715 static irqreturn_t mmc_omap_irq(int irq, void *dev_id) 716 { 717 struct mmc_omap_host * host = (struct mmc_omap_host *)dev_id; 718 u16 status; 719 int end_command; 720 int end_transfer; 721 int transfer_error, cmd_error; 722 723 if (host->cmd == NULL && host->data == NULL) { 724 status = OMAP_MMC_READ(host, STAT); 725 dev_info(mmc_dev(host->slots[0]->mmc), 726 "Spurious IRQ 0x%04x\n", status); 727 if (status != 0) { 728 OMAP_MMC_WRITE(host, STAT, status); 729 OMAP_MMC_WRITE(host, IE, 0); 730 } 731 return IRQ_HANDLED; 732 } 733 734 end_command = 0; 735 end_transfer = 0; 736 transfer_error = 0; 737 cmd_error = 0; 738 739 while ((status = OMAP_MMC_READ(host, STAT)) != 0) { 740 int cmd; 741 742 OMAP_MMC_WRITE(host, STAT, status); 743 if (host->cmd != NULL) 744 cmd = host->cmd->opcode; 745 else 746 cmd = -1; 747 #ifdef CONFIG_MMC_DEBUG 748 dev_dbg(mmc_dev(host->mmc), "MMC IRQ %04x (CMD %d): ", 749 status, cmd); 750 mmc_omap_report_irq(status); 751 printk("\n"); 752 #endif 753 if (host->total_bytes_left) { 754 if ((status & OMAP_MMC_STAT_A_FULL) || 755 (status & OMAP_MMC_STAT_END_OF_DATA)) 756 mmc_omap_xfer_data(host, 0); 757 if (status & OMAP_MMC_STAT_A_EMPTY) 758 mmc_omap_xfer_data(host, 1); 759 } 760 761 if (status & OMAP_MMC_STAT_END_OF_DATA) 762 end_transfer = 1; 763 764 if (status & OMAP_MMC_STAT_DATA_TOUT) { 765 dev_dbg(mmc_dev(host->mmc), "data timeout (CMD%d)\n", 766 cmd); 767 if (host->data) { 768 host->data->error = -ETIMEDOUT; 769 transfer_error = 1; 770 } 771 } 772 773 if (status & OMAP_MMC_STAT_DATA_CRC) { 774 if (host->data) { 775 host->data->error = -EILSEQ; 776 dev_dbg(mmc_dev(host->mmc), 777 "data CRC error, bytes left %d\n", 778 host->total_bytes_left); 779 transfer_error = 1; 780 } else { 781 dev_dbg(mmc_dev(host->mmc), "data CRC error\n"); 782 } 783 } 784 785 if (status & OMAP_MMC_STAT_CMD_TOUT) { 786 /* Timeouts are routine with some commands */ 787 if (host->cmd) { 788 struct mmc_omap_slot *slot = 789 host->current_slot; 790 if (slot == NULL || 791 !mmc_omap_cover_is_open(slot)) 792 dev_err(mmc_dev(host->mmc), 793 "command timeout (CMD%d)\n", 794 cmd); 795 host->cmd->error = -ETIMEDOUT; 796 end_command = 1; 797 cmd_error = 1; 798 } 799 } 800 801 if (status & OMAP_MMC_STAT_CMD_CRC) { 802 if (host->cmd) { 803 dev_err(mmc_dev(host->mmc), 804 "command CRC error (CMD%d, arg 0x%08x)\n", 805 cmd, host->cmd->arg); 806 host->cmd->error = -EILSEQ; 807 end_command = 1; 808 cmd_error = 1; 809 } else 810 dev_err(mmc_dev(host->mmc), 811 "command CRC error without cmd?\n"); 812 } 813 814 if (status & OMAP_MMC_STAT_CARD_ERR) { 815 dev_dbg(mmc_dev(host->mmc), 816 "ignoring card status error (CMD%d)\n", 817 cmd); 818 end_command = 1; 819 } 820 821 /* 822 * NOTE: On 1610 the END_OF_CMD may come too early when 823 * starting a write 824 */ 825 if ((status & OMAP_MMC_STAT_END_OF_CMD) && 826 (!(status & OMAP_MMC_STAT_A_EMPTY))) { 827 end_command = 1; 828 } 829 } 830 831 if (cmd_error && host->data) { 832 del_timer(&host->cmd_abort_timer); 833 host->abort = 1; 834 OMAP_MMC_WRITE(host, IE, 0); 835 disable_irq_nosync(host->irq); 836 queue_work(host->mmc_omap_wq, &host->cmd_abort_work); 837 return IRQ_HANDLED; 838 } 839 840 if (end_command && host->cmd) 841 mmc_omap_cmd_done(host, host->cmd); 842 if (host->data != NULL) { 843 if (transfer_error) 844 mmc_omap_xfer_done(host, host->data); 845 else if (end_transfer) 846 mmc_omap_end_of_data(host, host->data); 847 } 848 849 return IRQ_HANDLED; 850 } 851 852 void omap_mmc_notify_cover_event(struct device *dev, int num, int is_closed) 853 { 854 int cover_open; 855 struct mmc_omap_host *host = dev_get_drvdata(dev); 856 struct mmc_omap_slot *slot = host->slots[num]; 857 858 BUG_ON(num >= host->nr_slots); 859 860 /* Other subsystems can call in here before we're initialised. */ 861 if (host->nr_slots == 0 || !host->slots[num]) 862 return; 863 864 cover_open = mmc_omap_cover_is_open(slot); 865 if (cover_open != slot->cover_open) { 866 slot->cover_open = cover_open; 867 sysfs_notify(&slot->mmc->class_dev.kobj, NULL, "cover_switch"); 868 } 869 870 tasklet_hi_schedule(&slot->cover_tasklet); 871 } 872 873 static void mmc_omap_cover_timer(unsigned long arg) 874 { 875 struct mmc_omap_slot *slot = (struct mmc_omap_slot *) arg; 876 tasklet_schedule(&slot->cover_tasklet); 877 } 878 879 static void mmc_omap_cover_handler(unsigned long param) 880 { 881 struct mmc_omap_slot *slot = (struct mmc_omap_slot *)param; 882 int cover_open = mmc_omap_cover_is_open(slot); 883 884 mmc_detect_change(slot->mmc, 0); 885 if (!cover_open) 886 return; 887 888 /* 889 * If no card is inserted, we postpone polling until 890 * the cover has been closed. 891 */ 892 if (slot->mmc->card == NULL || !mmc_card_present(slot->mmc->card)) 893 return; 894 895 mod_timer(&slot->cover_timer, 896 jiffies + msecs_to_jiffies(OMAP_MMC_COVER_POLL_DELAY)); 897 } 898 899 static void mmc_omap_dma_callback(void *priv) 900 { 901 struct mmc_omap_host *host = priv; 902 struct mmc_data *data = host->data; 903 904 /* If we got to the end of DMA, assume everything went well */ 905 data->bytes_xfered += data->blocks * data->blksz; 906 907 mmc_omap_dma_done(host, data); 908 } 909 910 static inline void set_cmd_timeout(struct mmc_omap_host *host, struct mmc_request *req) 911 { 912 u16 reg; 913 914 reg = OMAP_MMC_READ(host, SDIO); 915 reg &= ~(1 << 5); 916 OMAP_MMC_WRITE(host, SDIO, reg); 917 /* Set maximum timeout */ 918 OMAP_MMC_WRITE(host, CTO, 0xff); 919 } 920 921 static inline void set_data_timeout(struct mmc_omap_host *host, struct mmc_request *req) 922 { 923 unsigned int timeout, cycle_ns; 924 u16 reg; 925 926 cycle_ns = 1000000000 / host->current_slot->fclk_freq; 927 timeout = req->data->timeout_ns / cycle_ns; 928 timeout += req->data->timeout_clks; 929 930 /* Check if we need to use timeout multiplier register */ 931 reg = OMAP_MMC_READ(host, SDIO); 932 if (timeout > 0xffff) { 933 reg |= (1 << 5); 934 timeout /= 1024; 935 } else 936 reg &= ~(1 << 5); 937 OMAP_MMC_WRITE(host, SDIO, reg); 938 OMAP_MMC_WRITE(host, DTO, timeout); 939 } 940 941 static void 942 mmc_omap_prepare_data(struct mmc_omap_host *host, struct mmc_request *req) 943 { 944 struct mmc_data *data = req->data; 945 int i, use_dma, block_size; 946 unsigned sg_len; 947 948 host->data = data; 949 if (data == NULL) { 950 OMAP_MMC_WRITE(host, BLEN, 0); 951 OMAP_MMC_WRITE(host, NBLK, 0); 952 OMAP_MMC_WRITE(host, BUF, 0); 953 host->dma_in_use = 0; 954 set_cmd_timeout(host, req); 955 return; 956 } 957 958 block_size = data->blksz; 959 960 OMAP_MMC_WRITE(host, NBLK, data->blocks - 1); 961 OMAP_MMC_WRITE(host, BLEN, block_size - 1); 962 set_data_timeout(host, req); 963 964 /* cope with calling layer confusion; it issues "single 965 * block" writes using multi-block scatterlists. 966 */ 967 sg_len = (data->blocks == 1) ? 1 : data->sg_len; 968 969 /* Only do DMA for entire blocks */ 970 use_dma = host->use_dma; 971 if (use_dma) { 972 for (i = 0; i < sg_len; i++) { 973 if ((data->sg[i].length % block_size) != 0) { 974 use_dma = 0; 975 break; 976 } 977 } 978 } 979 980 host->sg_idx = 0; 981 if (use_dma) { 982 enum dma_data_direction dma_data_dir; 983 struct dma_async_tx_descriptor *tx; 984 struct dma_chan *c; 985 u32 burst, *bp; 986 u16 buf; 987 988 /* 989 * FIFO is 16x2 bytes on 15xx, and 32x2 bytes on 16xx 990 * and 24xx. Use 16 or 32 word frames when the 991 * blocksize is at least that large. Blocksize is 992 * usually 512 bytes; but not for some SD reads. 993 */ 994 burst = cpu_is_omap15xx() ? 32 : 64; 995 if (burst > data->blksz) 996 burst = data->blksz; 997 998 burst >>= 1; 999 1000 if (data->flags & MMC_DATA_WRITE) { 1001 c = host->dma_tx; 1002 bp = &host->dma_tx_burst; 1003 buf = 0x0f80 | (burst - 1) << 0; 1004 dma_data_dir = DMA_TO_DEVICE; 1005 } else { 1006 c = host->dma_rx; 1007 bp = &host->dma_rx_burst; 1008 buf = 0x800f | (burst - 1) << 8; 1009 dma_data_dir = DMA_FROM_DEVICE; 1010 } 1011 1012 if (!c) 1013 goto use_pio; 1014 1015 /* Only reconfigure if we have a different burst size */ 1016 if (*bp != burst) { 1017 struct dma_slave_config cfg; 1018 1019 cfg.src_addr = host->phys_base + OMAP_MMC_REG(host, DATA); 1020 cfg.dst_addr = host->phys_base + OMAP_MMC_REG(host, DATA); 1021 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1022 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; 1023 cfg.src_maxburst = burst; 1024 cfg.dst_maxburst = burst; 1025 1026 if (dmaengine_slave_config(c, &cfg)) 1027 goto use_pio; 1028 1029 *bp = burst; 1030 } 1031 1032 host->sg_len = dma_map_sg(c->device->dev, data->sg, sg_len, 1033 dma_data_dir); 1034 if (host->sg_len == 0) 1035 goto use_pio; 1036 1037 tx = dmaengine_prep_slave_sg(c, data->sg, host->sg_len, 1038 data->flags & MMC_DATA_WRITE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM, 1039 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 1040 if (!tx) 1041 goto use_pio; 1042 1043 OMAP_MMC_WRITE(host, BUF, buf); 1044 1045 tx->callback = mmc_omap_dma_callback; 1046 tx->callback_param = host; 1047 dmaengine_submit(tx); 1048 host->brs_received = 0; 1049 host->dma_done = 0; 1050 host->dma_in_use = 1; 1051 return; 1052 } 1053 use_pio: 1054 1055 /* Revert to PIO? */ 1056 OMAP_MMC_WRITE(host, BUF, 0x1f1f); 1057 host->total_bytes_left = data->blocks * block_size; 1058 host->sg_len = sg_len; 1059 mmc_omap_sg_to_buf(host); 1060 host->dma_in_use = 0; 1061 } 1062 1063 static void mmc_omap_start_request(struct mmc_omap_host *host, 1064 struct mmc_request *req) 1065 { 1066 BUG_ON(host->mrq != NULL); 1067 1068 host->mrq = req; 1069 1070 /* only touch fifo AFTER the controller readies it */ 1071 mmc_omap_prepare_data(host, req); 1072 mmc_omap_start_command(host, req->cmd); 1073 if (host->dma_in_use) { 1074 struct dma_chan *c = host->data->flags & MMC_DATA_WRITE ? 1075 host->dma_tx : host->dma_rx; 1076 1077 dma_async_issue_pending(c); 1078 } 1079 } 1080 1081 static void mmc_omap_request(struct mmc_host *mmc, struct mmc_request *req) 1082 { 1083 struct mmc_omap_slot *slot = mmc_priv(mmc); 1084 struct mmc_omap_host *host = slot->host; 1085 unsigned long flags; 1086 1087 spin_lock_irqsave(&host->slot_lock, flags); 1088 if (host->mmc != NULL) { 1089 BUG_ON(slot->mrq != NULL); 1090 slot->mrq = req; 1091 spin_unlock_irqrestore(&host->slot_lock, flags); 1092 return; 1093 } else 1094 host->mmc = mmc; 1095 spin_unlock_irqrestore(&host->slot_lock, flags); 1096 mmc_omap_select_slot(slot, 1); 1097 mmc_omap_start_request(host, req); 1098 } 1099 1100 static void mmc_omap_set_power(struct mmc_omap_slot *slot, int power_on, 1101 int vdd) 1102 { 1103 struct mmc_omap_host *host; 1104 1105 host = slot->host; 1106 1107 if (slot->pdata->set_power != NULL) 1108 slot->pdata->set_power(mmc_dev(slot->mmc), slot->id, power_on, 1109 vdd); 1110 1111 if (cpu_is_omap24xx()) { 1112 u16 w; 1113 1114 if (power_on) { 1115 w = OMAP_MMC_READ(host, CON); 1116 OMAP_MMC_WRITE(host, CON, w | (1 << 11)); 1117 } else { 1118 w = OMAP_MMC_READ(host, CON); 1119 OMAP_MMC_WRITE(host, CON, w & ~(1 << 11)); 1120 } 1121 } 1122 } 1123 1124 static int mmc_omap_calc_divisor(struct mmc_host *mmc, struct mmc_ios *ios) 1125 { 1126 struct mmc_omap_slot *slot = mmc_priv(mmc); 1127 struct mmc_omap_host *host = slot->host; 1128 int func_clk_rate = clk_get_rate(host->fclk); 1129 int dsor; 1130 1131 if (ios->clock == 0) 1132 return 0; 1133 1134 dsor = func_clk_rate / ios->clock; 1135 if (dsor < 1) 1136 dsor = 1; 1137 1138 if (func_clk_rate / dsor > ios->clock) 1139 dsor++; 1140 1141 if (dsor > 250) 1142 dsor = 250; 1143 1144 slot->fclk_freq = func_clk_rate / dsor; 1145 1146 if (ios->bus_width == MMC_BUS_WIDTH_4) 1147 dsor |= 1 << 15; 1148 1149 return dsor; 1150 } 1151 1152 static void mmc_omap_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1153 { 1154 struct mmc_omap_slot *slot = mmc_priv(mmc); 1155 struct mmc_omap_host *host = slot->host; 1156 int i, dsor; 1157 int clk_enabled; 1158 1159 mmc_omap_select_slot(slot, 0); 1160 1161 dsor = mmc_omap_calc_divisor(mmc, ios); 1162 1163 if (ios->vdd != slot->vdd) 1164 slot->vdd = ios->vdd; 1165 1166 clk_enabled = 0; 1167 switch (ios->power_mode) { 1168 case MMC_POWER_OFF: 1169 mmc_omap_set_power(slot, 0, ios->vdd); 1170 break; 1171 case MMC_POWER_UP: 1172 /* Cannot touch dsor yet, just power up MMC */ 1173 mmc_omap_set_power(slot, 1, ios->vdd); 1174 goto exit; 1175 case MMC_POWER_ON: 1176 mmc_omap_fclk_enable(host, 1); 1177 clk_enabled = 1; 1178 dsor |= 1 << 11; 1179 break; 1180 } 1181 1182 if (slot->bus_mode != ios->bus_mode) { 1183 if (slot->pdata->set_bus_mode != NULL) 1184 slot->pdata->set_bus_mode(mmc_dev(mmc), slot->id, 1185 ios->bus_mode); 1186 slot->bus_mode = ios->bus_mode; 1187 } 1188 1189 /* On insanely high arm_per frequencies something sometimes 1190 * goes somehow out of sync, and the POW bit is not being set, 1191 * which results in the while loop below getting stuck. 1192 * Writing to the CON register twice seems to do the trick. */ 1193 for (i = 0; i < 2; i++) 1194 OMAP_MMC_WRITE(host, CON, dsor); 1195 slot->saved_con = dsor; 1196 if (ios->power_mode == MMC_POWER_ON) { 1197 /* worst case at 400kHz, 80 cycles makes 200 microsecs */ 1198 int usecs = 250; 1199 1200 /* Send clock cycles, poll completion */ 1201 OMAP_MMC_WRITE(host, IE, 0); 1202 OMAP_MMC_WRITE(host, STAT, 0xffff); 1203 OMAP_MMC_WRITE(host, CMD, 1 << 7); 1204 while (usecs > 0 && (OMAP_MMC_READ(host, STAT) & 1) == 0) { 1205 udelay(1); 1206 usecs--; 1207 } 1208 OMAP_MMC_WRITE(host, STAT, 1); 1209 } 1210 1211 exit: 1212 mmc_omap_release_slot(slot, clk_enabled); 1213 } 1214 1215 static const struct mmc_host_ops mmc_omap_ops = { 1216 .request = mmc_omap_request, 1217 .set_ios = mmc_omap_set_ios, 1218 }; 1219 1220 static int __devinit mmc_omap_new_slot(struct mmc_omap_host *host, int id) 1221 { 1222 struct mmc_omap_slot *slot = NULL; 1223 struct mmc_host *mmc; 1224 int r; 1225 1226 mmc = mmc_alloc_host(sizeof(struct mmc_omap_slot), host->dev); 1227 if (mmc == NULL) 1228 return -ENOMEM; 1229 1230 slot = mmc_priv(mmc); 1231 slot->host = host; 1232 slot->mmc = mmc; 1233 slot->id = id; 1234 slot->pdata = &host->pdata->slots[id]; 1235 1236 host->slots[id] = slot; 1237 1238 mmc->caps = 0; 1239 if (host->pdata->slots[id].wires >= 4) 1240 mmc->caps |= MMC_CAP_4_BIT_DATA; 1241 1242 mmc->ops = &mmc_omap_ops; 1243 mmc->f_min = 400000; 1244 1245 if (cpu_class_is_omap2()) 1246 mmc->f_max = 48000000; 1247 else 1248 mmc->f_max = 24000000; 1249 if (host->pdata->max_freq) 1250 mmc->f_max = min(host->pdata->max_freq, mmc->f_max); 1251 mmc->ocr_avail = slot->pdata->ocr_mask; 1252 1253 /* Use scatterlist DMA to reduce per-transfer costs. 1254 * NOTE max_seg_size assumption that small blocks aren't 1255 * normally used (except e.g. for reading SD registers). 1256 */ 1257 mmc->max_segs = 32; 1258 mmc->max_blk_size = 2048; /* BLEN is 11 bits (+1) */ 1259 mmc->max_blk_count = 2048; /* NBLK is 11 bits (+1) */ 1260 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 1261 mmc->max_seg_size = mmc->max_req_size; 1262 1263 r = mmc_add_host(mmc); 1264 if (r < 0) 1265 goto err_remove_host; 1266 1267 if (slot->pdata->name != NULL) { 1268 r = device_create_file(&mmc->class_dev, 1269 &dev_attr_slot_name); 1270 if (r < 0) 1271 goto err_remove_host; 1272 } 1273 1274 if (slot->pdata->get_cover_state != NULL) { 1275 r = device_create_file(&mmc->class_dev, 1276 &dev_attr_cover_switch); 1277 if (r < 0) 1278 goto err_remove_slot_name; 1279 1280 setup_timer(&slot->cover_timer, mmc_omap_cover_timer, 1281 (unsigned long)slot); 1282 tasklet_init(&slot->cover_tasklet, mmc_omap_cover_handler, 1283 (unsigned long)slot); 1284 tasklet_schedule(&slot->cover_tasklet); 1285 } 1286 1287 return 0; 1288 1289 err_remove_slot_name: 1290 if (slot->pdata->name != NULL) 1291 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1292 err_remove_host: 1293 mmc_remove_host(mmc); 1294 mmc_free_host(mmc); 1295 return r; 1296 } 1297 1298 static void mmc_omap_remove_slot(struct mmc_omap_slot *slot) 1299 { 1300 struct mmc_host *mmc = slot->mmc; 1301 1302 if (slot->pdata->name != NULL) 1303 device_remove_file(&mmc->class_dev, &dev_attr_slot_name); 1304 if (slot->pdata->get_cover_state != NULL) 1305 device_remove_file(&mmc->class_dev, &dev_attr_cover_switch); 1306 1307 tasklet_kill(&slot->cover_tasklet); 1308 del_timer_sync(&slot->cover_timer); 1309 flush_workqueue(slot->host->mmc_omap_wq); 1310 1311 mmc_remove_host(mmc); 1312 mmc_free_host(mmc); 1313 } 1314 1315 static int __devinit mmc_omap_probe(struct platform_device *pdev) 1316 { 1317 struct omap_mmc_platform_data *pdata = pdev->dev.platform_data; 1318 struct mmc_omap_host *host = NULL; 1319 struct resource *res; 1320 dma_cap_mask_t mask; 1321 unsigned sig; 1322 int i, ret = 0; 1323 int irq; 1324 1325 if (pdata == NULL) { 1326 dev_err(&pdev->dev, "platform data missing\n"); 1327 return -ENXIO; 1328 } 1329 if (pdata->nr_slots == 0) { 1330 dev_err(&pdev->dev, "no slots\n"); 1331 return -ENXIO; 1332 } 1333 1334 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1335 irq = platform_get_irq(pdev, 0); 1336 if (res == NULL || irq < 0) 1337 return -ENXIO; 1338 1339 res = request_mem_region(res->start, resource_size(res), 1340 pdev->name); 1341 if (res == NULL) 1342 return -EBUSY; 1343 1344 host = kzalloc(sizeof(struct mmc_omap_host), GFP_KERNEL); 1345 if (host == NULL) { 1346 ret = -ENOMEM; 1347 goto err_free_mem_region; 1348 } 1349 1350 INIT_WORK(&host->slot_release_work, mmc_omap_slot_release_work); 1351 INIT_WORK(&host->send_stop_work, mmc_omap_send_stop_work); 1352 1353 INIT_WORK(&host->cmd_abort_work, mmc_omap_abort_command); 1354 setup_timer(&host->cmd_abort_timer, mmc_omap_cmd_timer, 1355 (unsigned long) host); 1356 1357 spin_lock_init(&host->clk_lock); 1358 setup_timer(&host->clk_timer, mmc_omap_clk_timer, (unsigned long) host); 1359 1360 spin_lock_init(&host->dma_lock); 1361 spin_lock_init(&host->slot_lock); 1362 init_waitqueue_head(&host->slot_wq); 1363 1364 host->pdata = pdata; 1365 host->dev = &pdev->dev; 1366 platform_set_drvdata(pdev, host); 1367 1368 host->id = pdev->id; 1369 host->mem_res = res; 1370 host->irq = irq; 1371 host->use_dma = 1; 1372 host->irq = irq; 1373 host->phys_base = host->mem_res->start; 1374 host->virt_base = ioremap(res->start, resource_size(res)); 1375 if (!host->virt_base) 1376 goto err_ioremap; 1377 1378 host->iclk = clk_get(&pdev->dev, "ick"); 1379 if (IS_ERR(host->iclk)) { 1380 ret = PTR_ERR(host->iclk); 1381 goto err_free_mmc_host; 1382 } 1383 clk_enable(host->iclk); 1384 1385 host->fclk = clk_get(&pdev->dev, "fck"); 1386 if (IS_ERR(host->fclk)) { 1387 ret = PTR_ERR(host->fclk); 1388 goto err_free_iclk; 1389 } 1390 1391 dma_cap_zero(mask); 1392 dma_cap_set(DMA_SLAVE, mask); 1393 1394 host->dma_tx_burst = -1; 1395 host->dma_rx_burst = -1; 1396 1397 if (cpu_is_omap24xx()) 1398 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_TX : OMAP24XX_DMA_MMC2_TX; 1399 else 1400 sig = host->id == 0 ? OMAP_DMA_MMC_TX : OMAP_DMA_MMC2_TX; 1401 host->dma_tx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 1402 #if 0 1403 if (!host->dma_tx) { 1404 dev_err(host->dev, "unable to obtain TX DMA engine channel %u\n", 1405 sig); 1406 goto err_dma; 1407 } 1408 #else 1409 if (!host->dma_tx) 1410 dev_warn(host->dev, "unable to obtain TX DMA engine channel %u\n", 1411 sig); 1412 #endif 1413 if (cpu_is_omap24xx()) 1414 sig = host->id == 0 ? OMAP24XX_DMA_MMC1_RX : OMAP24XX_DMA_MMC2_RX; 1415 else 1416 sig = host->id == 0 ? OMAP_DMA_MMC_RX : OMAP_DMA_MMC2_RX; 1417 host->dma_rx = dma_request_channel(mask, omap_dma_filter_fn, &sig); 1418 #if 0 1419 if (!host->dma_rx) { 1420 dev_err(host->dev, "unable to obtain RX DMA engine channel %u\n", 1421 sig); 1422 goto err_dma; 1423 } 1424 #else 1425 if (!host->dma_rx) 1426 dev_warn(host->dev, "unable to obtain RX DMA engine channel %u\n", 1427 sig); 1428 #endif 1429 1430 ret = request_irq(host->irq, mmc_omap_irq, 0, DRIVER_NAME, host); 1431 if (ret) 1432 goto err_free_dma; 1433 1434 if (pdata->init != NULL) { 1435 ret = pdata->init(&pdev->dev); 1436 if (ret < 0) 1437 goto err_free_irq; 1438 } 1439 1440 host->nr_slots = pdata->nr_slots; 1441 host->reg_shift = (cpu_is_omap7xx() ? 1 : 2); 1442 1443 host->mmc_omap_wq = alloc_workqueue("mmc_omap", 0, 0); 1444 if (!host->mmc_omap_wq) 1445 goto err_plat_cleanup; 1446 1447 for (i = 0; i < pdata->nr_slots; i++) { 1448 ret = mmc_omap_new_slot(host, i); 1449 if (ret < 0) { 1450 while (--i >= 0) 1451 mmc_omap_remove_slot(host->slots[i]); 1452 1453 goto err_destroy_wq; 1454 } 1455 } 1456 1457 return 0; 1458 1459 err_destroy_wq: 1460 destroy_workqueue(host->mmc_omap_wq); 1461 err_plat_cleanup: 1462 if (pdata->cleanup) 1463 pdata->cleanup(&pdev->dev); 1464 err_free_irq: 1465 free_irq(host->irq, host); 1466 err_free_dma: 1467 if (host->dma_tx) 1468 dma_release_channel(host->dma_tx); 1469 if (host->dma_rx) 1470 dma_release_channel(host->dma_rx); 1471 clk_put(host->fclk); 1472 err_free_iclk: 1473 clk_disable(host->iclk); 1474 clk_put(host->iclk); 1475 err_free_mmc_host: 1476 iounmap(host->virt_base); 1477 err_ioremap: 1478 kfree(host); 1479 err_free_mem_region: 1480 release_mem_region(res->start, resource_size(res)); 1481 return ret; 1482 } 1483 1484 static int __devexit mmc_omap_remove(struct platform_device *pdev) 1485 { 1486 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1487 int i; 1488 1489 platform_set_drvdata(pdev, NULL); 1490 1491 BUG_ON(host == NULL); 1492 1493 for (i = 0; i < host->nr_slots; i++) 1494 mmc_omap_remove_slot(host->slots[i]); 1495 1496 if (host->pdata->cleanup) 1497 host->pdata->cleanup(&pdev->dev); 1498 1499 mmc_omap_fclk_enable(host, 0); 1500 free_irq(host->irq, host); 1501 clk_put(host->fclk); 1502 clk_disable(host->iclk); 1503 clk_put(host->iclk); 1504 1505 if (host->dma_tx) 1506 dma_release_channel(host->dma_tx); 1507 if (host->dma_rx) 1508 dma_release_channel(host->dma_rx); 1509 1510 iounmap(host->virt_base); 1511 release_mem_region(pdev->resource[0].start, 1512 pdev->resource[0].end - pdev->resource[0].start + 1); 1513 destroy_workqueue(host->mmc_omap_wq); 1514 1515 kfree(host); 1516 1517 return 0; 1518 } 1519 1520 #ifdef CONFIG_PM 1521 static int mmc_omap_suspend(struct platform_device *pdev, pm_message_t mesg) 1522 { 1523 int i, ret = 0; 1524 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1525 1526 if (host == NULL || host->suspended) 1527 return 0; 1528 1529 for (i = 0; i < host->nr_slots; i++) { 1530 struct mmc_omap_slot *slot; 1531 1532 slot = host->slots[i]; 1533 ret = mmc_suspend_host(slot->mmc); 1534 if (ret < 0) { 1535 while (--i >= 0) { 1536 slot = host->slots[i]; 1537 mmc_resume_host(slot->mmc); 1538 } 1539 return ret; 1540 } 1541 } 1542 host->suspended = 1; 1543 return 0; 1544 } 1545 1546 static int mmc_omap_resume(struct platform_device *pdev) 1547 { 1548 int i, ret = 0; 1549 struct mmc_omap_host *host = platform_get_drvdata(pdev); 1550 1551 if (host == NULL || !host->suspended) 1552 return 0; 1553 1554 for (i = 0; i < host->nr_slots; i++) { 1555 struct mmc_omap_slot *slot; 1556 slot = host->slots[i]; 1557 ret = mmc_resume_host(slot->mmc); 1558 if (ret < 0) 1559 return ret; 1560 1561 host->suspended = 0; 1562 } 1563 return 0; 1564 } 1565 #else 1566 #define mmc_omap_suspend NULL 1567 #define mmc_omap_resume NULL 1568 #endif 1569 1570 static struct platform_driver mmc_omap_driver = { 1571 .probe = mmc_omap_probe, 1572 .remove = __devexit_p(mmc_omap_remove), 1573 .suspend = mmc_omap_suspend, 1574 .resume = mmc_omap_resume, 1575 .driver = { 1576 .name = DRIVER_NAME, 1577 .owner = THIS_MODULE, 1578 }, 1579 }; 1580 1581 module_platform_driver(mmc_omap_driver); 1582 MODULE_DESCRIPTION("OMAP Multimedia Card driver"); 1583 MODULE_LICENSE("GPL"); 1584 MODULE_ALIAS("platform:" DRIVER_NAME); 1585 MODULE_AUTHOR("Juha Yrjölä"); 1586