1 /* 2 * linux/drivers/mmc/host/mxcmmc.c - Freescale i.MX MMCI driver 3 * 4 * This is a driver for the SDHC controller found in Freescale MX2/MX3 5 * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c). 6 * Unlike the hardware found on MX1, this hardware just works and does 7 * not need all the quirks found in imxmmc.c, hence the separate driver. 8 * 9 * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de> 10 * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com> 11 * 12 * derived from pxamci.c by Russell King 13 * 14 * This program is free software; you can redistribute it and/or modify 15 * it under the terms of the GNU General Public License version 2 as 16 * published by the Free Software Foundation. 17 * 18 */ 19 20 #include <linux/module.h> 21 #include <linux/init.h> 22 #include <linux/ioport.h> 23 #include <linux/platform_device.h> 24 #include <linux/interrupt.h> 25 #include <linux/irq.h> 26 #include <linux/blkdev.h> 27 #include <linux/dma-mapping.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/card.h> 30 #include <linux/delay.h> 31 #include <linux/clk.h> 32 #include <linux/io.h> 33 #include <linux/gpio.h> 34 35 #include <asm/dma.h> 36 #include <asm/irq.h> 37 #include <asm/sizes.h> 38 #include <mach/mmc.h> 39 40 #ifdef CONFIG_ARCH_MX2 41 #include <mach/dma-mx1-mx2.h> 42 #define HAS_DMA 43 #endif 44 45 #define DRIVER_NAME "mxc-mmc" 46 47 #define MMC_REG_STR_STP_CLK 0x00 48 #define MMC_REG_STATUS 0x04 49 #define MMC_REG_CLK_RATE 0x08 50 #define MMC_REG_CMD_DAT_CONT 0x0C 51 #define MMC_REG_RES_TO 0x10 52 #define MMC_REG_READ_TO 0x14 53 #define MMC_REG_BLK_LEN 0x18 54 #define MMC_REG_NOB 0x1C 55 #define MMC_REG_REV_NO 0x20 56 #define MMC_REG_INT_CNTR 0x24 57 #define MMC_REG_CMD 0x28 58 #define MMC_REG_ARG 0x2C 59 #define MMC_REG_RES_FIFO 0x34 60 #define MMC_REG_BUFFER_ACCESS 0x38 61 62 #define STR_STP_CLK_RESET (1 << 3) 63 #define STR_STP_CLK_START_CLK (1 << 1) 64 #define STR_STP_CLK_STOP_CLK (1 << 0) 65 66 #define STATUS_CARD_INSERTION (1 << 31) 67 #define STATUS_CARD_REMOVAL (1 << 30) 68 #define STATUS_YBUF_EMPTY (1 << 29) 69 #define STATUS_XBUF_EMPTY (1 << 28) 70 #define STATUS_YBUF_FULL (1 << 27) 71 #define STATUS_XBUF_FULL (1 << 26) 72 #define STATUS_BUF_UND_RUN (1 << 25) 73 #define STATUS_BUF_OVFL (1 << 24) 74 #define STATUS_SDIO_INT_ACTIVE (1 << 14) 75 #define STATUS_END_CMD_RESP (1 << 13) 76 #define STATUS_WRITE_OP_DONE (1 << 12) 77 #define STATUS_DATA_TRANS_DONE (1 << 11) 78 #define STATUS_READ_OP_DONE (1 << 11) 79 #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10) 80 #define STATUS_CARD_BUS_CLK_RUN (1 << 8) 81 #define STATUS_BUF_READ_RDY (1 << 7) 82 #define STATUS_BUF_WRITE_RDY (1 << 6) 83 #define STATUS_RESP_CRC_ERR (1 << 5) 84 #define STATUS_CRC_READ_ERR (1 << 3) 85 #define STATUS_CRC_WRITE_ERR (1 << 2) 86 #define STATUS_TIME_OUT_RESP (1 << 1) 87 #define STATUS_TIME_OUT_READ (1 << 0) 88 #define STATUS_ERR_MASK 0x2f 89 90 #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12) 91 #define CMD_DAT_CONT_STOP_READWAIT (1 << 11) 92 #define CMD_DAT_CONT_START_READWAIT (1 << 10) 93 #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8) 94 #define CMD_DAT_CONT_INIT (1 << 7) 95 #define CMD_DAT_CONT_WRITE (1 << 4) 96 #define CMD_DAT_CONT_DATA_ENABLE (1 << 3) 97 #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0) 98 #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0) 99 #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0) 100 101 #define INT_SDIO_INT_WKP_EN (1 << 18) 102 #define INT_CARD_INSERTION_WKP_EN (1 << 17) 103 #define INT_CARD_REMOVAL_WKP_EN (1 << 16) 104 #define INT_CARD_INSERTION_EN (1 << 15) 105 #define INT_CARD_REMOVAL_EN (1 << 14) 106 #define INT_SDIO_IRQ_EN (1 << 13) 107 #define INT_DAT0_EN (1 << 12) 108 #define INT_BUF_READ_EN (1 << 4) 109 #define INT_BUF_WRITE_EN (1 << 3) 110 #define INT_END_CMD_RES_EN (1 << 2) 111 #define INT_WRITE_OP_DONE_EN (1 << 1) 112 #define INT_READ_OP_EN (1 << 0) 113 114 struct mxcmci_host { 115 struct mmc_host *mmc; 116 struct resource *res; 117 void __iomem *base; 118 int irq; 119 int detect_irq; 120 int dma; 121 int do_dma; 122 int use_sdio; 123 unsigned int power_mode; 124 struct imxmmc_platform_data *pdata; 125 126 struct mmc_request *req; 127 struct mmc_command *cmd; 128 struct mmc_data *data; 129 130 unsigned int dma_nents; 131 unsigned int datasize; 132 unsigned int dma_dir; 133 134 u16 rev_no; 135 unsigned int cmdat; 136 137 struct clk *clk; 138 139 int clock; 140 141 struct work_struct datawork; 142 spinlock_t lock; 143 }; 144 145 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios); 146 147 static inline int mxcmci_use_dma(struct mxcmci_host *host) 148 { 149 return host->do_dma; 150 } 151 152 static void mxcmci_softreset(struct mxcmci_host *host) 153 { 154 int i; 155 156 dev_dbg(mmc_dev(host->mmc), "mxcmci_softreset\n"); 157 158 /* reset sequence */ 159 writew(STR_STP_CLK_RESET, host->base + MMC_REG_STR_STP_CLK); 160 writew(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK, 161 host->base + MMC_REG_STR_STP_CLK); 162 163 for (i = 0; i < 8; i++) 164 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 165 166 writew(0xff, host->base + MMC_REG_RES_TO); 167 } 168 169 static int mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data) 170 { 171 unsigned int nob = data->blocks; 172 unsigned int blksz = data->blksz; 173 unsigned int datasize = nob * blksz; 174 #ifdef HAS_DMA 175 struct scatterlist *sg; 176 int i; 177 int ret; 178 #endif 179 if (data->flags & MMC_DATA_STREAM) 180 nob = 0xffff; 181 182 host->data = data; 183 data->bytes_xfered = 0; 184 185 writew(nob, host->base + MMC_REG_NOB); 186 writew(blksz, host->base + MMC_REG_BLK_LEN); 187 host->datasize = datasize; 188 189 #ifdef HAS_DMA 190 for_each_sg(data->sg, sg, data->sg_len, i) { 191 if (sg->offset & 3 || sg->length & 3) { 192 host->do_dma = 0; 193 return 0; 194 } 195 } 196 197 if (data->flags & MMC_DATA_READ) { 198 host->dma_dir = DMA_FROM_DEVICE; 199 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 200 data->sg_len, host->dma_dir); 201 202 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, 203 datasize, 204 host->res->start + MMC_REG_BUFFER_ACCESS, 205 DMA_MODE_READ); 206 } else { 207 host->dma_dir = DMA_TO_DEVICE; 208 host->dma_nents = dma_map_sg(mmc_dev(host->mmc), data->sg, 209 data->sg_len, host->dma_dir); 210 211 ret = imx_dma_setup_sg(host->dma, data->sg, host->dma_nents, 212 datasize, 213 host->res->start + MMC_REG_BUFFER_ACCESS, 214 DMA_MODE_WRITE); 215 } 216 217 if (ret) { 218 dev_err(mmc_dev(host->mmc), "failed to setup DMA : %d\n", ret); 219 return ret; 220 } 221 wmb(); 222 223 imx_dma_enable(host->dma); 224 #endif /* HAS_DMA */ 225 return 0; 226 } 227 228 static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_command *cmd, 229 unsigned int cmdat) 230 { 231 u32 int_cntr; 232 unsigned long flags; 233 234 WARN_ON(host->cmd != NULL); 235 host->cmd = cmd; 236 237 switch (mmc_resp_type(cmd)) { 238 case MMC_RSP_R1: /* short CRC, OPCODE */ 239 case MMC_RSP_R1B:/* short CRC, OPCODE, BUSY */ 240 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC; 241 break; 242 case MMC_RSP_R2: /* long 136 bit + CRC */ 243 cmdat |= CMD_DAT_CONT_RESPONSE_136BIT; 244 break; 245 case MMC_RSP_R3: /* short */ 246 cmdat |= CMD_DAT_CONT_RESPONSE_48BIT; 247 break; 248 case MMC_RSP_NONE: 249 break; 250 default: 251 dev_err(mmc_dev(host->mmc), "unhandled response type 0x%x\n", 252 mmc_resp_type(cmd)); 253 cmd->error = -EINVAL; 254 return -EINVAL; 255 } 256 257 int_cntr = INT_END_CMD_RES_EN; 258 259 if (mxcmci_use_dma(host)) 260 int_cntr |= INT_READ_OP_EN | INT_WRITE_OP_DONE_EN; 261 262 spin_lock_irqsave(&host->lock, flags); 263 if (host->use_sdio) 264 int_cntr |= INT_SDIO_IRQ_EN; 265 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 266 spin_unlock_irqrestore(&host->lock, flags); 267 268 writew(cmd->opcode, host->base + MMC_REG_CMD); 269 writel(cmd->arg, host->base + MMC_REG_ARG); 270 writew(cmdat, host->base + MMC_REG_CMD_DAT_CONT); 271 272 return 0; 273 } 274 275 static void mxcmci_finish_request(struct mxcmci_host *host, 276 struct mmc_request *req) 277 { 278 u32 int_cntr = 0; 279 unsigned long flags; 280 281 spin_lock_irqsave(&host->lock, flags); 282 if (host->use_sdio) 283 int_cntr |= INT_SDIO_IRQ_EN; 284 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 285 spin_unlock_irqrestore(&host->lock, flags); 286 287 host->req = NULL; 288 host->cmd = NULL; 289 host->data = NULL; 290 291 mmc_request_done(host->mmc, req); 292 } 293 294 static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat) 295 { 296 struct mmc_data *data = host->data; 297 int data_error; 298 299 #ifdef HAS_DMA 300 if (mxcmci_use_dma(host)) { 301 imx_dma_disable(host->dma); 302 dma_unmap_sg(mmc_dev(host->mmc), data->sg, host->dma_nents, 303 host->dma_dir); 304 } 305 #endif 306 307 if (stat & STATUS_ERR_MASK) { 308 dev_dbg(mmc_dev(host->mmc), "request failed. status: 0x%08x\n", 309 stat); 310 if (stat & STATUS_CRC_READ_ERR) { 311 dev_err(mmc_dev(host->mmc), "%s: -EILSEQ\n", __func__); 312 data->error = -EILSEQ; 313 } else if (stat & STATUS_CRC_WRITE_ERR) { 314 u32 err_code = (stat >> 9) & 0x3; 315 if (err_code == 2) { /* No CRC response */ 316 dev_err(mmc_dev(host->mmc), 317 "%s: No CRC -ETIMEDOUT\n", __func__); 318 data->error = -ETIMEDOUT; 319 } else { 320 dev_err(mmc_dev(host->mmc), 321 "%s: -EILSEQ\n", __func__); 322 data->error = -EILSEQ; 323 } 324 } else if (stat & STATUS_TIME_OUT_READ) { 325 dev_err(mmc_dev(host->mmc), 326 "%s: read -ETIMEDOUT\n", __func__); 327 data->error = -ETIMEDOUT; 328 } else { 329 dev_err(mmc_dev(host->mmc), "%s: -EIO\n", __func__); 330 data->error = -EIO; 331 } 332 } else { 333 data->bytes_xfered = host->datasize; 334 } 335 336 data_error = data->error; 337 338 host->data = NULL; 339 340 return data_error; 341 } 342 343 static void mxcmci_read_response(struct mxcmci_host *host, unsigned int stat) 344 { 345 struct mmc_command *cmd = host->cmd; 346 int i; 347 u32 a, b, c; 348 349 if (!cmd) 350 return; 351 352 if (stat & STATUS_TIME_OUT_RESP) { 353 dev_dbg(mmc_dev(host->mmc), "CMD TIMEOUT\n"); 354 cmd->error = -ETIMEDOUT; 355 } else if (stat & STATUS_RESP_CRC_ERR && cmd->flags & MMC_RSP_CRC) { 356 dev_dbg(mmc_dev(host->mmc), "cmd crc error\n"); 357 cmd->error = -EILSEQ; 358 } 359 360 if (cmd->flags & MMC_RSP_PRESENT) { 361 if (cmd->flags & MMC_RSP_136) { 362 for (i = 0; i < 4; i++) { 363 a = readw(host->base + MMC_REG_RES_FIFO); 364 b = readw(host->base + MMC_REG_RES_FIFO); 365 cmd->resp[i] = a << 16 | b; 366 } 367 } else { 368 a = readw(host->base + MMC_REG_RES_FIFO); 369 b = readw(host->base + MMC_REG_RES_FIFO); 370 c = readw(host->base + MMC_REG_RES_FIFO); 371 cmd->resp[0] = a << 24 | b << 8 | c >> 8; 372 } 373 } 374 } 375 376 static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask) 377 { 378 u32 stat; 379 unsigned long timeout = jiffies + HZ; 380 381 do { 382 stat = readl(host->base + MMC_REG_STATUS); 383 if (stat & STATUS_ERR_MASK) 384 return stat; 385 if (time_after(jiffies, timeout)) { 386 mxcmci_softreset(host); 387 mxcmci_set_clk_rate(host, host->clock); 388 return STATUS_TIME_OUT_READ; 389 } 390 if (stat & mask) 391 return 0; 392 cpu_relax(); 393 } while (1); 394 } 395 396 static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes) 397 { 398 unsigned int stat; 399 u32 *buf = _buf; 400 401 while (bytes > 3) { 402 stat = mxcmci_poll_status(host, 403 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 404 if (stat) 405 return stat; 406 *buf++ = readl(host->base + MMC_REG_BUFFER_ACCESS); 407 bytes -= 4; 408 } 409 410 if (bytes) { 411 u8 *b = (u8 *)buf; 412 u32 tmp; 413 414 stat = mxcmci_poll_status(host, 415 STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE); 416 if (stat) 417 return stat; 418 tmp = readl(host->base + MMC_REG_BUFFER_ACCESS); 419 memcpy(b, &tmp, bytes); 420 } 421 422 return 0; 423 } 424 425 static int mxcmci_push(struct mxcmci_host *host, void *_buf, int bytes) 426 { 427 unsigned int stat; 428 u32 *buf = _buf; 429 430 while (bytes > 3) { 431 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 432 if (stat) 433 return stat; 434 writel(*buf++, host->base + MMC_REG_BUFFER_ACCESS); 435 bytes -= 4; 436 } 437 438 if (bytes) { 439 u8 *b = (u8 *)buf; 440 u32 tmp; 441 442 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 443 if (stat) 444 return stat; 445 446 memcpy(&tmp, b, bytes); 447 writel(tmp, host->base + MMC_REG_BUFFER_ACCESS); 448 } 449 450 stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY); 451 if (stat) 452 return stat; 453 454 return 0; 455 } 456 457 static int mxcmci_transfer_data(struct mxcmci_host *host) 458 { 459 struct mmc_data *data = host->req->data; 460 struct scatterlist *sg; 461 int stat, i; 462 463 host->data = data; 464 host->datasize = 0; 465 466 if (data->flags & MMC_DATA_READ) { 467 for_each_sg(data->sg, sg, data->sg_len, i) { 468 stat = mxcmci_pull(host, sg_virt(sg), sg->length); 469 if (stat) 470 return stat; 471 host->datasize += sg->length; 472 } 473 } else { 474 for_each_sg(data->sg, sg, data->sg_len, i) { 475 stat = mxcmci_push(host, sg_virt(sg), sg->length); 476 if (stat) 477 return stat; 478 host->datasize += sg->length; 479 } 480 stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE); 481 if (stat) 482 return stat; 483 } 484 return 0; 485 } 486 487 static void mxcmci_datawork(struct work_struct *work) 488 { 489 struct mxcmci_host *host = container_of(work, struct mxcmci_host, 490 datawork); 491 int datastat = mxcmci_transfer_data(host); 492 493 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 494 host->base + MMC_REG_STATUS); 495 mxcmci_finish_data(host, datastat); 496 497 if (host->req->stop) { 498 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 499 mxcmci_finish_request(host, host->req); 500 return; 501 } 502 } else { 503 mxcmci_finish_request(host, host->req); 504 } 505 } 506 507 #ifdef HAS_DMA 508 static void mxcmci_data_done(struct mxcmci_host *host, unsigned int stat) 509 { 510 struct mmc_data *data = host->data; 511 int data_error; 512 513 if (!data) 514 return; 515 516 data_error = mxcmci_finish_data(host, stat); 517 518 mxcmci_read_response(host, stat); 519 host->cmd = NULL; 520 521 if (host->req->stop) { 522 if (mxcmci_start_cmd(host, host->req->stop, 0)) { 523 mxcmci_finish_request(host, host->req); 524 return; 525 } 526 } else { 527 mxcmci_finish_request(host, host->req); 528 } 529 } 530 #endif /* HAS_DMA */ 531 532 static void mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat) 533 { 534 mxcmci_read_response(host, stat); 535 host->cmd = NULL; 536 537 if (!host->data && host->req) { 538 mxcmci_finish_request(host, host->req); 539 return; 540 } 541 542 /* For the DMA case the DMA engine handles the data transfer 543 * automatically. For non DMA we have to do it ourselves. 544 * Don't do it in interrupt context though. 545 */ 546 if (!mxcmci_use_dma(host) && host->data) 547 schedule_work(&host->datawork); 548 549 } 550 551 static irqreturn_t mxcmci_irq(int irq, void *devid) 552 { 553 struct mxcmci_host *host = devid; 554 unsigned long flags; 555 bool sdio_irq; 556 u32 stat; 557 558 stat = readl(host->base + MMC_REG_STATUS); 559 writel(stat & ~(STATUS_SDIO_INT_ACTIVE | STATUS_DATA_TRANS_DONE | 560 STATUS_WRITE_OP_DONE), host->base + MMC_REG_STATUS); 561 562 dev_dbg(mmc_dev(host->mmc), "%s: 0x%08x\n", __func__, stat); 563 564 spin_lock_irqsave(&host->lock, flags); 565 sdio_irq = (stat & STATUS_SDIO_INT_ACTIVE) && host->use_sdio; 566 spin_unlock_irqrestore(&host->lock, flags); 567 568 #ifdef HAS_DMA 569 if (mxcmci_use_dma(host) && 570 (stat & (STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE))) 571 writel(STATUS_READ_OP_DONE | STATUS_WRITE_OP_DONE, 572 host->base + MMC_REG_STATUS); 573 #endif 574 575 if (sdio_irq) { 576 writel(STATUS_SDIO_INT_ACTIVE, host->base + MMC_REG_STATUS); 577 mmc_signal_sdio_irq(host->mmc); 578 } 579 580 if (stat & STATUS_END_CMD_RESP) 581 mxcmci_cmd_done(host, stat); 582 583 #ifdef HAS_DMA 584 if (mxcmci_use_dma(host) && 585 (stat & (STATUS_DATA_TRANS_DONE | STATUS_WRITE_OP_DONE))) 586 mxcmci_data_done(host, stat); 587 #endif 588 return IRQ_HANDLED; 589 } 590 591 static void mxcmci_request(struct mmc_host *mmc, struct mmc_request *req) 592 { 593 struct mxcmci_host *host = mmc_priv(mmc); 594 unsigned int cmdat = host->cmdat; 595 int error; 596 597 WARN_ON(host->req != NULL); 598 599 host->req = req; 600 host->cmdat &= ~CMD_DAT_CONT_INIT; 601 #ifdef HAS_DMA 602 host->do_dma = 1; 603 #endif 604 if (req->data) { 605 error = mxcmci_setup_data(host, req->data); 606 if (error) { 607 req->cmd->error = error; 608 goto out; 609 } 610 611 612 cmdat |= CMD_DAT_CONT_DATA_ENABLE; 613 614 if (req->data->flags & MMC_DATA_WRITE) 615 cmdat |= CMD_DAT_CONT_WRITE; 616 } 617 618 error = mxcmci_start_cmd(host, req->cmd, cmdat); 619 out: 620 if (error) 621 mxcmci_finish_request(host, req); 622 } 623 624 static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios) 625 { 626 unsigned int divider; 627 int prescaler = 0; 628 unsigned int clk_in = clk_get_rate(host->clk); 629 630 while (prescaler <= 0x800) { 631 for (divider = 1; divider <= 0xF; divider++) { 632 int x; 633 634 x = (clk_in / (divider + 1)); 635 636 if (prescaler) 637 x /= (prescaler * 2); 638 639 if (x <= clk_ios) 640 break; 641 } 642 if (divider < 0x10) 643 break; 644 645 if (prescaler == 0) 646 prescaler = 1; 647 else 648 prescaler <<= 1; 649 } 650 651 writew((prescaler << 4) | divider, host->base + MMC_REG_CLK_RATE); 652 653 dev_dbg(mmc_dev(host->mmc), "scaler: %d divider: %d in: %d out: %d\n", 654 prescaler, divider, clk_in, clk_ios); 655 } 656 657 static void mxcmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 658 { 659 struct mxcmci_host *host = mmc_priv(mmc); 660 #ifdef HAS_DMA 661 unsigned int blen; 662 /* 663 * use burstlen of 64 in 4 bit mode (--> reg value 0) 664 * use burstlen of 16 in 1 bit mode (--> reg value 16) 665 */ 666 if (ios->bus_width == MMC_BUS_WIDTH_4) 667 blen = 0; 668 else 669 blen = 16; 670 671 imx_dma_config_burstlen(host->dma, blen); 672 #endif 673 if (ios->bus_width == MMC_BUS_WIDTH_4) 674 host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4; 675 else 676 host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4; 677 678 if (host->power_mode != ios->power_mode) { 679 if (host->pdata && host->pdata->setpower) 680 host->pdata->setpower(mmc_dev(mmc), ios->vdd); 681 host->power_mode = ios->power_mode; 682 if (ios->power_mode == MMC_POWER_ON) 683 host->cmdat |= CMD_DAT_CONT_INIT; 684 } 685 686 if (ios->clock) { 687 mxcmci_set_clk_rate(host, ios->clock); 688 writew(STR_STP_CLK_START_CLK, host->base + MMC_REG_STR_STP_CLK); 689 } else { 690 writew(STR_STP_CLK_STOP_CLK, host->base + MMC_REG_STR_STP_CLK); 691 } 692 693 host->clock = ios->clock; 694 } 695 696 static irqreturn_t mxcmci_detect_irq(int irq, void *data) 697 { 698 struct mmc_host *mmc = data; 699 700 dev_dbg(mmc_dev(mmc), "%s\n", __func__); 701 702 mmc_detect_change(mmc, msecs_to_jiffies(250)); 703 return IRQ_HANDLED; 704 } 705 706 static int mxcmci_get_ro(struct mmc_host *mmc) 707 { 708 struct mxcmci_host *host = mmc_priv(mmc); 709 710 if (host->pdata && host->pdata->get_ro) 711 return !!host->pdata->get_ro(mmc_dev(mmc)); 712 /* 713 * Board doesn't support read only detection; let the mmc core 714 * decide what to do. 715 */ 716 return -ENOSYS; 717 } 718 719 static void mxcmci_enable_sdio_irq(struct mmc_host *mmc, int enable) 720 { 721 struct mxcmci_host *host = mmc_priv(mmc); 722 unsigned long flags; 723 u32 int_cntr; 724 725 spin_lock_irqsave(&host->lock, flags); 726 host->use_sdio = enable; 727 int_cntr = readl(host->base + MMC_REG_INT_CNTR); 728 729 if (enable) 730 int_cntr |= INT_SDIO_IRQ_EN; 731 else 732 int_cntr &= ~INT_SDIO_IRQ_EN; 733 734 writel(int_cntr, host->base + MMC_REG_INT_CNTR); 735 spin_unlock_irqrestore(&host->lock, flags); 736 } 737 738 static void mxcmci_init_card(struct mmc_host *host, struct mmc_card *card) 739 { 740 /* 741 * MX3 SoCs have a silicon bug which corrupts CRC calculation of 742 * multi-block transfers when connected SDIO peripheral doesn't 743 * drive the BUSY line as required by the specs. 744 * One way to prevent this is to only allow 1-bit transfers. 745 */ 746 747 if (cpu_is_mx3() && card->type == MMC_TYPE_SDIO) 748 host->caps &= ~MMC_CAP_4_BIT_DATA; 749 else 750 host->caps |= MMC_CAP_4_BIT_DATA; 751 } 752 753 static const struct mmc_host_ops mxcmci_ops = { 754 .request = mxcmci_request, 755 .set_ios = mxcmci_set_ios, 756 .get_ro = mxcmci_get_ro, 757 .enable_sdio_irq = mxcmci_enable_sdio_irq, 758 .init_card = mxcmci_init_card, 759 }; 760 761 static int mxcmci_probe(struct platform_device *pdev) 762 { 763 struct mmc_host *mmc; 764 struct mxcmci_host *host = NULL; 765 struct resource *iores, *r; 766 int ret = 0, irq; 767 768 printk(KERN_INFO "i.MX SDHC driver\n"); 769 770 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 771 irq = platform_get_irq(pdev, 0); 772 if (!iores || irq < 0) 773 return -EINVAL; 774 775 r = request_mem_region(iores->start, resource_size(iores), pdev->name); 776 if (!r) 777 return -EBUSY; 778 779 mmc = mmc_alloc_host(sizeof(struct mxcmci_host), &pdev->dev); 780 if (!mmc) { 781 ret = -ENOMEM; 782 goto out_release_mem; 783 } 784 785 mmc->ops = &mxcmci_ops; 786 mmc->caps = MMC_CAP_4_BIT_DATA | MMC_CAP_SDIO_IRQ; 787 788 /* MMC core transfer sizes tunable parameters */ 789 mmc->max_hw_segs = 64; 790 mmc->max_phys_segs = 64; 791 mmc->max_blk_size = 2048; 792 mmc->max_blk_count = 65535; 793 mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; 794 mmc->max_seg_size = mmc->max_req_size; 795 796 host = mmc_priv(mmc); 797 host->base = ioremap(r->start, resource_size(r)); 798 if (!host->base) { 799 ret = -ENOMEM; 800 goto out_free; 801 } 802 803 host->mmc = mmc; 804 host->pdata = pdev->dev.platform_data; 805 spin_lock_init(&host->lock); 806 807 if (host->pdata && host->pdata->ocr_avail) 808 mmc->ocr_avail = host->pdata->ocr_avail; 809 else 810 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; 811 812 host->res = r; 813 host->irq = irq; 814 815 host->clk = clk_get(&pdev->dev, NULL); 816 if (IS_ERR(host->clk)) { 817 ret = PTR_ERR(host->clk); 818 goto out_iounmap; 819 } 820 clk_enable(host->clk); 821 822 mxcmci_softreset(host); 823 824 host->rev_no = readw(host->base + MMC_REG_REV_NO); 825 if (host->rev_no != 0x400) { 826 ret = -ENODEV; 827 dev_err(mmc_dev(host->mmc), "wrong rev.no. 0x%08x. aborting.\n", 828 host->rev_no); 829 goto out_clk_put; 830 } 831 832 mmc->f_min = clk_get_rate(host->clk) >> 16; 833 mmc->f_max = clk_get_rate(host->clk) >> 1; 834 835 /* recommended in data sheet */ 836 writew(0x2db4, host->base + MMC_REG_READ_TO); 837 838 writel(0, host->base + MMC_REG_INT_CNTR); 839 840 #ifdef HAS_DMA 841 host->dma = imx_dma_request_by_prio(DRIVER_NAME, DMA_PRIO_LOW); 842 if (host->dma < 0) { 843 dev_err(mmc_dev(host->mmc), "imx_dma_request_by_prio failed\n"); 844 ret = -EBUSY; 845 goto out_clk_put; 846 } 847 848 r = platform_get_resource(pdev, IORESOURCE_DMA, 0); 849 if (!r) { 850 ret = -EINVAL; 851 goto out_free_dma; 852 } 853 854 ret = imx_dma_config_channel(host->dma, 855 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_FIFO, 856 IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR, 857 r->start, 0); 858 if (ret) { 859 dev_err(mmc_dev(host->mmc), "failed to config DMA channel\n"); 860 goto out_free_dma; 861 } 862 #endif 863 INIT_WORK(&host->datawork, mxcmci_datawork); 864 865 ret = request_irq(host->irq, mxcmci_irq, 0, DRIVER_NAME, host); 866 if (ret) 867 goto out_free_dma; 868 869 platform_set_drvdata(pdev, mmc); 870 871 if (host->pdata && host->pdata->init) { 872 ret = host->pdata->init(&pdev->dev, mxcmci_detect_irq, 873 host->mmc); 874 if (ret) 875 goto out_free_irq; 876 } 877 878 mmc_add_host(mmc); 879 880 return 0; 881 882 out_free_irq: 883 free_irq(host->irq, host); 884 out_free_dma: 885 #ifdef HAS_DMA 886 imx_dma_free(host->dma); 887 #endif 888 out_clk_put: 889 clk_disable(host->clk); 890 clk_put(host->clk); 891 out_iounmap: 892 iounmap(host->base); 893 out_free: 894 mmc_free_host(mmc); 895 out_release_mem: 896 release_mem_region(iores->start, resource_size(iores)); 897 return ret; 898 } 899 900 static int mxcmci_remove(struct platform_device *pdev) 901 { 902 struct mmc_host *mmc = platform_get_drvdata(pdev); 903 struct mxcmci_host *host = mmc_priv(mmc); 904 905 platform_set_drvdata(pdev, NULL); 906 907 mmc_remove_host(mmc); 908 909 if (host->pdata && host->pdata->exit) 910 host->pdata->exit(&pdev->dev, mmc); 911 912 free_irq(host->irq, host); 913 iounmap(host->base); 914 #ifdef HAS_DMA 915 imx_dma_free(host->dma); 916 #endif 917 clk_disable(host->clk); 918 clk_put(host->clk); 919 920 release_mem_region(host->res->start, resource_size(host->res)); 921 release_resource(host->res); 922 923 mmc_free_host(mmc); 924 925 return 0; 926 } 927 928 #ifdef CONFIG_PM 929 static int mxcmci_suspend(struct platform_device *dev, pm_message_t state) 930 { 931 struct mmc_host *mmc = platform_get_drvdata(dev); 932 int ret = 0; 933 934 if (mmc) 935 ret = mmc_suspend_host(mmc); 936 937 return ret; 938 } 939 940 static int mxcmci_resume(struct platform_device *dev) 941 { 942 struct mmc_host *mmc = platform_get_drvdata(dev); 943 struct mxcmci_host *host; 944 int ret = 0; 945 946 if (mmc) { 947 host = mmc_priv(mmc); 948 ret = mmc_resume_host(mmc); 949 } 950 951 return ret; 952 } 953 #else 954 #define mxcmci_suspend NULL 955 #define mxcmci_resume NULL 956 #endif /* CONFIG_PM */ 957 958 static struct platform_driver mxcmci_driver = { 959 .probe = mxcmci_probe, 960 .remove = mxcmci_remove, 961 .suspend = mxcmci_suspend, 962 .resume = mxcmci_resume, 963 .driver = { 964 .name = DRIVER_NAME, 965 .owner = THIS_MODULE, 966 } 967 }; 968 969 static int __init mxcmci_init(void) 970 { 971 return platform_driver_register(&mxcmci_driver); 972 } 973 974 static void __exit mxcmci_exit(void) 975 { 976 platform_driver_unregister(&mxcmci_driver); 977 } 978 979 module_init(mxcmci_init); 980 module_exit(mxcmci_exit); 981 982 MODULE_DESCRIPTION("i.MX Multimedia Card Interface Driver"); 983 MODULE_AUTHOR("Sascha Hauer, Pengutronix"); 984 MODULE_LICENSE("GPL"); 985 MODULE_ALIAS("platform:imx-mmc"); 986