1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_device.h> 23 #include <linux/of_irq.h> 24 #include <linux/of_gpio.h> 25 #include <linux/pinctrl/consumer.h> 26 #include <linux/platform_device.h> 27 #include <linux/pm.h> 28 #include <linux/pm_runtime.h> 29 #include <linux/regulator/consumer.h> 30 #include <linux/slab.h> 31 #include <linux/spinlock.h> 32 #include <linux/interrupt.h> 33 34 #include <linux/mmc/card.h> 35 #include <linux/mmc/core.h> 36 #include <linux/mmc/host.h> 37 #include <linux/mmc/mmc.h> 38 #include <linux/mmc/sd.h> 39 #include <linux/mmc/sdio.h> 40 #include <linux/mmc/slot-gpio.h> 41 42 #define MAX_BD_NUM 1024 43 44 /*--------------------------------------------------------------------------*/ 45 /* Common Definition */ 46 /*--------------------------------------------------------------------------*/ 47 #define MSDC_BUS_1BITS 0x0 48 #define MSDC_BUS_4BITS 0x1 49 #define MSDC_BUS_8BITS 0x2 50 51 #define MSDC_BURST_64B 0x6 52 53 /*--------------------------------------------------------------------------*/ 54 /* Register Offset */ 55 /*--------------------------------------------------------------------------*/ 56 #define MSDC_CFG 0x0 57 #define MSDC_IOCON 0x04 58 #define MSDC_PS 0x08 59 #define MSDC_INT 0x0c 60 #define MSDC_INTEN 0x10 61 #define MSDC_FIFOCS 0x14 62 #define SDC_CFG 0x30 63 #define SDC_CMD 0x34 64 #define SDC_ARG 0x38 65 #define SDC_STS 0x3c 66 #define SDC_RESP0 0x40 67 #define SDC_RESP1 0x44 68 #define SDC_RESP2 0x48 69 #define SDC_RESP3 0x4c 70 #define SDC_BLK_NUM 0x50 71 #define SDC_ADV_CFG0 0x64 72 #define EMMC_IOCON 0x7c 73 #define SDC_ACMD_RESP 0x80 74 #define DMA_SA_H4BIT 0x8c 75 #define MSDC_DMA_SA 0x90 76 #define MSDC_DMA_CTRL 0x98 77 #define MSDC_DMA_CFG 0x9c 78 #define MSDC_PATCH_BIT 0xb0 79 #define MSDC_PATCH_BIT1 0xb4 80 #define MSDC_PATCH_BIT2 0xb8 81 #define MSDC_PAD_TUNE 0xec 82 #define MSDC_PAD_TUNE0 0xf0 83 #define PAD_DS_TUNE 0x188 84 #define PAD_CMD_TUNE 0x18c 85 #define EMMC50_CFG0 0x208 86 #define EMMC50_CFG3 0x220 87 #define SDC_FIFO_CFG 0x228 88 89 /*--------------------------------------------------------------------------*/ 90 /* Register Mask */ 91 /*--------------------------------------------------------------------------*/ 92 93 /* MSDC_CFG mask */ 94 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 95 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 96 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 97 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 98 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 99 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 100 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 101 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 102 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 103 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 104 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 105 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 106 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 107 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 108 109 /* MSDC_IOCON mask */ 110 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 111 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 112 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 113 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 114 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 115 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 116 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 117 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 118 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 119 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 120 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 121 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 122 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 123 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 124 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 125 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 126 127 /* MSDC_PS mask */ 128 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 129 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 130 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 131 #define MSDC_PS_DAT (0xff << 16) /* R */ 132 #define MSDC_PS_CMD (0x1 << 24) /* R */ 133 #define MSDC_PS_WP (0x1 << 31) /* R */ 134 135 /* MSDC_INT mask */ 136 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 137 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 138 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 139 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 140 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 141 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 142 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 143 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 144 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 145 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 146 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 147 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 148 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 149 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 150 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 151 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 152 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 153 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 154 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 155 156 /* MSDC_INTEN mask */ 157 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 158 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 159 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 160 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 161 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 162 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 163 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 164 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 165 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 166 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 167 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 168 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 169 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 170 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 171 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 172 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 173 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 174 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 175 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 176 177 /* MSDC_FIFOCS mask */ 178 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 179 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 180 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 181 182 /* SDC_CFG mask */ 183 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 184 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 185 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 186 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 187 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 188 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 189 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 190 191 /* SDC_STS mask */ 192 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 193 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 194 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 195 196 /* SDC_ADV_CFG0 mask */ 197 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 198 199 /* DMA_SA_H4BIT mask */ 200 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 201 202 /* MSDC_DMA_CTRL mask */ 203 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 204 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 205 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 206 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 207 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 208 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 209 210 /* MSDC_DMA_CFG mask */ 211 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 212 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 213 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 214 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 215 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 216 217 /* MSDC_PATCH_BIT mask */ 218 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 219 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 220 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 221 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 222 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 223 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 224 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 225 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 226 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 227 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 228 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 229 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 230 231 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 232 233 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 234 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 235 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 236 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 237 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 238 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 239 240 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 241 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 242 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 243 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 244 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 245 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 246 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 247 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 248 249 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 250 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 251 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 252 253 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 254 255 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 256 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 257 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 258 259 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 260 261 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 262 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 263 264 #define REQ_CMD_EIO (0x1 << 0) 265 #define REQ_CMD_TMO (0x1 << 1) 266 #define REQ_DAT_ERR (0x1 << 2) 267 #define REQ_STOP_EIO (0x1 << 3) 268 #define REQ_STOP_TMO (0x1 << 4) 269 #define REQ_CMD_BUSY (0x1 << 5) 270 271 #define MSDC_PREPARE_FLAG (0x1 << 0) 272 #define MSDC_ASYNC_FLAG (0x1 << 1) 273 #define MSDC_MMAP_FLAG (0x1 << 2) 274 275 #define MTK_MMC_AUTOSUSPEND_DELAY 50 276 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 277 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 278 279 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 280 /*--------------------------------------------------------------------------*/ 281 /* Descriptor Structure */ 282 /*--------------------------------------------------------------------------*/ 283 struct mt_gpdma_desc { 284 u32 gpd_info; 285 #define GPDMA_DESC_HWO (0x1 << 0) 286 #define GPDMA_DESC_BDP (0x1 << 1) 287 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 288 #define GPDMA_DESC_INT (0x1 << 16) 289 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 290 #define GPDMA_DESC_PTR_H4 (0xf << 28) 291 u32 next; 292 u32 ptr; 293 u32 gpd_data_len; 294 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 295 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 296 u32 arg; 297 u32 blknum; 298 u32 cmd; 299 }; 300 301 struct mt_bdma_desc { 302 u32 bd_info; 303 #define BDMA_DESC_EOL (0x1 << 0) 304 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 305 #define BDMA_DESC_BLKPAD (0x1 << 17) 306 #define BDMA_DESC_DWPAD (0x1 << 18) 307 #define BDMA_DESC_NEXT_H4 (0xf << 24) 308 #define BDMA_DESC_PTR_H4 (0xf << 28) 309 u32 next; 310 u32 ptr; 311 u32 bd_data_len; 312 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 313 }; 314 315 struct msdc_dma { 316 struct scatterlist *sg; /* I/O scatter list */ 317 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 318 struct mt_bdma_desc *bd; /* pointer to bd array */ 319 dma_addr_t gpd_addr; /* the physical address of gpd array */ 320 dma_addr_t bd_addr; /* the physical address of bd array */ 321 }; 322 323 struct msdc_save_para { 324 u32 msdc_cfg; 325 u32 iocon; 326 u32 sdc_cfg; 327 u32 pad_tune; 328 u32 patch_bit0; 329 u32 patch_bit1; 330 u32 patch_bit2; 331 u32 pad_ds_tune; 332 u32 pad_cmd_tune; 333 u32 emmc50_cfg0; 334 u32 emmc50_cfg3; 335 u32 sdc_fifo_cfg; 336 }; 337 338 struct mtk_mmc_compatible { 339 u8 clk_div_bits; 340 bool hs400_tune; /* only used for MT8173 */ 341 u32 pad_tune_reg; 342 bool async_fifo; 343 bool data_tune; 344 bool busy_check; 345 bool stop_clk_fix; 346 bool enhance_rx; 347 bool support_64g; 348 }; 349 350 struct msdc_tune_para { 351 u32 iocon; 352 u32 pad_tune; 353 u32 pad_cmd_tune; 354 }; 355 356 struct msdc_delay_phase { 357 u8 maxlen; 358 u8 start; 359 u8 final_phase; 360 }; 361 362 struct msdc_host { 363 struct device *dev; 364 const struct mtk_mmc_compatible *dev_comp; 365 struct mmc_host *mmc; /* mmc structure */ 366 int cmd_rsp; 367 368 spinlock_t lock; 369 struct mmc_request *mrq; 370 struct mmc_command *cmd; 371 struct mmc_data *data; 372 int error; 373 374 void __iomem *base; /* host base address */ 375 376 struct msdc_dma dma; /* dma channel */ 377 u64 dma_mask; 378 379 u32 timeout_ns; /* data timeout ns */ 380 u32 timeout_clks; /* data timeout clks */ 381 382 struct pinctrl *pinctrl; 383 struct pinctrl_state *pins_default; 384 struct pinctrl_state *pins_uhs; 385 struct delayed_work req_timeout; 386 int irq; /* host interrupt */ 387 388 struct clk *src_clk; /* msdc source clock */ 389 struct clk *h_clk; /* msdc h_clk */ 390 struct clk *src_clk_cg; /* msdc source clock control gate */ 391 u32 mclk; /* mmc subsystem clock frequency */ 392 u32 src_clk_freq; /* source clock frequency */ 393 u32 sclk; /* SD/MS bus clock frequency */ 394 unsigned char timing; 395 bool vqmmc_enabled; 396 u32 latch_ck; 397 u32 hs400_ds_delay; 398 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 399 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 400 bool hs400_cmd_resp_sel_rising; 401 /* cmd response sample selection for HS400 */ 402 bool hs400_mode; /* current eMMC will run at hs400 mode */ 403 struct msdc_save_para save_para; /* used when gate HCLK */ 404 struct msdc_tune_para def_tune_para; /* default tune setting */ 405 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 406 }; 407 408 static const struct mtk_mmc_compatible mt8135_compat = { 409 .clk_div_bits = 8, 410 .hs400_tune = false, 411 .pad_tune_reg = MSDC_PAD_TUNE, 412 .async_fifo = false, 413 .data_tune = false, 414 .busy_check = false, 415 .stop_clk_fix = false, 416 .enhance_rx = false, 417 .support_64g = false, 418 }; 419 420 static const struct mtk_mmc_compatible mt8173_compat = { 421 .clk_div_bits = 8, 422 .hs400_tune = true, 423 .pad_tune_reg = MSDC_PAD_TUNE, 424 .async_fifo = false, 425 .data_tune = false, 426 .busy_check = false, 427 .stop_clk_fix = false, 428 .enhance_rx = false, 429 .support_64g = false, 430 }; 431 432 static const struct mtk_mmc_compatible mt2701_compat = { 433 .clk_div_bits = 12, 434 .hs400_tune = false, 435 .pad_tune_reg = MSDC_PAD_TUNE0, 436 .async_fifo = true, 437 .data_tune = true, 438 .busy_check = false, 439 .stop_clk_fix = false, 440 .enhance_rx = false, 441 .support_64g = false, 442 }; 443 444 static const struct mtk_mmc_compatible mt2712_compat = { 445 .clk_div_bits = 12, 446 .hs400_tune = false, 447 .pad_tune_reg = MSDC_PAD_TUNE0, 448 .async_fifo = true, 449 .data_tune = true, 450 .busy_check = true, 451 .stop_clk_fix = true, 452 .enhance_rx = true, 453 .support_64g = true, 454 }; 455 456 static const struct mtk_mmc_compatible mt7622_compat = { 457 .clk_div_bits = 12, 458 .hs400_tune = false, 459 .pad_tune_reg = MSDC_PAD_TUNE0, 460 .async_fifo = true, 461 .data_tune = true, 462 .busy_check = true, 463 .stop_clk_fix = true, 464 .enhance_rx = true, 465 .support_64g = false, 466 }; 467 468 static const struct of_device_id msdc_of_ids[] = { 469 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 470 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 471 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 472 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 473 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 474 {} 475 }; 476 MODULE_DEVICE_TABLE(of, msdc_of_ids); 477 478 static void sdr_set_bits(void __iomem *reg, u32 bs) 479 { 480 u32 val = readl(reg); 481 482 val |= bs; 483 writel(val, reg); 484 } 485 486 static void sdr_clr_bits(void __iomem *reg, u32 bs) 487 { 488 u32 val = readl(reg); 489 490 val &= ~bs; 491 writel(val, reg); 492 } 493 494 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 495 { 496 unsigned int tv = readl(reg); 497 498 tv &= ~field; 499 tv |= ((val) << (ffs((unsigned int)field) - 1)); 500 writel(tv, reg); 501 } 502 503 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 504 { 505 unsigned int tv = readl(reg); 506 507 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 508 } 509 510 static void msdc_reset_hw(struct msdc_host *host) 511 { 512 u32 val; 513 514 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 515 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 516 cpu_relax(); 517 518 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 519 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 520 cpu_relax(); 521 522 val = readl(host->base + MSDC_INT); 523 writel(val, host->base + MSDC_INT); 524 } 525 526 static void msdc_cmd_next(struct msdc_host *host, 527 struct mmc_request *mrq, struct mmc_command *cmd); 528 529 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 530 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 531 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 532 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 533 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 534 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 535 536 static u8 msdc_dma_calcs(u8 *buf, u32 len) 537 { 538 u32 i, sum = 0; 539 540 for (i = 0; i < len; i++) 541 sum += buf[i]; 542 return 0xff - (u8) sum; 543 } 544 545 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 546 struct mmc_data *data) 547 { 548 unsigned int j, dma_len; 549 dma_addr_t dma_address; 550 u32 dma_ctrl; 551 struct scatterlist *sg; 552 struct mt_gpdma_desc *gpd; 553 struct mt_bdma_desc *bd; 554 555 sg = data->sg; 556 557 gpd = dma->gpd; 558 bd = dma->bd; 559 560 /* modify gpd */ 561 gpd->gpd_info |= GPDMA_DESC_HWO; 562 gpd->gpd_info |= GPDMA_DESC_BDP; 563 /* need to clear first. use these bits to calc checksum */ 564 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 565 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 566 567 /* modify bd */ 568 for_each_sg(data->sg, sg, data->sg_count, j) { 569 dma_address = sg_dma_address(sg); 570 dma_len = sg_dma_len(sg); 571 572 /* init bd */ 573 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 574 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 575 bd[j].ptr = lower_32_bits(dma_address); 576 if (host->dev_comp->support_64g) { 577 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 578 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 579 << 28; 580 } 581 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 582 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 583 584 if (j == data->sg_count - 1) /* the last bd */ 585 bd[j].bd_info |= BDMA_DESC_EOL; 586 else 587 bd[j].bd_info &= ~BDMA_DESC_EOL; 588 589 /* checksume need to clear first */ 590 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 591 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 592 } 593 594 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 595 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 596 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 597 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 598 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 599 if (host->dev_comp->support_64g) 600 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 601 upper_32_bits(dma->gpd_addr) & 0xf); 602 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 603 } 604 605 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 606 { 607 struct mmc_data *data = mrq->data; 608 609 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 610 data->host_cookie |= MSDC_PREPARE_FLAG; 611 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 612 mmc_get_dma_dir(data)); 613 } 614 } 615 616 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 617 { 618 struct mmc_data *data = mrq->data; 619 620 if (data->host_cookie & MSDC_ASYNC_FLAG) 621 return; 622 623 if (data->host_cookie & MSDC_PREPARE_FLAG) { 624 dma_unmap_sg(host->dev, data->sg, data->sg_len, 625 mmc_get_dma_dir(data)); 626 data->host_cookie &= ~MSDC_PREPARE_FLAG; 627 } 628 } 629 630 /* clock control primitives */ 631 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 632 { 633 u32 timeout, clk_ns; 634 u32 mode = 0; 635 636 host->timeout_ns = ns; 637 host->timeout_clks = clks; 638 if (host->sclk == 0) { 639 timeout = 0; 640 } else { 641 clk_ns = 1000000000UL / host->sclk; 642 timeout = (ns + clk_ns - 1) / clk_ns + clks; 643 /* in 1048576 sclk cycle unit */ 644 timeout = (timeout + (0x1 << 20) - 1) >> 20; 645 if (host->dev_comp->clk_div_bits == 8) 646 sdr_get_field(host->base + MSDC_CFG, 647 MSDC_CFG_CKMOD, &mode); 648 else 649 sdr_get_field(host->base + MSDC_CFG, 650 MSDC_CFG_CKMOD_EXTRA, &mode); 651 /*DDR mode will double the clk cycles for data timeout */ 652 timeout = mode >= 2 ? timeout * 2 : timeout; 653 timeout = timeout > 1 ? timeout - 1 : 0; 654 timeout = timeout > 255 ? 255 : timeout; 655 } 656 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 657 } 658 659 static void msdc_gate_clock(struct msdc_host *host) 660 { 661 clk_disable_unprepare(host->src_clk_cg); 662 clk_disable_unprepare(host->src_clk); 663 clk_disable_unprepare(host->h_clk); 664 } 665 666 static void msdc_ungate_clock(struct msdc_host *host) 667 { 668 clk_prepare_enable(host->h_clk); 669 clk_prepare_enable(host->src_clk); 670 clk_prepare_enable(host->src_clk_cg); 671 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 672 cpu_relax(); 673 } 674 675 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 676 { 677 u32 mode; 678 u32 flags; 679 u32 div; 680 u32 sclk; 681 u32 tune_reg = host->dev_comp->pad_tune_reg; 682 683 if (!hz) { 684 dev_dbg(host->dev, "set mclk to 0\n"); 685 host->mclk = 0; 686 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 687 return; 688 } 689 690 flags = readl(host->base + MSDC_INTEN); 691 sdr_clr_bits(host->base + MSDC_INTEN, flags); 692 if (host->dev_comp->clk_div_bits == 8) 693 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 694 else 695 sdr_clr_bits(host->base + MSDC_CFG, 696 MSDC_CFG_HS400_CK_MODE_EXTRA); 697 if (timing == MMC_TIMING_UHS_DDR50 || 698 timing == MMC_TIMING_MMC_DDR52 || 699 timing == MMC_TIMING_MMC_HS400) { 700 if (timing == MMC_TIMING_MMC_HS400) 701 mode = 0x3; 702 else 703 mode = 0x2; /* ddr mode and use divisor */ 704 705 if (hz >= (host->src_clk_freq >> 2)) { 706 div = 0; /* mean div = 1/4 */ 707 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 708 } else { 709 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 710 sclk = (host->src_clk_freq >> 2) / div; 711 div = (div >> 1); 712 } 713 714 if (timing == MMC_TIMING_MMC_HS400 && 715 hz >= (host->src_clk_freq >> 1)) { 716 if (host->dev_comp->clk_div_bits == 8) 717 sdr_set_bits(host->base + MSDC_CFG, 718 MSDC_CFG_HS400_CK_MODE); 719 else 720 sdr_set_bits(host->base + MSDC_CFG, 721 MSDC_CFG_HS400_CK_MODE_EXTRA); 722 sclk = host->src_clk_freq >> 1; 723 div = 0; /* div is ignore when bit18 is set */ 724 } 725 } else if (hz >= host->src_clk_freq) { 726 mode = 0x1; /* no divisor */ 727 div = 0; 728 sclk = host->src_clk_freq; 729 } else { 730 mode = 0x0; /* use divisor */ 731 if (hz >= (host->src_clk_freq >> 1)) { 732 div = 0; /* mean div = 1/2 */ 733 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 734 } else { 735 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 736 sclk = (host->src_clk_freq >> 2) / div; 737 } 738 } 739 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 740 /* 741 * As src_clk/HCLK use the same bit to gate/ungate, 742 * So if want to only gate src_clk, need gate its parent(mux). 743 */ 744 if (host->src_clk_cg) 745 clk_disable_unprepare(host->src_clk_cg); 746 else 747 clk_disable_unprepare(clk_get_parent(host->src_clk)); 748 if (host->dev_comp->clk_div_bits == 8) 749 sdr_set_field(host->base + MSDC_CFG, 750 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 751 (mode << 8) | div); 752 else 753 sdr_set_field(host->base + MSDC_CFG, 754 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 755 (mode << 12) | div); 756 if (host->src_clk_cg) 757 clk_prepare_enable(host->src_clk_cg); 758 else 759 clk_prepare_enable(clk_get_parent(host->src_clk)); 760 761 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 762 cpu_relax(); 763 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 764 host->sclk = sclk; 765 host->mclk = hz; 766 host->timing = timing; 767 /* need because clk changed. */ 768 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 769 sdr_set_bits(host->base + MSDC_INTEN, flags); 770 771 /* 772 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 773 * tune result of hs200/200Mhz is not suitable for 50Mhz 774 */ 775 if (host->sclk <= 52000000) { 776 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 777 writel(host->def_tune_para.pad_tune, host->base + tune_reg); 778 } else { 779 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 780 writel(host->saved_tune_para.pad_tune, host->base + tune_reg); 781 writel(host->saved_tune_para.pad_cmd_tune, 782 host->base + PAD_CMD_TUNE); 783 } 784 785 if (timing == MMC_TIMING_MMC_HS400 && 786 host->dev_comp->hs400_tune) 787 sdr_set_field(host->base + PAD_CMD_TUNE, 788 MSDC_PAD_TUNE_CMDRRDLY, 789 host->hs400_cmd_int_delay); 790 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 791 } 792 793 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 794 struct mmc_request *mrq, struct mmc_command *cmd) 795 { 796 u32 resp; 797 798 switch (mmc_resp_type(cmd)) { 799 /* Actually, R1, R5, R6, R7 are the same */ 800 case MMC_RSP_R1: 801 resp = 0x1; 802 break; 803 case MMC_RSP_R1B: 804 resp = 0x7; 805 break; 806 case MMC_RSP_R2: 807 resp = 0x2; 808 break; 809 case MMC_RSP_R3: 810 resp = 0x3; 811 break; 812 case MMC_RSP_NONE: 813 default: 814 resp = 0x0; 815 break; 816 } 817 818 return resp; 819 } 820 821 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 822 struct mmc_request *mrq, struct mmc_command *cmd) 823 { 824 /* rawcmd : 825 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 826 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 827 */ 828 u32 opcode = cmd->opcode; 829 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 830 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 831 832 host->cmd_rsp = resp; 833 834 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 835 opcode == MMC_STOP_TRANSMISSION) 836 rawcmd |= (0x1 << 14); 837 else if (opcode == SD_SWITCH_VOLTAGE) 838 rawcmd |= (0x1 << 30); 839 else if (opcode == SD_APP_SEND_SCR || 840 opcode == SD_APP_SEND_NUM_WR_BLKS || 841 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 842 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 843 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 844 rawcmd |= (0x1 << 11); 845 846 if (cmd->data) { 847 struct mmc_data *data = cmd->data; 848 849 if (mmc_op_multi(opcode)) { 850 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 851 !(mrq->sbc->arg & 0xFFFF0000)) 852 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 853 } 854 855 rawcmd |= ((data->blksz & 0xFFF) << 16); 856 if (data->flags & MMC_DATA_WRITE) 857 rawcmd |= (0x1 << 13); 858 if (data->blocks > 1) 859 rawcmd |= (0x2 << 11); 860 else 861 rawcmd |= (0x1 << 11); 862 /* Always use dma mode */ 863 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 864 865 if (host->timeout_ns != data->timeout_ns || 866 host->timeout_clks != data->timeout_clks) 867 msdc_set_timeout(host, data->timeout_ns, 868 data->timeout_clks); 869 870 writel(data->blocks, host->base + SDC_BLK_NUM); 871 } 872 return rawcmd; 873 } 874 875 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 876 struct mmc_command *cmd, struct mmc_data *data) 877 { 878 bool read; 879 880 WARN_ON(host->data); 881 host->data = data; 882 read = data->flags & MMC_DATA_READ; 883 884 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 885 msdc_dma_setup(host, &host->dma, data); 886 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 887 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 888 dev_dbg(host->dev, "DMA start\n"); 889 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 890 __func__, cmd->opcode, data->blocks, read); 891 } 892 893 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 894 struct mmc_command *cmd) 895 { 896 u32 *rsp = cmd->resp; 897 898 rsp[0] = readl(host->base + SDC_ACMD_RESP); 899 900 if (events & MSDC_INT_ACMDRDY) { 901 cmd->error = 0; 902 } else { 903 msdc_reset_hw(host); 904 if (events & MSDC_INT_ACMDCRCERR) { 905 cmd->error = -EILSEQ; 906 host->error |= REQ_STOP_EIO; 907 } else if (events & MSDC_INT_ACMDTMO) { 908 cmd->error = -ETIMEDOUT; 909 host->error |= REQ_STOP_TMO; 910 } 911 dev_err(host->dev, 912 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 913 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 914 } 915 return cmd->error; 916 } 917 918 static void msdc_track_cmd_data(struct msdc_host *host, 919 struct mmc_command *cmd, struct mmc_data *data) 920 { 921 if (host->error) 922 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 923 __func__, cmd->opcode, cmd->arg, host->error); 924 } 925 926 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 927 { 928 unsigned long flags; 929 bool ret; 930 931 ret = cancel_delayed_work(&host->req_timeout); 932 if (!ret) { 933 /* delay work already running */ 934 return; 935 } 936 spin_lock_irqsave(&host->lock, flags); 937 host->mrq = NULL; 938 spin_unlock_irqrestore(&host->lock, flags); 939 940 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 941 if (mrq->data) 942 msdc_unprepare_data(host, mrq); 943 mmc_request_done(host->mmc, mrq); 944 } 945 946 /* returns true if command is fully handled; returns false otherwise */ 947 static bool msdc_cmd_done(struct msdc_host *host, int events, 948 struct mmc_request *mrq, struct mmc_command *cmd) 949 { 950 bool done = false; 951 bool sbc_error; 952 unsigned long flags; 953 u32 *rsp = cmd->resp; 954 955 if (mrq->sbc && cmd == mrq->cmd && 956 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 957 | MSDC_INT_ACMDTMO))) 958 msdc_auto_cmd_done(host, events, mrq->sbc); 959 960 sbc_error = mrq->sbc && mrq->sbc->error; 961 962 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 963 | MSDC_INT_RSPCRCERR 964 | MSDC_INT_CMDTMO))) 965 return done; 966 967 spin_lock_irqsave(&host->lock, flags); 968 done = !host->cmd; 969 host->cmd = NULL; 970 spin_unlock_irqrestore(&host->lock, flags); 971 972 if (done) 973 return true; 974 975 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 976 977 if (cmd->flags & MMC_RSP_PRESENT) { 978 if (cmd->flags & MMC_RSP_136) { 979 rsp[0] = readl(host->base + SDC_RESP3); 980 rsp[1] = readl(host->base + SDC_RESP2); 981 rsp[2] = readl(host->base + SDC_RESP1); 982 rsp[3] = readl(host->base + SDC_RESP0); 983 } else { 984 rsp[0] = readl(host->base + SDC_RESP0); 985 } 986 } 987 988 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 989 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 990 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 991 /* 992 * should not clear fifo/interrupt as the tune data 993 * may have alreay come. 994 */ 995 msdc_reset_hw(host); 996 if (events & MSDC_INT_RSPCRCERR) { 997 cmd->error = -EILSEQ; 998 host->error |= REQ_CMD_EIO; 999 } else if (events & MSDC_INT_CMDTMO) { 1000 cmd->error = -ETIMEDOUT; 1001 host->error |= REQ_CMD_TMO; 1002 } 1003 } 1004 if (cmd->error) 1005 dev_dbg(host->dev, 1006 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1007 __func__, cmd->opcode, cmd->arg, rsp[0], 1008 cmd->error); 1009 1010 msdc_cmd_next(host, mrq, cmd); 1011 return true; 1012 } 1013 1014 /* It is the core layer's responsibility to ensure card status 1015 * is correct before issue a request. but host design do below 1016 * checks recommended. 1017 */ 1018 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1019 struct mmc_request *mrq, struct mmc_command *cmd) 1020 { 1021 /* The max busy time we can endure is 20ms */ 1022 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1023 1024 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1025 time_before(jiffies, tmo)) 1026 cpu_relax(); 1027 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1028 dev_err(host->dev, "CMD bus busy detected\n"); 1029 host->error |= REQ_CMD_BUSY; 1030 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1031 return false; 1032 } 1033 1034 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1035 tmo = jiffies + msecs_to_jiffies(20); 1036 /* R1B or with data, should check SDCBUSY */ 1037 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1038 time_before(jiffies, tmo)) 1039 cpu_relax(); 1040 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1041 dev_err(host->dev, "Controller busy detected\n"); 1042 host->error |= REQ_CMD_BUSY; 1043 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1044 return false; 1045 } 1046 } 1047 return true; 1048 } 1049 1050 static void msdc_start_command(struct msdc_host *host, 1051 struct mmc_request *mrq, struct mmc_command *cmd) 1052 { 1053 u32 rawcmd; 1054 1055 WARN_ON(host->cmd); 1056 host->cmd = cmd; 1057 1058 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1059 return; 1060 1061 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1062 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1063 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1064 msdc_reset_hw(host); 1065 } 1066 1067 cmd->error = 0; 1068 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1069 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1070 1071 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1072 writel(cmd->arg, host->base + SDC_ARG); 1073 writel(rawcmd, host->base + SDC_CMD); 1074 } 1075 1076 static void msdc_cmd_next(struct msdc_host *host, 1077 struct mmc_request *mrq, struct mmc_command *cmd) 1078 { 1079 if ((cmd->error && 1080 !(cmd->error == -EILSEQ && 1081 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1082 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1083 (mrq->sbc && mrq->sbc->error)) 1084 msdc_request_done(host, mrq); 1085 else if (cmd == mrq->sbc) 1086 msdc_start_command(host, mrq, mrq->cmd); 1087 else if (!cmd->data) 1088 msdc_request_done(host, mrq); 1089 else 1090 msdc_start_data(host, mrq, cmd, cmd->data); 1091 } 1092 1093 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1094 { 1095 struct msdc_host *host = mmc_priv(mmc); 1096 1097 host->error = 0; 1098 WARN_ON(host->mrq); 1099 host->mrq = mrq; 1100 1101 if (mrq->data) 1102 msdc_prepare_data(host, mrq); 1103 1104 /* if SBC is required, we have HW option and SW option. 1105 * if HW option is enabled, and SBC does not have "special" flags, 1106 * use HW option, otherwise use SW option 1107 */ 1108 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1109 (mrq->sbc->arg & 0xFFFF0000))) 1110 msdc_start_command(host, mrq, mrq->sbc); 1111 else 1112 msdc_start_command(host, mrq, mrq->cmd); 1113 } 1114 1115 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1116 { 1117 struct msdc_host *host = mmc_priv(mmc); 1118 struct mmc_data *data = mrq->data; 1119 1120 if (!data) 1121 return; 1122 1123 msdc_prepare_data(host, mrq); 1124 data->host_cookie |= MSDC_ASYNC_FLAG; 1125 } 1126 1127 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1128 int err) 1129 { 1130 struct msdc_host *host = mmc_priv(mmc); 1131 struct mmc_data *data; 1132 1133 data = mrq->data; 1134 if (!data) 1135 return; 1136 if (data->host_cookie) { 1137 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1138 msdc_unprepare_data(host, mrq); 1139 } 1140 } 1141 1142 static void msdc_data_xfer_next(struct msdc_host *host, 1143 struct mmc_request *mrq, struct mmc_data *data) 1144 { 1145 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1146 !mrq->sbc) 1147 msdc_start_command(host, mrq, mrq->stop); 1148 else 1149 msdc_request_done(host, mrq); 1150 } 1151 1152 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1153 struct mmc_request *mrq, struct mmc_data *data) 1154 { 1155 struct mmc_command *stop = data->stop; 1156 unsigned long flags; 1157 bool done; 1158 unsigned int check_data = events & 1159 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1160 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1161 | MSDC_INT_DMA_PROTECT); 1162 1163 spin_lock_irqsave(&host->lock, flags); 1164 done = !host->data; 1165 if (check_data) 1166 host->data = NULL; 1167 spin_unlock_irqrestore(&host->lock, flags); 1168 1169 if (done) 1170 return true; 1171 1172 if (check_data || (stop && stop->error)) { 1173 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1174 readl(host->base + MSDC_DMA_CFG)); 1175 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1176 1); 1177 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1178 cpu_relax(); 1179 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1180 dev_dbg(host->dev, "DMA stop\n"); 1181 1182 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1183 data->bytes_xfered = data->blocks * data->blksz; 1184 } else { 1185 dev_dbg(host->dev, "interrupt events: %x\n", events); 1186 msdc_reset_hw(host); 1187 host->error |= REQ_DAT_ERR; 1188 data->bytes_xfered = 0; 1189 1190 if (events & MSDC_INT_DATTMO) 1191 data->error = -ETIMEDOUT; 1192 else if (events & MSDC_INT_DATCRCERR) 1193 data->error = -EILSEQ; 1194 1195 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1196 __func__, mrq->cmd->opcode, data->blocks); 1197 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1198 (int)data->error, data->bytes_xfered); 1199 } 1200 1201 msdc_data_xfer_next(host, mrq, data); 1202 done = true; 1203 } 1204 return done; 1205 } 1206 1207 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1208 { 1209 u32 val = readl(host->base + SDC_CFG); 1210 1211 val &= ~SDC_CFG_BUSWIDTH; 1212 1213 switch (width) { 1214 default: 1215 case MMC_BUS_WIDTH_1: 1216 val |= (MSDC_BUS_1BITS << 16); 1217 break; 1218 case MMC_BUS_WIDTH_4: 1219 val |= (MSDC_BUS_4BITS << 16); 1220 break; 1221 case MMC_BUS_WIDTH_8: 1222 val |= (MSDC_BUS_8BITS << 16); 1223 break; 1224 } 1225 1226 writel(val, host->base + SDC_CFG); 1227 dev_dbg(host->dev, "Bus Width = %d", width); 1228 } 1229 1230 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1231 { 1232 struct msdc_host *host = mmc_priv(mmc); 1233 int ret = 0; 1234 1235 if (!IS_ERR(mmc->supply.vqmmc)) { 1236 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1237 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1238 dev_err(host->dev, "Unsupported signal voltage!\n"); 1239 return -EINVAL; 1240 } 1241 1242 ret = mmc_regulator_set_vqmmc(mmc, ios); 1243 if (ret) { 1244 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1245 ret, ios->signal_voltage); 1246 } else { 1247 /* Apply different pinctrl settings for different signal voltage */ 1248 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1249 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1250 else 1251 pinctrl_select_state(host->pinctrl, host->pins_default); 1252 } 1253 } 1254 return ret; 1255 } 1256 1257 static int msdc_card_busy(struct mmc_host *mmc) 1258 { 1259 struct msdc_host *host = mmc_priv(mmc); 1260 u32 status = readl(host->base + MSDC_PS); 1261 1262 /* only check if data0 is low */ 1263 return !(status & BIT(16)); 1264 } 1265 1266 static void msdc_request_timeout(struct work_struct *work) 1267 { 1268 struct msdc_host *host = container_of(work, struct msdc_host, 1269 req_timeout.work); 1270 1271 /* simulate HW timeout status */ 1272 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1273 if (host->mrq) { 1274 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1275 host->mrq, host->mrq->cmd->opcode); 1276 if (host->cmd) { 1277 dev_err(host->dev, "%s: aborting cmd=%d\n", 1278 __func__, host->cmd->opcode); 1279 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1280 host->cmd); 1281 } else if (host->data) { 1282 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1283 __func__, host->mrq->cmd->opcode, 1284 host->data->blocks); 1285 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1286 host->data); 1287 } 1288 } 1289 } 1290 1291 static irqreturn_t msdc_irq(int irq, void *dev_id) 1292 { 1293 struct msdc_host *host = (struct msdc_host *) dev_id; 1294 1295 while (true) { 1296 unsigned long flags; 1297 struct mmc_request *mrq; 1298 struct mmc_command *cmd; 1299 struct mmc_data *data; 1300 u32 events, event_mask; 1301 1302 spin_lock_irqsave(&host->lock, flags); 1303 events = readl(host->base + MSDC_INT); 1304 event_mask = readl(host->base + MSDC_INTEN); 1305 /* clear interrupts */ 1306 writel(events & event_mask, host->base + MSDC_INT); 1307 1308 mrq = host->mrq; 1309 cmd = host->cmd; 1310 data = host->data; 1311 spin_unlock_irqrestore(&host->lock, flags); 1312 1313 if (!(events & event_mask)) 1314 break; 1315 1316 if (!mrq) { 1317 dev_err(host->dev, 1318 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1319 __func__, events, event_mask); 1320 WARN_ON(1); 1321 break; 1322 } 1323 1324 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1325 1326 if (cmd) 1327 msdc_cmd_done(host, events, mrq, cmd); 1328 else if (data) 1329 msdc_data_xfer_done(host, events, mrq, data); 1330 } 1331 1332 return IRQ_HANDLED; 1333 } 1334 1335 static void msdc_init_hw(struct msdc_host *host) 1336 { 1337 u32 val; 1338 u32 tune_reg = host->dev_comp->pad_tune_reg; 1339 1340 /* Configure to MMC/SD mode, clock free running */ 1341 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1342 1343 /* Reset */ 1344 msdc_reset_hw(host); 1345 1346 /* Disable card detection */ 1347 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1348 1349 /* Disable and clear all interrupts */ 1350 writel(0, host->base + MSDC_INTEN); 1351 val = readl(host->base + MSDC_INT); 1352 writel(val, host->base + MSDC_INT); 1353 1354 writel(0, host->base + tune_reg); 1355 writel(0, host->base + MSDC_IOCON); 1356 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1357 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1358 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1359 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1360 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1361 1362 if (host->dev_comp->stop_clk_fix) { 1363 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1364 MSDC_PATCH_BIT1_STOP_DLY, 3); 1365 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1366 SDC_FIFO_CFG_WRVALIDSEL); 1367 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1368 SDC_FIFO_CFG_RDVALIDSEL); 1369 } 1370 1371 if (host->dev_comp->busy_check) 1372 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1373 1374 if (host->dev_comp->async_fifo) { 1375 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1376 MSDC_PB2_RESPWAIT, 3); 1377 if (host->dev_comp->enhance_rx) { 1378 sdr_set_bits(host->base + SDC_ADV_CFG0, 1379 SDC_RX_ENHANCE_EN); 1380 } else { 1381 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1382 MSDC_PB2_RESPSTSENSEL, 2); 1383 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1384 MSDC_PB2_CRCSTSENSEL, 2); 1385 } 1386 /* use async fifo, then no need tune internal delay */ 1387 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1388 MSDC_PATCH_BIT2_CFGRESP); 1389 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1390 MSDC_PATCH_BIT2_CFGCRCSTS); 1391 } 1392 1393 if (host->dev_comp->support_64g) 1394 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1395 MSDC_PB2_SUPPORT_64G); 1396 if (host->dev_comp->data_tune) { 1397 sdr_set_bits(host->base + tune_reg, 1398 MSDC_PAD_TUNE_RD_SEL | MSDC_PAD_TUNE_CMD_SEL); 1399 } else { 1400 /* choose clock tune */ 1401 sdr_set_bits(host->base + tune_reg, MSDC_PAD_TUNE_RXDLYSEL); 1402 } 1403 1404 /* Configure to enable SDIO mode. 1405 * it's must otherwise sdio cmd5 failed 1406 */ 1407 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1408 1409 /* disable detect SDIO device interrupt function */ 1410 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1411 1412 /* Configure to default data timeout */ 1413 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1414 1415 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1416 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1417 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1418 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1419 dev_dbg(host->dev, "init hardware done!"); 1420 } 1421 1422 static void msdc_deinit_hw(struct msdc_host *host) 1423 { 1424 u32 val; 1425 /* Disable and clear all interrupts */ 1426 writel(0, host->base + MSDC_INTEN); 1427 1428 val = readl(host->base + MSDC_INT); 1429 writel(val, host->base + MSDC_INT); 1430 } 1431 1432 /* init gpd and bd list in msdc_drv_probe */ 1433 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1434 { 1435 struct mt_gpdma_desc *gpd = dma->gpd; 1436 struct mt_bdma_desc *bd = dma->bd; 1437 dma_addr_t dma_addr; 1438 int i; 1439 1440 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1441 1442 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1443 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1444 /* gpd->next is must set for desc DMA 1445 * That's why must alloc 2 gpd structure. 1446 */ 1447 gpd->next = lower_32_bits(dma_addr); 1448 if (host->dev_comp->support_64g) 1449 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1450 1451 dma_addr = dma->bd_addr; 1452 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1453 if (host->dev_comp->support_64g) 1454 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1455 1456 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1457 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1458 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1459 bd[i].next = lower_32_bits(dma_addr); 1460 if (host->dev_comp->support_64g) 1461 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1462 } 1463 } 1464 1465 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1466 { 1467 struct msdc_host *host = mmc_priv(mmc); 1468 int ret; 1469 1470 msdc_set_buswidth(host, ios->bus_width); 1471 1472 /* Suspend/Resume will do power off/on */ 1473 switch (ios->power_mode) { 1474 case MMC_POWER_UP: 1475 if (!IS_ERR(mmc->supply.vmmc)) { 1476 msdc_init_hw(host); 1477 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1478 ios->vdd); 1479 if (ret) { 1480 dev_err(host->dev, "Failed to set vmmc power!\n"); 1481 return; 1482 } 1483 } 1484 break; 1485 case MMC_POWER_ON: 1486 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1487 ret = regulator_enable(mmc->supply.vqmmc); 1488 if (ret) 1489 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1490 else 1491 host->vqmmc_enabled = true; 1492 } 1493 break; 1494 case MMC_POWER_OFF: 1495 if (!IS_ERR(mmc->supply.vmmc)) 1496 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1497 1498 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1499 regulator_disable(mmc->supply.vqmmc); 1500 host->vqmmc_enabled = false; 1501 } 1502 break; 1503 default: 1504 break; 1505 } 1506 1507 if (host->mclk != ios->clock || host->timing != ios->timing) 1508 msdc_set_mclk(host, ios->timing, ios->clock); 1509 } 1510 1511 static u32 test_delay_bit(u32 delay, u32 bit) 1512 { 1513 bit %= PAD_DELAY_MAX; 1514 return delay & (1 << bit); 1515 } 1516 1517 static int get_delay_len(u32 delay, u32 start_bit) 1518 { 1519 int i; 1520 1521 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1522 if (test_delay_bit(delay, start_bit + i) == 0) 1523 return i; 1524 } 1525 return PAD_DELAY_MAX - start_bit; 1526 } 1527 1528 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1529 { 1530 int start = 0, len = 0; 1531 int start_final = 0, len_final = 0; 1532 u8 final_phase = 0xff; 1533 struct msdc_delay_phase delay_phase = { 0, }; 1534 1535 if (delay == 0) { 1536 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1537 delay_phase.final_phase = final_phase; 1538 return delay_phase; 1539 } 1540 1541 while (start < PAD_DELAY_MAX) { 1542 len = get_delay_len(delay, start); 1543 if (len_final < len) { 1544 start_final = start; 1545 len_final = len; 1546 } 1547 start += len ? len : 1; 1548 if (len >= 12 && start_final < 4) 1549 break; 1550 } 1551 1552 /* The rule is that to find the smallest delay cell */ 1553 if (start_final == 0) 1554 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1555 else 1556 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1557 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1558 delay, len_final, final_phase); 1559 1560 delay_phase.maxlen = len_final; 1561 delay_phase.start = start_final; 1562 delay_phase.final_phase = final_phase; 1563 return delay_phase; 1564 } 1565 1566 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1567 { 1568 struct msdc_host *host = mmc_priv(mmc); 1569 u32 rise_delay = 0, fall_delay = 0; 1570 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1571 struct msdc_delay_phase internal_delay_phase; 1572 u8 final_delay, final_maxlen; 1573 u32 internal_delay = 0; 1574 u32 tune_reg = host->dev_comp->pad_tune_reg; 1575 int cmd_err; 1576 int i, j; 1577 1578 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1579 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1580 sdr_set_field(host->base + tune_reg, 1581 MSDC_PAD_TUNE_CMDRRDLY, 1582 host->hs200_cmd_int_delay); 1583 1584 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1585 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1586 sdr_set_field(host->base + tune_reg, 1587 MSDC_PAD_TUNE_CMDRDLY, i); 1588 /* 1589 * Using the same parameters, it may sometimes pass the test, 1590 * but sometimes it may fail. To make sure the parameters are 1591 * more stable, we test each set of parameters 3 times. 1592 */ 1593 for (j = 0; j < 3; j++) { 1594 mmc_send_tuning(mmc, opcode, &cmd_err); 1595 if (!cmd_err) { 1596 rise_delay |= (1 << i); 1597 } else { 1598 rise_delay &= ~(1 << i); 1599 break; 1600 } 1601 } 1602 } 1603 final_rise_delay = get_best_delay(host, rise_delay); 1604 /* if rising edge has enough margin, then do not scan falling edge */ 1605 if (final_rise_delay.maxlen >= 12 || 1606 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1607 goto skip_fall; 1608 1609 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1610 for (i = 0; i < PAD_DELAY_MAX; i++) { 1611 sdr_set_field(host->base + tune_reg, 1612 MSDC_PAD_TUNE_CMDRDLY, i); 1613 /* 1614 * Using the same parameters, it may sometimes pass the test, 1615 * but sometimes it may fail. To make sure the parameters are 1616 * more stable, we test each set of parameters 3 times. 1617 */ 1618 for (j = 0; j < 3; j++) { 1619 mmc_send_tuning(mmc, opcode, &cmd_err); 1620 if (!cmd_err) { 1621 fall_delay |= (1 << i); 1622 } else { 1623 fall_delay &= ~(1 << i); 1624 break; 1625 } 1626 } 1627 } 1628 final_fall_delay = get_best_delay(host, fall_delay); 1629 1630 skip_fall: 1631 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1632 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1633 final_maxlen = final_fall_delay.maxlen; 1634 if (final_maxlen == final_rise_delay.maxlen) { 1635 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1636 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1637 final_rise_delay.final_phase); 1638 final_delay = final_rise_delay.final_phase; 1639 } else { 1640 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1641 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1642 final_fall_delay.final_phase); 1643 final_delay = final_fall_delay.final_phase; 1644 } 1645 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1646 goto skip_internal; 1647 1648 for (i = 0; i < PAD_DELAY_MAX; i++) { 1649 sdr_set_field(host->base + tune_reg, 1650 MSDC_PAD_TUNE_CMDRRDLY, i); 1651 mmc_send_tuning(mmc, opcode, &cmd_err); 1652 if (!cmd_err) 1653 internal_delay |= (1 << i); 1654 } 1655 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1656 internal_delay_phase = get_best_delay(host, internal_delay); 1657 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1658 internal_delay_phase.final_phase); 1659 skip_internal: 1660 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1661 return final_delay == 0xff ? -EIO : 0; 1662 } 1663 1664 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1665 { 1666 struct msdc_host *host = mmc_priv(mmc); 1667 u32 cmd_delay = 0; 1668 struct msdc_delay_phase final_cmd_delay = { 0,}; 1669 u8 final_delay; 1670 int cmd_err; 1671 int i, j; 1672 1673 /* select EMMC50 PAD CMD tune */ 1674 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 1675 1676 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1677 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1678 sdr_set_field(host->base + MSDC_PAD_TUNE, 1679 MSDC_PAD_TUNE_CMDRRDLY, 1680 host->hs200_cmd_int_delay); 1681 1682 if (host->hs400_cmd_resp_sel_rising) 1683 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1684 else 1685 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1686 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1687 sdr_set_field(host->base + PAD_CMD_TUNE, 1688 PAD_CMD_TUNE_RX_DLY3, i); 1689 /* 1690 * Using the same parameters, it may sometimes pass the test, 1691 * but sometimes it may fail. To make sure the parameters are 1692 * more stable, we test each set of parameters 3 times. 1693 */ 1694 for (j = 0; j < 3; j++) { 1695 mmc_send_tuning(mmc, opcode, &cmd_err); 1696 if (!cmd_err) { 1697 cmd_delay |= (1 << i); 1698 } else { 1699 cmd_delay &= ~(1 << i); 1700 break; 1701 } 1702 } 1703 } 1704 final_cmd_delay = get_best_delay(host, cmd_delay); 1705 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 1706 final_cmd_delay.final_phase); 1707 final_delay = final_cmd_delay.final_phase; 1708 1709 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1710 return final_delay == 0xff ? -EIO : 0; 1711 } 1712 1713 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1714 { 1715 struct msdc_host *host = mmc_priv(mmc); 1716 u32 rise_delay = 0, fall_delay = 0; 1717 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1718 u8 final_delay, final_maxlen; 1719 u32 tune_reg = host->dev_comp->pad_tune_reg; 1720 int i, ret; 1721 1722 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 1723 host->latch_ck); 1724 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1725 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1726 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1727 sdr_set_field(host->base + tune_reg, 1728 MSDC_PAD_TUNE_DATRRDLY, i); 1729 ret = mmc_send_tuning(mmc, opcode, NULL); 1730 if (!ret) 1731 rise_delay |= (1 << i); 1732 } 1733 final_rise_delay = get_best_delay(host, rise_delay); 1734 /* if rising edge has enough margin, then do not scan falling edge */ 1735 if (final_rise_delay.maxlen >= 12 || 1736 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1737 goto skip_fall; 1738 1739 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1740 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1741 for (i = 0; i < PAD_DELAY_MAX; i++) { 1742 sdr_set_field(host->base + tune_reg, 1743 MSDC_PAD_TUNE_DATRRDLY, i); 1744 ret = mmc_send_tuning(mmc, opcode, NULL); 1745 if (!ret) 1746 fall_delay |= (1 << i); 1747 } 1748 final_fall_delay = get_best_delay(host, fall_delay); 1749 1750 skip_fall: 1751 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1752 if (final_maxlen == final_rise_delay.maxlen) { 1753 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1754 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1755 sdr_set_field(host->base + tune_reg, 1756 MSDC_PAD_TUNE_DATRRDLY, 1757 final_rise_delay.final_phase); 1758 final_delay = final_rise_delay.final_phase; 1759 } else { 1760 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1761 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1762 sdr_set_field(host->base + tune_reg, 1763 MSDC_PAD_TUNE_DATRRDLY, 1764 final_fall_delay.final_phase); 1765 final_delay = final_fall_delay.final_phase; 1766 } 1767 1768 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 1769 return final_delay == 0xff ? -EIO : 0; 1770 } 1771 1772 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1773 { 1774 struct msdc_host *host = mmc_priv(mmc); 1775 int ret; 1776 u32 tune_reg = host->dev_comp->pad_tune_reg; 1777 1778 if (host->hs400_mode && 1779 host->dev_comp->hs400_tune) 1780 ret = hs400_tune_response(mmc, opcode); 1781 else 1782 ret = msdc_tune_response(mmc, opcode); 1783 if (ret == -EIO) { 1784 dev_err(host->dev, "Tune response fail!\n"); 1785 return ret; 1786 } 1787 if (host->hs400_mode == false) { 1788 ret = msdc_tune_data(mmc, opcode); 1789 if (ret == -EIO) 1790 dev_err(host->dev, "Tune data fail!\n"); 1791 } 1792 1793 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1794 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1795 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 1796 return ret; 1797 } 1798 1799 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1800 { 1801 struct msdc_host *host = mmc_priv(mmc); 1802 host->hs400_mode = true; 1803 1804 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 1805 /* hs400 mode must set it to 0 */ 1806 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 1807 /* to improve read performance, set outstanding to 2 */ 1808 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 1809 1810 return 0; 1811 } 1812 1813 static void msdc_hw_reset(struct mmc_host *mmc) 1814 { 1815 struct msdc_host *host = mmc_priv(mmc); 1816 1817 sdr_set_bits(host->base + EMMC_IOCON, 1); 1818 udelay(10); /* 10us is enough */ 1819 sdr_clr_bits(host->base + EMMC_IOCON, 1); 1820 } 1821 1822 static const struct mmc_host_ops mt_msdc_ops = { 1823 .post_req = msdc_post_req, 1824 .pre_req = msdc_pre_req, 1825 .request = msdc_ops_request, 1826 .set_ios = msdc_ops_set_ios, 1827 .get_ro = mmc_gpio_get_ro, 1828 .get_cd = mmc_gpio_get_cd, 1829 .start_signal_voltage_switch = msdc_ops_switch_volt, 1830 .card_busy = msdc_card_busy, 1831 .execute_tuning = msdc_execute_tuning, 1832 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1833 .hw_reset = msdc_hw_reset, 1834 }; 1835 1836 static void msdc_of_property_parse(struct platform_device *pdev, 1837 struct msdc_host *host) 1838 { 1839 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 1840 &host->latch_ck); 1841 1842 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 1843 &host->hs400_ds_delay); 1844 1845 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 1846 &host->hs200_cmd_int_delay); 1847 1848 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 1849 &host->hs400_cmd_int_delay); 1850 1851 if (of_property_read_bool(pdev->dev.of_node, 1852 "mediatek,hs400-cmd-resp-sel-rising")) 1853 host->hs400_cmd_resp_sel_rising = true; 1854 else 1855 host->hs400_cmd_resp_sel_rising = false; 1856 } 1857 1858 static int msdc_drv_probe(struct platform_device *pdev) 1859 { 1860 struct mmc_host *mmc; 1861 struct msdc_host *host; 1862 struct resource *res; 1863 int ret; 1864 1865 if (!pdev->dev.of_node) { 1866 dev_err(&pdev->dev, "No DT found\n"); 1867 return -EINVAL; 1868 } 1869 1870 /* Allocate MMC host for this device */ 1871 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1872 if (!mmc) 1873 return -ENOMEM; 1874 1875 host = mmc_priv(mmc); 1876 ret = mmc_of_parse(mmc); 1877 if (ret) 1878 goto host_free; 1879 1880 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1881 host->base = devm_ioremap_resource(&pdev->dev, res); 1882 if (IS_ERR(host->base)) { 1883 ret = PTR_ERR(host->base); 1884 goto host_free; 1885 } 1886 1887 ret = mmc_regulator_get_supply(mmc); 1888 if (ret) 1889 goto host_free; 1890 1891 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1892 if (IS_ERR(host->src_clk)) { 1893 ret = PTR_ERR(host->src_clk); 1894 goto host_free; 1895 } 1896 1897 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1898 if (IS_ERR(host->h_clk)) { 1899 ret = PTR_ERR(host->h_clk); 1900 goto host_free; 1901 } 1902 1903 /*source clock control gate is optional clock*/ 1904 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 1905 if (IS_ERR(host->src_clk_cg)) 1906 host->src_clk_cg = NULL; 1907 1908 host->irq = platform_get_irq(pdev, 0); 1909 if (host->irq < 0) { 1910 ret = -EINVAL; 1911 goto host_free; 1912 } 1913 1914 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1915 if (IS_ERR(host->pinctrl)) { 1916 ret = PTR_ERR(host->pinctrl); 1917 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1918 goto host_free; 1919 } 1920 1921 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1922 if (IS_ERR(host->pins_default)) { 1923 ret = PTR_ERR(host->pins_default); 1924 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1925 goto host_free; 1926 } 1927 1928 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1929 if (IS_ERR(host->pins_uhs)) { 1930 ret = PTR_ERR(host->pins_uhs); 1931 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1932 goto host_free; 1933 } 1934 1935 msdc_of_property_parse(pdev, host); 1936 1937 host->dev = &pdev->dev; 1938 host->dev_comp = of_device_get_match_data(&pdev->dev); 1939 host->mmc = mmc; 1940 host->src_clk_freq = clk_get_rate(host->src_clk); 1941 /* Set host parameters to mmc */ 1942 mmc->ops = &mt_msdc_ops; 1943 if (host->dev_comp->clk_div_bits == 8) 1944 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 1945 else 1946 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 1947 1948 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1949 /* MMC core transfer sizes tunable parameters */ 1950 mmc->max_segs = MAX_BD_NUM; 1951 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1952 mmc->max_blk_size = 2048; 1953 mmc->max_req_size = 512 * 1024; 1954 mmc->max_blk_count = mmc->max_req_size / 512; 1955 if (host->dev_comp->support_64g) 1956 host->dma_mask = DMA_BIT_MASK(36); 1957 else 1958 host->dma_mask = DMA_BIT_MASK(32); 1959 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1960 1961 host->timeout_clks = 3 * 1048576; 1962 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1963 2 * sizeof(struct mt_gpdma_desc), 1964 &host->dma.gpd_addr, GFP_KERNEL); 1965 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1966 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1967 &host->dma.bd_addr, GFP_KERNEL); 1968 if (!host->dma.gpd || !host->dma.bd) { 1969 ret = -ENOMEM; 1970 goto release_mem; 1971 } 1972 msdc_init_gpd_bd(host, &host->dma); 1973 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1974 spin_lock_init(&host->lock); 1975 1976 platform_set_drvdata(pdev, mmc); 1977 msdc_ungate_clock(host); 1978 msdc_init_hw(host); 1979 1980 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1981 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1982 if (ret) 1983 goto release; 1984 1985 pm_runtime_set_active(host->dev); 1986 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1987 pm_runtime_use_autosuspend(host->dev); 1988 pm_runtime_enable(host->dev); 1989 ret = mmc_add_host(mmc); 1990 1991 if (ret) 1992 goto end; 1993 1994 return 0; 1995 end: 1996 pm_runtime_disable(host->dev); 1997 release: 1998 platform_set_drvdata(pdev, NULL); 1999 msdc_deinit_hw(host); 2000 msdc_gate_clock(host); 2001 release_mem: 2002 if (host->dma.gpd) 2003 dma_free_coherent(&pdev->dev, 2004 2 * sizeof(struct mt_gpdma_desc), 2005 host->dma.gpd, host->dma.gpd_addr); 2006 if (host->dma.bd) 2007 dma_free_coherent(&pdev->dev, 2008 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2009 host->dma.bd, host->dma.bd_addr); 2010 host_free: 2011 mmc_free_host(mmc); 2012 2013 return ret; 2014 } 2015 2016 static int msdc_drv_remove(struct platform_device *pdev) 2017 { 2018 struct mmc_host *mmc; 2019 struct msdc_host *host; 2020 2021 mmc = platform_get_drvdata(pdev); 2022 host = mmc_priv(mmc); 2023 2024 pm_runtime_get_sync(host->dev); 2025 2026 platform_set_drvdata(pdev, NULL); 2027 mmc_remove_host(host->mmc); 2028 msdc_deinit_hw(host); 2029 msdc_gate_clock(host); 2030 2031 pm_runtime_disable(host->dev); 2032 pm_runtime_put_noidle(host->dev); 2033 dma_free_coherent(&pdev->dev, 2034 2 * sizeof(struct mt_gpdma_desc), 2035 host->dma.gpd, host->dma.gpd_addr); 2036 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2037 host->dma.bd, host->dma.bd_addr); 2038 2039 mmc_free_host(host->mmc); 2040 2041 return 0; 2042 } 2043 2044 #ifdef CONFIG_PM 2045 static void msdc_save_reg(struct msdc_host *host) 2046 { 2047 u32 tune_reg = host->dev_comp->pad_tune_reg; 2048 2049 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2050 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2051 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2052 host->save_para.pad_tune = readl(host->base + tune_reg); 2053 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2054 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2055 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2056 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2057 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2058 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2059 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2060 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2061 } 2062 2063 static void msdc_restore_reg(struct msdc_host *host) 2064 { 2065 u32 tune_reg = host->dev_comp->pad_tune_reg; 2066 2067 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2068 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2069 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2070 writel(host->save_para.pad_tune, host->base + tune_reg); 2071 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2072 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2073 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2074 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2075 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2076 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2077 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2078 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2079 } 2080 2081 static int msdc_runtime_suspend(struct device *dev) 2082 { 2083 struct mmc_host *mmc = dev_get_drvdata(dev); 2084 struct msdc_host *host = mmc_priv(mmc); 2085 2086 msdc_save_reg(host); 2087 msdc_gate_clock(host); 2088 return 0; 2089 } 2090 2091 static int msdc_runtime_resume(struct device *dev) 2092 { 2093 struct mmc_host *mmc = dev_get_drvdata(dev); 2094 struct msdc_host *host = mmc_priv(mmc); 2095 2096 msdc_ungate_clock(host); 2097 msdc_restore_reg(host); 2098 return 0; 2099 } 2100 #endif 2101 2102 static const struct dev_pm_ops msdc_dev_pm_ops = { 2103 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2104 pm_runtime_force_resume) 2105 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2106 }; 2107 2108 static struct platform_driver mt_msdc_driver = { 2109 .probe = msdc_drv_probe, 2110 .remove = msdc_drv_remove, 2111 .driver = { 2112 .name = "mtk-msdc", 2113 .of_match_table = msdc_of_ids, 2114 .pm = &msdc_dev_pm_ops, 2115 }, 2116 }; 2117 2118 module_platform_driver(mt_msdc_driver); 2119 MODULE_LICENSE("GPL v2"); 2120 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2121