1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 #include <linux/interrupt.h> 32 33 #include <linux/mmc/card.h> 34 #include <linux/mmc/core.h> 35 #include <linux/mmc/host.h> 36 #include <linux/mmc/mmc.h> 37 #include <linux/mmc/sd.h> 38 #include <linux/mmc/sdio.h> 39 #include <linux/mmc/slot-gpio.h> 40 41 #define MAX_BD_NUM 1024 42 43 /*--------------------------------------------------------------------------*/ 44 /* Common Definition */ 45 /*--------------------------------------------------------------------------*/ 46 #define MSDC_BUS_1BITS 0x0 47 #define MSDC_BUS_4BITS 0x1 48 #define MSDC_BUS_8BITS 0x2 49 50 #define MSDC_BURST_64B 0x6 51 52 /*--------------------------------------------------------------------------*/ 53 /* Register Offset */ 54 /*--------------------------------------------------------------------------*/ 55 #define MSDC_CFG 0x0 56 #define MSDC_IOCON 0x04 57 #define MSDC_PS 0x08 58 #define MSDC_INT 0x0c 59 #define MSDC_INTEN 0x10 60 #define MSDC_FIFOCS 0x14 61 #define SDC_CFG 0x30 62 #define SDC_CMD 0x34 63 #define SDC_ARG 0x38 64 #define SDC_STS 0x3c 65 #define SDC_RESP0 0x40 66 #define SDC_RESP1 0x44 67 #define SDC_RESP2 0x48 68 #define SDC_RESP3 0x4c 69 #define SDC_BLK_NUM 0x50 70 #define EMMC_IOCON 0x7c 71 #define SDC_ACMD_RESP 0x80 72 #define MSDC_DMA_SA 0x90 73 #define MSDC_DMA_CTRL 0x98 74 #define MSDC_DMA_CFG 0x9c 75 #define MSDC_PATCH_BIT 0xb0 76 #define MSDC_PATCH_BIT1 0xb4 77 #define MSDC_PAD_TUNE 0xec 78 #define PAD_DS_TUNE 0x188 79 #define PAD_CMD_TUNE 0x18c 80 #define EMMC50_CFG0 0x208 81 82 /*--------------------------------------------------------------------------*/ 83 /* Register Mask */ 84 /*--------------------------------------------------------------------------*/ 85 86 /* MSDC_CFG mask */ 87 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 88 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 89 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 90 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 91 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 92 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 93 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 94 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 95 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 96 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 97 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 98 99 /* MSDC_IOCON mask */ 100 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 101 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 102 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 103 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 104 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 105 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 106 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 107 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 108 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 109 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 110 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 111 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 112 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 113 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 114 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 115 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 116 117 /* MSDC_PS mask */ 118 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 119 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 120 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 121 #define MSDC_PS_DAT (0xff << 16) /* R */ 122 #define MSDC_PS_CMD (0x1 << 24) /* R */ 123 #define MSDC_PS_WP (0x1 << 31) /* R */ 124 125 /* MSDC_INT mask */ 126 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 127 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 128 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 129 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 130 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 131 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 132 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 133 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 134 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 135 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 136 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 137 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 138 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 139 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 140 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 141 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 142 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 143 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 144 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 145 146 /* MSDC_INTEN mask */ 147 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 148 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 149 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 150 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 151 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 152 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 153 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 154 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 155 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 156 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 157 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 158 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 159 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 160 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 161 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 162 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 163 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 164 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 165 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 166 167 /* MSDC_FIFOCS mask */ 168 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 169 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 170 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 171 172 /* SDC_CFG mask */ 173 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 174 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 175 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 176 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 177 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 178 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 179 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 180 181 /* SDC_STS mask */ 182 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 183 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 184 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 185 186 /* MSDC_DMA_CTRL mask */ 187 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 188 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 189 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 190 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 191 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 192 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 193 194 /* MSDC_DMA_CFG mask */ 195 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 196 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 197 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 198 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 199 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 200 201 /* MSDC_PATCH_BIT mask */ 202 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 203 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 204 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 205 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 206 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 207 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 208 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 209 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 210 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 211 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 212 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 213 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 214 215 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 216 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 217 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 218 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 219 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 220 221 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 222 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 223 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 224 225 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 226 227 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 228 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 229 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 230 231 #define REQ_CMD_EIO (0x1 << 0) 232 #define REQ_CMD_TMO (0x1 << 1) 233 #define REQ_DAT_ERR (0x1 << 2) 234 #define REQ_STOP_EIO (0x1 << 3) 235 #define REQ_STOP_TMO (0x1 << 4) 236 #define REQ_CMD_BUSY (0x1 << 5) 237 238 #define MSDC_PREPARE_FLAG (0x1 << 0) 239 #define MSDC_ASYNC_FLAG (0x1 << 1) 240 #define MSDC_MMAP_FLAG (0x1 << 2) 241 242 #define MTK_MMC_AUTOSUSPEND_DELAY 50 243 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 244 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 245 246 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 247 /*--------------------------------------------------------------------------*/ 248 /* Descriptor Structure */ 249 /*--------------------------------------------------------------------------*/ 250 struct mt_gpdma_desc { 251 u32 gpd_info; 252 #define GPDMA_DESC_HWO (0x1 << 0) 253 #define GPDMA_DESC_BDP (0x1 << 1) 254 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 255 #define GPDMA_DESC_INT (0x1 << 16) 256 u32 next; 257 u32 ptr; 258 u32 gpd_data_len; 259 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 260 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 261 u32 arg; 262 u32 blknum; 263 u32 cmd; 264 }; 265 266 struct mt_bdma_desc { 267 u32 bd_info; 268 #define BDMA_DESC_EOL (0x1 << 0) 269 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 270 #define BDMA_DESC_BLKPAD (0x1 << 17) 271 #define BDMA_DESC_DWPAD (0x1 << 18) 272 u32 next; 273 u32 ptr; 274 u32 bd_data_len; 275 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 276 }; 277 278 struct msdc_dma { 279 struct scatterlist *sg; /* I/O scatter list */ 280 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 281 struct mt_bdma_desc *bd; /* pointer to bd array */ 282 dma_addr_t gpd_addr; /* the physical address of gpd array */ 283 dma_addr_t bd_addr; /* the physical address of bd array */ 284 }; 285 286 struct msdc_save_para { 287 u32 msdc_cfg; 288 u32 iocon; 289 u32 sdc_cfg; 290 u32 pad_tune; 291 u32 patch_bit0; 292 u32 patch_bit1; 293 u32 pad_ds_tune; 294 u32 pad_cmd_tune; 295 u32 emmc50_cfg0; 296 }; 297 298 struct msdc_tune_para { 299 u32 iocon; 300 u32 pad_tune; 301 u32 pad_cmd_tune; 302 }; 303 304 struct msdc_delay_phase { 305 u8 maxlen; 306 u8 start; 307 u8 final_phase; 308 }; 309 310 struct msdc_host { 311 struct device *dev; 312 struct mmc_host *mmc; /* mmc structure */ 313 int cmd_rsp; 314 315 spinlock_t lock; 316 struct mmc_request *mrq; 317 struct mmc_command *cmd; 318 struct mmc_data *data; 319 int error; 320 321 void __iomem *base; /* host base address */ 322 323 struct msdc_dma dma; /* dma channel */ 324 u64 dma_mask; 325 326 u32 timeout_ns; /* data timeout ns */ 327 u32 timeout_clks; /* data timeout clks */ 328 329 struct pinctrl *pinctrl; 330 struct pinctrl_state *pins_default; 331 struct pinctrl_state *pins_uhs; 332 struct delayed_work req_timeout; 333 int irq; /* host interrupt */ 334 335 struct clk *src_clk; /* msdc source clock */ 336 struct clk *h_clk; /* msdc h_clk */ 337 u32 mclk; /* mmc subsystem clock frequency */ 338 u32 src_clk_freq; /* source clock frequency */ 339 u32 sclk; /* SD/MS bus clock frequency */ 340 unsigned char timing; 341 bool vqmmc_enabled; 342 u32 hs400_ds_delay; 343 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 344 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 345 bool hs400_cmd_resp_sel_rising; 346 /* cmd response sample selection for HS400 */ 347 bool hs400_mode; /* current eMMC will run at hs400 mode */ 348 struct msdc_save_para save_para; /* used when gate HCLK */ 349 struct msdc_tune_para def_tune_para; /* default tune setting */ 350 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 351 }; 352 353 static void sdr_set_bits(void __iomem *reg, u32 bs) 354 { 355 u32 val = readl(reg); 356 357 val |= bs; 358 writel(val, reg); 359 } 360 361 static void sdr_clr_bits(void __iomem *reg, u32 bs) 362 { 363 u32 val = readl(reg); 364 365 val &= ~bs; 366 writel(val, reg); 367 } 368 369 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 370 { 371 unsigned int tv = readl(reg); 372 373 tv &= ~field; 374 tv |= ((val) << (ffs((unsigned int)field) - 1)); 375 writel(tv, reg); 376 } 377 378 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 379 { 380 unsigned int tv = readl(reg); 381 382 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 383 } 384 385 static void msdc_reset_hw(struct msdc_host *host) 386 { 387 u32 val; 388 389 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 390 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 391 cpu_relax(); 392 393 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 394 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 395 cpu_relax(); 396 397 val = readl(host->base + MSDC_INT); 398 writel(val, host->base + MSDC_INT); 399 } 400 401 static void msdc_cmd_next(struct msdc_host *host, 402 struct mmc_request *mrq, struct mmc_command *cmd); 403 404 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 405 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 406 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 407 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 408 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 409 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 410 411 static u8 msdc_dma_calcs(u8 *buf, u32 len) 412 { 413 u32 i, sum = 0; 414 415 for (i = 0; i < len; i++) 416 sum += buf[i]; 417 return 0xff - (u8) sum; 418 } 419 420 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 421 struct mmc_data *data) 422 { 423 unsigned int j, dma_len; 424 dma_addr_t dma_address; 425 u32 dma_ctrl; 426 struct scatterlist *sg; 427 struct mt_gpdma_desc *gpd; 428 struct mt_bdma_desc *bd; 429 430 sg = data->sg; 431 432 gpd = dma->gpd; 433 bd = dma->bd; 434 435 /* modify gpd */ 436 gpd->gpd_info |= GPDMA_DESC_HWO; 437 gpd->gpd_info |= GPDMA_DESC_BDP; 438 /* need to clear first. use these bits to calc checksum */ 439 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 440 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 441 442 /* modify bd */ 443 for_each_sg(data->sg, sg, data->sg_count, j) { 444 dma_address = sg_dma_address(sg); 445 dma_len = sg_dma_len(sg); 446 447 /* init bd */ 448 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 449 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 450 bd[j].ptr = (u32)dma_address; 451 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 452 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 453 454 if (j == data->sg_count - 1) /* the last bd */ 455 bd[j].bd_info |= BDMA_DESC_EOL; 456 else 457 bd[j].bd_info &= ~BDMA_DESC_EOL; 458 459 /* checksume need to clear first */ 460 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 461 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 462 } 463 464 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 465 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 466 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 467 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 468 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 469 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 470 } 471 472 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 473 { 474 struct mmc_data *data = mrq->data; 475 476 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 477 data->host_cookie |= MSDC_PREPARE_FLAG; 478 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 479 mmc_get_dma_dir(data)); 480 } 481 } 482 483 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 484 { 485 struct mmc_data *data = mrq->data; 486 487 if (data->host_cookie & MSDC_ASYNC_FLAG) 488 return; 489 490 if (data->host_cookie & MSDC_PREPARE_FLAG) { 491 dma_unmap_sg(host->dev, data->sg, data->sg_len, 492 mmc_get_dma_dir(data)); 493 data->host_cookie &= ~MSDC_PREPARE_FLAG; 494 } 495 } 496 497 /* clock control primitives */ 498 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 499 { 500 u32 timeout, clk_ns; 501 u32 mode = 0; 502 503 host->timeout_ns = ns; 504 host->timeout_clks = clks; 505 if (host->sclk == 0) { 506 timeout = 0; 507 } else { 508 clk_ns = 1000000000UL / host->sclk; 509 timeout = (ns + clk_ns - 1) / clk_ns + clks; 510 /* in 1048576 sclk cycle unit */ 511 timeout = (timeout + (0x1 << 20) - 1) >> 20; 512 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 513 /*DDR mode will double the clk cycles for data timeout */ 514 timeout = mode >= 2 ? timeout * 2 : timeout; 515 timeout = timeout > 1 ? timeout - 1 : 0; 516 timeout = timeout > 255 ? 255 : timeout; 517 } 518 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 519 } 520 521 static void msdc_gate_clock(struct msdc_host *host) 522 { 523 clk_disable_unprepare(host->src_clk); 524 clk_disable_unprepare(host->h_clk); 525 } 526 527 static void msdc_ungate_clock(struct msdc_host *host) 528 { 529 clk_prepare_enable(host->h_clk); 530 clk_prepare_enable(host->src_clk); 531 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 532 cpu_relax(); 533 } 534 535 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 536 { 537 u32 mode; 538 u32 flags; 539 u32 div; 540 u32 sclk; 541 542 if (!hz) { 543 dev_dbg(host->dev, "set mclk to 0\n"); 544 host->mclk = 0; 545 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 546 return; 547 } 548 549 flags = readl(host->base + MSDC_INTEN); 550 sdr_clr_bits(host->base + MSDC_INTEN, flags); 551 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 552 if (timing == MMC_TIMING_UHS_DDR50 || 553 timing == MMC_TIMING_MMC_DDR52 || 554 timing == MMC_TIMING_MMC_HS400) { 555 if (timing == MMC_TIMING_MMC_HS400) 556 mode = 0x3; 557 else 558 mode = 0x2; /* ddr mode and use divisor */ 559 560 if (hz >= (host->src_clk_freq >> 2)) { 561 div = 0; /* mean div = 1/4 */ 562 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 563 } else { 564 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 565 sclk = (host->src_clk_freq >> 2) / div; 566 div = (div >> 1); 567 } 568 569 if (timing == MMC_TIMING_MMC_HS400 && 570 hz >= (host->src_clk_freq >> 1)) { 571 sdr_set_bits(host->base + MSDC_CFG, 572 MSDC_CFG_HS400_CK_MODE); 573 sclk = host->src_clk_freq >> 1; 574 div = 0; /* div is ignore when bit18 is set */ 575 } 576 } else if (hz >= host->src_clk_freq) { 577 mode = 0x1; /* no divisor */ 578 div = 0; 579 sclk = host->src_clk_freq; 580 } else { 581 mode = 0x0; /* use divisor */ 582 if (hz >= (host->src_clk_freq >> 1)) { 583 div = 0; /* mean div = 1/2 */ 584 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 585 } else { 586 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 587 sclk = (host->src_clk_freq >> 2) / div; 588 } 589 } 590 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 591 (mode << 8) | div); 592 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 593 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 594 cpu_relax(); 595 host->sclk = sclk; 596 host->mclk = hz; 597 host->timing = timing; 598 /* need because clk changed. */ 599 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 600 sdr_set_bits(host->base + MSDC_INTEN, flags); 601 602 /* 603 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 604 * tune result of hs200/200Mhz is not suitable for 50Mhz 605 */ 606 if (host->sclk <= 52000000) { 607 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 608 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 609 } else { 610 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 611 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 612 writel(host->saved_tune_para.pad_cmd_tune, 613 host->base + PAD_CMD_TUNE); 614 } 615 616 if (timing == MMC_TIMING_MMC_HS400) 617 sdr_set_field(host->base + PAD_CMD_TUNE, 618 MSDC_PAD_TUNE_CMDRRDLY, 619 host->hs400_cmd_int_delay); 620 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 621 } 622 623 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 624 struct mmc_request *mrq, struct mmc_command *cmd) 625 { 626 u32 resp; 627 628 switch (mmc_resp_type(cmd)) { 629 /* Actually, R1, R5, R6, R7 are the same */ 630 case MMC_RSP_R1: 631 resp = 0x1; 632 break; 633 case MMC_RSP_R1B: 634 resp = 0x7; 635 break; 636 case MMC_RSP_R2: 637 resp = 0x2; 638 break; 639 case MMC_RSP_R3: 640 resp = 0x3; 641 break; 642 case MMC_RSP_NONE: 643 default: 644 resp = 0x0; 645 break; 646 } 647 648 return resp; 649 } 650 651 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 652 struct mmc_request *mrq, struct mmc_command *cmd) 653 { 654 /* rawcmd : 655 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 656 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 657 */ 658 u32 opcode = cmd->opcode; 659 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 660 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 661 662 host->cmd_rsp = resp; 663 664 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 665 opcode == MMC_STOP_TRANSMISSION) 666 rawcmd |= (0x1 << 14); 667 else if (opcode == SD_SWITCH_VOLTAGE) 668 rawcmd |= (0x1 << 30); 669 else if (opcode == SD_APP_SEND_SCR || 670 opcode == SD_APP_SEND_NUM_WR_BLKS || 671 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 672 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 673 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 674 rawcmd |= (0x1 << 11); 675 676 if (cmd->data) { 677 struct mmc_data *data = cmd->data; 678 679 if (mmc_op_multi(opcode)) { 680 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 681 !(mrq->sbc->arg & 0xFFFF0000)) 682 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 683 } 684 685 rawcmd |= ((data->blksz & 0xFFF) << 16); 686 if (data->flags & MMC_DATA_WRITE) 687 rawcmd |= (0x1 << 13); 688 if (data->blocks > 1) 689 rawcmd |= (0x2 << 11); 690 else 691 rawcmd |= (0x1 << 11); 692 /* Always use dma mode */ 693 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 694 695 if (host->timeout_ns != data->timeout_ns || 696 host->timeout_clks != data->timeout_clks) 697 msdc_set_timeout(host, data->timeout_ns, 698 data->timeout_clks); 699 700 writel(data->blocks, host->base + SDC_BLK_NUM); 701 } 702 return rawcmd; 703 } 704 705 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 706 struct mmc_command *cmd, struct mmc_data *data) 707 { 708 bool read; 709 710 WARN_ON(host->data); 711 host->data = data; 712 read = data->flags & MMC_DATA_READ; 713 714 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 715 msdc_dma_setup(host, &host->dma, data); 716 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 717 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 718 dev_dbg(host->dev, "DMA start\n"); 719 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 720 __func__, cmd->opcode, data->blocks, read); 721 } 722 723 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 724 struct mmc_command *cmd) 725 { 726 u32 *rsp = cmd->resp; 727 728 rsp[0] = readl(host->base + SDC_ACMD_RESP); 729 730 if (events & MSDC_INT_ACMDRDY) { 731 cmd->error = 0; 732 } else { 733 msdc_reset_hw(host); 734 if (events & MSDC_INT_ACMDCRCERR) { 735 cmd->error = -EILSEQ; 736 host->error |= REQ_STOP_EIO; 737 } else if (events & MSDC_INT_ACMDTMO) { 738 cmd->error = -ETIMEDOUT; 739 host->error |= REQ_STOP_TMO; 740 } 741 dev_err(host->dev, 742 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 743 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 744 } 745 return cmd->error; 746 } 747 748 static void msdc_track_cmd_data(struct msdc_host *host, 749 struct mmc_command *cmd, struct mmc_data *data) 750 { 751 if (host->error) 752 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 753 __func__, cmd->opcode, cmd->arg, host->error); 754 } 755 756 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 757 { 758 unsigned long flags; 759 bool ret; 760 761 ret = cancel_delayed_work(&host->req_timeout); 762 if (!ret) { 763 /* delay work already running */ 764 return; 765 } 766 spin_lock_irqsave(&host->lock, flags); 767 host->mrq = NULL; 768 spin_unlock_irqrestore(&host->lock, flags); 769 770 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 771 if (mrq->data) 772 msdc_unprepare_data(host, mrq); 773 mmc_request_done(host->mmc, mrq); 774 } 775 776 /* returns true if command is fully handled; returns false otherwise */ 777 static bool msdc_cmd_done(struct msdc_host *host, int events, 778 struct mmc_request *mrq, struct mmc_command *cmd) 779 { 780 bool done = false; 781 bool sbc_error; 782 unsigned long flags; 783 u32 *rsp = cmd->resp; 784 785 if (mrq->sbc && cmd == mrq->cmd && 786 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 787 | MSDC_INT_ACMDTMO))) 788 msdc_auto_cmd_done(host, events, mrq->sbc); 789 790 sbc_error = mrq->sbc && mrq->sbc->error; 791 792 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 793 | MSDC_INT_RSPCRCERR 794 | MSDC_INT_CMDTMO))) 795 return done; 796 797 spin_lock_irqsave(&host->lock, flags); 798 done = !host->cmd; 799 host->cmd = NULL; 800 spin_unlock_irqrestore(&host->lock, flags); 801 802 if (done) 803 return true; 804 805 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 806 807 if (cmd->flags & MMC_RSP_PRESENT) { 808 if (cmd->flags & MMC_RSP_136) { 809 rsp[0] = readl(host->base + SDC_RESP3); 810 rsp[1] = readl(host->base + SDC_RESP2); 811 rsp[2] = readl(host->base + SDC_RESP1); 812 rsp[3] = readl(host->base + SDC_RESP0); 813 } else { 814 rsp[0] = readl(host->base + SDC_RESP0); 815 } 816 } 817 818 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 819 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 820 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 821 /* 822 * should not clear fifo/interrupt as the tune data 823 * may have alreay come. 824 */ 825 msdc_reset_hw(host); 826 if (events & MSDC_INT_RSPCRCERR) { 827 cmd->error = -EILSEQ; 828 host->error |= REQ_CMD_EIO; 829 } else if (events & MSDC_INT_CMDTMO) { 830 cmd->error = -ETIMEDOUT; 831 host->error |= REQ_CMD_TMO; 832 } 833 } 834 if (cmd->error) 835 dev_dbg(host->dev, 836 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 837 __func__, cmd->opcode, cmd->arg, rsp[0], 838 cmd->error); 839 840 msdc_cmd_next(host, mrq, cmd); 841 return true; 842 } 843 844 /* It is the core layer's responsibility to ensure card status 845 * is correct before issue a request. but host design do below 846 * checks recommended. 847 */ 848 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 849 struct mmc_request *mrq, struct mmc_command *cmd) 850 { 851 /* The max busy time we can endure is 20ms */ 852 unsigned long tmo = jiffies + msecs_to_jiffies(20); 853 854 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 855 time_before(jiffies, tmo)) 856 cpu_relax(); 857 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 858 dev_err(host->dev, "CMD bus busy detected\n"); 859 host->error |= REQ_CMD_BUSY; 860 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 861 return false; 862 } 863 864 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 865 tmo = jiffies + msecs_to_jiffies(20); 866 /* R1B or with data, should check SDCBUSY */ 867 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 868 time_before(jiffies, tmo)) 869 cpu_relax(); 870 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 871 dev_err(host->dev, "Controller busy detected\n"); 872 host->error |= REQ_CMD_BUSY; 873 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 874 return false; 875 } 876 } 877 return true; 878 } 879 880 static void msdc_start_command(struct msdc_host *host, 881 struct mmc_request *mrq, struct mmc_command *cmd) 882 { 883 u32 rawcmd; 884 885 WARN_ON(host->cmd); 886 host->cmd = cmd; 887 888 if (!msdc_cmd_is_ready(host, mrq, cmd)) 889 return; 890 891 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 892 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 893 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 894 msdc_reset_hw(host); 895 } 896 897 cmd->error = 0; 898 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 899 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 900 901 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 902 writel(cmd->arg, host->base + SDC_ARG); 903 writel(rawcmd, host->base + SDC_CMD); 904 } 905 906 static void msdc_cmd_next(struct msdc_host *host, 907 struct mmc_request *mrq, struct mmc_command *cmd) 908 { 909 if ((cmd->error && 910 !(cmd->error == -EILSEQ && 911 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 912 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 913 (mrq->sbc && mrq->sbc->error)) 914 msdc_request_done(host, mrq); 915 else if (cmd == mrq->sbc) 916 msdc_start_command(host, mrq, mrq->cmd); 917 else if (!cmd->data) 918 msdc_request_done(host, mrq); 919 else 920 msdc_start_data(host, mrq, cmd, cmd->data); 921 } 922 923 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 924 { 925 struct msdc_host *host = mmc_priv(mmc); 926 927 host->error = 0; 928 WARN_ON(host->mrq); 929 host->mrq = mrq; 930 931 if (mrq->data) 932 msdc_prepare_data(host, mrq); 933 934 /* if SBC is required, we have HW option and SW option. 935 * if HW option is enabled, and SBC does not have "special" flags, 936 * use HW option, otherwise use SW option 937 */ 938 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 939 (mrq->sbc->arg & 0xFFFF0000))) 940 msdc_start_command(host, mrq, mrq->sbc); 941 else 942 msdc_start_command(host, mrq, mrq->cmd); 943 } 944 945 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 946 { 947 struct msdc_host *host = mmc_priv(mmc); 948 struct mmc_data *data = mrq->data; 949 950 if (!data) 951 return; 952 953 msdc_prepare_data(host, mrq); 954 data->host_cookie |= MSDC_ASYNC_FLAG; 955 } 956 957 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 958 int err) 959 { 960 struct msdc_host *host = mmc_priv(mmc); 961 struct mmc_data *data; 962 963 data = mrq->data; 964 if (!data) 965 return; 966 if (data->host_cookie) { 967 data->host_cookie &= ~MSDC_ASYNC_FLAG; 968 msdc_unprepare_data(host, mrq); 969 } 970 } 971 972 static void msdc_data_xfer_next(struct msdc_host *host, 973 struct mmc_request *mrq, struct mmc_data *data) 974 { 975 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 976 !mrq->sbc) 977 msdc_start_command(host, mrq, mrq->stop); 978 else 979 msdc_request_done(host, mrq); 980 } 981 982 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 983 struct mmc_request *mrq, struct mmc_data *data) 984 { 985 struct mmc_command *stop = data->stop; 986 unsigned long flags; 987 bool done; 988 unsigned int check_data = events & 989 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 990 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 991 | MSDC_INT_DMA_PROTECT); 992 993 spin_lock_irqsave(&host->lock, flags); 994 done = !host->data; 995 if (check_data) 996 host->data = NULL; 997 spin_unlock_irqrestore(&host->lock, flags); 998 999 if (done) 1000 return true; 1001 1002 if (check_data || (stop && stop->error)) { 1003 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1004 readl(host->base + MSDC_DMA_CFG)); 1005 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1006 1); 1007 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1008 cpu_relax(); 1009 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1010 dev_dbg(host->dev, "DMA stop\n"); 1011 1012 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1013 data->bytes_xfered = data->blocks * data->blksz; 1014 } else { 1015 dev_dbg(host->dev, "interrupt events: %x\n", events); 1016 msdc_reset_hw(host); 1017 host->error |= REQ_DAT_ERR; 1018 data->bytes_xfered = 0; 1019 1020 if (events & MSDC_INT_DATTMO) 1021 data->error = -ETIMEDOUT; 1022 else if (events & MSDC_INT_DATCRCERR) 1023 data->error = -EILSEQ; 1024 1025 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1026 __func__, mrq->cmd->opcode, data->blocks); 1027 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1028 (int)data->error, data->bytes_xfered); 1029 } 1030 1031 msdc_data_xfer_next(host, mrq, data); 1032 done = true; 1033 } 1034 return done; 1035 } 1036 1037 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1038 { 1039 u32 val = readl(host->base + SDC_CFG); 1040 1041 val &= ~SDC_CFG_BUSWIDTH; 1042 1043 switch (width) { 1044 default: 1045 case MMC_BUS_WIDTH_1: 1046 val |= (MSDC_BUS_1BITS << 16); 1047 break; 1048 case MMC_BUS_WIDTH_4: 1049 val |= (MSDC_BUS_4BITS << 16); 1050 break; 1051 case MMC_BUS_WIDTH_8: 1052 val |= (MSDC_BUS_8BITS << 16); 1053 break; 1054 } 1055 1056 writel(val, host->base + SDC_CFG); 1057 dev_dbg(host->dev, "Bus Width = %d", width); 1058 } 1059 1060 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1061 { 1062 struct msdc_host *host = mmc_priv(mmc); 1063 int ret = 0; 1064 1065 if (!IS_ERR(mmc->supply.vqmmc)) { 1066 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1067 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1068 dev_err(host->dev, "Unsupported signal voltage!\n"); 1069 return -EINVAL; 1070 } 1071 1072 ret = mmc_regulator_set_vqmmc(mmc, ios); 1073 if (ret) { 1074 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1075 ret, ios->signal_voltage); 1076 } else { 1077 /* Apply different pinctrl settings for different signal voltage */ 1078 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1079 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1080 else 1081 pinctrl_select_state(host->pinctrl, host->pins_default); 1082 } 1083 } 1084 return ret; 1085 } 1086 1087 static int msdc_card_busy(struct mmc_host *mmc) 1088 { 1089 struct msdc_host *host = mmc_priv(mmc); 1090 u32 status = readl(host->base + MSDC_PS); 1091 1092 /* only check if data0 is low */ 1093 return !(status & BIT(16)); 1094 } 1095 1096 static void msdc_request_timeout(struct work_struct *work) 1097 { 1098 struct msdc_host *host = container_of(work, struct msdc_host, 1099 req_timeout.work); 1100 1101 /* simulate HW timeout status */ 1102 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1103 if (host->mrq) { 1104 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1105 host->mrq, host->mrq->cmd->opcode); 1106 if (host->cmd) { 1107 dev_err(host->dev, "%s: aborting cmd=%d\n", 1108 __func__, host->cmd->opcode); 1109 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1110 host->cmd); 1111 } else if (host->data) { 1112 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1113 __func__, host->mrq->cmd->opcode, 1114 host->data->blocks); 1115 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1116 host->data); 1117 } 1118 } 1119 } 1120 1121 static irqreturn_t msdc_irq(int irq, void *dev_id) 1122 { 1123 struct msdc_host *host = (struct msdc_host *) dev_id; 1124 1125 while (true) { 1126 unsigned long flags; 1127 struct mmc_request *mrq; 1128 struct mmc_command *cmd; 1129 struct mmc_data *data; 1130 u32 events, event_mask; 1131 1132 spin_lock_irqsave(&host->lock, flags); 1133 events = readl(host->base + MSDC_INT); 1134 event_mask = readl(host->base + MSDC_INTEN); 1135 /* clear interrupts */ 1136 writel(events & event_mask, host->base + MSDC_INT); 1137 1138 mrq = host->mrq; 1139 cmd = host->cmd; 1140 data = host->data; 1141 spin_unlock_irqrestore(&host->lock, flags); 1142 1143 if (!(events & event_mask)) 1144 break; 1145 1146 if (!mrq) { 1147 dev_err(host->dev, 1148 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1149 __func__, events, event_mask); 1150 WARN_ON(1); 1151 break; 1152 } 1153 1154 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1155 1156 if (cmd) 1157 msdc_cmd_done(host, events, mrq, cmd); 1158 else if (data) 1159 msdc_data_xfer_done(host, events, mrq, data); 1160 } 1161 1162 return IRQ_HANDLED; 1163 } 1164 1165 static void msdc_init_hw(struct msdc_host *host) 1166 { 1167 u32 val; 1168 1169 /* Configure to MMC/SD mode, clock free running */ 1170 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1171 1172 /* Reset */ 1173 msdc_reset_hw(host); 1174 1175 /* Disable card detection */ 1176 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1177 1178 /* Disable and clear all interrupts */ 1179 writel(0, host->base + MSDC_INTEN); 1180 val = readl(host->base + MSDC_INT); 1181 writel(val, host->base + MSDC_INT); 1182 1183 writel(0, host->base + MSDC_PAD_TUNE); 1184 writel(0, host->base + MSDC_IOCON); 1185 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1186 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1187 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1188 writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 1189 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1190 1191 /* Configure to enable SDIO mode. 1192 * it's must otherwise sdio cmd5 failed 1193 */ 1194 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1195 1196 /* disable detect SDIO device interrupt function */ 1197 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1198 1199 /* Configure to default data timeout */ 1200 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1201 1202 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1203 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1204 dev_dbg(host->dev, "init hardware done!"); 1205 } 1206 1207 static void msdc_deinit_hw(struct msdc_host *host) 1208 { 1209 u32 val; 1210 /* Disable and clear all interrupts */ 1211 writel(0, host->base + MSDC_INTEN); 1212 1213 val = readl(host->base + MSDC_INT); 1214 writel(val, host->base + MSDC_INT); 1215 } 1216 1217 /* init gpd and bd list in msdc_drv_probe */ 1218 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1219 { 1220 struct mt_gpdma_desc *gpd = dma->gpd; 1221 struct mt_bdma_desc *bd = dma->bd; 1222 int i; 1223 1224 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1225 1226 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1227 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1228 /* gpd->next is must set for desc DMA 1229 * That's why must alloc 2 gpd structure. 1230 */ 1231 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1232 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1233 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1234 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1235 } 1236 1237 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1238 { 1239 struct msdc_host *host = mmc_priv(mmc); 1240 int ret; 1241 1242 msdc_set_buswidth(host, ios->bus_width); 1243 1244 /* Suspend/Resume will do power off/on */ 1245 switch (ios->power_mode) { 1246 case MMC_POWER_UP: 1247 if (!IS_ERR(mmc->supply.vmmc)) { 1248 msdc_init_hw(host); 1249 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1250 ios->vdd); 1251 if (ret) { 1252 dev_err(host->dev, "Failed to set vmmc power!\n"); 1253 return; 1254 } 1255 } 1256 break; 1257 case MMC_POWER_ON: 1258 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1259 ret = regulator_enable(mmc->supply.vqmmc); 1260 if (ret) 1261 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1262 else 1263 host->vqmmc_enabled = true; 1264 } 1265 break; 1266 case MMC_POWER_OFF: 1267 if (!IS_ERR(mmc->supply.vmmc)) 1268 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1269 1270 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1271 regulator_disable(mmc->supply.vqmmc); 1272 host->vqmmc_enabled = false; 1273 } 1274 break; 1275 default: 1276 break; 1277 } 1278 1279 if (host->mclk != ios->clock || host->timing != ios->timing) 1280 msdc_set_mclk(host, ios->timing, ios->clock); 1281 } 1282 1283 static u32 test_delay_bit(u32 delay, u32 bit) 1284 { 1285 bit %= PAD_DELAY_MAX; 1286 return delay & (1 << bit); 1287 } 1288 1289 static int get_delay_len(u32 delay, u32 start_bit) 1290 { 1291 int i; 1292 1293 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1294 if (test_delay_bit(delay, start_bit + i) == 0) 1295 return i; 1296 } 1297 return PAD_DELAY_MAX - start_bit; 1298 } 1299 1300 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1301 { 1302 int start = 0, len = 0; 1303 int start_final = 0, len_final = 0; 1304 u8 final_phase = 0xff; 1305 struct msdc_delay_phase delay_phase = { 0, }; 1306 1307 if (delay == 0) { 1308 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1309 delay_phase.final_phase = final_phase; 1310 return delay_phase; 1311 } 1312 1313 while (start < PAD_DELAY_MAX) { 1314 len = get_delay_len(delay, start); 1315 if (len_final < len) { 1316 start_final = start; 1317 len_final = len; 1318 } 1319 start += len ? len : 1; 1320 if (len >= 12 && start_final < 4) 1321 break; 1322 } 1323 1324 /* The rule is that to find the smallest delay cell */ 1325 if (start_final == 0) 1326 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1327 else 1328 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1329 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1330 delay, len_final, final_phase); 1331 1332 delay_phase.maxlen = len_final; 1333 delay_phase.start = start_final; 1334 delay_phase.final_phase = final_phase; 1335 return delay_phase; 1336 } 1337 1338 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1339 { 1340 struct msdc_host *host = mmc_priv(mmc); 1341 u32 rise_delay = 0, fall_delay = 0; 1342 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1343 struct msdc_delay_phase internal_delay_phase; 1344 u8 final_delay, final_maxlen; 1345 u32 internal_delay = 0; 1346 int cmd_err; 1347 int i, j; 1348 1349 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1350 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1351 sdr_set_field(host->base + MSDC_PAD_TUNE, 1352 MSDC_PAD_TUNE_CMDRRDLY, 1353 host->hs200_cmd_int_delay); 1354 1355 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1356 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1357 sdr_set_field(host->base + MSDC_PAD_TUNE, 1358 MSDC_PAD_TUNE_CMDRDLY, i); 1359 /* 1360 * Using the same parameters, it may sometimes pass the test, 1361 * but sometimes it may fail. To make sure the parameters are 1362 * more stable, we test each set of parameters 3 times. 1363 */ 1364 for (j = 0; j < 3; j++) { 1365 mmc_send_tuning(mmc, opcode, &cmd_err); 1366 if (!cmd_err) { 1367 rise_delay |= (1 << i); 1368 } else { 1369 rise_delay &= ~(1 << i); 1370 break; 1371 } 1372 } 1373 } 1374 final_rise_delay = get_best_delay(host, rise_delay); 1375 /* if rising edge has enough margin, then do not scan falling edge */ 1376 if (final_rise_delay.maxlen >= 12 && final_rise_delay.start < 4) 1377 goto skip_fall; 1378 1379 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1380 for (i = 0; i < PAD_DELAY_MAX; i++) { 1381 sdr_set_field(host->base + MSDC_PAD_TUNE, 1382 MSDC_PAD_TUNE_CMDRDLY, i); 1383 /* 1384 * Using the same parameters, it may sometimes pass the test, 1385 * but sometimes it may fail. To make sure the parameters are 1386 * more stable, we test each set of parameters 3 times. 1387 */ 1388 for (j = 0; j < 3; j++) { 1389 mmc_send_tuning(mmc, opcode, &cmd_err); 1390 if (!cmd_err) { 1391 fall_delay |= (1 << i); 1392 } else { 1393 fall_delay &= ~(1 << i); 1394 break; 1395 } 1396 } 1397 } 1398 final_fall_delay = get_best_delay(host, fall_delay); 1399 1400 skip_fall: 1401 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1402 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1403 final_maxlen = final_fall_delay.maxlen; 1404 if (final_maxlen == final_rise_delay.maxlen) { 1405 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1406 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1407 final_rise_delay.final_phase); 1408 final_delay = final_rise_delay.final_phase; 1409 } else { 1410 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1411 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1412 final_fall_delay.final_phase); 1413 final_delay = final_fall_delay.final_phase; 1414 } 1415 if (host->hs200_cmd_int_delay) 1416 goto skip_internal; 1417 1418 for (i = 0; i < PAD_DELAY_MAX; i++) { 1419 sdr_set_field(host->base + MSDC_PAD_TUNE, 1420 MSDC_PAD_TUNE_CMDRRDLY, i); 1421 mmc_send_tuning(mmc, opcode, &cmd_err); 1422 if (!cmd_err) 1423 internal_delay |= (1 << i); 1424 } 1425 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1426 internal_delay_phase = get_best_delay(host, internal_delay); 1427 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRRDLY, 1428 internal_delay_phase.final_phase); 1429 skip_internal: 1430 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1431 return final_delay == 0xff ? -EIO : 0; 1432 } 1433 1434 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1435 { 1436 struct msdc_host *host = mmc_priv(mmc); 1437 u32 cmd_delay = 0; 1438 struct msdc_delay_phase final_cmd_delay = { 0,}; 1439 u8 final_delay; 1440 int cmd_err; 1441 int i, j; 1442 1443 /* select EMMC50 PAD CMD tune */ 1444 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 1445 1446 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1447 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1448 sdr_set_field(host->base + MSDC_PAD_TUNE, 1449 MSDC_PAD_TUNE_CMDRRDLY, 1450 host->hs200_cmd_int_delay); 1451 1452 if (host->hs400_cmd_resp_sel_rising) 1453 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1454 else 1455 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1456 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1457 sdr_set_field(host->base + PAD_CMD_TUNE, 1458 PAD_CMD_TUNE_RX_DLY3, i); 1459 /* 1460 * Using the same parameters, it may sometimes pass the test, 1461 * but sometimes it may fail. To make sure the parameters are 1462 * more stable, we test each set of parameters 3 times. 1463 */ 1464 for (j = 0; j < 3; j++) { 1465 mmc_send_tuning(mmc, opcode, &cmd_err); 1466 if (!cmd_err) { 1467 cmd_delay |= (1 << i); 1468 } else { 1469 cmd_delay &= ~(1 << i); 1470 break; 1471 } 1472 } 1473 } 1474 final_cmd_delay = get_best_delay(host, cmd_delay); 1475 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 1476 final_cmd_delay.final_phase); 1477 final_delay = final_cmd_delay.final_phase; 1478 1479 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1480 return final_delay == 0xff ? -EIO : 0; 1481 } 1482 1483 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1484 { 1485 struct msdc_host *host = mmc_priv(mmc); 1486 u32 rise_delay = 0, fall_delay = 0; 1487 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1488 u8 final_delay, final_maxlen; 1489 int i, ret; 1490 1491 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1492 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1493 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1494 sdr_set_field(host->base + MSDC_PAD_TUNE, 1495 MSDC_PAD_TUNE_DATRRDLY, i); 1496 ret = mmc_send_tuning(mmc, opcode, NULL); 1497 if (!ret) 1498 rise_delay |= (1 << i); 1499 } 1500 final_rise_delay = get_best_delay(host, rise_delay); 1501 /* if rising edge has enough margin, then do not scan falling edge */ 1502 if (final_rise_delay.maxlen >= 12 || 1503 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1504 goto skip_fall; 1505 1506 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1507 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1508 for (i = 0; i < PAD_DELAY_MAX; i++) { 1509 sdr_set_field(host->base + MSDC_PAD_TUNE, 1510 MSDC_PAD_TUNE_DATRRDLY, i); 1511 ret = mmc_send_tuning(mmc, opcode, NULL); 1512 if (!ret) 1513 fall_delay |= (1 << i); 1514 } 1515 final_fall_delay = get_best_delay(host, fall_delay); 1516 1517 skip_fall: 1518 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1519 if (final_maxlen == final_rise_delay.maxlen) { 1520 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1521 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1522 sdr_set_field(host->base + MSDC_PAD_TUNE, 1523 MSDC_PAD_TUNE_DATRRDLY, 1524 final_rise_delay.final_phase); 1525 final_delay = final_rise_delay.final_phase; 1526 } else { 1527 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1528 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1529 sdr_set_field(host->base + MSDC_PAD_TUNE, 1530 MSDC_PAD_TUNE_DATRRDLY, 1531 final_fall_delay.final_phase); 1532 final_delay = final_fall_delay.final_phase; 1533 } 1534 1535 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 1536 return final_delay == 0xff ? -EIO : 0; 1537 } 1538 1539 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1540 { 1541 struct msdc_host *host = mmc_priv(mmc); 1542 int ret; 1543 1544 if (host->hs400_mode) 1545 ret = hs400_tune_response(mmc, opcode); 1546 else 1547 ret = msdc_tune_response(mmc, opcode); 1548 if (ret == -EIO) { 1549 dev_err(host->dev, "Tune response fail!\n"); 1550 return ret; 1551 } 1552 if (host->hs400_mode == false) { 1553 ret = msdc_tune_data(mmc, opcode); 1554 if (ret == -EIO) 1555 dev_err(host->dev, "Tune data fail!\n"); 1556 } 1557 1558 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1559 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1560 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 1561 return ret; 1562 } 1563 1564 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1565 { 1566 struct msdc_host *host = mmc_priv(mmc); 1567 host->hs400_mode = true; 1568 1569 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 1570 return 0; 1571 } 1572 1573 static void msdc_hw_reset(struct mmc_host *mmc) 1574 { 1575 struct msdc_host *host = mmc_priv(mmc); 1576 1577 sdr_set_bits(host->base + EMMC_IOCON, 1); 1578 udelay(10); /* 10us is enough */ 1579 sdr_clr_bits(host->base + EMMC_IOCON, 1); 1580 } 1581 1582 static struct mmc_host_ops mt_msdc_ops = { 1583 .post_req = msdc_post_req, 1584 .pre_req = msdc_pre_req, 1585 .request = msdc_ops_request, 1586 .set_ios = msdc_ops_set_ios, 1587 .get_ro = mmc_gpio_get_ro, 1588 .start_signal_voltage_switch = msdc_ops_switch_volt, 1589 .card_busy = msdc_card_busy, 1590 .execute_tuning = msdc_execute_tuning, 1591 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1592 .hw_reset = msdc_hw_reset, 1593 }; 1594 1595 static void msdc_of_property_parse(struct platform_device *pdev, 1596 struct msdc_host *host) 1597 { 1598 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 1599 &host->hs400_ds_delay); 1600 1601 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 1602 &host->hs200_cmd_int_delay); 1603 1604 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 1605 &host->hs400_cmd_int_delay); 1606 1607 if (of_property_read_bool(pdev->dev.of_node, 1608 "mediatek,hs400-cmd-resp-sel-rising")) 1609 host->hs400_cmd_resp_sel_rising = true; 1610 else 1611 host->hs400_cmd_resp_sel_rising = false; 1612 } 1613 1614 static int msdc_drv_probe(struct platform_device *pdev) 1615 { 1616 struct mmc_host *mmc; 1617 struct msdc_host *host; 1618 struct resource *res; 1619 int ret; 1620 1621 if (!pdev->dev.of_node) { 1622 dev_err(&pdev->dev, "No DT found\n"); 1623 return -EINVAL; 1624 } 1625 /* Allocate MMC host for this device */ 1626 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1627 if (!mmc) 1628 return -ENOMEM; 1629 1630 host = mmc_priv(mmc); 1631 ret = mmc_of_parse(mmc); 1632 if (ret) 1633 goto host_free; 1634 1635 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1636 host->base = devm_ioremap_resource(&pdev->dev, res); 1637 if (IS_ERR(host->base)) { 1638 ret = PTR_ERR(host->base); 1639 goto host_free; 1640 } 1641 1642 ret = mmc_regulator_get_supply(mmc); 1643 if (ret == -EPROBE_DEFER) 1644 goto host_free; 1645 1646 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1647 if (IS_ERR(host->src_clk)) { 1648 ret = PTR_ERR(host->src_clk); 1649 goto host_free; 1650 } 1651 1652 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1653 if (IS_ERR(host->h_clk)) { 1654 ret = PTR_ERR(host->h_clk); 1655 goto host_free; 1656 } 1657 1658 host->irq = platform_get_irq(pdev, 0); 1659 if (host->irq < 0) { 1660 ret = -EINVAL; 1661 goto host_free; 1662 } 1663 1664 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1665 if (IS_ERR(host->pinctrl)) { 1666 ret = PTR_ERR(host->pinctrl); 1667 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1668 goto host_free; 1669 } 1670 1671 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1672 if (IS_ERR(host->pins_default)) { 1673 ret = PTR_ERR(host->pins_default); 1674 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1675 goto host_free; 1676 } 1677 1678 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1679 if (IS_ERR(host->pins_uhs)) { 1680 ret = PTR_ERR(host->pins_uhs); 1681 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1682 goto host_free; 1683 } 1684 1685 msdc_of_property_parse(pdev, host); 1686 1687 host->dev = &pdev->dev; 1688 host->mmc = mmc; 1689 host->src_clk_freq = clk_get_rate(host->src_clk); 1690 /* Set host parameters to mmc */ 1691 mmc->ops = &mt_msdc_ops; 1692 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 1693 1694 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1695 /* MMC core transfer sizes tunable parameters */ 1696 mmc->max_segs = MAX_BD_NUM; 1697 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1698 mmc->max_blk_size = 2048; 1699 mmc->max_req_size = 512 * 1024; 1700 mmc->max_blk_count = mmc->max_req_size / 512; 1701 host->dma_mask = DMA_BIT_MASK(32); 1702 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1703 1704 host->timeout_clks = 3 * 1048576; 1705 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1706 2 * sizeof(struct mt_gpdma_desc), 1707 &host->dma.gpd_addr, GFP_KERNEL); 1708 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1709 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1710 &host->dma.bd_addr, GFP_KERNEL); 1711 if (!host->dma.gpd || !host->dma.bd) { 1712 ret = -ENOMEM; 1713 goto release_mem; 1714 } 1715 msdc_init_gpd_bd(host, &host->dma); 1716 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1717 spin_lock_init(&host->lock); 1718 1719 platform_set_drvdata(pdev, mmc); 1720 msdc_ungate_clock(host); 1721 msdc_init_hw(host); 1722 1723 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1724 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1725 if (ret) 1726 goto release; 1727 1728 pm_runtime_set_active(host->dev); 1729 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1730 pm_runtime_use_autosuspend(host->dev); 1731 pm_runtime_enable(host->dev); 1732 ret = mmc_add_host(mmc); 1733 1734 if (ret) 1735 goto end; 1736 1737 return 0; 1738 end: 1739 pm_runtime_disable(host->dev); 1740 release: 1741 platform_set_drvdata(pdev, NULL); 1742 msdc_deinit_hw(host); 1743 msdc_gate_clock(host); 1744 release_mem: 1745 if (host->dma.gpd) 1746 dma_free_coherent(&pdev->dev, 1747 2 * sizeof(struct mt_gpdma_desc), 1748 host->dma.gpd, host->dma.gpd_addr); 1749 if (host->dma.bd) 1750 dma_free_coherent(&pdev->dev, 1751 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1752 host->dma.bd, host->dma.bd_addr); 1753 host_free: 1754 mmc_free_host(mmc); 1755 1756 return ret; 1757 } 1758 1759 static int msdc_drv_remove(struct platform_device *pdev) 1760 { 1761 struct mmc_host *mmc; 1762 struct msdc_host *host; 1763 1764 mmc = platform_get_drvdata(pdev); 1765 host = mmc_priv(mmc); 1766 1767 pm_runtime_get_sync(host->dev); 1768 1769 platform_set_drvdata(pdev, NULL); 1770 mmc_remove_host(host->mmc); 1771 msdc_deinit_hw(host); 1772 msdc_gate_clock(host); 1773 1774 pm_runtime_disable(host->dev); 1775 pm_runtime_put_noidle(host->dev); 1776 dma_free_coherent(&pdev->dev, 1777 sizeof(struct mt_gpdma_desc), 1778 host->dma.gpd, host->dma.gpd_addr); 1779 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1780 host->dma.bd, host->dma.bd_addr); 1781 1782 mmc_free_host(host->mmc); 1783 1784 return 0; 1785 } 1786 1787 #ifdef CONFIG_PM 1788 static void msdc_save_reg(struct msdc_host *host) 1789 { 1790 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 1791 host->save_para.iocon = readl(host->base + MSDC_IOCON); 1792 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 1793 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1794 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 1795 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 1796 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 1797 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 1798 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 1799 } 1800 1801 static void msdc_restore_reg(struct msdc_host *host) 1802 { 1803 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 1804 writel(host->save_para.iocon, host->base + MSDC_IOCON); 1805 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 1806 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 1807 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 1808 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 1809 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 1810 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 1811 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 1812 } 1813 1814 static int msdc_runtime_suspend(struct device *dev) 1815 { 1816 struct mmc_host *mmc = dev_get_drvdata(dev); 1817 struct msdc_host *host = mmc_priv(mmc); 1818 1819 msdc_save_reg(host); 1820 msdc_gate_clock(host); 1821 return 0; 1822 } 1823 1824 static int msdc_runtime_resume(struct device *dev) 1825 { 1826 struct mmc_host *mmc = dev_get_drvdata(dev); 1827 struct msdc_host *host = mmc_priv(mmc); 1828 1829 msdc_ungate_clock(host); 1830 msdc_restore_reg(host); 1831 return 0; 1832 } 1833 #endif 1834 1835 static const struct dev_pm_ops msdc_dev_pm_ops = { 1836 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1837 pm_runtime_force_resume) 1838 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 1839 }; 1840 1841 static const struct of_device_id msdc_of_ids[] = { 1842 { .compatible = "mediatek,mt8135-mmc", }, 1843 {} 1844 }; 1845 MODULE_DEVICE_TABLE(of, msdc_of_ids); 1846 1847 static struct platform_driver mt_msdc_driver = { 1848 .probe = msdc_drv_probe, 1849 .remove = msdc_drv_remove, 1850 .driver = { 1851 .name = "mtk-msdc", 1852 .of_match_table = msdc_of_ids, 1853 .pm = &msdc_dev_pm_ops, 1854 }, 1855 }; 1856 1857 module_platform_driver(mt_msdc_driver); 1858 MODULE_LICENSE("GPL v2"); 1859 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1860