1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 26 #include <linux/mmc/card.h> 27 #include <linux/mmc/core.h> 28 #include <linux/mmc/host.h> 29 #include <linux/mmc/mmc.h> 30 #include <linux/mmc/sd.h> 31 #include <linux/mmc/sdio.h> 32 #include <linux/mmc/slot-gpio.h> 33 34 #include "cqhci.h" 35 36 #define MAX_BD_NUM 1024 37 38 /*--------------------------------------------------------------------------*/ 39 /* Common Definition */ 40 /*--------------------------------------------------------------------------*/ 41 #define MSDC_BUS_1BITS 0x0 42 #define MSDC_BUS_4BITS 0x1 43 #define MSDC_BUS_8BITS 0x2 44 45 #define MSDC_BURST_64B 0x6 46 47 /*--------------------------------------------------------------------------*/ 48 /* Register Offset */ 49 /*--------------------------------------------------------------------------*/ 50 #define MSDC_CFG 0x0 51 #define MSDC_IOCON 0x04 52 #define MSDC_PS 0x08 53 #define MSDC_INT 0x0c 54 #define MSDC_INTEN 0x10 55 #define MSDC_FIFOCS 0x14 56 #define SDC_CFG 0x30 57 #define SDC_CMD 0x34 58 #define SDC_ARG 0x38 59 #define SDC_STS 0x3c 60 #define SDC_RESP0 0x40 61 #define SDC_RESP1 0x44 62 #define SDC_RESP2 0x48 63 #define SDC_RESP3 0x4c 64 #define SDC_BLK_NUM 0x50 65 #define SDC_ADV_CFG0 0x64 66 #define EMMC_IOCON 0x7c 67 #define SDC_ACMD_RESP 0x80 68 #define DMA_SA_H4BIT 0x8c 69 #define MSDC_DMA_SA 0x90 70 #define MSDC_DMA_CTRL 0x98 71 #define MSDC_DMA_CFG 0x9c 72 #define MSDC_PATCH_BIT 0xb0 73 #define MSDC_PATCH_BIT1 0xb4 74 #define MSDC_PATCH_BIT2 0xb8 75 #define MSDC_PAD_TUNE 0xec 76 #define MSDC_PAD_TUNE0 0xf0 77 #define PAD_DS_TUNE 0x188 78 #define PAD_CMD_TUNE 0x18c 79 #define EMMC50_CFG0 0x208 80 #define EMMC50_CFG3 0x220 81 #define SDC_FIFO_CFG 0x228 82 83 /*--------------------------------------------------------------------------*/ 84 /* Top Pad Register Offset */ 85 /*--------------------------------------------------------------------------*/ 86 #define EMMC_TOP_CONTROL 0x00 87 #define EMMC_TOP_CMD 0x04 88 #define EMMC50_PAD_DS_TUNE 0x0c 89 90 /*--------------------------------------------------------------------------*/ 91 /* Register Mask */ 92 /*--------------------------------------------------------------------------*/ 93 94 /* MSDC_CFG mask */ 95 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 96 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 97 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 98 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 99 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 100 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 101 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 102 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 103 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 104 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 105 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 106 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 107 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 108 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 109 110 /* MSDC_IOCON mask */ 111 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 112 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 113 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 114 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 115 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 116 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 117 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 118 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 119 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 120 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 121 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 122 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 123 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 124 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 125 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 126 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 127 128 /* MSDC_PS mask */ 129 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 130 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 131 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 132 #define MSDC_PS_DAT (0xff << 16) /* R */ 133 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 134 #define MSDC_PS_CMD (0x1 << 24) /* R */ 135 #define MSDC_PS_WP (0x1 << 31) /* R */ 136 137 /* MSDC_INT mask */ 138 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 139 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 140 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 141 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 142 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 143 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 144 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 145 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 146 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 147 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 148 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 149 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 150 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 151 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 152 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 153 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 154 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 155 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 156 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 157 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 158 159 /* MSDC_INTEN mask */ 160 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 161 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 162 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 163 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 164 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 165 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 166 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 167 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 168 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 169 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 170 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 171 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 172 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 173 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 174 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 175 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 176 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 177 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 178 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 179 180 /* MSDC_FIFOCS mask */ 181 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 182 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 183 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 184 185 /* SDC_CFG mask */ 186 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 187 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 188 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 189 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 190 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 191 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 192 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 193 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 194 195 /* SDC_STS mask */ 196 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 197 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 198 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 199 200 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 201 /* SDC_ADV_CFG0 mask */ 202 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 203 204 /* DMA_SA_H4BIT mask */ 205 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 206 207 /* MSDC_DMA_CTRL mask */ 208 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 209 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 210 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 211 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 212 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 213 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 214 215 /* MSDC_DMA_CFG mask */ 216 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 217 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 218 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 219 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 220 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 221 222 /* MSDC_PATCH_BIT mask */ 223 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 224 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 225 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 226 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 227 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 228 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 229 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 230 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 231 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 232 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 233 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 234 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 235 236 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 237 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 238 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 239 240 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 241 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 242 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 243 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 244 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 245 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 246 247 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 248 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 249 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 250 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 251 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 252 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 253 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 254 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 255 256 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 257 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 258 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 259 260 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 261 262 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 263 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 264 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 265 266 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 267 268 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 269 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 270 271 /* EMMC_TOP_CONTROL mask */ 272 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 273 #define DELAY_EN (0x1 << 1) /* RW */ 274 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 275 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 276 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 277 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 278 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 279 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 280 281 /* EMMC_TOP_CMD mask */ 282 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 283 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 284 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 285 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 286 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 287 288 #define REQ_CMD_EIO (0x1 << 0) 289 #define REQ_CMD_TMO (0x1 << 1) 290 #define REQ_DAT_ERR (0x1 << 2) 291 #define REQ_STOP_EIO (0x1 << 3) 292 #define REQ_STOP_TMO (0x1 << 4) 293 #define REQ_CMD_BUSY (0x1 << 5) 294 295 #define MSDC_PREPARE_FLAG (0x1 << 0) 296 #define MSDC_ASYNC_FLAG (0x1 << 1) 297 #define MSDC_MMAP_FLAG (0x1 << 2) 298 299 #define MTK_MMC_AUTOSUSPEND_DELAY 50 300 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 301 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 302 303 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 304 305 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 306 /*--------------------------------------------------------------------------*/ 307 /* Descriptor Structure */ 308 /*--------------------------------------------------------------------------*/ 309 struct mt_gpdma_desc { 310 u32 gpd_info; 311 #define GPDMA_DESC_HWO (0x1 << 0) 312 #define GPDMA_DESC_BDP (0x1 << 1) 313 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 314 #define GPDMA_DESC_INT (0x1 << 16) 315 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 316 #define GPDMA_DESC_PTR_H4 (0xf << 28) 317 u32 next; 318 u32 ptr; 319 u32 gpd_data_len; 320 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 321 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 322 u32 arg; 323 u32 blknum; 324 u32 cmd; 325 }; 326 327 struct mt_bdma_desc { 328 u32 bd_info; 329 #define BDMA_DESC_EOL (0x1 << 0) 330 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 331 #define BDMA_DESC_BLKPAD (0x1 << 17) 332 #define BDMA_DESC_DWPAD (0x1 << 18) 333 #define BDMA_DESC_NEXT_H4 (0xf << 24) 334 #define BDMA_DESC_PTR_H4 (0xf << 28) 335 u32 next; 336 u32 ptr; 337 u32 bd_data_len; 338 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 339 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 340 }; 341 342 struct msdc_dma { 343 struct scatterlist *sg; /* I/O scatter list */ 344 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 345 struct mt_bdma_desc *bd; /* pointer to bd array */ 346 dma_addr_t gpd_addr; /* the physical address of gpd array */ 347 dma_addr_t bd_addr; /* the physical address of bd array */ 348 }; 349 350 struct msdc_save_para { 351 u32 msdc_cfg; 352 u32 iocon; 353 u32 sdc_cfg; 354 u32 pad_tune; 355 u32 patch_bit0; 356 u32 patch_bit1; 357 u32 patch_bit2; 358 u32 pad_ds_tune; 359 u32 pad_cmd_tune; 360 u32 emmc50_cfg0; 361 u32 emmc50_cfg3; 362 u32 sdc_fifo_cfg; 363 u32 emmc_top_control; 364 u32 emmc_top_cmd; 365 u32 emmc50_pad_ds_tune; 366 }; 367 368 struct mtk_mmc_compatible { 369 u8 clk_div_bits; 370 bool recheck_sdio_irq; 371 bool hs400_tune; /* only used for MT8173 */ 372 u32 pad_tune_reg; 373 bool async_fifo; 374 bool data_tune; 375 bool busy_check; 376 bool stop_clk_fix; 377 bool enhance_rx; 378 bool support_64g; 379 bool use_internal_cd; 380 }; 381 382 struct msdc_tune_para { 383 u32 iocon; 384 u32 pad_tune; 385 u32 pad_cmd_tune; 386 u32 emmc_top_control; 387 u32 emmc_top_cmd; 388 }; 389 390 struct msdc_delay_phase { 391 u8 maxlen; 392 u8 start; 393 u8 final_phase; 394 }; 395 396 struct msdc_host { 397 struct device *dev; 398 const struct mtk_mmc_compatible *dev_comp; 399 struct mmc_host *mmc; /* mmc structure */ 400 int cmd_rsp; 401 402 spinlock_t lock; 403 struct mmc_request *mrq; 404 struct mmc_command *cmd; 405 struct mmc_data *data; 406 int error; 407 408 void __iomem *base; /* host base address */ 409 void __iomem *top_base; /* host top register base address */ 410 411 struct msdc_dma dma; /* dma channel */ 412 u64 dma_mask; 413 414 u32 timeout_ns; /* data timeout ns */ 415 u32 timeout_clks; /* data timeout clks */ 416 417 struct pinctrl *pinctrl; 418 struct pinctrl_state *pins_default; 419 struct pinctrl_state *pins_uhs; 420 struct delayed_work req_timeout; 421 int irq; /* host interrupt */ 422 423 struct clk *src_clk; /* msdc source clock */ 424 struct clk *h_clk; /* msdc h_clk */ 425 struct clk *bus_clk; /* bus clock which used to access register */ 426 struct clk *src_clk_cg; /* msdc source clock control gate */ 427 u32 mclk; /* mmc subsystem clock frequency */ 428 u32 src_clk_freq; /* source clock frequency */ 429 unsigned char timing; 430 bool vqmmc_enabled; 431 u32 latch_ck; 432 u32 hs400_ds_delay; 433 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 434 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 435 bool hs400_cmd_resp_sel_rising; 436 /* cmd response sample selection for HS400 */ 437 bool hs400_mode; /* current eMMC will run at hs400 mode */ 438 bool internal_cd; /* Use internal card-detect logic */ 439 bool cqhci; /* support eMMC hw cmdq */ 440 struct msdc_save_para save_para; /* used when gate HCLK */ 441 struct msdc_tune_para def_tune_para; /* default tune setting */ 442 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 443 struct cqhci_host *cq_host; 444 }; 445 446 static const struct mtk_mmc_compatible mt8135_compat = { 447 .clk_div_bits = 8, 448 .recheck_sdio_irq = false, 449 .hs400_tune = false, 450 .pad_tune_reg = MSDC_PAD_TUNE, 451 .async_fifo = false, 452 .data_tune = false, 453 .busy_check = false, 454 .stop_clk_fix = false, 455 .enhance_rx = false, 456 .support_64g = false, 457 }; 458 459 static const struct mtk_mmc_compatible mt8173_compat = { 460 .clk_div_bits = 8, 461 .recheck_sdio_irq = true, 462 .hs400_tune = true, 463 .pad_tune_reg = MSDC_PAD_TUNE, 464 .async_fifo = false, 465 .data_tune = false, 466 .busy_check = false, 467 .stop_clk_fix = false, 468 .enhance_rx = false, 469 .support_64g = false, 470 }; 471 472 static const struct mtk_mmc_compatible mt8183_compat = { 473 .clk_div_bits = 12, 474 .recheck_sdio_irq = false, 475 .hs400_tune = false, 476 .pad_tune_reg = MSDC_PAD_TUNE0, 477 .async_fifo = true, 478 .data_tune = true, 479 .busy_check = true, 480 .stop_clk_fix = true, 481 .enhance_rx = true, 482 .support_64g = true, 483 }; 484 485 static const struct mtk_mmc_compatible mt2701_compat = { 486 .clk_div_bits = 12, 487 .recheck_sdio_irq = false, 488 .hs400_tune = false, 489 .pad_tune_reg = MSDC_PAD_TUNE0, 490 .async_fifo = true, 491 .data_tune = true, 492 .busy_check = false, 493 .stop_clk_fix = false, 494 .enhance_rx = false, 495 .support_64g = false, 496 }; 497 498 static const struct mtk_mmc_compatible mt2712_compat = { 499 .clk_div_bits = 12, 500 .recheck_sdio_irq = false, 501 .hs400_tune = false, 502 .pad_tune_reg = MSDC_PAD_TUNE0, 503 .async_fifo = true, 504 .data_tune = true, 505 .busy_check = true, 506 .stop_clk_fix = true, 507 .enhance_rx = true, 508 .support_64g = true, 509 }; 510 511 static const struct mtk_mmc_compatible mt7622_compat = { 512 .clk_div_bits = 12, 513 .recheck_sdio_irq = false, 514 .hs400_tune = false, 515 .pad_tune_reg = MSDC_PAD_TUNE0, 516 .async_fifo = true, 517 .data_tune = true, 518 .busy_check = true, 519 .stop_clk_fix = true, 520 .enhance_rx = true, 521 .support_64g = false, 522 }; 523 524 static const struct mtk_mmc_compatible mt8516_compat = { 525 .clk_div_bits = 12, 526 .recheck_sdio_irq = false, 527 .hs400_tune = false, 528 .pad_tune_reg = MSDC_PAD_TUNE0, 529 .async_fifo = true, 530 .data_tune = true, 531 .busy_check = true, 532 .stop_clk_fix = true, 533 }; 534 535 static const struct mtk_mmc_compatible mt7620_compat = { 536 .clk_div_bits = 8, 537 .recheck_sdio_irq = false, 538 .hs400_tune = false, 539 .pad_tune_reg = MSDC_PAD_TUNE, 540 .async_fifo = false, 541 .data_tune = false, 542 .busy_check = false, 543 .stop_clk_fix = false, 544 .enhance_rx = false, 545 .use_internal_cd = true, 546 }; 547 548 static const struct mtk_mmc_compatible mt6779_compat = { 549 .clk_div_bits = 12, 550 .hs400_tune = false, 551 .pad_tune_reg = MSDC_PAD_TUNE0, 552 .async_fifo = true, 553 .data_tune = true, 554 .busy_check = true, 555 .stop_clk_fix = true, 556 .enhance_rx = true, 557 .support_64g = true, 558 }; 559 560 static const struct of_device_id msdc_of_ids[] = { 561 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 562 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 563 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 564 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 565 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 566 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 567 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 568 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 569 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 570 {} 571 }; 572 MODULE_DEVICE_TABLE(of, msdc_of_ids); 573 574 static void sdr_set_bits(void __iomem *reg, u32 bs) 575 { 576 u32 val = readl(reg); 577 578 val |= bs; 579 writel(val, reg); 580 } 581 582 static void sdr_clr_bits(void __iomem *reg, u32 bs) 583 { 584 u32 val = readl(reg); 585 586 val &= ~bs; 587 writel(val, reg); 588 } 589 590 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 591 { 592 unsigned int tv = readl(reg); 593 594 tv &= ~field; 595 tv |= ((val) << (ffs((unsigned int)field) - 1)); 596 writel(tv, reg); 597 } 598 599 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 600 { 601 unsigned int tv = readl(reg); 602 603 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 604 } 605 606 static void msdc_reset_hw(struct msdc_host *host) 607 { 608 u32 val; 609 610 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 611 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 612 cpu_relax(); 613 614 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 615 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 616 cpu_relax(); 617 618 val = readl(host->base + MSDC_INT); 619 writel(val, host->base + MSDC_INT); 620 } 621 622 static void msdc_cmd_next(struct msdc_host *host, 623 struct mmc_request *mrq, struct mmc_command *cmd); 624 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 625 626 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 627 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 628 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 629 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 630 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 631 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 632 633 static u8 msdc_dma_calcs(u8 *buf, u32 len) 634 { 635 u32 i, sum = 0; 636 637 for (i = 0; i < len; i++) 638 sum += buf[i]; 639 return 0xff - (u8) sum; 640 } 641 642 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 643 struct mmc_data *data) 644 { 645 unsigned int j, dma_len; 646 dma_addr_t dma_address; 647 u32 dma_ctrl; 648 struct scatterlist *sg; 649 struct mt_gpdma_desc *gpd; 650 struct mt_bdma_desc *bd; 651 652 sg = data->sg; 653 654 gpd = dma->gpd; 655 bd = dma->bd; 656 657 /* modify gpd */ 658 gpd->gpd_info |= GPDMA_DESC_HWO; 659 gpd->gpd_info |= GPDMA_DESC_BDP; 660 /* need to clear first. use these bits to calc checksum */ 661 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 662 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 663 664 /* modify bd */ 665 for_each_sg(data->sg, sg, data->sg_count, j) { 666 dma_address = sg_dma_address(sg); 667 dma_len = sg_dma_len(sg); 668 669 /* init bd */ 670 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 671 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 672 bd[j].ptr = lower_32_bits(dma_address); 673 if (host->dev_comp->support_64g) { 674 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 675 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 676 << 28; 677 } 678 679 if (host->dev_comp->support_64g) { 680 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 681 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 682 } else { 683 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 684 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 685 } 686 687 if (j == data->sg_count - 1) /* the last bd */ 688 bd[j].bd_info |= BDMA_DESC_EOL; 689 else 690 bd[j].bd_info &= ~BDMA_DESC_EOL; 691 692 /* checksume need to clear first */ 693 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 694 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 695 } 696 697 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 698 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 699 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 700 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 701 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 702 if (host->dev_comp->support_64g) 703 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 704 upper_32_bits(dma->gpd_addr) & 0xf); 705 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 706 } 707 708 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 709 { 710 struct mmc_data *data = mrq->data; 711 712 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 713 data->host_cookie |= MSDC_PREPARE_FLAG; 714 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 715 mmc_get_dma_dir(data)); 716 } 717 } 718 719 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 720 { 721 struct mmc_data *data = mrq->data; 722 723 if (data->host_cookie & MSDC_ASYNC_FLAG) 724 return; 725 726 if (data->host_cookie & MSDC_PREPARE_FLAG) { 727 dma_unmap_sg(host->dev, data->sg, data->sg_len, 728 mmc_get_dma_dir(data)); 729 data->host_cookie &= ~MSDC_PREPARE_FLAG; 730 } 731 } 732 733 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 734 { 735 u64 timeout, clk_ns; 736 u32 mode = 0; 737 738 if (host->mmc->actual_clock == 0) { 739 timeout = 0; 740 } else { 741 clk_ns = 1000000000ULL; 742 do_div(clk_ns, host->mmc->actual_clock); 743 timeout = ns + clk_ns - 1; 744 do_div(timeout, clk_ns); 745 timeout += clks; 746 /* in 1048576 sclk cycle unit */ 747 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 748 if (host->dev_comp->clk_div_bits == 8) 749 sdr_get_field(host->base + MSDC_CFG, 750 MSDC_CFG_CKMOD, &mode); 751 else 752 sdr_get_field(host->base + MSDC_CFG, 753 MSDC_CFG_CKMOD_EXTRA, &mode); 754 /*DDR mode will double the clk cycles for data timeout */ 755 timeout = mode >= 2 ? timeout * 2 : timeout; 756 timeout = timeout > 1 ? timeout - 1 : 0; 757 } 758 return timeout; 759 } 760 761 /* clock control primitives */ 762 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 763 { 764 u64 timeout; 765 766 host->timeout_ns = ns; 767 host->timeout_clks = clks; 768 769 timeout = msdc_timeout_cal(host, ns, clks); 770 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 771 (u32)(timeout > 255 ? 255 : timeout)); 772 } 773 774 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 775 { 776 u64 timeout; 777 778 timeout = msdc_timeout_cal(host, ns, clks); 779 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 780 (u32)(timeout > 8191 ? 8191 : timeout)); 781 } 782 783 static void msdc_gate_clock(struct msdc_host *host) 784 { 785 clk_disable_unprepare(host->src_clk_cg); 786 clk_disable_unprepare(host->src_clk); 787 clk_disable_unprepare(host->bus_clk); 788 clk_disable_unprepare(host->h_clk); 789 } 790 791 static void msdc_ungate_clock(struct msdc_host *host) 792 { 793 clk_prepare_enable(host->h_clk); 794 clk_prepare_enable(host->bus_clk); 795 clk_prepare_enable(host->src_clk); 796 clk_prepare_enable(host->src_clk_cg); 797 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 798 cpu_relax(); 799 } 800 801 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 802 { 803 u32 mode; 804 u32 flags; 805 u32 div; 806 u32 sclk; 807 u32 tune_reg = host->dev_comp->pad_tune_reg; 808 809 if (!hz) { 810 dev_dbg(host->dev, "set mclk to 0\n"); 811 host->mclk = 0; 812 host->mmc->actual_clock = 0; 813 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 814 return; 815 } 816 817 flags = readl(host->base + MSDC_INTEN); 818 sdr_clr_bits(host->base + MSDC_INTEN, flags); 819 if (host->dev_comp->clk_div_bits == 8) 820 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 821 else 822 sdr_clr_bits(host->base + MSDC_CFG, 823 MSDC_CFG_HS400_CK_MODE_EXTRA); 824 if (timing == MMC_TIMING_UHS_DDR50 || 825 timing == MMC_TIMING_MMC_DDR52 || 826 timing == MMC_TIMING_MMC_HS400) { 827 if (timing == MMC_TIMING_MMC_HS400) 828 mode = 0x3; 829 else 830 mode = 0x2; /* ddr mode and use divisor */ 831 832 if (hz >= (host->src_clk_freq >> 2)) { 833 div = 0; /* mean div = 1/4 */ 834 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 835 } else { 836 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 837 sclk = (host->src_clk_freq >> 2) / div; 838 div = (div >> 1); 839 } 840 841 if (timing == MMC_TIMING_MMC_HS400 && 842 hz >= (host->src_clk_freq >> 1)) { 843 if (host->dev_comp->clk_div_bits == 8) 844 sdr_set_bits(host->base + MSDC_CFG, 845 MSDC_CFG_HS400_CK_MODE); 846 else 847 sdr_set_bits(host->base + MSDC_CFG, 848 MSDC_CFG_HS400_CK_MODE_EXTRA); 849 sclk = host->src_clk_freq >> 1; 850 div = 0; /* div is ignore when bit18 is set */ 851 } 852 } else if (hz >= host->src_clk_freq) { 853 mode = 0x1; /* no divisor */ 854 div = 0; 855 sclk = host->src_clk_freq; 856 } else { 857 mode = 0x0; /* use divisor */ 858 if (hz >= (host->src_clk_freq >> 1)) { 859 div = 0; /* mean div = 1/2 */ 860 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 861 } else { 862 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 863 sclk = (host->src_clk_freq >> 2) / div; 864 } 865 } 866 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 867 /* 868 * As src_clk/HCLK use the same bit to gate/ungate, 869 * So if want to only gate src_clk, need gate its parent(mux). 870 */ 871 if (host->src_clk_cg) 872 clk_disable_unprepare(host->src_clk_cg); 873 else 874 clk_disable_unprepare(clk_get_parent(host->src_clk)); 875 if (host->dev_comp->clk_div_bits == 8) 876 sdr_set_field(host->base + MSDC_CFG, 877 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 878 (mode << 8) | div); 879 else 880 sdr_set_field(host->base + MSDC_CFG, 881 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 882 (mode << 12) | div); 883 if (host->src_clk_cg) 884 clk_prepare_enable(host->src_clk_cg); 885 else 886 clk_prepare_enable(clk_get_parent(host->src_clk)); 887 888 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 889 cpu_relax(); 890 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 891 host->mmc->actual_clock = sclk; 892 host->mclk = hz; 893 host->timing = timing; 894 /* need because clk changed. */ 895 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 896 sdr_set_bits(host->base + MSDC_INTEN, flags); 897 898 /* 899 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 900 * tune result of hs200/200Mhz is not suitable for 50Mhz 901 */ 902 if (host->mmc->actual_clock <= 52000000) { 903 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 904 if (host->top_base) { 905 writel(host->def_tune_para.emmc_top_control, 906 host->top_base + EMMC_TOP_CONTROL); 907 writel(host->def_tune_para.emmc_top_cmd, 908 host->top_base + EMMC_TOP_CMD); 909 } else { 910 writel(host->def_tune_para.pad_tune, 911 host->base + tune_reg); 912 } 913 } else { 914 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 915 writel(host->saved_tune_para.pad_cmd_tune, 916 host->base + PAD_CMD_TUNE); 917 if (host->top_base) { 918 writel(host->saved_tune_para.emmc_top_control, 919 host->top_base + EMMC_TOP_CONTROL); 920 writel(host->saved_tune_para.emmc_top_cmd, 921 host->top_base + EMMC_TOP_CMD); 922 } else { 923 writel(host->saved_tune_para.pad_tune, 924 host->base + tune_reg); 925 } 926 } 927 928 if (timing == MMC_TIMING_MMC_HS400 && 929 host->dev_comp->hs400_tune) 930 sdr_set_field(host->base + tune_reg, 931 MSDC_PAD_TUNE_CMDRRDLY, 932 host->hs400_cmd_int_delay); 933 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->mmc->actual_clock, 934 timing); 935 } 936 937 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 938 struct mmc_request *mrq, struct mmc_command *cmd) 939 { 940 u32 resp; 941 942 switch (mmc_resp_type(cmd)) { 943 /* Actually, R1, R5, R6, R7 are the same */ 944 case MMC_RSP_R1: 945 resp = 0x1; 946 break; 947 case MMC_RSP_R1B: 948 resp = 0x7; 949 break; 950 case MMC_RSP_R2: 951 resp = 0x2; 952 break; 953 case MMC_RSP_R3: 954 resp = 0x3; 955 break; 956 case MMC_RSP_NONE: 957 default: 958 resp = 0x0; 959 break; 960 } 961 962 return resp; 963 } 964 965 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 966 struct mmc_request *mrq, struct mmc_command *cmd) 967 { 968 /* rawcmd : 969 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 970 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 971 */ 972 u32 opcode = cmd->opcode; 973 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 974 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 975 976 host->cmd_rsp = resp; 977 978 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 979 opcode == MMC_STOP_TRANSMISSION) 980 rawcmd |= (0x1 << 14); 981 else if (opcode == SD_SWITCH_VOLTAGE) 982 rawcmd |= (0x1 << 30); 983 else if (opcode == SD_APP_SEND_SCR || 984 opcode == SD_APP_SEND_NUM_WR_BLKS || 985 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 986 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 987 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 988 rawcmd |= (0x1 << 11); 989 990 if (cmd->data) { 991 struct mmc_data *data = cmd->data; 992 993 if (mmc_op_multi(opcode)) { 994 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 995 !(mrq->sbc->arg & 0xFFFF0000)) 996 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 997 } 998 999 rawcmd |= ((data->blksz & 0xFFF) << 16); 1000 if (data->flags & MMC_DATA_WRITE) 1001 rawcmd |= (0x1 << 13); 1002 if (data->blocks > 1) 1003 rawcmd |= (0x2 << 11); 1004 else 1005 rawcmd |= (0x1 << 11); 1006 /* Always use dma mode */ 1007 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1008 1009 if (host->timeout_ns != data->timeout_ns || 1010 host->timeout_clks != data->timeout_clks) 1011 msdc_set_timeout(host, data->timeout_ns, 1012 data->timeout_clks); 1013 1014 writel(data->blocks, host->base + SDC_BLK_NUM); 1015 } 1016 return rawcmd; 1017 } 1018 1019 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1020 struct mmc_command *cmd, struct mmc_data *data) 1021 { 1022 bool read; 1023 1024 WARN_ON(host->data); 1025 host->data = data; 1026 read = data->flags & MMC_DATA_READ; 1027 1028 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1029 msdc_dma_setup(host, &host->dma, data); 1030 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1031 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1032 dev_dbg(host->dev, "DMA start\n"); 1033 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1034 __func__, cmd->opcode, data->blocks, read); 1035 } 1036 1037 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1038 struct mmc_command *cmd) 1039 { 1040 u32 *rsp = cmd->resp; 1041 1042 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1043 1044 if (events & MSDC_INT_ACMDRDY) { 1045 cmd->error = 0; 1046 } else { 1047 msdc_reset_hw(host); 1048 if (events & MSDC_INT_ACMDCRCERR) { 1049 cmd->error = -EILSEQ; 1050 host->error |= REQ_STOP_EIO; 1051 } else if (events & MSDC_INT_ACMDTMO) { 1052 cmd->error = -ETIMEDOUT; 1053 host->error |= REQ_STOP_TMO; 1054 } 1055 dev_err(host->dev, 1056 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1057 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1058 } 1059 return cmd->error; 1060 } 1061 1062 /* 1063 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1064 * 1065 * Host controller may lost interrupt in some special case. 1066 * Add SDIO irq recheck mechanism to make sure all interrupts 1067 * can be processed immediately 1068 */ 1069 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1070 { 1071 u32 reg_int, reg_inten, reg_ps; 1072 1073 if (host->mmc->caps & MMC_CAP_SDIO_IRQ) { 1074 reg_inten = readl(host->base + MSDC_INTEN); 1075 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1076 reg_int = readl(host->base + MSDC_INT); 1077 reg_ps = readl(host->base + MSDC_PS); 1078 if (!(reg_int & MSDC_INT_SDIOIRQ || 1079 reg_ps & MSDC_PS_DATA1)) { 1080 __msdc_enable_sdio_irq(host, 0); 1081 sdio_signal_irq(host->mmc); 1082 } 1083 } 1084 } 1085 } 1086 1087 static void msdc_track_cmd_data(struct msdc_host *host, 1088 struct mmc_command *cmd, struct mmc_data *data) 1089 { 1090 if (host->error) 1091 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1092 __func__, cmd->opcode, cmd->arg, host->error); 1093 } 1094 1095 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1096 { 1097 unsigned long flags; 1098 bool ret; 1099 1100 ret = cancel_delayed_work(&host->req_timeout); 1101 if (!ret) { 1102 /* delay work already running */ 1103 return; 1104 } 1105 spin_lock_irqsave(&host->lock, flags); 1106 host->mrq = NULL; 1107 spin_unlock_irqrestore(&host->lock, flags); 1108 1109 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1110 if (mrq->data) 1111 msdc_unprepare_data(host, mrq); 1112 if (host->error) 1113 msdc_reset_hw(host); 1114 mmc_request_done(host->mmc, mrq); 1115 if (host->dev_comp->recheck_sdio_irq) 1116 msdc_recheck_sdio_irq(host); 1117 } 1118 1119 /* returns true if command is fully handled; returns false otherwise */ 1120 static bool msdc_cmd_done(struct msdc_host *host, int events, 1121 struct mmc_request *mrq, struct mmc_command *cmd) 1122 { 1123 bool done = false; 1124 bool sbc_error; 1125 unsigned long flags; 1126 u32 *rsp = cmd->resp; 1127 1128 if (mrq->sbc && cmd == mrq->cmd && 1129 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1130 | MSDC_INT_ACMDTMO))) 1131 msdc_auto_cmd_done(host, events, mrq->sbc); 1132 1133 sbc_error = mrq->sbc && mrq->sbc->error; 1134 1135 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1136 | MSDC_INT_RSPCRCERR 1137 | MSDC_INT_CMDTMO))) 1138 return done; 1139 1140 spin_lock_irqsave(&host->lock, flags); 1141 done = !host->cmd; 1142 host->cmd = NULL; 1143 spin_unlock_irqrestore(&host->lock, flags); 1144 1145 if (done) 1146 return true; 1147 1148 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1149 1150 if (cmd->flags & MMC_RSP_PRESENT) { 1151 if (cmd->flags & MMC_RSP_136) { 1152 rsp[0] = readl(host->base + SDC_RESP3); 1153 rsp[1] = readl(host->base + SDC_RESP2); 1154 rsp[2] = readl(host->base + SDC_RESP1); 1155 rsp[3] = readl(host->base + SDC_RESP0); 1156 } else { 1157 rsp[0] = readl(host->base + SDC_RESP0); 1158 } 1159 } 1160 1161 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1162 if (events & MSDC_INT_CMDTMO || 1163 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1164 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1165 /* 1166 * should not clear fifo/interrupt as the tune data 1167 * may have alreay come when cmd19/cmd21 gets response 1168 * CRC error. 1169 */ 1170 msdc_reset_hw(host); 1171 if (events & MSDC_INT_RSPCRCERR) { 1172 cmd->error = -EILSEQ; 1173 host->error |= REQ_CMD_EIO; 1174 } else if (events & MSDC_INT_CMDTMO) { 1175 cmd->error = -ETIMEDOUT; 1176 host->error |= REQ_CMD_TMO; 1177 } 1178 } 1179 if (cmd->error) 1180 dev_dbg(host->dev, 1181 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1182 __func__, cmd->opcode, cmd->arg, rsp[0], 1183 cmd->error); 1184 1185 msdc_cmd_next(host, mrq, cmd); 1186 return true; 1187 } 1188 1189 /* It is the core layer's responsibility to ensure card status 1190 * is correct before issue a request. but host design do below 1191 * checks recommended. 1192 */ 1193 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1194 struct mmc_request *mrq, struct mmc_command *cmd) 1195 { 1196 /* The max busy time we can endure is 20ms */ 1197 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1198 1199 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1200 time_before(jiffies, tmo)) 1201 cpu_relax(); 1202 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1203 dev_err(host->dev, "CMD bus busy detected\n"); 1204 host->error |= REQ_CMD_BUSY; 1205 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1206 return false; 1207 } 1208 1209 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1210 tmo = jiffies + msecs_to_jiffies(20); 1211 /* R1B or with data, should check SDCBUSY */ 1212 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1213 time_before(jiffies, tmo)) 1214 cpu_relax(); 1215 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1216 dev_err(host->dev, "Controller busy detected\n"); 1217 host->error |= REQ_CMD_BUSY; 1218 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1219 return false; 1220 } 1221 } 1222 return true; 1223 } 1224 1225 static void msdc_start_command(struct msdc_host *host, 1226 struct mmc_request *mrq, struct mmc_command *cmd) 1227 { 1228 u32 rawcmd; 1229 unsigned long flags; 1230 1231 WARN_ON(host->cmd); 1232 host->cmd = cmd; 1233 1234 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1235 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1236 return; 1237 1238 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1239 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1240 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1241 msdc_reset_hw(host); 1242 } 1243 1244 cmd->error = 0; 1245 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1246 1247 spin_lock_irqsave(&host->lock, flags); 1248 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1249 spin_unlock_irqrestore(&host->lock, flags); 1250 1251 writel(cmd->arg, host->base + SDC_ARG); 1252 writel(rawcmd, host->base + SDC_CMD); 1253 } 1254 1255 static void msdc_cmd_next(struct msdc_host *host, 1256 struct mmc_request *mrq, struct mmc_command *cmd) 1257 { 1258 if ((cmd->error && 1259 !(cmd->error == -EILSEQ && 1260 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1261 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1262 (mrq->sbc && mrq->sbc->error)) 1263 msdc_request_done(host, mrq); 1264 else if (cmd == mrq->sbc) 1265 msdc_start_command(host, mrq, mrq->cmd); 1266 else if (!cmd->data) 1267 msdc_request_done(host, mrq); 1268 else 1269 msdc_start_data(host, mrq, cmd, cmd->data); 1270 } 1271 1272 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1273 { 1274 struct msdc_host *host = mmc_priv(mmc); 1275 1276 host->error = 0; 1277 WARN_ON(host->mrq); 1278 host->mrq = mrq; 1279 1280 if (mrq->data) 1281 msdc_prepare_data(host, mrq); 1282 1283 /* if SBC is required, we have HW option and SW option. 1284 * if HW option is enabled, and SBC does not have "special" flags, 1285 * use HW option, otherwise use SW option 1286 */ 1287 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1288 (mrq->sbc->arg & 0xFFFF0000))) 1289 msdc_start_command(host, mrq, mrq->sbc); 1290 else 1291 msdc_start_command(host, mrq, mrq->cmd); 1292 } 1293 1294 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1295 { 1296 struct msdc_host *host = mmc_priv(mmc); 1297 struct mmc_data *data = mrq->data; 1298 1299 if (!data) 1300 return; 1301 1302 msdc_prepare_data(host, mrq); 1303 data->host_cookie |= MSDC_ASYNC_FLAG; 1304 } 1305 1306 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1307 int err) 1308 { 1309 struct msdc_host *host = mmc_priv(mmc); 1310 struct mmc_data *data; 1311 1312 data = mrq->data; 1313 if (!data) 1314 return; 1315 if (data->host_cookie) { 1316 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1317 msdc_unprepare_data(host, mrq); 1318 } 1319 } 1320 1321 static void msdc_data_xfer_next(struct msdc_host *host, 1322 struct mmc_request *mrq, struct mmc_data *data) 1323 { 1324 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1325 !mrq->sbc) 1326 msdc_start_command(host, mrq, mrq->stop); 1327 else 1328 msdc_request_done(host, mrq); 1329 } 1330 1331 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1332 struct mmc_request *mrq, struct mmc_data *data) 1333 { 1334 struct mmc_command *stop = data->stop; 1335 unsigned long flags; 1336 bool done; 1337 unsigned int check_data = events & 1338 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1339 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1340 | MSDC_INT_DMA_PROTECT); 1341 1342 spin_lock_irqsave(&host->lock, flags); 1343 done = !host->data; 1344 if (check_data) 1345 host->data = NULL; 1346 spin_unlock_irqrestore(&host->lock, flags); 1347 1348 if (done) 1349 return true; 1350 1351 if (check_data || (stop && stop->error)) { 1352 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1353 readl(host->base + MSDC_DMA_CFG)); 1354 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1355 1); 1356 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1357 cpu_relax(); 1358 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1359 dev_dbg(host->dev, "DMA stop\n"); 1360 1361 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1362 data->bytes_xfered = data->blocks * data->blksz; 1363 } else { 1364 dev_dbg(host->dev, "interrupt events: %x\n", events); 1365 msdc_reset_hw(host); 1366 host->error |= REQ_DAT_ERR; 1367 data->bytes_xfered = 0; 1368 1369 if (events & MSDC_INT_DATTMO) 1370 data->error = -ETIMEDOUT; 1371 else if (events & MSDC_INT_DATCRCERR) 1372 data->error = -EILSEQ; 1373 1374 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1375 __func__, mrq->cmd->opcode, data->blocks); 1376 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1377 (int)data->error, data->bytes_xfered); 1378 } 1379 1380 msdc_data_xfer_next(host, mrq, data); 1381 done = true; 1382 } 1383 return done; 1384 } 1385 1386 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1387 { 1388 u32 val = readl(host->base + SDC_CFG); 1389 1390 val &= ~SDC_CFG_BUSWIDTH; 1391 1392 switch (width) { 1393 default: 1394 case MMC_BUS_WIDTH_1: 1395 val |= (MSDC_BUS_1BITS << 16); 1396 break; 1397 case MMC_BUS_WIDTH_4: 1398 val |= (MSDC_BUS_4BITS << 16); 1399 break; 1400 case MMC_BUS_WIDTH_8: 1401 val |= (MSDC_BUS_8BITS << 16); 1402 break; 1403 } 1404 1405 writel(val, host->base + SDC_CFG); 1406 dev_dbg(host->dev, "Bus Width = %d", width); 1407 } 1408 1409 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1410 { 1411 struct msdc_host *host = mmc_priv(mmc); 1412 int ret; 1413 1414 if (!IS_ERR(mmc->supply.vqmmc)) { 1415 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1416 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1417 dev_err(host->dev, "Unsupported signal voltage!\n"); 1418 return -EINVAL; 1419 } 1420 1421 ret = mmc_regulator_set_vqmmc(mmc, ios); 1422 if (ret < 0) { 1423 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1424 ret, ios->signal_voltage); 1425 return ret; 1426 } 1427 1428 /* Apply different pinctrl settings for different signal voltage */ 1429 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1430 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1431 else 1432 pinctrl_select_state(host->pinctrl, host->pins_default); 1433 } 1434 return 0; 1435 } 1436 1437 static int msdc_card_busy(struct mmc_host *mmc) 1438 { 1439 struct msdc_host *host = mmc_priv(mmc); 1440 u32 status = readl(host->base + MSDC_PS); 1441 1442 /* only check if data0 is low */ 1443 return !(status & BIT(16)); 1444 } 1445 1446 static void msdc_request_timeout(struct work_struct *work) 1447 { 1448 struct msdc_host *host = container_of(work, struct msdc_host, 1449 req_timeout.work); 1450 1451 /* simulate HW timeout status */ 1452 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1453 if (host->mrq) { 1454 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1455 host->mrq, host->mrq->cmd->opcode); 1456 if (host->cmd) { 1457 dev_err(host->dev, "%s: aborting cmd=%d\n", 1458 __func__, host->cmd->opcode); 1459 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1460 host->cmd); 1461 } else if (host->data) { 1462 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1463 __func__, host->mrq->cmd->opcode, 1464 host->data->blocks); 1465 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1466 host->data); 1467 } 1468 } 1469 } 1470 1471 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1472 { 1473 if (enb) { 1474 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1475 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1476 if (host->dev_comp->recheck_sdio_irq) 1477 msdc_recheck_sdio_irq(host); 1478 } else { 1479 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1480 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1481 } 1482 } 1483 1484 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1485 { 1486 unsigned long flags; 1487 struct msdc_host *host = mmc_priv(mmc); 1488 1489 spin_lock_irqsave(&host->lock, flags); 1490 __msdc_enable_sdio_irq(host, enb); 1491 spin_unlock_irqrestore(&host->lock, flags); 1492 1493 if (enb) 1494 pm_runtime_get_noresume(host->dev); 1495 else 1496 pm_runtime_put_noidle(host->dev); 1497 } 1498 1499 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1500 { 1501 int cmd_err = 0, dat_err = 0; 1502 1503 if (intsts & MSDC_INT_RSPCRCERR) { 1504 cmd_err = -EILSEQ; 1505 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1506 } else if (intsts & MSDC_INT_CMDTMO) { 1507 cmd_err = -ETIMEDOUT; 1508 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1509 } 1510 1511 if (intsts & MSDC_INT_DATCRCERR) { 1512 dat_err = -EILSEQ; 1513 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1514 } else if (intsts & MSDC_INT_DATTMO) { 1515 dat_err = -ETIMEDOUT; 1516 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1517 } 1518 1519 if (cmd_err || dat_err) { 1520 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1521 cmd_err, dat_err, intsts); 1522 } 1523 1524 return cqhci_irq(host->mmc, 0, cmd_err, dat_err); 1525 } 1526 1527 static irqreturn_t msdc_irq(int irq, void *dev_id) 1528 { 1529 struct msdc_host *host = (struct msdc_host *) dev_id; 1530 1531 while (true) { 1532 unsigned long flags; 1533 struct mmc_request *mrq; 1534 struct mmc_command *cmd; 1535 struct mmc_data *data; 1536 u32 events, event_mask; 1537 1538 spin_lock_irqsave(&host->lock, flags); 1539 events = readl(host->base + MSDC_INT); 1540 event_mask = readl(host->base + MSDC_INTEN); 1541 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1542 __msdc_enable_sdio_irq(host, 0); 1543 /* clear interrupts */ 1544 writel(events & event_mask, host->base + MSDC_INT); 1545 1546 mrq = host->mrq; 1547 cmd = host->cmd; 1548 data = host->data; 1549 spin_unlock_irqrestore(&host->lock, flags); 1550 1551 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1552 sdio_signal_irq(host->mmc); 1553 1554 if ((events & event_mask) & MSDC_INT_CDSC) { 1555 if (host->internal_cd) 1556 mmc_detect_change(host->mmc, msecs_to_jiffies(20)); 1557 events &= ~MSDC_INT_CDSC; 1558 } 1559 1560 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1561 break; 1562 1563 if ((host->mmc->caps2 & MMC_CAP2_CQE) && 1564 (events & MSDC_INT_CMDQ)) { 1565 msdc_cmdq_irq(host, events); 1566 /* clear interrupts */ 1567 writel(events, host->base + MSDC_INT); 1568 return IRQ_HANDLED; 1569 } 1570 1571 if (!mrq) { 1572 dev_err(host->dev, 1573 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1574 __func__, events, event_mask); 1575 WARN_ON(1); 1576 break; 1577 } 1578 1579 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1580 1581 if (cmd) 1582 msdc_cmd_done(host, events, mrq, cmd); 1583 else if (data) 1584 msdc_data_xfer_done(host, events, mrq, data); 1585 } 1586 1587 return IRQ_HANDLED; 1588 } 1589 1590 static void msdc_init_hw(struct msdc_host *host) 1591 { 1592 u32 val; 1593 u32 tune_reg = host->dev_comp->pad_tune_reg; 1594 1595 /* Configure to MMC/SD mode, clock free running */ 1596 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1597 1598 /* Reset */ 1599 msdc_reset_hw(host); 1600 1601 /* Disable and clear all interrupts */ 1602 writel(0, host->base + MSDC_INTEN); 1603 val = readl(host->base + MSDC_INT); 1604 writel(val, host->base + MSDC_INT); 1605 1606 /* Configure card detection */ 1607 if (host->internal_cd) { 1608 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1609 DEFAULT_DEBOUNCE); 1610 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1611 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1612 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1613 } else { 1614 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1615 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1616 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1617 } 1618 1619 if (host->top_base) { 1620 writel(0, host->top_base + EMMC_TOP_CONTROL); 1621 writel(0, host->top_base + EMMC_TOP_CMD); 1622 } else { 1623 writel(0, host->base + tune_reg); 1624 } 1625 writel(0, host->base + MSDC_IOCON); 1626 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1627 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1628 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1629 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1630 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1631 1632 if (host->dev_comp->stop_clk_fix) { 1633 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1634 MSDC_PATCH_BIT1_STOP_DLY, 3); 1635 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1636 SDC_FIFO_CFG_WRVALIDSEL); 1637 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1638 SDC_FIFO_CFG_RDVALIDSEL); 1639 } 1640 1641 if (host->dev_comp->busy_check) 1642 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1643 1644 if (host->dev_comp->async_fifo) { 1645 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1646 MSDC_PB2_RESPWAIT, 3); 1647 if (host->dev_comp->enhance_rx) { 1648 if (host->top_base) 1649 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1650 SDC_RX_ENH_EN); 1651 else 1652 sdr_set_bits(host->base + SDC_ADV_CFG0, 1653 SDC_RX_ENHANCE_EN); 1654 } else { 1655 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1656 MSDC_PB2_RESPSTSENSEL, 2); 1657 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1658 MSDC_PB2_CRCSTSENSEL, 2); 1659 } 1660 /* use async fifo, then no need tune internal delay */ 1661 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1662 MSDC_PATCH_BIT2_CFGRESP); 1663 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1664 MSDC_PATCH_BIT2_CFGCRCSTS); 1665 } 1666 1667 if (host->dev_comp->support_64g) 1668 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1669 MSDC_PB2_SUPPORT_64G); 1670 if (host->dev_comp->data_tune) { 1671 if (host->top_base) { 1672 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1673 PAD_DAT_RD_RXDLY_SEL); 1674 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1675 DATA_K_VALUE_SEL); 1676 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1677 PAD_CMD_RD_RXDLY_SEL); 1678 } else { 1679 sdr_set_bits(host->base + tune_reg, 1680 MSDC_PAD_TUNE_RD_SEL | 1681 MSDC_PAD_TUNE_CMD_SEL); 1682 } 1683 } else { 1684 /* choose clock tune */ 1685 if (host->top_base) 1686 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1687 PAD_RXDLY_SEL); 1688 else 1689 sdr_set_bits(host->base + tune_reg, 1690 MSDC_PAD_TUNE_RXDLYSEL); 1691 } 1692 1693 /* Configure to enable SDIO mode. 1694 * it's must otherwise sdio cmd5 failed 1695 */ 1696 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1697 1698 /* Config SDIO device detect interrupt function */ 1699 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1700 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1701 1702 /* Configure to default data timeout */ 1703 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1704 1705 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1706 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1707 if (host->top_base) { 1708 host->def_tune_para.emmc_top_control = 1709 readl(host->top_base + EMMC_TOP_CONTROL); 1710 host->def_tune_para.emmc_top_cmd = 1711 readl(host->top_base + EMMC_TOP_CMD); 1712 host->saved_tune_para.emmc_top_control = 1713 readl(host->top_base + EMMC_TOP_CONTROL); 1714 host->saved_tune_para.emmc_top_cmd = 1715 readl(host->top_base + EMMC_TOP_CMD); 1716 } else { 1717 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1718 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1719 } 1720 dev_dbg(host->dev, "init hardware done!"); 1721 } 1722 1723 static void msdc_deinit_hw(struct msdc_host *host) 1724 { 1725 u32 val; 1726 1727 if (host->internal_cd) { 1728 /* Disabled card-detect */ 1729 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1730 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1731 } 1732 1733 /* Disable and clear all interrupts */ 1734 writel(0, host->base + MSDC_INTEN); 1735 1736 val = readl(host->base + MSDC_INT); 1737 writel(val, host->base + MSDC_INT); 1738 } 1739 1740 /* init gpd and bd list in msdc_drv_probe */ 1741 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1742 { 1743 struct mt_gpdma_desc *gpd = dma->gpd; 1744 struct mt_bdma_desc *bd = dma->bd; 1745 dma_addr_t dma_addr; 1746 int i; 1747 1748 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1749 1750 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1751 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1752 /* gpd->next is must set for desc DMA 1753 * That's why must alloc 2 gpd structure. 1754 */ 1755 gpd->next = lower_32_bits(dma_addr); 1756 if (host->dev_comp->support_64g) 1757 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1758 1759 dma_addr = dma->bd_addr; 1760 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1761 if (host->dev_comp->support_64g) 1762 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1763 1764 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1765 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1766 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1767 bd[i].next = lower_32_bits(dma_addr); 1768 if (host->dev_comp->support_64g) 1769 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1770 } 1771 } 1772 1773 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1774 { 1775 struct msdc_host *host = mmc_priv(mmc); 1776 int ret; 1777 1778 msdc_set_buswidth(host, ios->bus_width); 1779 1780 /* Suspend/Resume will do power off/on */ 1781 switch (ios->power_mode) { 1782 case MMC_POWER_UP: 1783 if (!IS_ERR(mmc->supply.vmmc)) { 1784 msdc_init_hw(host); 1785 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1786 ios->vdd); 1787 if (ret) { 1788 dev_err(host->dev, "Failed to set vmmc power!\n"); 1789 return; 1790 } 1791 } 1792 break; 1793 case MMC_POWER_ON: 1794 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1795 ret = regulator_enable(mmc->supply.vqmmc); 1796 if (ret) 1797 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1798 else 1799 host->vqmmc_enabled = true; 1800 } 1801 break; 1802 case MMC_POWER_OFF: 1803 if (!IS_ERR(mmc->supply.vmmc)) 1804 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1805 1806 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1807 regulator_disable(mmc->supply.vqmmc); 1808 host->vqmmc_enabled = false; 1809 } 1810 break; 1811 default: 1812 break; 1813 } 1814 1815 if (host->mclk != ios->clock || host->timing != ios->timing) 1816 msdc_set_mclk(host, ios->timing, ios->clock); 1817 } 1818 1819 static u32 test_delay_bit(u32 delay, u32 bit) 1820 { 1821 bit %= PAD_DELAY_MAX; 1822 return delay & (1 << bit); 1823 } 1824 1825 static int get_delay_len(u32 delay, u32 start_bit) 1826 { 1827 int i; 1828 1829 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1830 if (test_delay_bit(delay, start_bit + i) == 0) 1831 return i; 1832 } 1833 return PAD_DELAY_MAX - start_bit; 1834 } 1835 1836 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1837 { 1838 int start = 0, len = 0; 1839 int start_final = 0, len_final = 0; 1840 u8 final_phase = 0xff; 1841 struct msdc_delay_phase delay_phase = { 0, }; 1842 1843 if (delay == 0) { 1844 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1845 delay_phase.final_phase = final_phase; 1846 return delay_phase; 1847 } 1848 1849 while (start < PAD_DELAY_MAX) { 1850 len = get_delay_len(delay, start); 1851 if (len_final < len) { 1852 start_final = start; 1853 len_final = len; 1854 } 1855 start += len ? len : 1; 1856 if (len >= 12 && start_final < 4) 1857 break; 1858 } 1859 1860 /* The rule is that to find the smallest delay cell */ 1861 if (start_final == 0) 1862 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1863 else 1864 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1865 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1866 delay, len_final, final_phase); 1867 1868 delay_phase.maxlen = len_final; 1869 delay_phase.start = start_final; 1870 delay_phase.final_phase = final_phase; 1871 return delay_phase; 1872 } 1873 1874 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1875 { 1876 u32 tune_reg = host->dev_comp->pad_tune_reg; 1877 1878 if (host->top_base) 1879 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1880 value); 1881 else 1882 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1883 value); 1884 } 1885 1886 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1887 { 1888 u32 tune_reg = host->dev_comp->pad_tune_reg; 1889 1890 if (host->top_base) 1891 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1892 PAD_DAT_RD_RXDLY, value); 1893 else 1894 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1895 value); 1896 } 1897 1898 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1899 { 1900 struct msdc_host *host = mmc_priv(mmc); 1901 u32 rise_delay = 0, fall_delay = 0; 1902 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1903 struct msdc_delay_phase internal_delay_phase; 1904 u8 final_delay, final_maxlen; 1905 u32 internal_delay = 0; 1906 u32 tune_reg = host->dev_comp->pad_tune_reg; 1907 int cmd_err; 1908 int i, j; 1909 1910 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1911 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1912 sdr_set_field(host->base + tune_reg, 1913 MSDC_PAD_TUNE_CMDRRDLY, 1914 host->hs200_cmd_int_delay); 1915 1916 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1917 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1918 msdc_set_cmd_delay(host, i); 1919 /* 1920 * Using the same parameters, it may sometimes pass the test, 1921 * but sometimes it may fail. To make sure the parameters are 1922 * more stable, we test each set of parameters 3 times. 1923 */ 1924 for (j = 0; j < 3; j++) { 1925 mmc_send_tuning(mmc, opcode, &cmd_err); 1926 if (!cmd_err) { 1927 rise_delay |= (1 << i); 1928 } else { 1929 rise_delay &= ~(1 << i); 1930 break; 1931 } 1932 } 1933 } 1934 final_rise_delay = get_best_delay(host, rise_delay); 1935 /* if rising edge has enough margin, then do not scan falling edge */ 1936 if (final_rise_delay.maxlen >= 12 || 1937 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1938 goto skip_fall; 1939 1940 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1941 for (i = 0; i < PAD_DELAY_MAX; i++) { 1942 msdc_set_cmd_delay(host, i); 1943 /* 1944 * Using the same parameters, it may sometimes pass the test, 1945 * but sometimes it may fail. To make sure the parameters are 1946 * more stable, we test each set of parameters 3 times. 1947 */ 1948 for (j = 0; j < 3; j++) { 1949 mmc_send_tuning(mmc, opcode, &cmd_err); 1950 if (!cmd_err) { 1951 fall_delay |= (1 << i); 1952 } else { 1953 fall_delay &= ~(1 << i); 1954 break; 1955 } 1956 } 1957 } 1958 final_fall_delay = get_best_delay(host, fall_delay); 1959 1960 skip_fall: 1961 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1962 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1963 final_maxlen = final_fall_delay.maxlen; 1964 if (final_maxlen == final_rise_delay.maxlen) { 1965 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1966 final_delay = final_rise_delay.final_phase; 1967 } else { 1968 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1969 final_delay = final_fall_delay.final_phase; 1970 } 1971 msdc_set_cmd_delay(host, final_delay); 1972 1973 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 1974 goto skip_internal; 1975 1976 for (i = 0; i < PAD_DELAY_MAX; i++) { 1977 sdr_set_field(host->base + tune_reg, 1978 MSDC_PAD_TUNE_CMDRRDLY, i); 1979 mmc_send_tuning(mmc, opcode, &cmd_err); 1980 if (!cmd_err) 1981 internal_delay |= (1 << i); 1982 } 1983 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 1984 internal_delay_phase = get_best_delay(host, internal_delay); 1985 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 1986 internal_delay_phase.final_phase); 1987 skip_internal: 1988 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 1989 return final_delay == 0xff ? -EIO : 0; 1990 } 1991 1992 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 1993 { 1994 struct msdc_host *host = mmc_priv(mmc); 1995 u32 cmd_delay = 0; 1996 struct msdc_delay_phase final_cmd_delay = { 0,}; 1997 u8 final_delay; 1998 int cmd_err; 1999 int i, j; 2000 2001 /* select EMMC50 PAD CMD tune */ 2002 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2003 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2004 2005 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2006 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2007 sdr_set_field(host->base + MSDC_PAD_TUNE, 2008 MSDC_PAD_TUNE_CMDRRDLY, 2009 host->hs200_cmd_int_delay); 2010 2011 if (host->hs400_cmd_resp_sel_rising) 2012 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2013 else 2014 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2015 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2016 sdr_set_field(host->base + PAD_CMD_TUNE, 2017 PAD_CMD_TUNE_RX_DLY3, i); 2018 /* 2019 * Using the same parameters, it may sometimes pass the test, 2020 * but sometimes it may fail. To make sure the parameters are 2021 * more stable, we test each set of parameters 3 times. 2022 */ 2023 for (j = 0; j < 3; j++) { 2024 mmc_send_tuning(mmc, opcode, &cmd_err); 2025 if (!cmd_err) { 2026 cmd_delay |= (1 << i); 2027 } else { 2028 cmd_delay &= ~(1 << i); 2029 break; 2030 } 2031 } 2032 } 2033 final_cmd_delay = get_best_delay(host, cmd_delay); 2034 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2035 final_cmd_delay.final_phase); 2036 final_delay = final_cmd_delay.final_phase; 2037 2038 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2039 return final_delay == 0xff ? -EIO : 0; 2040 } 2041 2042 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2043 { 2044 struct msdc_host *host = mmc_priv(mmc); 2045 u32 rise_delay = 0, fall_delay = 0; 2046 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2047 u8 final_delay, final_maxlen; 2048 int i, ret; 2049 2050 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2051 host->latch_ck); 2052 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2053 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2054 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2055 msdc_set_data_delay(host, i); 2056 ret = mmc_send_tuning(mmc, opcode, NULL); 2057 if (!ret) 2058 rise_delay |= (1 << i); 2059 } 2060 final_rise_delay = get_best_delay(host, rise_delay); 2061 /* if rising edge has enough margin, then do not scan falling edge */ 2062 if (final_rise_delay.maxlen >= 12 || 2063 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2064 goto skip_fall; 2065 2066 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2067 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2068 for (i = 0; i < PAD_DELAY_MAX; i++) { 2069 msdc_set_data_delay(host, i); 2070 ret = mmc_send_tuning(mmc, opcode, NULL); 2071 if (!ret) 2072 fall_delay |= (1 << i); 2073 } 2074 final_fall_delay = get_best_delay(host, fall_delay); 2075 2076 skip_fall: 2077 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2078 if (final_maxlen == final_rise_delay.maxlen) { 2079 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2080 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2081 final_delay = final_rise_delay.final_phase; 2082 } else { 2083 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2084 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2085 final_delay = final_fall_delay.final_phase; 2086 } 2087 msdc_set_data_delay(host, final_delay); 2088 2089 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2090 return final_delay == 0xff ? -EIO : 0; 2091 } 2092 2093 /* 2094 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2095 * together, which can save the tuning time. 2096 */ 2097 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2098 { 2099 struct msdc_host *host = mmc_priv(mmc); 2100 u32 rise_delay = 0, fall_delay = 0; 2101 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2102 u8 final_delay, final_maxlen; 2103 int i, ret; 2104 2105 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2106 host->latch_ck); 2107 2108 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2109 sdr_clr_bits(host->base + MSDC_IOCON, 2110 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2111 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2112 msdc_set_cmd_delay(host, i); 2113 msdc_set_data_delay(host, i); 2114 ret = mmc_send_tuning(mmc, opcode, NULL); 2115 if (!ret) 2116 rise_delay |= (1 << i); 2117 } 2118 final_rise_delay = get_best_delay(host, rise_delay); 2119 /* if rising edge has enough margin, then do not scan falling edge */ 2120 if (final_rise_delay.maxlen >= 12 || 2121 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2122 goto skip_fall; 2123 2124 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2125 sdr_set_bits(host->base + MSDC_IOCON, 2126 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2127 for (i = 0; i < PAD_DELAY_MAX; i++) { 2128 msdc_set_cmd_delay(host, i); 2129 msdc_set_data_delay(host, i); 2130 ret = mmc_send_tuning(mmc, opcode, NULL); 2131 if (!ret) 2132 fall_delay |= (1 << i); 2133 } 2134 final_fall_delay = get_best_delay(host, fall_delay); 2135 2136 skip_fall: 2137 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2138 if (final_maxlen == final_rise_delay.maxlen) { 2139 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2140 sdr_clr_bits(host->base + MSDC_IOCON, 2141 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2142 final_delay = final_rise_delay.final_phase; 2143 } else { 2144 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2145 sdr_set_bits(host->base + MSDC_IOCON, 2146 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2147 final_delay = final_fall_delay.final_phase; 2148 } 2149 2150 msdc_set_cmd_delay(host, final_delay); 2151 msdc_set_data_delay(host, final_delay); 2152 2153 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2154 return final_delay == 0xff ? -EIO : 0; 2155 } 2156 2157 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2158 { 2159 struct msdc_host *host = mmc_priv(mmc); 2160 int ret; 2161 u32 tune_reg = host->dev_comp->pad_tune_reg; 2162 2163 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2164 ret = msdc_tune_together(mmc, opcode); 2165 if (host->hs400_mode) { 2166 sdr_clr_bits(host->base + MSDC_IOCON, 2167 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2168 msdc_set_data_delay(host, 0); 2169 } 2170 goto tune_done; 2171 } 2172 if (host->hs400_mode && 2173 host->dev_comp->hs400_tune) 2174 ret = hs400_tune_response(mmc, opcode); 2175 else 2176 ret = msdc_tune_response(mmc, opcode); 2177 if (ret == -EIO) { 2178 dev_err(host->dev, "Tune response fail!\n"); 2179 return ret; 2180 } 2181 if (host->hs400_mode == false) { 2182 ret = msdc_tune_data(mmc, opcode); 2183 if (ret == -EIO) 2184 dev_err(host->dev, "Tune data fail!\n"); 2185 } 2186 2187 tune_done: 2188 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2189 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2190 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2191 if (host->top_base) { 2192 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2193 EMMC_TOP_CONTROL); 2194 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2195 EMMC_TOP_CMD); 2196 } 2197 return ret; 2198 } 2199 2200 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2201 { 2202 struct msdc_host *host = mmc_priv(mmc); 2203 host->hs400_mode = true; 2204 2205 if (host->top_base) 2206 writel(host->hs400_ds_delay, 2207 host->top_base + EMMC50_PAD_DS_TUNE); 2208 else 2209 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2210 /* hs400 mode must set it to 0 */ 2211 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2212 /* to improve read performance, set outstanding to 2 */ 2213 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2214 2215 return 0; 2216 } 2217 2218 static void msdc_hw_reset(struct mmc_host *mmc) 2219 { 2220 struct msdc_host *host = mmc_priv(mmc); 2221 2222 sdr_set_bits(host->base + EMMC_IOCON, 1); 2223 udelay(10); /* 10us is enough */ 2224 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2225 } 2226 2227 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2228 { 2229 unsigned long flags; 2230 struct msdc_host *host = mmc_priv(mmc); 2231 2232 spin_lock_irqsave(&host->lock, flags); 2233 __msdc_enable_sdio_irq(host, 1); 2234 spin_unlock_irqrestore(&host->lock, flags); 2235 } 2236 2237 static int msdc_get_cd(struct mmc_host *mmc) 2238 { 2239 struct msdc_host *host = mmc_priv(mmc); 2240 int val; 2241 2242 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2243 return 1; 2244 2245 if (!host->internal_cd) 2246 return mmc_gpio_get_cd(mmc); 2247 2248 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2249 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2250 return !!val; 2251 else 2252 return !val; 2253 } 2254 2255 static void msdc_cqe_enable(struct mmc_host *mmc) 2256 { 2257 struct msdc_host *host = mmc_priv(mmc); 2258 2259 /* enable cmdq irq */ 2260 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2261 /* enable busy check */ 2262 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2263 /* default write data / busy timeout 20s */ 2264 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2265 /* default read data timeout 1s */ 2266 msdc_set_timeout(host, 1000000000ULL, 0); 2267 } 2268 2269 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2270 { 2271 struct msdc_host *host = mmc_priv(mmc); 2272 2273 /* disable cmdq irq */ 2274 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2275 /* disable busy check */ 2276 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2277 2278 if (recovery) { 2279 sdr_set_field(host->base + MSDC_DMA_CTRL, 2280 MSDC_DMA_CTRL_STOP, 1); 2281 msdc_reset_hw(host); 2282 } 2283 } 2284 2285 static const struct mmc_host_ops mt_msdc_ops = { 2286 .post_req = msdc_post_req, 2287 .pre_req = msdc_pre_req, 2288 .request = msdc_ops_request, 2289 .set_ios = msdc_ops_set_ios, 2290 .get_ro = mmc_gpio_get_ro, 2291 .get_cd = msdc_get_cd, 2292 .enable_sdio_irq = msdc_enable_sdio_irq, 2293 .ack_sdio_irq = msdc_ack_sdio_irq, 2294 .start_signal_voltage_switch = msdc_ops_switch_volt, 2295 .card_busy = msdc_card_busy, 2296 .execute_tuning = msdc_execute_tuning, 2297 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2298 .hw_reset = msdc_hw_reset, 2299 }; 2300 2301 static const struct cqhci_host_ops msdc_cmdq_ops = { 2302 .enable = msdc_cqe_enable, 2303 .disable = msdc_cqe_disable, 2304 }; 2305 2306 static void msdc_of_property_parse(struct platform_device *pdev, 2307 struct msdc_host *host) 2308 { 2309 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2310 &host->latch_ck); 2311 2312 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2313 &host->hs400_ds_delay); 2314 2315 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2316 &host->hs200_cmd_int_delay); 2317 2318 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2319 &host->hs400_cmd_int_delay); 2320 2321 if (of_property_read_bool(pdev->dev.of_node, 2322 "mediatek,hs400-cmd-resp-sel-rising")) 2323 host->hs400_cmd_resp_sel_rising = true; 2324 else 2325 host->hs400_cmd_resp_sel_rising = false; 2326 2327 if (of_property_read_bool(pdev->dev.of_node, 2328 "supports-cqe")) 2329 host->cqhci = true; 2330 else 2331 host->cqhci = false; 2332 } 2333 2334 static int msdc_drv_probe(struct platform_device *pdev) 2335 { 2336 struct mmc_host *mmc; 2337 struct msdc_host *host; 2338 struct resource *res; 2339 int ret; 2340 2341 if (!pdev->dev.of_node) { 2342 dev_err(&pdev->dev, "No DT found\n"); 2343 return -EINVAL; 2344 } 2345 2346 /* Allocate MMC host for this device */ 2347 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2348 if (!mmc) 2349 return -ENOMEM; 2350 2351 host = mmc_priv(mmc); 2352 ret = mmc_of_parse(mmc); 2353 if (ret) 2354 goto host_free; 2355 2356 host->base = devm_platform_ioremap_resource(pdev, 0); 2357 if (IS_ERR(host->base)) { 2358 ret = PTR_ERR(host->base); 2359 goto host_free; 2360 } 2361 2362 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2363 if (res) { 2364 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2365 if (IS_ERR(host->top_base)) 2366 host->top_base = NULL; 2367 } 2368 2369 ret = mmc_regulator_get_supply(mmc); 2370 if (ret) 2371 goto host_free; 2372 2373 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2374 if (IS_ERR(host->src_clk)) { 2375 ret = PTR_ERR(host->src_clk); 2376 goto host_free; 2377 } 2378 2379 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2380 if (IS_ERR(host->h_clk)) { 2381 ret = PTR_ERR(host->h_clk); 2382 goto host_free; 2383 } 2384 2385 host->bus_clk = devm_clk_get(&pdev->dev, "bus_clk"); 2386 if (IS_ERR(host->bus_clk)) 2387 host->bus_clk = NULL; 2388 /*source clock control gate is optional clock*/ 2389 host->src_clk_cg = devm_clk_get(&pdev->dev, "source_cg"); 2390 if (IS_ERR(host->src_clk_cg)) 2391 host->src_clk_cg = NULL; 2392 2393 host->irq = platform_get_irq(pdev, 0); 2394 if (host->irq < 0) { 2395 ret = -EINVAL; 2396 goto host_free; 2397 } 2398 2399 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2400 if (IS_ERR(host->pinctrl)) { 2401 ret = PTR_ERR(host->pinctrl); 2402 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2403 goto host_free; 2404 } 2405 2406 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2407 if (IS_ERR(host->pins_default)) { 2408 ret = PTR_ERR(host->pins_default); 2409 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2410 goto host_free; 2411 } 2412 2413 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2414 if (IS_ERR(host->pins_uhs)) { 2415 ret = PTR_ERR(host->pins_uhs); 2416 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2417 goto host_free; 2418 } 2419 2420 msdc_of_property_parse(pdev, host); 2421 2422 host->dev = &pdev->dev; 2423 host->dev_comp = of_device_get_match_data(&pdev->dev); 2424 host->mmc = mmc; 2425 host->src_clk_freq = clk_get_rate(host->src_clk); 2426 /* Set host parameters to mmc */ 2427 mmc->ops = &mt_msdc_ops; 2428 if (host->dev_comp->clk_div_bits == 8) 2429 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2430 else 2431 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2432 2433 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2434 !mmc_can_gpio_cd(mmc) && 2435 host->dev_comp->use_internal_cd) { 2436 /* 2437 * Is removable but no GPIO declared, so 2438 * use internal functionality. 2439 */ 2440 host->internal_cd = true; 2441 } 2442 2443 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2444 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2445 2446 mmc->caps |= MMC_CAP_CMD23; 2447 if (host->cqhci) 2448 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2449 /* MMC core transfer sizes tunable parameters */ 2450 mmc->max_segs = MAX_BD_NUM; 2451 if (host->dev_comp->support_64g) 2452 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2453 else 2454 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2455 mmc->max_blk_size = 2048; 2456 mmc->max_req_size = 512 * 1024; 2457 mmc->max_blk_count = mmc->max_req_size / 512; 2458 if (host->dev_comp->support_64g) 2459 host->dma_mask = DMA_BIT_MASK(36); 2460 else 2461 host->dma_mask = DMA_BIT_MASK(32); 2462 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2463 2464 if (mmc->caps2 & MMC_CAP2_CQE) { 2465 host->cq_host = devm_kzalloc(host->mmc->parent, 2466 sizeof(*host->cq_host), 2467 GFP_KERNEL); 2468 if (!host->cq_host) { 2469 ret = -ENOMEM; 2470 goto host_free; 2471 } 2472 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2473 host->cq_host->mmio = host->base + 0x800; 2474 host->cq_host->ops = &msdc_cmdq_ops; 2475 ret = cqhci_init(host->cq_host, mmc, true); 2476 if (ret) 2477 goto host_free; 2478 mmc->max_segs = 128; 2479 /* cqhci 16bit length */ 2480 /* 0 size, means 65536 so we don't have to -1 here */ 2481 mmc->max_seg_size = 64 * 1024; 2482 } 2483 2484 host->timeout_clks = 3 * 1048576; 2485 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2486 2 * sizeof(struct mt_gpdma_desc), 2487 &host->dma.gpd_addr, GFP_KERNEL); 2488 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2489 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2490 &host->dma.bd_addr, GFP_KERNEL); 2491 if (!host->dma.gpd || !host->dma.bd) { 2492 ret = -ENOMEM; 2493 goto release_mem; 2494 } 2495 msdc_init_gpd_bd(host, &host->dma); 2496 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2497 spin_lock_init(&host->lock); 2498 2499 platform_set_drvdata(pdev, mmc); 2500 msdc_ungate_clock(host); 2501 msdc_init_hw(host); 2502 2503 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2504 IRQF_TRIGGER_NONE, pdev->name, host); 2505 if (ret) 2506 goto release; 2507 2508 pm_runtime_set_active(host->dev); 2509 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2510 pm_runtime_use_autosuspend(host->dev); 2511 pm_runtime_enable(host->dev); 2512 ret = mmc_add_host(mmc); 2513 2514 if (ret) 2515 goto end; 2516 2517 return 0; 2518 end: 2519 pm_runtime_disable(host->dev); 2520 release: 2521 platform_set_drvdata(pdev, NULL); 2522 msdc_deinit_hw(host); 2523 msdc_gate_clock(host); 2524 release_mem: 2525 if (host->dma.gpd) 2526 dma_free_coherent(&pdev->dev, 2527 2 * sizeof(struct mt_gpdma_desc), 2528 host->dma.gpd, host->dma.gpd_addr); 2529 if (host->dma.bd) 2530 dma_free_coherent(&pdev->dev, 2531 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2532 host->dma.bd, host->dma.bd_addr); 2533 host_free: 2534 mmc_free_host(mmc); 2535 2536 return ret; 2537 } 2538 2539 static int msdc_drv_remove(struct platform_device *pdev) 2540 { 2541 struct mmc_host *mmc; 2542 struct msdc_host *host; 2543 2544 mmc = platform_get_drvdata(pdev); 2545 host = mmc_priv(mmc); 2546 2547 pm_runtime_get_sync(host->dev); 2548 2549 platform_set_drvdata(pdev, NULL); 2550 mmc_remove_host(host->mmc); 2551 msdc_deinit_hw(host); 2552 msdc_gate_clock(host); 2553 2554 pm_runtime_disable(host->dev); 2555 pm_runtime_put_noidle(host->dev); 2556 dma_free_coherent(&pdev->dev, 2557 2 * sizeof(struct mt_gpdma_desc), 2558 host->dma.gpd, host->dma.gpd_addr); 2559 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2560 host->dma.bd, host->dma.bd_addr); 2561 2562 mmc_free_host(host->mmc); 2563 2564 return 0; 2565 } 2566 2567 #ifdef CONFIG_PM 2568 static void msdc_save_reg(struct msdc_host *host) 2569 { 2570 u32 tune_reg = host->dev_comp->pad_tune_reg; 2571 2572 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2573 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2574 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2575 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2576 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2577 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2578 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2579 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2580 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2581 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2582 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2583 if (host->top_base) { 2584 host->save_para.emmc_top_control = 2585 readl(host->top_base + EMMC_TOP_CONTROL); 2586 host->save_para.emmc_top_cmd = 2587 readl(host->top_base + EMMC_TOP_CMD); 2588 host->save_para.emmc50_pad_ds_tune = 2589 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2590 } else { 2591 host->save_para.pad_tune = readl(host->base + tune_reg); 2592 } 2593 } 2594 2595 static void msdc_restore_reg(struct msdc_host *host) 2596 { 2597 u32 tune_reg = host->dev_comp->pad_tune_reg; 2598 2599 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2600 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2601 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2602 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2603 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2604 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2605 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2606 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2607 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2608 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2609 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2610 if (host->top_base) { 2611 writel(host->save_para.emmc_top_control, 2612 host->top_base + EMMC_TOP_CONTROL); 2613 writel(host->save_para.emmc_top_cmd, 2614 host->top_base + EMMC_TOP_CMD); 2615 writel(host->save_para.emmc50_pad_ds_tune, 2616 host->top_base + EMMC50_PAD_DS_TUNE); 2617 } else { 2618 writel(host->save_para.pad_tune, host->base + tune_reg); 2619 } 2620 2621 if (sdio_irq_claimed(host->mmc)) 2622 __msdc_enable_sdio_irq(host, 1); 2623 } 2624 2625 static int msdc_runtime_suspend(struct device *dev) 2626 { 2627 struct mmc_host *mmc = dev_get_drvdata(dev); 2628 struct msdc_host *host = mmc_priv(mmc); 2629 2630 msdc_save_reg(host); 2631 msdc_gate_clock(host); 2632 return 0; 2633 } 2634 2635 static int msdc_runtime_resume(struct device *dev) 2636 { 2637 struct mmc_host *mmc = dev_get_drvdata(dev); 2638 struct msdc_host *host = mmc_priv(mmc); 2639 2640 msdc_ungate_clock(host); 2641 msdc_restore_reg(host); 2642 return 0; 2643 } 2644 #endif 2645 2646 static const struct dev_pm_ops msdc_dev_pm_ops = { 2647 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2648 pm_runtime_force_resume) 2649 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2650 }; 2651 2652 static struct platform_driver mt_msdc_driver = { 2653 .probe = msdc_drv_probe, 2654 .remove = msdc_drv_remove, 2655 .driver = { 2656 .name = "mtk-msdc", 2657 .of_match_table = msdc_of_ids, 2658 .pm = &msdc_dev_pm_ops, 2659 }, 2660 }; 2661 2662 module_platform_driver(mt_msdc_driver); 2663 MODULE_LICENSE("GPL v2"); 2664 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2665