1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/iopoll.h> 12 #include <linux/ioport.h> 13 #include <linux/irq.h> 14 #include <linux/of_address.h> 15 #include <linux/of_device.h> 16 #include <linux/of_irq.h> 17 #include <linux/of_gpio.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/slab.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/reset.h> 27 28 #include <linux/mmc/card.h> 29 #include <linux/mmc/core.h> 30 #include <linux/mmc/host.h> 31 #include <linux/mmc/mmc.h> 32 #include <linux/mmc/sd.h> 33 #include <linux/mmc/sdio.h> 34 #include <linux/mmc/slot-gpio.h> 35 36 #include "cqhci.h" 37 38 #define MAX_BD_NUM 1024 39 #define MSDC_NR_CLOCKS 3 40 41 /*--------------------------------------------------------------------------*/ 42 /* Common Definition */ 43 /*--------------------------------------------------------------------------*/ 44 #define MSDC_BUS_1BITS 0x0 45 #define MSDC_BUS_4BITS 0x1 46 #define MSDC_BUS_8BITS 0x2 47 48 #define MSDC_BURST_64B 0x6 49 50 /*--------------------------------------------------------------------------*/ 51 /* Register Offset */ 52 /*--------------------------------------------------------------------------*/ 53 #define MSDC_CFG 0x0 54 #define MSDC_IOCON 0x04 55 #define MSDC_PS 0x08 56 #define MSDC_INT 0x0c 57 #define MSDC_INTEN 0x10 58 #define MSDC_FIFOCS 0x14 59 #define SDC_CFG 0x30 60 #define SDC_CMD 0x34 61 #define SDC_ARG 0x38 62 #define SDC_STS 0x3c 63 #define SDC_RESP0 0x40 64 #define SDC_RESP1 0x44 65 #define SDC_RESP2 0x48 66 #define SDC_RESP3 0x4c 67 #define SDC_BLK_NUM 0x50 68 #define SDC_ADV_CFG0 0x64 69 #define EMMC_IOCON 0x7c 70 #define SDC_ACMD_RESP 0x80 71 #define DMA_SA_H4BIT 0x8c 72 #define MSDC_DMA_SA 0x90 73 #define MSDC_DMA_CTRL 0x98 74 #define MSDC_DMA_CFG 0x9c 75 #define MSDC_PATCH_BIT 0xb0 76 #define MSDC_PATCH_BIT1 0xb4 77 #define MSDC_PATCH_BIT2 0xb8 78 #define MSDC_PAD_TUNE 0xec 79 #define MSDC_PAD_TUNE0 0xf0 80 #define PAD_DS_TUNE 0x188 81 #define PAD_CMD_TUNE 0x18c 82 #define EMMC51_CFG0 0x204 83 #define EMMC50_CFG0 0x208 84 #define EMMC50_CFG1 0x20c 85 #define EMMC50_CFG3 0x220 86 #define SDC_FIFO_CFG 0x228 87 #define CQHCI_SETTING 0x7fc 88 89 /*--------------------------------------------------------------------------*/ 90 /* Top Pad Register Offset */ 91 /*--------------------------------------------------------------------------*/ 92 #define EMMC_TOP_CONTROL 0x00 93 #define EMMC_TOP_CMD 0x04 94 #define EMMC50_PAD_DS_TUNE 0x0c 95 96 /*--------------------------------------------------------------------------*/ 97 /* Register Mask */ 98 /*--------------------------------------------------------------------------*/ 99 100 /* MSDC_CFG mask */ 101 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 102 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 103 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 104 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 105 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 106 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 107 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 108 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 109 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 110 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 111 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 112 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 113 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 114 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 115 116 /* MSDC_IOCON mask */ 117 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 118 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 119 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 120 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 121 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 122 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 123 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 124 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 125 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 126 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 127 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 128 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 129 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 130 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 131 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 132 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 133 134 /* MSDC_PS mask */ 135 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 136 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 137 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 138 #define MSDC_PS_DAT (0xff << 16) /* R */ 139 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 140 #define MSDC_PS_CMD (0x1 << 24) /* R */ 141 #define MSDC_PS_WP (0x1 << 31) /* R */ 142 143 /* MSDC_INT mask */ 144 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 145 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 146 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 147 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 148 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 149 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 150 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 151 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 152 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 153 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 154 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 155 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 156 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 157 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 158 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 159 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 160 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 161 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 162 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 163 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 164 165 /* MSDC_INTEN mask */ 166 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 167 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 168 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 169 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 170 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 171 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 172 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 173 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 174 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 175 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 176 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 177 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 178 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 179 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 180 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 181 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 182 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 183 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 184 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 185 186 /* MSDC_FIFOCS mask */ 187 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 188 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 189 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 190 191 /* SDC_CFG mask */ 192 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 193 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 194 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 195 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 196 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 197 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 198 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 199 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 200 201 /* SDC_STS mask */ 202 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 203 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 204 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 205 206 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 207 /* SDC_ADV_CFG0 mask */ 208 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 209 210 /* DMA_SA_H4BIT mask */ 211 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 212 213 /* MSDC_DMA_CTRL mask */ 214 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 215 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 216 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 217 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 218 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 219 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 220 221 /* MSDC_DMA_CFG mask */ 222 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 223 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 224 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 225 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 226 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 227 228 /* MSDC_PATCH_BIT mask */ 229 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 230 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 231 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 232 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 233 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 234 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 235 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 236 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 237 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 238 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 239 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 240 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 241 242 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 243 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 244 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 245 246 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 247 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 248 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 249 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 250 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 251 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 252 253 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 254 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 255 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 256 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 257 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 258 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 259 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 260 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 261 262 #define PAD_DS_TUNE_DLY_SEL (0x1 << 0) /* RW */ 263 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 264 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 265 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 266 267 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 268 269 /* EMMC51_CFG0 mask */ 270 #define CMDQ_RDAT_CNT (0x3ff << 12) /* RW */ 271 272 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 273 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 274 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 275 #define EMMC50_CFG_CMD_RESP_SEL (0x1 << 9) /* RW */ 276 277 /* EMMC50_CFG1 mask */ 278 #define EMMC50_CFG1_DS_CFG (0x1 << 28) /* RW */ 279 280 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 281 282 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 283 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 284 285 /* CQHCI_SETTING */ 286 #define CQHCI_RD_CMD_WND_SEL (0x1 << 14) /* RW */ 287 #define CQHCI_WR_CMD_WND_SEL (0x1 << 15) /* RW */ 288 289 /* EMMC_TOP_CONTROL mask */ 290 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 291 #define DELAY_EN (0x1 << 1) /* RW */ 292 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 293 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 294 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 295 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 296 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 297 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 298 299 /* EMMC_TOP_CMD mask */ 300 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 301 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 302 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 303 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 304 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 305 306 /* EMMC50_PAD_DS_TUNE mask */ 307 #define PAD_DS_DLY_SEL (0x1 << 16) /* RW */ 308 #define PAD_DS_DLY1 (0x1f << 10) /* RW */ 309 #define PAD_DS_DLY3 (0x1f << 0) /* RW */ 310 311 #define REQ_CMD_EIO (0x1 << 0) 312 #define REQ_CMD_TMO (0x1 << 1) 313 #define REQ_DAT_ERR (0x1 << 2) 314 #define REQ_STOP_EIO (0x1 << 3) 315 #define REQ_STOP_TMO (0x1 << 4) 316 #define REQ_CMD_BUSY (0x1 << 5) 317 318 #define MSDC_PREPARE_FLAG (0x1 << 0) 319 #define MSDC_ASYNC_FLAG (0x1 << 1) 320 #define MSDC_MMAP_FLAG (0x1 << 2) 321 322 #define MTK_MMC_AUTOSUSPEND_DELAY 50 323 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 324 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 325 326 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 327 328 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 329 /*--------------------------------------------------------------------------*/ 330 /* Descriptor Structure */ 331 /*--------------------------------------------------------------------------*/ 332 struct mt_gpdma_desc { 333 u32 gpd_info; 334 #define GPDMA_DESC_HWO (0x1 << 0) 335 #define GPDMA_DESC_BDP (0x1 << 1) 336 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 337 #define GPDMA_DESC_INT (0x1 << 16) 338 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 339 #define GPDMA_DESC_PTR_H4 (0xf << 28) 340 u32 next; 341 u32 ptr; 342 u32 gpd_data_len; 343 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 344 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 345 u32 arg; 346 u32 blknum; 347 u32 cmd; 348 }; 349 350 struct mt_bdma_desc { 351 u32 bd_info; 352 #define BDMA_DESC_EOL (0x1 << 0) 353 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 354 #define BDMA_DESC_BLKPAD (0x1 << 17) 355 #define BDMA_DESC_DWPAD (0x1 << 18) 356 #define BDMA_DESC_NEXT_H4 (0xf << 24) 357 #define BDMA_DESC_PTR_H4 (0xf << 28) 358 u32 next; 359 u32 ptr; 360 u32 bd_data_len; 361 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 362 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 363 }; 364 365 struct msdc_dma { 366 struct scatterlist *sg; /* I/O scatter list */ 367 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 368 struct mt_bdma_desc *bd; /* pointer to bd array */ 369 dma_addr_t gpd_addr; /* the physical address of gpd array */ 370 dma_addr_t bd_addr; /* the physical address of bd array */ 371 }; 372 373 struct msdc_save_para { 374 u32 msdc_cfg; 375 u32 iocon; 376 u32 sdc_cfg; 377 u32 pad_tune; 378 u32 patch_bit0; 379 u32 patch_bit1; 380 u32 patch_bit2; 381 u32 pad_ds_tune; 382 u32 pad_cmd_tune; 383 u32 emmc50_cfg0; 384 u32 emmc50_cfg3; 385 u32 sdc_fifo_cfg; 386 u32 emmc_top_control; 387 u32 emmc_top_cmd; 388 u32 emmc50_pad_ds_tune; 389 }; 390 391 struct mtk_mmc_compatible { 392 u8 clk_div_bits; 393 bool recheck_sdio_irq; 394 bool hs400_tune; /* only used for MT8173 */ 395 u32 pad_tune_reg; 396 bool async_fifo; 397 bool data_tune; 398 bool busy_check; 399 bool stop_clk_fix; 400 bool enhance_rx; 401 bool support_64g; 402 bool use_internal_cd; 403 }; 404 405 struct msdc_tune_para { 406 u32 iocon; 407 u32 pad_tune; 408 u32 pad_cmd_tune; 409 u32 emmc_top_control; 410 u32 emmc_top_cmd; 411 }; 412 413 struct msdc_delay_phase { 414 u8 maxlen; 415 u8 start; 416 u8 final_phase; 417 }; 418 419 struct msdc_host { 420 struct device *dev; 421 const struct mtk_mmc_compatible *dev_comp; 422 int cmd_rsp; 423 424 spinlock_t lock; 425 struct mmc_request *mrq; 426 struct mmc_command *cmd; 427 struct mmc_data *data; 428 int error; 429 430 void __iomem *base; /* host base address */ 431 void __iomem *top_base; /* host top register base address */ 432 433 struct msdc_dma dma; /* dma channel */ 434 u64 dma_mask; 435 436 u32 timeout_ns; /* data timeout ns */ 437 u32 timeout_clks; /* data timeout clks */ 438 439 struct pinctrl *pinctrl; 440 struct pinctrl_state *pins_default; 441 struct pinctrl_state *pins_uhs; 442 struct delayed_work req_timeout; 443 int irq; /* host interrupt */ 444 struct reset_control *reset; 445 446 struct clk *src_clk; /* msdc source clock */ 447 struct clk *h_clk; /* msdc h_clk */ 448 struct clk *bus_clk; /* bus clock which used to access register */ 449 struct clk *src_clk_cg; /* msdc source clock control gate */ 450 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 451 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 452 u32 mclk; /* mmc subsystem clock frequency */ 453 u32 src_clk_freq; /* source clock frequency */ 454 unsigned char timing; 455 bool vqmmc_enabled; 456 u32 latch_ck; 457 u32 hs400_ds_delay; 458 u32 hs400_ds_dly3; 459 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 460 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 461 bool hs400_cmd_resp_sel_rising; 462 /* cmd response sample selection for HS400 */ 463 bool hs400_mode; /* current eMMC will run at hs400 mode */ 464 bool hs400_tuning; /* hs400 mode online tuning */ 465 bool internal_cd; /* Use internal card-detect logic */ 466 bool cqhci; /* support eMMC hw cmdq */ 467 struct msdc_save_para save_para; /* used when gate HCLK */ 468 struct msdc_tune_para def_tune_para; /* default tune setting */ 469 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 470 struct cqhci_host *cq_host; 471 }; 472 473 static const struct mtk_mmc_compatible mt8135_compat = { 474 .clk_div_bits = 8, 475 .recheck_sdio_irq = true, 476 .hs400_tune = false, 477 .pad_tune_reg = MSDC_PAD_TUNE, 478 .async_fifo = false, 479 .data_tune = false, 480 .busy_check = false, 481 .stop_clk_fix = false, 482 .enhance_rx = false, 483 .support_64g = false, 484 }; 485 486 static const struct mtk_mmc_compatible mt8173_compat = { 487 .clk_div_bits = 8, 488 .recheck_sdio_irq = true, 489 .hs400_tune = true, 490 .pad_tune_reg = MSDC_PAD_TUNE, 491 .async_fifo = false, 492 .data_tune = false, 493 .busy_check = false, 494 .stop_clk_fix = false, 495 .enhance_rx = false, 496 .support_64g = false, 497 }; 498 499 static const struct mtk_mmc_compatible mt8183_compat = { 500 .clk_div_bits = 12, 501 .recheck_sdio_irq = false, 502 .hs400_tune = false, 503 .pad_tune_reg = MSDC_PAD_TUNE0, 504 .async_fifo = true, 505 .data_tune = true, 506 .busy_check = true, 507 .stop_clk_fix = true, 508 .enhance_rx = true, 509 .support_64g = true, 510 }; 511 512 static const struct mtk_mmc_compatible mt2701_compat = { 513 .clk_div_bits = 12, 514 .recheck_sdio_irq = true, 515 .hs400_tune = false, 516 .pad_tune_reg = MSDC_PAD_TUNE0, 517 .async_fifo = true, 518 .data_tune = true, 519 .busy_check = false, 520 .stop_clk_fix = false, 521 .enhance_rx = false, 522 .support_64g = false, 523 }; 524 525 static const struct mtk_mmc_compatible mt2712_compat = { 526 .clk_div_bits = 12, 527 .recheck_sdio_irq = false, 528 .hs400_tune = false, 529 .pad_tune_reg = MSDC_PAD_TUNE0, 530 .async_fifo = true, 531 .data_tune = true, 532 .busy_check = true, 533 .stop_clk_fix = true, 534 .enhance_rx = true, 535 .support_64g = true, 536 }; 537 538 static const struct mtk_mmc_compatible mt7622_compat = { 539 .clk_div_bits = 12, 540 .recheck_sdio_irq = true, 541 .hs400_tune = false, 542 .pad_tune_reg = MSDC_PAD_TUNE0, 543 .async_fifo = true, 544 .data_tune = true, 545 .busy_check = true, 546 .stop_clk_fix = true, 547 .enhance_rx = true, 548 .support_64g = false, 549 }; 550 551 static const struct mtk_mmc_compatible mt8516_compat = { 552 .clk_div_bits = 12, 553 .recheck_sdio_irq = true, 554 .hs400_tune = false, 555 .pad_tune_reg = MSDC_PAD_TUNE0, 556 .async_fifo = true, 557 .data_tune = true, 558 .busy_check = true, 559 .stop_clk_fix = true, 560 }; 561 562 static const struct mtk_mmc_compatible mt7620_compat = { 563 .clk_div_bits = 8, 564 .recheck_sdio_irq = true, 565 .hs400_tune = false, 566 .pad_tune_reg = MSDC_PAD_TUNE, 567 .async_fifo = false, 568 .data_tune = false, 569 .busy_check = false, 570 .stop_clk_fix = false, 571 .enhance_rx = false, 572 .use_internal_cd = true, 573 }; 574 575 static const struct mtk_mmc_compatible mt6779_compat = { 576 .clk_div_bits = 12, 577 .recheck_sdio_irq = false, 578 .hs400_tune = false, 579 .pad_tune_reg = MSDC_PAD_TUNE0, 580 .async_fifo = true, 581 .data_tune = true, 582 .busy_check = true, 583 .stop_clk_fix = true, 584 .enhance_rx = true, 585 .support_64g = true, 586 }; 587 588 static const struct of_device_id msdc_of_ids[] = { 589 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 590 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 591 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 592 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 593 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 594 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 595 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 596 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 597 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 598 {} 599 }; 600 MODULE_DEVICE_TABLE(of, msdc_of_ids); 601 602 static void sdr_set_bits(void __iomem *reg, u32 bs) 603 { 604 u32 val = readl(reg); 605 606 val |= bs; 607 writel(val, reg); 608 } 609 610 static void sdr_clr_bits(void __iomem *reg, u32 bs) 611 { 612 u32 val = readl(reg); 613 614 val &= ~bs; 615 writel(val, reg); 616 } 617 618 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 619 { 620 unsigned int tv = readl(reg); 621 622 tv &= ~field; 623 tv |= ((val) << (ffs((unsigned int)field) - 1)); 624 writel(tv, reg); 625 } 626 627 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 628 { 629 unsigned int tv = readl(reg); 630 631 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 632 } 633 634 static void msdc_reset_hw(struct msdc_host *host) 635 { 636 u32 val; 637 638 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 639 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 640 cpu_relax(); 641 642 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 643 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 644 cpu_relax(); 645 646 val = readl(host->base + MSDC_INT); 647 writel(val, host->base + MSDC_INT); 648 } 649 650 static void msdc_cmd_next(struct msdc_host *host, 651 struct mmc_request *mrq, struct mmc_command *cmd); 652 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 653 654 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 655 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 656 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 657 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 658 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 659 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 660 661 static u8 msdc_dma_calcs(u8 *buf, u32 len) 662 { 663 u32 i, sum = 0; 664 665 for (i = 0; i < len; i++) 666 sum += buf[i]; 667 return 0xff - (u8) sum; 668 } 669 670 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 671 struct mmc_data *data) 672 { 673 unsigned int j, dma_len; 674 dma_addr_t dma_address; 675 u32 dma_ctrl; 676 struct scatterlist *sg; 677 struct mt_gpdma_desc *gpd; 678 struct mt_bdma_desc *bd; 679 680 sg = data->sg; 681 682 gpd = dma->gpd; 683 bd = dma->bd; 684 685 /* modify gpd */ 686 gpd->gpd_info |= GPDMA_DESC_HWO; 687 gpd->gpd_info |= GPDMA_DESC_BDP; 688 /* need to clear first. use these bits to calc checksum */ 689 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 690 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 691 692 /* modify bd */ 693 for_each_sg(data->sg, sg, data->sg_count, j) { 694 dma_address = sg_dma_address(sg); 695 dma_len = sg_dma_len(sg); 696 697 /* init bd */ 698 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 699 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 700 bd[j].ptr = lower_32_bits(dma_address); 701 if (host->dev_comp->support_64g) { 702 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 703 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 704 << 28; 705 } 706 707 if (host->dev_comp->support_64g) { 708 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 709 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 710 } else { 711 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 712 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 713 } 714 715 if (j == data->sg_count - 1) /* the last bd */ 716 bd[j].bd_info |= BDMA_DESC_EOL; 717 else 718 bd[j].bd_info &= ~BDMA_DESC_EOL; 719 720 /* checksume need to clear first */ 721 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 722 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 723 } 724 725 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 726 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 727 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 728 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 729 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 730 if (host->dev_comp->support_64g) 731 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 732 upper_32_bits(dma->gpd_addr) & 0xf); 733 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 734 } 735 736 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 737 { 738 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 739 data->host_cookie |= MSDC_PREPARE_FLAG; 740 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 741 mmc_get_dma_dir(data)); 742 } 743 } 744 745 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 746 { 747 if (data->host_cookie & MSDC_ASYNC_FLAG) 748 return; 749 750 if (data->host_cookie & MSDC_PREPARE_FLAG) { 751 dma_unmap_sg(host->dev, data->sg, data->sg_len, 752 mmc_get_dma_dir(data)); 753 data->host_cookie &= ~MSDC_PREPARE_FLAG; 754 } 755 } 756 757 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 758 { 759 struct mmc_host *mmc = mmc_from_priv(host); 760 u64 timeout, clk_ns; 761 u32 mode = 0; 762 763 if (mmc->actual_clock == 0) { 764 timeout = 0; 765 } else { 766 clk_ns = 1000000000ULL; 767 do_div(clk_ns, mmc->actual_clock); 768 timeout = ns + clk_ns - 1; 769 do_div(timeout, clk_ns); 770 timeout += clks; 771 /* in 1048576 sclk cycle unit */ 772 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 773 if (host->dev_comp->clk_div_bits == 8) 774 sdr_get_field(host->base + MSDC_CFG, 775 MSDC_CFG_CKMOD, &mode); 776 else 777 sdr_get_field(host->base + MSDC_CFG, 778 MSDC_CFG_CKMOD_EXTRA, &mode); 779 /*DDR mode will double the clk cycles for data timeout */ 780 timeout = mode >= 2 ? timeout * 2 : timeout; 781 timeout = timeout > 1 ? timeout - 1 : 0; 782 } 783 return timeout; 784 } 785 786 /* clock control primitives */ 787 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 788 { 789 u64 timeout; 790 791 host->timeout_ns = ns; 792 host->timeout_clks = clks; 793 794 timeout = msdc_timeout_cal(host, ns, clks); 795 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 796 (u32)(timeout > 255 ? 255 : timeout)); 797 } 798 799 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 800 { 801 u64 timeout; 802 803 timeout = msdc_timeout_cal(host, ns, clks); 804 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 805 (u32)(timeout > 8191 ? 8191 : timeout)); 806 } 807 808 static void msdc_gate_clock(struct msdc_host *host) 809 { 810 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 811 clk_disable_unprepare(host->src_clk_cg); 812 clk_disable_unprepare(host->src_clk); 813 clk_disable_unprepare(host->bus_clk); 814 clk_disable_unprepare(host->h_clk); 815 } 816 817 static void msdc_ungate_clock(struct msdc_host *host) 818 { 819 int ret; 820 821 clk_prepare_enable(host->h_clk); 822 clk_prepare_enable(host->bus_clk); 823 clk_prepare_enable(host->src_clk); 824 clk_prepare_enable(host->src_clk_cg); 825 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 826 if (ret) { 827 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 828 return; 829 } 830 831 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 832 cpu_relax(); 833 } 834 835 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 836 { 837 struct mmc_host *mmc = mmc_from_priv(host); 838 u32 mode; 839 u32 flags; 840 u32 div; 841 u32 sclk; 842 u32 tune_reg = host->dev_comp->pad_tune_reg; 843 844 if (!hz) { 845 dev_dbg(host->dev, "set mclk to 0\n"); 846 host->mclk = 0; 847 mmc->actual_clock = 0; 848 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 849 return; 850 } 851 852 flags = readl(host->base + MSDC_INTEN); 853 sdr_clr_bits(host->base + MSDC_INTEN, flags); 854 if (host->dev_comp->clk_div_bits == 8) 855 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 856 else 857 sdr_clr_bits(host->base + MSDC_CFG, 858 MSDC_CFG_HS400_CK_MODE_EXTRA); 859 if (timing == MMC_TIMING_UHS_DDR50 || 860 timing == MMC_TIMING_MMC_DDR52 || 861 timing == MMC_TIMING_MMC_HS400) { 862 if (timing == MMC_TIMING_MMC_HS400) 863 mode = 0x3; 864 else 865 mode = 0x2; /* ddr mode and use divisor */ 866 867 if (hz >= (host->src_clk_freq >> 2)) { 868 div = 0; /* mean div = 1/4 */ 869 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 870 } else { 871 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 872 sclk = (host->src_clk_freq >> 2) / div; 873 div = (div >> 1); 874 } 875 876 if (timing == MMC_TIMING_MMC_HS400 && 877 hz >= (host->src_clk_freq >> 1)) { 878 if (host->dev_comp->clk_div_bits == 8) 879 sdr_set_bits(host->base + MSDC_CFG, 880 MSDC_CFG_HS400_CK_MODE); 881 else 882 sdr_set_bits(host->base + MSDC_CFG, 883 MSDC_CFG_HS400_CK_MODE_EXTRA); 884 sclk = host->src_clk_freq >> 1; 885 div = 0; /* div is ignore when bit18 is set */ 886 } 887 } else if (hz >= host->src_clk_freq) { 888 mode = 0x1; /* no divisor */ 889 div = 0; 890 sclk = host->src_clk_freq; 891 } else { 892 mode = 0x0; /* use divisor */ 893 if (hz >= (host->src_clk_freq >> 1)) { 894 div = 0; /* mean div = 1/2 */ 895 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 896 } else { 897 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 898 sclk = (host->src_clk_freq >> 2) / div; 899 } 900 } 901 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 902 /* 903 * As src_clk/HCLK use the same bit to gate/ungate, 904 * So if want to only gate src_clk, need gate its parent(mux). 905 */ 906 if (host->src_clk_cg) 907 clk_disable_unprepare(host->src_clk_cg); 908 else 909 clk_disable_unprepare(clk_get_parent(host->src_clk)); 910 if (host->dev_comp->clk_div_bits == 8) 911 sdr_set_field(host->base + MSDC_CFG, 912 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 913 (mode << 8) | div); 914 else 915 sdr_set_field(host->base + MSDC_CFG, 916 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 917 (mode << 12) | div); 918 if (host->src_clk_cg) 919 clk_prepare_enable(host->src_clk_cg); 920 else 921 clk_prepare_enable(clk_get_parent(host->src_clk)); 922 923 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 924 cpu_relax(); 925 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 926 mmc->actual_clock = sclk; 927 host->mclk = hz; 928 host->timing = timing; 929 /* need because clk changed. */ 930 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 931 sdr_set_bits(host->base + MSDC_INTEN, flags); 932 933 /* 934 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 935 * tune result of hs200/200Mhz is not suitable for 50Mhz 936 */ 937 if (mmc->actual_clock <= 52000000) { 938 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 939 if (host->top_base) { 940 writel(host->def_tune_para.emmc_top_control, 941 host->top_base + EMMC_TOP_CONTROL); 942 writel(host->def_tune_para.emmc_top_cmd, 943 host->top_base + EMMC_TOP_CMD); 944 } else { 945 writel(host->def_tune_para.pad_tune, 946 host->base + tune_reg); 947 } 948 } else { 949 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 950 writel(host->saved_tune_para.pad_cmd_tune, 951 host->base + PAD_CMD_TUNE); 952 if (host->top_base) { 953 writel(host->saved_tune_para.emmc_top_control, 954 host->top_base + EMMC_TOP_CONTROL); 955 writel(host->saved_tune_para.emmc_top_cmd, 956 host->top_base + EMMC_TOP_CMD); 957 } else { 958 writel(host->saved_tune_para.pad_tune, 959 host->base + tune_reg); 960 } 961 } 962 963 if (timing == MMC_TIMING_MMC_HS400 && 964 host->dev_comp->hs400_tune) 965 sdr_set_field(host->base + tune_reg, 966 MSDC_PAD_TUNE_CMDRRDLY, 967 host->hs400_cmd_int_delay); 968 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 969 timing); 970 } 971 972 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 973 struct mmc_command *cmd) 974 { 975 u32 resp; 976 977 switch (mmc_resp_type(cmd)) { 978 /* Actually, R1, R5, R6, R7 are the same */ 979 case MMC_RSP_R1: 980 resp = 0x1; 981 break; 982 case MMC_RSP_R1B: 983 resp = 0x7; 984 break; 985 case MMC_RSP_R2: 986 resp = 0x2; 987 break; 988 case MMC_RSP_R3: 989 resp = 0x3; 990 break; 991 case MMC_RSP_NONE: 992 default: 993 resp = 0x0; 994 break; 995 } 996 997 return resp; 998 } 999 1000 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 1001 struct mmc_request *mrq, struct mmc_command *cmd) 1002 { 1003 struct mmc_host *mmc = mmc_from_priv(host); 1004 /* rawcmd : 1005 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 1006 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 1007 */ 1008 u32 opcode = cmd->opcode; 1009 u32 resp = msdc_cmd_find_resp(host, cmd); 1010 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1011 1012 host->cmd_rsp = resp; 1013 1014 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1015 opcode == MMC_STOP_TRANSMISSION) 1016 rawcmd |= (0x1 << 14); 1017 else if (opcode == SD_SWITCH_VOLTAGE) 1018 rawcmd |= (0x1 << 30); 1019 else if (opcode == SD_APP_SEND_SCR || 1020 opcode == SD_APP_SEND_NUM_WR_BLKS || 1021 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1022 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1023 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1024 rawcmd |= (0x1 << 11); 1025 1026 if (cmd->data) { 1027 struct mmc_data *data = cmd->data; 1028 1029 if (mmc_op_multi(opcode)) { 1030 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1031 !(mrq->sbc->arg & 0xFFFF0000)) 1032 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 1033 } 1034 1035 rawcmd |= ((data->blksz & 0xFFF) << 16); 1036 if (data->flags & MMC_DATA_WRITE) 1037 rawcmd |= (0x1 << 13); 1038 if (data->blocks > 1) 1039 rawcmd |= (0x2 << 11); 1040 else 1041 rawcmd |= (0x1 << 11); 1042 /* Always use dma mode */ 1043 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1044 1045 if (host->timeout_ns != data->timeout_ns || 1046 host->timeout_clks != data->timeout_clks) 1047 msdc_set_timeout(host, data->timeout_ns, 1048 data->timeout_clks); 1049 1050 writel(data->blocks, host->base + SDC_BLK_NUM); 1051 } 1052 return rawcmd; 1053 } 1054 1055 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1056 struct mmc_data *data) 1057 { 1058 bool read; 1059 1060 WARN_ON(host->data); 1061 host->data = data; 1062 read = data->flags & MMC_DATA_READ; 1063 1064 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1065 msdc_dma_setup(host, &host->dma, data); 1066 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1067 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1068 dev_dbg(host->dev, "DMA start\n"); 1069 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1070 __func__, cmd->opcode, data->blocks, read); 1071 } 1072 1073 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1074 struct mmc_command *cmd) 1075 { 1076 u32 *rsp = cmd->resp; 1077 1078 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1079 1080 if (events & MSDC_INT_ACMDRDY) { 1081 cmd->error = 0; 1082 } else { 1083 msdc_reset_hw(host); 1084 if (events & MSDC_INT_ACMDCRCERR) { 1085 cmd->error = -EILSEQ; 1086 host->error |= REQ_STOP_EIO; 1087 } else if (events & MSDC_INT_ACMDTMO) { 1088 cmd->error = -ETIMEDOUT; 1089 host->error |= REQ_STOP_TMO; 1090 } 1091 dev_err(host->dev, 1092 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1093 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1094 } 1095 return cmd->error; 1096 } 1097 1098 /* 1099 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1100 * 1101 * Host controller may lost interrupt in some special case. 1102 * Add SDIO irq recheck mechanism to make sure all interrupts 1103 * can be processed immediately 1104 */ 1105 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1106 { 1107 struct mmc_host *mmc = mmc_from_priv(host); 1108 u32 reg_int, reg_inten, reg_ps; 1109 1110 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1111 reg_inten = readl(host->base + MSDC_INTEN); 1112 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1113 reg_int = readl(host->base + MSDC_INT); 1114 reg_ps = readl(host->base + MSDC_PS); 1115 if (!(reg_int & MSDC_INT_SDIOIRQ || 1116 reg_ps & MSDC_PS_DATA1)) { 1117 __msdc_enable_sdio_irq(host, 0); 1118 sdio_signal_irq(mmc); 1119 } 1120 } 1121 } 1122 } 1123 1124 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 1125 { 1126 if (host->error) 1127 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1128 __func__, cmd->opcode, cmd->arg, host->error); 1129 } 1130 1131 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1132 { 1133 unsigned long flags; 1134 1135 /* 1136 * No need check the return value of cancel_delayed_work, as only ONE 1137 * path will go here! 1138 */ 1139 cancel_delayed_work(&host->req_timeout); 1140 1141 spin_lock_irqsave(&host->lock, flags); 1142 host->mrq = NULL; 1143 spin_unlock_irqrestore(&host->lock, flags); 1144 1145 msdc_track_cmd_data(host, mrq->cmd); 1146 if (mrq->data) 1147 msdc_unprepare_data(host, mrq->data); 1148 if (host->error) 1149 msdc_reset_hw(host); 1150 mmc_request_done(mmc_from_priv(host), mrq); 1151 if (host->dev_comp->recheck_sdio_irq) 1152 msdc_recheck_sdio_irq(host); 1153 } 1154 1155 /* returns true if command is fully handled; returns false otherwise */ 1156 static bool msdc_cmd_done(struct msdc_host *host, int events, 1157 struct mmc_request *mrq, struct mmc_command *cmd) 1158 { 1159 bool done = false; 1160 bool sbc_error; 1161 unsigned long flags; 1162 u32 *rsp; 1163 1164 if (mrq->sbc && cmd == mrq->cmd && 1165 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1166 | MSDC_INT_ACMDTMO))) 1167 msdc_auto_cmd_done(host, events, mrq->sbc); 1168 1169 sbc_error = mrq->sbc && mrq->sbc->error; 1170 1171 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1172 | MSDC_INT_RSPCRCERR 1173 | MSDC_INT_CMDTMO))) 1174 return done; 1175 1176 spin_lock_irqsave(&host->lock, flags); 1177 done = !host->cmd; 1178 host->cmd = NULL; 1179 spin_unlock_irqrestore(&host->lock, flags); 1180 1181 if (done) 1182 return true; 1183 rsp = cmd->resp; 1184 1185 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1186 1187 if (cmd->flags & MMC_RSP_PRESENT) { 1188 if (cmd->flags & MMC_RSP_136) { 1189 rsp[0] = readl(host->base + SDC_RESP3); 1190 rsp[1] = readl(host->base + SDC_RESP2); 1191 rsp[2] = readl(host->base + SDC_RESP1); 1192 rsp[3] = readl(host->base + SDC_RESP0); 1193 } else { 1194 rsp[0] = readl(host->base + SDC_RESP0); 1195 } 1196 } 1197 1198 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1199 if (events & MSDC_INT_CMDTMO || 1200 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1201 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1202 !host->hs400_tuning)) 1203 /* 1204 * should not clear fifo/interrupt as the tune data 1205 * may have alreay come when cmd19/cmd21 gets response 1206 * CRC error. 1207 */ 1208 msdc_reset_hw(host); 1209 if (events & MSDC_INT_RSPCRCERR) { 1210 cmd->error = -EILSEQ; 1211 host->error |= REQ_CMD_EIO; 1212 } else if (events & MSDC_INT_CMDTMO) { 1213 cmd->error = -ETIMEDOUT; 1214 host->error |= REQ_CMD_TMO; 1215 } 1216 } 1217 if (cmd->error) 1218 dev_dbg(host->dev, 1219 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1220 __func__, cmd->opcode, cmd->arg, rsp[0], 1221 cmd->error); 1222 1223 msdc_cmd_next(host, mrq, cmd); 1224 return true; 1225 } 1226 1227 /* It is the core layer's responsibility to ensure card status 1228 * is correct before issue a request. but host design do below 1229 * checks recommended. 1230 */ 1231 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1232 struct mmc_request *mrq, struct mmc_command *cmd) 1233 { 1234 /* The max busy time we can endure is 20ms */ 1235 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1236 1237 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1238 time_before(jiffies, tmo)) 1239 cpu_relax(); 1240 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1241 dev_err(host->dev, "CMD bus busy detected\n"); 1242 host->error |= REQ_CMD_BUSY; 1243 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1244 return false; 1245 } 1246 1247 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1248 tmo = jiffies + msecs_to_jiffies(20); 1249 /* R1B or with data, should check SDCBUSY */ 1250 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1251 time_before(jiffies, tmo)) 1252 cpu_relax(); 1253 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1254 dev_err(host->dev, "Controller busy detected\n"); 1255 host->error |= REQ_CMD_BUSY; 1256 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1257 return false; 1258 } 1259 } 1260 return true; 1261 } 1262 1263 static void msdc_start_command(struct msdc_host *host, 1264 struct mmc_request *mrq, struct mmc_command *cmd) 1265 { 1266 u32 rawcmd; 1267 unsigned long flags; 1268 1269 WARN_ON(host->cmd); 1270 host->cmd = cmd; 1271 1272 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1273 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1274 return; 1275 1276 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1277 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1278 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1279 msdc_reset_hw(host); 1280 } 1281 1282 cmd->error = 0; 1283 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1284 1285 spin_lock_irqsave(&host->lock, flags); 1286 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1287 spin_unlock_irqrestore(&host->lock, flags); 1288 1289 writel(cmd->arg, host->base + SDC_ARG); 1290 writel(rawcmd, host->base + SDC_CMD); 1291 } 1292 1293 static void msdc_cmd_next(struct msdc_host *host, 1294 struct mmc_request *mrq, struct mmc_command *cmd) 1295 { 1296 if ((cmd->error && 1297 !(cmd->error == -EILSEQ && 1298 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1299 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1300 host->hs400_tuning))) || 1301 (mrq->sbc && mrq->sbc->error)) 1302 msdc_request_done(host, mrq); 1303 else if (cmd == mrq->sbc) 1304 msdc_start_command(host, mrq, mrq->cmd); 1305 else if (!cmd->data) 1306 msdc_request_done(host, mrq); 1307 else 1308 msdc_start_data(host, cmd, cmd->data); 1309 } 1310 1311 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1312 { 1313 struct msdc_host *host = mmc_priv(mmc); 1314 1315 host->error = 0; 1316 WARN_ON(host->mrq); 1317 host->mrq = mrq; 1318 1319 if (mrq->data) 1320 msdc_prepare_data(host, mrq->data); 1321 1322 /* if SBC is required, we have HW option and SW option. 1323 * if HW option is enabled, and SBC does not have "special" flags, 1324 * use HW option, otherwise use SW option 1325 */ 1326 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1327 (mrq->sbc->arg & 0xFFFF0000))) 1328 msdc_start_command(host, mrq, mrq->sbc); 1329 else 1330 msdc_start_command(host, mrq, mrq->cmd); 1331 } 1332 1333 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1334 { 1335 struct msdc_host *host = mmc_priv(mmc); 1336 struct mmc_data *data = mrq->data; 1337 1338 if (!data) 1339 return; 1340 1341 msdc_prepare_data(host, data); 1342 data->host_cookie |= MSDC_ASYNC_FLAG; 1343 } 1344 1345 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1346 int err) 1347 { 1348 struct msdc_host *host = mmc_priv(mmc); 1349 struct mmc_data *data = mrq->data; 1350 1351 if (!data) 1352 return; 1353 1354 if (data->host_cookie) { 1355 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1356 msdc_unprepare_data(host, data); 1357 } 1358 } 1359 1360 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 1361 { 1362 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1363 !mrq->sbc) 1364 msdc_start_command(host, mrq, mrq->stop); 1365 else 1366 msdc_request_done(host, mrq); 1367 } 1368 1369 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1370 struct mmc_request *mrq, struct mmc_data *data) 1371 { 1372 struct mmc_command *stop; 1373 unsigned long flags; 1374 bool done; 1375 unsigned int check_data = events & 1376 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1377 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1378 | MSDC_INT_DMA_PROTECT); 1379 1380 spin_lock_irqsave(&host->lock, flags); 1381 done = !host->data; 1382 if (check_data) 1383 host->data = NULL; 1384 spin_unlock_irqrestore(&host->lock, flags); 1385 1386 if (done) 1387 return true; 1388 stop = data->stop; 1389 1390 if (check_data || (stop && stop->error)) { 1391 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1392 readl(host->base + MSDC_DMA_CFG)); 1393 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1394 1); 1395 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1396 cpu_relax(); 1397 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1398 dev_dbg(host->dev, "DMA stop\n"); 1399 1400 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1401 data->bytes_xfered = data->blocks * data->blksz; 1402 } else { 1403 dev_dbg(host->dev, "interrupt events: %x\n", events); 1404 msdc_reset_hw(host); 1405 host->error |= REQ_DAT_ERR; 1406 data->bytes_xfered = 0; 1407 1408 if (events & MSDC_INT_DATTMO) 1409 data->error = -ETIMEDOUT; 1410 else if (events & MSDC_INT_DATCRCERR) 1411 data->error = -EILSEQ; 1412 1413 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1414 __func__, mrq->cmd->opcode, data->blocks); 1415 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1416 (int)data->error, data->bytes_xfered); 1417 } 1418 1419 msdc_data_xfer_next(host, mrq); 1420 done = true; 1421 } 1422 return done; 1423 } 1424 1425 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1426 { 1427 u32 val = readl(host->base + SDC_CFG); 1428 1429 val &= ~SDC_CFG_BUSWIDTH; 1430 1431 switch (width) { 1432 default: 1433 case MMC_BUS_WIDTH_1: 1434 val |= (MSDC_BUS_1BITS << 16); 1435 break; 1436 case MMC_BUS_WIDTH_4: 1437 val |= (MSDC_BUS_4BITS << 16); 1438 break; 1439 case MMC_BUS_WIDTH_8: 1440 val |= (MSDC_BUS_8BITS << 16); 1441 break; 1442 } 1443 1444 writel(val, host->base + SDC_CFG); 1445 dev_dbg(host->dev, "Bus Width = %d", width); 1446 } 1447 1448 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1449 { 1450 struct msdc_host *host = mmc_priv(mmc); 1451 int ret; 1452 1453 if (!IS_ERR(mmc->supply.vqmmc)) { 1454 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1455 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1456 dev_err(host->dev, "Unsupported signal voltage!\n"); 1457 return -EINVAL; 1458 } 1459 1460 ret = mmc_regulator_set_vqmmc(mmc, ios); 1461 if (ret < 0) { 1462 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1463 ret, ios->signal_voltage); 1464 return ret; 1465 } 1466 1467 /* Apply different pinctrl settings for different signal voltage */ 1468 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1469 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1470 else 1471 pinctrl_select_state(host->pinctrl, host->pins_default); 1472 } 1473 return 0; 1474 } 1475 1476 static int msdc_card_busy(struct mmc_host *mmc) 1477 { 1478 struct msdc_host *host = mmc_priv(mmc); 1479 u32 status = readl(host->base + MSDC_PS); 1480 1481 /* only check if data0 is low */ 1482 return !(status & BIT(16)); 1483 } 1484 1485 static void msdc_request_timeout(struct work_struct *work) 1486 { 1487 struct msdc_host *host = container_of(work, struct msdc_host, 1488 req_timeout.work); 1489 1490 /* simulate HW timeout status */ 1491 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1492 if (host->mrq) { 1493 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1494 host->mrq, host->mrq->cmd->opcode); 1495 if (host->cmd) { 1496 dev_err(host->dev, "%s: aborting cmd=%d\n", 1497 __func__, host->cmd->opcode); 1498 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1499 host->cmd); 1500 } else if (host->data) { 1501 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1502 __func__, host->mrq->cmd->opcode, 1503 host->data->blocks); 1504 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1505 host->data); 1506 } 1507 } 1508 } 1509 1510 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1511 { 1512 if (enb) { 1513 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1514 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1515 if (host->dev_comp->recheck_sdio_irq) 1516 msdc_recheck_sdio_irq(host); 1517 } else { 1518 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1519 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1520 } 1521 } 1522 1523 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1524 { 1525 unsigned long flags; 1526 struct msdc_host *host = mmc_priv(mmc); 1527 1528 spin_lock_irqsave(&host->lock, flags); 1529 __msdc_enable_sdio_irq(host, enb); 1530 spin_unlock_irqrestore(&host->lock, flags); 1531 1532 if (enb) 1533 pm_runtime_get_noresume(host->dev); 1534 else 1535 pm_runtime_put_noidle(host->dev); 1536 } 1537 1538 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1539 { 1540 struct mmc_host *mmc = mmc_from_priv(host); 1541 int cmd_err = 0, dat_err = 0; 1542 1543 if (intsts & MSDC_INT_RSPCRCERR) { 1544 cmd_err = -EILSEQ; 1545 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1546 } else if (intsts & MSDC_INT_CMDTMO) { 1547 cmd_err = -ETIMEDOUT; 1548 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1549 } 1550 1551 if (intsts & MSDC_INT_DATCRCERR) { 1552 dat_err = -EILSEQ; 1553 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1554 } else if (intsts & MSDC_INT_DATTMO) { 1555 dat_err = -ETIMEDOUT; 1556 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1557 } 1558 1559 if (cmd_err || dat_err) { 1560 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1561 cmd_err, dat_err, intsts); 1562 } 1563 1564 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1565 } 1566 1567 static irqreturn_t msdc_irq(int irq, void *dev_id) 1568 { 1569 struct msdc_host *host = (struct msdc_host *) dev_id; 1570 struct mmc_host *mmc = mmc_from_priv(host); 1571 1572 while (true) { 1573 struct mmc_request *mrq; 1574 struct mmc_command *cmd; 1575 struct mmc_data *data; 1576 u32 events, event_mask; 1577 1578 spin_lock(&host->lock); 1579 events = readl(host->base + MSDC_INT); 1580 event_mask = readl(host->base + MSDC_INTEN); 1581 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1582 __msdc_enable_sdio_irq(host, 0); 1583 /* clear interrupts */ 1584 writel(events & event_mask, host->base + MSDC_INT); 1585 1586 mrq = host->mrq; 1587 cmd = host->cmd; 1588 data = host->data; 1589 spin_unlock(&host->lock); 1590 1591 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1592 sdio_signal_irq(mmc); 1593 1594 if ((events & event_mask) & MSDC_INT_CDSC) { 1595 if (host->internal_cd) 1596 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1597 events &= ~MSDC_INT_CDSC; 1598 } 1599 1600 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1601 break; 1602 1603 if ((mmc->caps2 & MMC_CAP2_CQE) && 1604 (events & MSDC_INT_CMDQ)) { 1605 msdc_cmdq_irq(host, events); 1606 /* clear interrupts */ 1607 writel(events, host->base + MSDC_INT); 1608 return IRQ_HANDLED; 1609 } 1610 1611 if (!mrq) { 1612 dev_err(host->dev, 1613 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1614 __func__, events, event_mask); 1615 WARN_ON(1); 1616 break; 1617 } 1618 1619 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1620 1621 if (cmd) 1622 msdc_cmd_done(host, events, mrq, cmd); 1623 else if (data) 1624 msdc_data_xfer_done(host, events, mrq, data); 1625 } 1626 1627 return IRQ_HANDLED; 1628 } 1629 1630 static void msdc_init_hw(struct msdc_host *host) 1631 { 1632 u32 val; 1633 u32 tune_reg = host->dev_comp->pad_tune_reg; 1634 1635 if (host->reset) { 1636 reset_control_assert(host->reset); 1637 usleep_range(10, 50); 1638 reset_control_deassert(host->reset); 1639 } 1640 1641 /* Configure to MMC/SD mode, clock free running */ 1642 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1643 1644 /* Reset */ 1645 msdc_reset_hw(host); 1646 1647 /* Disable and clear all interrupts */ 1648 writel(0, host->base + MSDC_INTEN); 1649 val = readl(host->base + MSDC_INT); 1650 writel(val, host->base + MSDC_INT); 1651 1652 /* Configure card detection */ 1653 if (host->internal_cd) { 1654 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1655 DEFAULT_DEBOUNCE); 1656 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1657 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1658 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1659 } else { 1660 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1661 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1662 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1663 } 1664 1665 if (host->top_base) { 1666 writel(0, host->top_base + EMMC_TOP_CONTROL); 1667 writel(0, host->top_base + EMMC_TOP_CMD); 1668 } else { 1669 writel(0, host->base + tune_reg); 1670 } 1671 writel(0, host->base + MSDC_IOCON); 1672 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1673 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1674 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1675 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1676 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1677 1678 if (host->dev_comp->stop_clk_fix) { 1679 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1680 MSDC_PATCH_BIT1_STOP_DLY, 3); 1681 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1682 SDC_FIFO_CFG_WRVALIDSEL); 1683 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1684 SDC_FIFO_CFG_RDVALIDSEL); 1685 } 1686 1687 if (host->dev_comp->busy_check) 1688 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1689 1690 if (host->dev_comp->async_fifo) { 1691 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1692 MSDC_PB2_RESPWAIT, 3); 1693 if (host->dev_comp->enhance_rx) { 1694 if (host->top_base) 1695 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1696 SDC_RX_ENH_EN); 1697 else 1698 sdr_set_bits(host->base + SDC_ADV_CFG0, 1699 SDC_RX_ENHANCE_EN); 1700 } else { 1701 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1702 MSDC_PB2_RESPSTSENSEL, 2); 1703 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1704 MSDC_PB2_CRCSTSENSEL, 2); 1705 } 1706 /* use async fifo, then no need tune internal delay */ 1707 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1708 MSDC_PATCH_BIT2_CFGRESP); 1709 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1710 MSDC_PATCH_BIT2_CFGCRCSTS); 1711 } 1712 1713 if (host->dev_comp->support_64g) 1714 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1715 MSDC_PB2_SUPPORT_64G); 1716 if (host->dev_comp->data_tune) { 1717 if (host->top_base) { 1718 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1719 PAD_DAT_RD_RXDLY_SEL); 1720 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1721 DATA_K_VALUE_SEL); 1722 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1723 PAD_CMD_RD_RXDLY_SEL); 1724 } else { 1725 sdr_set_bits(host->base + tune_reg, 1726 MSDC_PAD_TUNE_RD_SEL | 1727 MSDC_PAD_TUNE_CMD_SEL); 1728 } 1729 } else { 1730 /* choose clock tune */ 1731 if (host->top_base) 1732 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1733 PAD_RXDLY_SEL); 1734 else 1735 sdr_set_bits(host->base + tune_reg, 1736 MSDC_PAD_TUNE_RXDLYSEL); 1737 } 1738 1739 /* Configure to enable SDIO mode. 1740 * it's must otherwise sdio cmd5 failed 1741 */ 1742 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1743 1744 /* Config SDIO device detect interrupt function */ 1745 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1746 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1747 1748 /* Configure to default data timeout */ 1749 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1750 1751 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1752 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1753 if (host->top_base) { 1754 host->def_tune_para.emmc_top_control = 1755 readl(host->top_base + EMMC_TOP_CONTROL); 1756 host->def_tune_para.emmc_top_cmd = 1757 readl(host->top_base + EMMC_TOP_CMD); 1758 host->saved_tune_para.emmc_top_control = 1759 readl(host->top_base + EMMC_TOP_CONTROL); 1760 host->saved_tune_para.emmc_top_cmd = 1761 readl(host->top_base + EMMC_TOP_CMD); 1762 } else { 1763 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1764 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1765 } 1766 dev_dbg(host->dev, "init hardware done!"); 1767 } 1768 1769 static void msdc_deinit_hw(struct msdc_host *host) 1770 { 1771 u32 val; 1772 1773 if (host->internal_cd) { 1774 /* Disabled card-detect */ 1775 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1776 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1777 } 1778 1779 /* Disable and clear all interrupts */ 1780 writel(0, host->base + MSDC_INTEN); 1781 1782 val = readl(host->base + MSDC_INT); 1783 writel(val, host->base + MSDC_INT); 1784 } 1785 1786 /* init gpd and bd list in msdc_drv_probe */ 1787 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1788 { 1789 struct mt_gpdma_desc *gpd = dma->gpd; 1790 struct mt_bdma_desc *bd = dma->bd; 1791 dma_addr_t dma_addr; 1792 int i; 1793 1794 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1795 1796 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1797 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1798 /* gpd->next is must set for desc DMA 1799 * That's why must alloc 2 gpd structure. 1800 */ 1801 gpd->next = lower_32_bits(dma_addr); 1802 if (host->dev_comp->support_64g) 1803 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1804 1805 dma_addr = dma->bd_addr; 1806 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1807 if (host->dev_comp->support_64g) 1808 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1809 1810 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1811 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1812 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1813 bd[i].next = lower_32_bits(dma_addr); 1814 if (host->dev_comp->support_64g) 1815 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1816 } 1817 } 1818 1819 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1820 { 1821 struct msdc_host *host = mmc_priv(mmc); 1822 int ret; 1823 1824 msdc_set_buswidth(host, ios->bus_width); 1825 1826 /* Suspend/Resume will do power off/on */ 1827 switch (ios->power_mode) { 1828 case MMC_POWER_UP: 1829 if (!IS_ERR(mmc->supply.vmmc)) { 1830 msdc_init_hw(host); 1831 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1832 ios->vdd); 1833 if (ret) { 1834 dev_err(host->dev, "Failed to set vmmc power!\n"); 1835 return; 1836 } 1837 } 1838 break; 1839 case MMC_POWER_ON: 1840 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1841 ret = regulator_enable(mmc->supply.vqmmc); 1842 if (ret) 1843 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1844 else 1845 host->vqmmc_enabled = true; 1846 } 1847 break; 1848 case MMC_POWER_OFF: 1849 if (!IS_ERR(mmc->supply.vmmc)) 1850 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1851 1852 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1853 regulator_disable(mmc->supply.vqmmc); 1854 host->vqmmc_enabled = false; 1855 } 1856 break; 1857 default: 1858 break; 1859 } 1860 1861 if (host->mclk != ios->clock || host->timing != ios->timing) 1862 msdc_set_mclk(host, ios->timing, ios->clock); 1863 } 1864 1865 static u32 test_delay_bit(u32 delay, u32 bit) 1866 { 1867 bit %= PAD_DELAY_MAX; 1868 return delay & (1 << bit); 1869 } 1870 1871 static int get_delay_len(u32 delay, u32 start_bit) 1872 { 1873 int i; 1874 1875 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1876 if (test_delay_bit(delay, start_bit + i) == 0) 1877 return i; 1878 } 1879 return PAD_DELAY_MAX - start_bit; 1880 } 1881 1882 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1883 { 1884 int start = 0, len = 0; 1885 int start_final = 0, len_final = 0; 1886 u8 final_phase = 0xff; 1887 struct msdc_delay_phase delay_phase = { 0, }; 1888 1889 if (delay == 0) { 1890 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1891 delay_phase.final_phase = final_phase; 1892 return delay_phase; 1893 } 1894 1895 while (start < PAD_DELAY_MAX) { 1896 len = get_delay_len(delay, start); 1897 if (len_final < len) { 1898 start_final = start; 1899 len_final = len; 1900 } 1901 start += len ? len : 1; 1902 if (len >= 12 && start_final < 4) 1903 break; 1904 } 1905 1906 /* The rule is that to find the smallest delay cell */ 1907 if (start_final == 0) 1908 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1909 else 1910 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1911 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1912 delay, len_final, final_phase); 1913 1914 delay_phase.maxlen = len_final; 1915 delay_phase.start = start_final; 1916 delay_phase.final_phase = final_phase; 1917 return delay_phase; 1918 } 1919 1920 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1921 { 1922 u32 tune_reg = host->dev_comp->pad_tune_reg; 1923 1924 if (host->top_base) 1925 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1926 value); 1927 else 1928 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1929 value); 1930 } 1931 1932 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1933 { 1934 u32 tune_reg = host->dev_comp->pad_tune_reg; 1935 1936 if (host->top_base) 1937 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1938 PAD_DAT_RD_RXDLY, value); 1939 else 1940 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1941 value); 1942 } 1943 1944 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1945 { 1946 struct msdc_host *host = mmc_priv(mmc); 1947 u32 rise_delay = 0, fall_delay = 0; 1948 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1949 struct msdc_delay_phase internal_delay_phase; 1950 u8 final_delay, final_maxlen; 1951 u32 internal_delay = 0; 1952 u32 tune_reg = host->dev_comp->pad_tune_reg; 1953 int cmd_err; 1954 int i, j; 1955 1956 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1957 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1958 sdr_set_field(host->base + tune_reg, 1959 MSDC_PAD_TUNE_CMDRRDLY, 1960 host->hs200_cmd_int_delay); 1961 1962 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1963 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1964 msdc_set_cmd_delay(host, i); 1965 /* 1966 * Using the same parameters, it may sometimes pass the test, 1967 * but sometimes it may fail. To make sure the parameters are 1968 * more stable, we test each set of parameters 3 times. 1969 */ 1970 for (j = 0; j < 3; j++) { 1971 mmc_send_tuning(mmc, opcode, &cmd_err); 1972 if (!cmd_err) { 1973 rise_delay |= (1 << i); 1974 } else { 1975 rise_delay &= ~(1 << i); 1976 break; 1977 } 1978 } 1979 } 1980 final_rise_delay = get_best_delay(host, rise_delay); 1981 /* if rising edge has enough margin, then do not scan falling edge */ 1982 if (final_rise_delay.maxlen >= 12 || 1983 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1984 goto skip_fall; 1985 1986 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1987 for (i = 0; i < PAD_DELAY_MAX; i++) { 1988 msdc_set_cmd_delay(host, i); 1989 /* 1990 * Using the same parameters, it may sometimes pass the test, 1991 * but sometimes it may fail. To make sure the parameters are 1992 * more stable, we test each set of parameters 3 times. 1993 */ 1994 for (j = 0; j < 3; j++) { 1995 mmc_send_tuning(mmc, opcode, &cmd_err); 1996 if (!cmd_err) { 1997 fall_delay |= (1 << i); 1998 } else { 1999 fall_delay &= ~(1 << i); 2000 break; 2001 } 2002 } 2003 } 2004 final_fall_delay = get_best_delay(host, fall_delay); 2005 2006 skip_fall: 2007 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2008 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2009 final_maxlen = final_fall_delay.maxlen; 2010 if (final_maxlen == final_rise_delay.maxlen) { 2011 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2012 final_delay = final_rise_delay.final_phase; 2013 } else { 2014 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2015 final_delay = final_fall_delay.final_phase; 2016 } 2017 msdc_set_cmd_delay(host, final_delay); 2018 2019 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2020 goto skip_internal; 2021 2022 for (i = 0; i < PAD_DELAY_MAX; i++) { 2023 sdr_set_field(host->base + tune_reg, 2024 MSDC_PAD_TUNE_CMDRRDLY, i); 2025 mmc_send_tuning(mmc, opcode, &cmd_err); 2026 if (!cmd_err) 2027 internal_delay |= (1 << i); 2028 } 2029 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2030 internal_delay_phase = get_best_delay(host, internal_delay); 2031 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2032 internal_delay_phase.final_phase); 2033 skip_internal: 2034 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2035 return final_delay == 0xff ? -EIO : 0; 2036 } 2037 2038 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2039 { 2040 struct msdc_host *host = mmc_priv(mmc); 2041 u32 cmd_delay = 0; 2042 struct msdc_delay_phase final_cmd_delay = { 0,}; 2043 u8 final_delay; 2044 int cmd_err; 2045 int i, j; 2046 2047 /* select EMMC50 PAD CMD tune */ 2048 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2049 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2050 2051 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2052 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2053 sdr_set_field(host->base + MSDC_PAD_TUNE, 2054 MSDC_PAD_TUNE_CMDRRDLY, 2055 host->hs200_cmd_int_delay); 2056 2057 if (host->hs400_cmd_resp_sel_rising) 2058 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2059 else 2060 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2061 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2062 sdr_set_field(host->base + PAD_CMD_TUNE, 2063 PAD_CMD_TUNE_RX_DLY3, i); 2064 /* 2065 * Using the same parameters, it may sometimes pass the test, 2066 * but sometimes it may fail. To make sure the parameters are 2067 * more stable, we test each set of parameters 3 times. 2068 */ 2069 for (j = 0; j < 3; j++) { 2070 mmc_send_tuning(mmc, opcode, &cmd_err); 2071 if (!cmd_err) { 2072 cmd_delay |= (1 << i); 2073 } else { 2074 cmd_delay &= ~(1 << i); 2075 break; 2076 } 2077 } 2078 } 2079 final_cmd_delay = get_best_delay(host, cmd_delay); 2080 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2081 final_cmd_delay.final_phase); 2082 final_delay = final_cmd_delay.final_phase; 2083 2084 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2085 return final_delay == 0xff ? -EIO : 0; 2086 } 2087 2088 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2089 { 2090 struct msdc_host *host = mmc_priv(mmc); 2091 u32 rise_delay = 0, fall_delay = 0; 2092 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2093 u8 final_delay, final_maxlen; 2094 int i, ret; 2095 2096 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2097 host->latch_ck); 2098 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2099 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2100 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2101 msdc_set_data_delay(host, i); 2102 ret = mmc_send_tuning(mmc, opcode, NULL); 2103 if (!ret) 2104 rise_delay |= (1 << i); 2105 } 2106 final_rise_delay = get_best_delay(host, rise_delay); 2107 /* if rising edge has enough margin, then do not scan falling edge */ 2108 if (final_rise_delay.maxlen >= 12 || 2109 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2110 goto skip_fall; 2111 2112 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2113 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2114 for (i = 0; i < PAD_DELAY_MAX; i++) { 2115 msdc_set_data_delay(host, i); 2116 ret = mmc_send_tuning(mmc, opcode, NULL); 2117 if (!ret) 2118 fall_delay |= (1 << i); 2119 } 2120 final_fall_delay = get_best_delay(host, fall_delay); 2121 2122 skip_fall: 2123 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2124 if (final_maxlen == final_rise_delay.maxlen) { 2125 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2126 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2127 final_delay = final_rise_delay.final_phase; 2128 } else { 2129 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2130 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2131 final_delay = final_fall_delay.final_phase; 2132 } 2133 msdc_set_data_delay(host, final_delay); 2134 2135 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2136 return final_delay == 0xff ? -EIO : 0; 2137 } 2138 2139 /* 2140 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2141 * together, which can save the tuning time. 2142 */ 2143 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2144 { 2145 struct msdc_host *host = mmc_priv(mmc); 2146 u32 rise_delay = 0, fall_delay = 0; 2147 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2148 u8 final_delay, final_maxlen; 2149 int i, ret; 2150 2151 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2152 host->latch_ck); 2153 2154 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2155 sdr_clr_bits(host->base + MSDC_IOCON, 2156 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2157 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2158 msdc_set_cmd_delay(host, i); 2159 msdc_set_data_delay(host, i); 2160 ret = mmc_send_tuning(mmc, opcode, NULL); 2161 if (!ret) 2162 rise_delay |= (1 << i); 2163 } 2164 final_rise_delay = get_best_delay(host, rise_delay); 2165 /* if rising edge has enough margin, then do not scan falling edge */ 2166 if (final_rise_delay.maxlen >= 12 || 2167 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2168 goto skip_fall; 2169 2170 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2171 sdr_set_bits(host->base + MSDC_IOCON, 2172 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2173 for (i = 0; i < PAD_DELAY_MAX; i++) { 2174 msdc_set_cmd_delay(host, i); 2175 msdc_set_data_delay(host, i); 2176 ret = mmc_send_tuning(mmc, opcode, NULL); 2177 if (!ret) 2178 fall_delay |= (1 << i); 2179 } 2180 final_fall_delay = get_best_delay(host, fall_delay); 2181 2182 skip_fall: 2183 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2184 if (final_maxlen == final_rise_delay.maxlen) { 2185 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2186 sdr_clr_bits(host->base + MSDC_IOCON, 2187 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2188 final_delay = final_rise_delay.final_phase; 2189 } else { 2190 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2191 sdr_set_bits(host->base + MSDC_IOCON, 2192 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2193 final_delay = final_fall_delay.final_phase; 2194 } 2195 2196 msdc_set_cmd_delay(host, final_delay); 2197 msdc_set_data_delay(host, final_delay); 2198 2199 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2200 return final_delay == 0xff ? -EIO : 0; 2201 } 2202 2203 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2204 { 2205 struct msdc_host *host = mmc_priv(mmc); 2206 int ret; 2207 u32 tune_reg = host->dev_comp->pad_tune_reg; 2208 2209 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2210 ret = msdc_tune_together(mmc, opcode); 2211 if (host->hs400_mode) { 2212 sdr_clr_bits(host->base + MSDC_IOCON, 2213 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2214 msdc_set_data_delay(host, 0); 2215 } 2216 goto tune_done; 2217 } 2218 if (host->hs400_mode && 2219 host->dev_comp->hs400_tune) 2220 ret = hs400_tune_response(mmc, opcode); 2221 else 2222 ret = msdc_tune_response(mmc, opcode); 2223 if (ret == -EIO) { 2224 dev_err(host->dev, "Tune response fail!\n"); 2225 return ret; 2226 } 2227 if (host->hs400_mode == false) { 2228 ret = msdc_tune_data(mmc, opcode); 2229 if (ret == -EIO) 2230 dev_err(host->dev, "Tune data fail!\n"); 2231 } 2232 2233 tune_done: 2234 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2235 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2236 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2237 if (host->top_base) { 2238 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2239 EMMC_TOP_CONTROL); 2240 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2241 EMMC_TOP_CMD); 2242 } 2243 return ret; 2244 } 2245 2246 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2247 { 2248 struct msdc_host *host = mmc_priv(mmc); 2249 host->hs400_mode = true; 2250 2251 if (host->top_base) 2252 writel(host->hs400_ds_delay, 2253 host->top_base + EMMC50_PAD_DS_TUNE); 2254 else 2255 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2256 /* hs400 mode must set it to 0 */ 2257 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2258 /* to improve read performance, set outstanding to 2 */ 2259 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2260 2261 return 0; 2262 } 2263 2264 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2265 { 2266 struct msdc_host *host = mmc_priv(mmc); 2267 struct msdc_delay_phase dly1_delay; 2268 u32 val, result_dly1 = 0; 2269 u8 *ext_csd; 2270 int i, ret; 2271 2272 if (host->top_base) { 2273 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2274 PAD_DS_DLY_SEL); 2275 if (host->hs400_ds_dly3) 2276 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2277 PAD_DS_DLY3, host->hs400_ds_dly3); 2278 } else { 2279 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2280 if (host->hs400_ds_dly3) 2281 sdr_set_field(host->base + PAD_DS_TUNE, 2282 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2283 } 2284 2285 host->hs400_tuning = true; 2286 for (i = 0; i < PAD_DELAY_MAX; i++) { 2287 if (host->top_base) 2288 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2289 PAD_DS_DLY1, i); 2290 else 2291 sdr_set_field(host->base + PAD_DS_TUNE, 2292 PAD_DS_TUNE_DLY1, i); 2293 ret = mmc_get_ext_csd(card, &ext_csd); 2294 if (!ret) 2295 result_dly1 |= (1 << i); 2296 } 2297 host->hs400_tuning = false; 2298 2299 dly1_delay = get_best_delay(host, result_dly1); 2300 if (dly1_delay.maxlen == 0) { 2301 dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2302 goto fail; 2303 } 2304 if (host->top_base) 2305 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2306 PAD_DS_DLY1, dly1_delay.final_phase); 2307 else 2308 sdr_set_field(host->base + PAD_DS_TUNE, 2309 PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2310 2311 if (host->top_base) 2312 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2313 else 2314 val = readl(host->base + PAD_DS_TUNE); 2315 2316 dev_info(host->dev, "Fianl PAD_DS_TUNE: 0x%x\n", val); 2317 2318 return 0; 2319 2320 fail: 2321 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2322 return -EIO; 2323 } 2324 2325 static void msdc_hw_reset(struct mmc_host *mmc) 2326 { 2327 struct msdc_host *host = mmc_priv(mmc); 2328 2329 sdr_set_bits(host->base + EMMC_IOCON, 1); 2330 udelay(10); /* 10us is enough */ 2331 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2332 } 2333 2334 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2335 { 2336 unsigned long flags; 2337 struct msdc_host *host = mmc_priv(mmc); 2338 2339 spin_lock_irqsave(&host->lock, flags); 2340 __msdc_enable_sdio_irq(host, 1); 2341 spin_unlock_irqrestore(&host->lock, flags); 2342 } 2343 2344 static int msdc_get_cd(struct mmc_host *mmc) 2345 { 2346 struct msdc_host *host = mmc_priv(mmc); 2347 int val; 2348 2349 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2350 return 1; 2351 2352 if (!host->internal_cd) 2353 return mmc_gpio_get_cd(mmc); 2354 2355 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2356 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2357 return !!val; 2358 else 2359 return !val; 2360 } 2361 2362 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2363 struct mmc_ios *ios) 2364 { 2365 struct msdc_host *host = mmc_priv(mmc); 2366 2367 if (ios->enhanced_strobe) { 2368 msdc_prepare_hs400_tuning(mmc, ios); 2369 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2370 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2371 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2372 2373 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2374 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2375 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2376 } else { 2377 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2378 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2379 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2380 2381 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2382 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2383 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2384 } 2385 } 2386 2387 static void msdc_cqe_enable(struct mmc_host *mmc) 2388 { 2389 struct msdc_host *host = mmc_priv(mmc); 2390 2391 /* enable cmdq irq */ 2392 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2393 /* enable busy check */ 2394 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2395 /* default write data / busy timeout 20s */ 2396 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2397 /* default read data timeout 1s */ 2398 msdc_set_timeout(host, 1000000000ULL, 0); 2399 } 2400 2401 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2402 { 2403 struct msdc_host *host = mmc_priv(mmc); 2404 unsigned int val = 0; 2405 2406 /* disable cmdq irq */ 2407 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2408 /* disable busy check */ 2409 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2410 2411 if (recovery) { 2412 sdr_set_field(host->base + MSDC_DMA_CTRL, 2413 MSDC_DMA_CTRL_STOP, 1); 2414 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 2415 !(val & MSDC_DMA_CFG_STS), 1, 3000))) 2416 return; 2417 msdc_reset_hw(host); 2418 } 2419 } 2420 2421 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2422 { 2423 struct cqhci_host *cq_host = mmc->cqe_private; 2424 u32 reg; 2425 2426 reg = cqhci_readl(cq_host, CQHCI_CFG); 2427 reg |= CQHCI_ENABLE; 2428 cqhci_writel(cq_host, reg, CQHCI_CFG); 2429 } 2430 2431 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2432 { 2433 struct cqhci_host *cq_host = mmc->cqe_private; 2434 u32 reg; 2435 2436 reg = cqhci_readl(cq_host, CQHCI_CFG); 2437 reg &= ~CQHCI_ENABLE; 2438 cqhci_writel(cq_host, reg, CQHCI_CFG); 2439 } 2440 2441 static const struct mmc_host_ops mt_msdc_ops = { 2442 .post_req = msdc_post_req, 2443 .pre_req = msdc_pre_req, 2444 .request = msdc_ops_request, 2445 .set_ios = msdc_ops_set_ios, 2446 .get_ro = mmc_gpio_get_ro, 2447 .get_cd = msdc_get_cd, 2448 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2449 .enable_sdio_irq = msdc_enable_sdio_irq, 2450 .ack_sdio_irq = msdc_ack_sdio_irq, 2451 .start_signal_voltage_switch = msdc_ops_switch_volt, 2452 .card_busy = msdc_card_busy, 2453 .execute_tuning = msdc_execute_tuning, 2454 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2455 .execute_hs400_tuning = msdc_execute_hs400_tuning, 2456 .hw_reset = msdc_hw_reset, 2457 }; 2458 2459 static const struct cqhci_host_ops msdc_cmdq_ops = { 2460 .enable = msdc_cqe_enable, 2461 .disable = msdc_cqe_disable, 2462 .pre_enable = msdc_cqe_pre_enable, 2463 .post_disable = msdc_cqe_post_disable, 2464 }; 2465 2466 static void msdc_of_property_parse(struct platform_device *pdev, 2467 struct msdc_host *host) 2468 { 2469 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2470 &host->latch_ck); 2471 2472 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2473 &host->hs400_ds_delay); 2474 2475 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2476 &host->hs400_ds_dly3); 2477 2478 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2479 &host->hs200_cmd_int_delay); 2480 2481 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2482 &host->hs400_cmd_int_delay); 2483 2484 if (of_property_read_bool(pdev->dev.of_node, 2485 "mediatek,hs400-cmd-resp-sel-rising")) 2486 host->hs400_cmd_resp_sel_rising = true; 2487 else 2488 host->hs400_cmd_resp_sel_rising = false; 2489 2490 if (of_property_read_bool(pdev->dev.of_node, 2491 "supports-cqe")) 2492 host->cqhci = true; 2493 else 2494 host->cqhci = false; 2495 } 2496 2497 static int msdc_of_clock_parse(struct platform_device *pdev, 2498 struct msdc_host *host) 2499 { 2500 int ret; 2501 2502 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2503 if (IS_ERR(host->src_clk)) 2504 return PTR_ERR(host->src_clk); 2505 2506 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2507 if (IS_ERR(host->h_clk)) 2508 return PTR_ERR(host->h_clk); 2509 2510 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2511 if (IS_ERR(host->bus_clk)) 2512 host->bus_clk = NULL; 2513 2514 /*source clock control gate is optional clock*/ 2515 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2516 if (IS_ERR(host->src_clk_cg)) 2517 host->src_clk_cg = NULL; 2518 2519 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2520 if (IS_ERR(host->sys_clk_cg)) 2521 host->sys_clk_cg = NULL; 2522 2523 /* If present, always enable for this clock gate */ 2524 clk_prepare_enable(host->sys_clk_cg); 2525 2526 host->bulk_clks[0].id = "pclk_cg"; 2527 host->bulk_clks[1].id = "axi_cg"; 2528 host->bulk_clks[2].id = "ahb_cg"; 2529 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2530 host->bulk_clks); 2531 if (ret) { 2532 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2533 return ret; 2534 } 2535 2536 return 0; 2537 } 2538 2539 static int msdc_drv_probe(struct platform_device *pdev) 2540 { 2541 struct mmc_host *mmc; 2542 struct msdc_host *host; 2543 struct resource *res; 2544 int ret; 2545 2546 if (!pdev->dev.of_node) { 2547 dev_err(&pdev->dev, "No DT found\n"); 2548 return -EINVAL; 2549 } 2550 2551 /* Allocate MMC host for this device */ 2552 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2553 if (!mmc) 2554 return -ENOMEM; 2555 2556 host = mmc_priv(mmc); 2557 ret = mmc_of_parse(mmc); 2558 if (ret) 2559 goto host_free; 2560 2561 host->base = devm_platform_ioremap_resource(pdev, 0); 2562 if (IS_ERR(host->base)) { 2563 ret = PTR_ERR(host->base); 2564 goto host_free; 2565 } 2566 2567 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2568 if (res) { 2569 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2570 if (IS_ERR(host->top_base)) 2571 host->top_base = NULL; 2572 } 2573 2574 ret = mmc_regulator_get_supply(mmc); 2575 if (ret) 2576 goto host_free; 2577 2578 ret = msdc_of_clock_parse(pdev, host); 2579 if (ret) 2580 goto host_free; 2581 2582 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2583 "hrst"); 2584 if (IS_ERR(host->reset)) { 2585 ret = PTR_ERR(host->reset); 2586 goto host_free; 2587 } 2588 2589 host->irq = platform_get_irq(pdev, 0); 2590 if (host->irq < 0) { 2591 ret = -EINVAL; 2592 goto host_free; 2593 } 2594 2595 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2596 if (IS_ERR(host->pinctrl)) { 2597 ret = PTR_ERR(host->pinctrl); 2598 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2599 goto host_free; 2600 } 2601 2602 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2603 if (IS_ERR(host->pins_default)) { 2604 ret = PTR_ERR(host->pins_default); 2605 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2606 goto host_free; 2607 } 2608 2609 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2610 if (IS_ERR(host->pins_uhs)) { 2611 ret = PTR_ERR(host->pins_uhs); 2612 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2613 goto host_free; 2614 } 2615 2616 msdc_of_property_parse(pdev, host); 2617 2618 host->dev = &pdev->dev; 2619 host->dev_comp = of_device_get_match_data(&pdev->dev); 2620 host->src_clk_freq = clk_get_rate(host->src_clk); 2621 /* Set host parameters to mmc */ 2622 mmc->ops = &mt_msdc_ops; 2623 if (host->dev_comp->clk_div_bits == 8) 2624 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2625 else 2626 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2627 2628 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2629 !mmc_can_gpio_cd(mmc) && 2630 host->dev_comp->use_internal_cd) { 2631 /* 2632 * Is removable but no GPIO declared, so 2633 * use internal functionality. 2634 */ 2635 host->internal_cd = true; 2636 } 2637 2638 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2639 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2640 2641 mmc->caps |= MMC_CAP_CMD23; 2642 if (host->cqhci) 2643 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2644 /* MMC core transfer sizes tunable parameters */ 2645 mmc->max_segs = MAX_BD_NUM; 2646 if (host->dev_comp->support_64g) 2647 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2648 else 2649 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2650 mmc->max_blk_size = 2048; 2651 mmc->max_req_size = 512 * 1024; 2652 mmc->max_blk_count = mmc->max_req_size / 512; 2653 if (host->dev_comp->support_64g) 2654 host->dma_mask = DMA_BIT_MASK(36); 2655 else 2656 host->dma_mask = DMA_BIT_MASK(32); 2657 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2658 2659 host->timeout_clks = 3 * 1048576; 2660 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2661 2 * sizeof(struct mt_gpdma_desc), 2662 &host->dma.gpd_addr, GFP_KERNEL); 2663 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2664 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2665 &host->dma.bd_addr, GFP_KERNEL); 2666 if (!host->dma.gpd || !host->dma.bd) { 2667 ret = -ENOMEM; 2668 goto release_mem; 2669 } 2670 msdc_init_gpd_bd(host, &host->dma); 2671 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2672 spin_lock_init(&host->lock); 2673 2674 platform_set_drvdata(pdev, mmc); 2675 msdc_ungate_clock(host); 2676 msdc_init_hw(host); 2677 2678 if (mmc->caps2 & MMC_CAP2_CQE) { 2679 host->cq_host = devm_kzalloc(mmc->parent, 2680 sizeof(*host->cq_host), 2681 GFP_KERNEL); 2682 if (!host->cq_host) { 2683 ret = -ENOMEM; 2684 goto host_free; 2685 } 2686 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2687 host->cq_host->mmio = host->base + 0x800; 2688 host->cq_host->ops = &msdc_cmdq_ops; 2689 ret = cqhci_init(host->cq_host, mmc, true); 2690 if (ret) 2691 goto host_free; 2692 mmc->max_segs = 128; 2693 /* cqhci 16bit length */ 2694 /* 0 size, means 65536 so we don't have to -1 here */ 2695 mmc->max_seg_size = 64 * 1024; 2696 } 2697 2698 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2699 IRQF_TRIGGER_NONE, pdev->name, host); 2700 if (ret) 2701 goto release; 2702 2703 pm_runtime_set_active(host->dev); 2704 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2705 pm_runtime_use_autosuspend(host->dev); 2706 pm_runtime_enable(host->dev); 2707 ret = mmc_add_host(mmc); 2708 2709 if (ret) 2710 goto end; 2711 2712 return 0; 2713 end: 2714 pm_runtime_disable(host->dev); 2715 release: 2716 platform_set_drvdata(pdev, NULL); 2717 msdc_deinit_hw(host); 2718 msdc_gate_clock(host); 2719 release_mem: 2720 if (host->dma.gpd) 2721 dma_free_coherent(&pdev->dev, 2722 2 * sizeof(struct mt_gpdma_desc), 2723 host->dma.gpd, host->dma.gpd_addr); 2724 if (host->dma.bd) 2725 dma_free_coherent(&pdev->dev, 2726 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2727 host->dma.bd, host->dma.bd_addr); 2728 host_free: 2729 mmc_free_host(mmc); 2730 2731 return ret; 2732 } 2733 2734 static int msdc_drv_remove(struct platform_device *pdev) 2735 { 2736 struct mmc_host *mmc; 2737 struct msdc_host *host; 2738 2739 mmc = platform_get_drvdata(pdev); 2740 host = mmc_priv(mmc); 2741 2742 pm_runtime_get_sync(host->dev); 2743 2744 platform_set_drvdata(pdev, NULL); 2745 mmc_remove_host(mmc); 2746 msdc_deinit_hw(host); 2747 msdc_gate_clock(host); 2748 2749 pm_runtime_disable(host->dev); 2750 pm_runtime_put_noidle(host->dev); 2751 dma_free_coherent(&pdev->dev, 2752 2 * sizeof(struct mt_gpdma_desc), 2753 host->dma.gpd, host->dma.gpd_addr); 2754 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2755 host->dma.bd, host->dma.bd_addr); 2756 2757 mmc_free_host(mmc); 2758 2759 return 0; 2760 } 2761 2762 static void msdc_save_reg(struct msdc_host *host) 2763 { 2764 u32 tune_reg = host->dev_comp->pad_tune_reg; 2765 2766 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2767 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2768 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2769 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2770 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2771 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2772 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2773 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2774 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2775 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2776 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2777 if (host->top_base) { 2778 host->save_para.emmc_top_control = 2779 readl(host->top_base + EMMC_TOP_CONTROL); 2780 host->save_para.emmc_top_cmd = 2781 readl(host->top_base + EMMC_TOP_CMD); 2782 host->save_para.emmc50_pad_ds_tune = 2783 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2784 } else { 2785 host->save_para.pad_tune = readl(host->base + tune_reg); 2786 } 2787 } 2788 2789 static void msdc_restore_reg(struct msdc_host *host) 2790 { 2791 struct mmc_host *mmc = mmc_from_priv(host); 2792 u32 tune_reg = host->dev_comp->pad_tune_reg; 2793 2794 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2795 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2796 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2797 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2798 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2799 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2800 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2801 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2802 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2803 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2804 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2805 if (host->top_base) { 2806 writel(host->save_para.emmc_top_control, 2807 host->top_base + EMMC_TOP_CONTROL); 2808 writel(host->save_para.emmc_top_cmd, 2809 host->top_base + EMMC_TOP_CMD); 2810 writel(host->save_para.emmc50_pad_ds_tune, 2811 host->top_base + EMMC50_PAD_DS_TUNE); 2812 } else { 2813 writel(host->save_para.pad_tune, host->base + tune_reg); 2814 } 2815 2816 if (sdio_irq_claimed(mmc)) 2817 __msdc_enable_sdio_irq(host, 1); 2818 } 2819 2820 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2821 { 2822 struct mmc_host *mmc = dev_get_drvdata(dev); 2823 struct msdc_host *host = mmc_priv(mmc); 2824 2825 msdc_save_reg(host); 2826 msdc_gate_clock(host); 2827 return 0; 2828 } 2829 2830 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2831 { 2832 struct mmc_host *mmc = dev_get_drvdata(dev); 2833 struct msdc_host *host = mmc_priv(mmc); 2834 2835 msdc_ungate_clock(host); 2836 msdc_restore_reg(host); 2837 return 0; 2838 } 2839 2840 static int __maybe_unused msdc_suspend(struct device *dev) 2841 { 2842 struct mmc_host *mmc = dev_get_drvdata(dev); 2843 int ret; 2844 2845 if (mmc->caps2 & MMC_CAP2_CQE) { 2846 ret = cqhci_suspend(mmc); 2847 if (ret) 2848 return ret; 2849 } 2850 2851 return pm_runtime_force_suspend(dev); 2852 } 2853 2854 static int __maybe_unused msdc_resume(struct device *dev) 2855 { 2856 return pm_runtime_force_resume(dev); 2857 } 2858 2859 static const struct dev_pm_ops msdc_dev_pm_ops = { 2860 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2861 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2862 }; 2863 2864 static struct platform_driver mt_msdc_driver = { 2865 .probe = msdc_drv_probe, 2866 .remove = msdc_drv_remove, 2867 .driver = { 2868 .name = "mtk-msdc", 2869 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2870 .of_match_table = msdc_of_ids, 2871 .pm = &msdc_dev_pm_ops, 2872 }, 2873 }; 2874 2875 module_platform_driver(mt_msdc_driver); 2876 MODULE_LICENSE("GPL v2"); 2877 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2878