1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/bitops.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/iopoll.h> 13 #include <linux/ioport.h> 14 #include <linux/irq.h> 15 #include <linux/of_address.h> 16 #include <linux/of_device.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_gpio.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/regulator/consumer.h> 24 #include <linux/slab.h> 25 #include <linux/spinlock.h> 26 #include <linux/interrupt.h> 27 #include <linux/reset.h> 28 29 #include <linux/mmc/card.h> 30 #include <linux/mmc/core.h> 31 #include <linux/mmc/host.h> 32 #include <linux/mmc/mmc.h> 33 #include <linux/mmc/sd.h> 34 #include <linux/mmc/sdio.h> 35 #include <linux/mmc/slot-gpio.h> 36 37 #include "cqhci.h" 38 39 #define MAX_BD_NUM 1024 40 #define MSDC_NR_CLOCKS 3 41 42 /*--------------------------------------------------------------------------*/ 43 /* Common Definition */ 44 /*--------------------------------------------------------------------------*/ 45 #define MSDC_BUS_1BITS 0x0 46 #define MSDC_BUS_4BITS 0x1 47 #define MSDC_BUS_8BITS 0x2 48 49 #define MSDC_BURST_64B 0x6 50 51 /*--------------------------------------------------------------------------*/ 52 /* Register Offset */ 53 /*--------------------------------------------------------------------------*/ 54 #define MSDC_CFG 0x0 55 #define MSDC_IOCON 0x04 56 #define MSDC_PS 0x08 57 #define MSDC_INT 0x0c 58 #define MSDC_INTEN 0x10 59 #define MSDC_FIFOCS 0x14 60 #define SDC_CFG 0x30 61 #define SDC_CMD 0x34 62 #define SDC_ARG 0x38 63 #define SDC_STS 0x3c 64 #define SDC_RESP0 0x40 65 #define SDC_RESP1 0x44 66 #define SDC_RESP2 0x48 67 #define SDC_RESP3 0x4c 68 #define SDC_BLK_NUM 0x50 69 #define SDC_ADV_CFG0 0x64 70 #define EMMC_IOCON 0x7c 71 #define SDC_ACMD_RESP 0x80 72 #define DMA_SA_H4BIT 0x8c 73 #define MSDC_DMA_SA 0x90 74 #define MSDC_DMA_CTRL 0x98 75 #define MSDC_DMA_CFG 0x9c 76 #define MSDC_PATCH_BIT 0xb0 77 #define MSDC_PATCH_BIT1 0xb4 78 #define MSDC_PATCH_BIT2 0xb8 79 #define MSDC_PAD_TUNE 0xec 80 #define MSDC_PAD_TUNE0 0xf0 81 #define PAD_DS_TUNE 0x188 82 #define PAD_CMD_TUNE 0x18c 83 #define EMMC51_CFG0 0x204 84 #define EMMC50_CFG0 0x208 85 #define EMMC50_CFG1 0x20c 86 #define EMMC50_CFG3 0x220 87 #define SDC_FIFO_CFG 0x228 88 #define CQHCI_SETTING 0x7fc 89 90 /*--------------------------------------------------------------------------*/ 91 /* Top Pad Register Offset */ 92 /*--------------------------------------------------------------------------*/ 93 #define EMMC_TOP_CONTROL 0x00 94 #define EMMC_TOP_CMD 0x04 95 #define EMMC50_PAD_DS_TUNE 0x0c 96 97 /*--------------------------------------------------------------------------*/ 98 /* Register Mask */ 99 /*--------------------------------------------------------------------------*/ 100 101 /* MSDC_CFG mask */ 102 #define MSDC_CFG_MODE BIT(0) /* RW */ 103 #define MSDC_CFG_CKPDN BIT(1) /* RW */ 104 #define MSDC_CFG_RST BIT(2) /* RW */ 105 #define MSDC_CFG_PIO BIT(3) /* RW */ 106 #define MSDC_CFG_CKDRVEN BIT(4) /* RW */ 107 #define MSDC_CFG_BV18SDT BIT(5) /* RW */ 108 #define MSDC_CFG_BV18PSS BIT(6) /* R */ 109 #define MSDC_CFG_CKSTB BIT(7) /* R */ 110 #define MSDC_CFG_CKDIV GENMASK(15, 8) /* RW */ 111 #define MSDC_CFG_CKMOD GENMASK(17, 16) /* RW */ 112 #define MSDC_CFG_HS400_CK_MODE BIT(18) /* RW */ 113 #define MSDC_CFG_HS400_CK_MODE_EXTRA BIT(22) /* RW */ 114 #define MSDC_CFG_CKDIV_EXTRA GENMASK(19, 8) /* RW */ 115 #define MSDC_CFG_CKMOD_EXTRA GENMASK(21, 20) /* RW */ 116 117 /* MSDC_IOCON mask */ 118 #define MSDC_IOCON_SDR104CKS BIT(0) /* RW */ 119 #define MSDC_IOCON_RSPL BIT(1) /* RW */ 120 #define MSDC_IOCON_DSPL BIT(2) /* RW */ 121 #define MSDC_IOCON_DDLSEL BIT(3) /* RW */ 122 #define MSDC_IOCON_DDR50CKD BIT(4) /* RW */ 123 #define MSDC_IOCON_DSPLSEL BIT(5) /* RW */ 124 #define MSDC_IOCON_W_DSPL BIT(8) /* RW */ 125 #define MSDC_IOCON_D0SPL BIT(16) /* RW */ 126 #define MSDC_IOCON_D1SPL BIT(17) /* RW */ 127 #define MSDC_IOCON_D2SPL BIT(18) /* RW */ 128 #define MSDC_IOCON_D3SPL BIT(19) /* RW */ 129 #define MSDC_IOCON_D4SPL BIT(20) /* RW */ 130 #define MSDC_IOCON_D5SPL BIT(21) /* RW */ 131 #define MSDC_IOCON_D6SPL BIT(22) /* RW */ 132 #define MSDC_IOCON_D7SPL BIT(23) /* RW */ 133 #define MSDC_IOCON_RISCSZ GENMASK(25, 24) /* RW */ 134 135 /* MSDC_PS mask */ 136 #define MSDC_PS_CDEN BIT(0) /* RW */ 137 #define MSDC_PS_CDSTS BIT(1) /* R */ 138 #define MSDC_PS_CDDEBOUNCE GENMASK(15, 12) /* RW */ 139 #define MSDC_PS_DAT GENMASK(23, 16) /* R */ 140 #define MSDC_PS_DATA1 BIT(17) /* R */ 141 #define MSDC_PS_CMD BIT(24) /* R */ 142 #define MSDC_PS_WP BIT(31) /* R */ 143 144 /* MSDC_INT mask */ 145 #define MSDC_INT_MMCIRQ BIT(0) /* W1C */ 146 #define MSDC_INT_CDSC BIT(1) /* W1C */ 147 #define MSDC_INT_ACMDRDY BIT(3) /* W1C */ 148 #define MSDC_INT_ACMDTMO BIT(4) /* W1C */ 149 #define MSDC_INT_ACMDCRCERR BIT(5) /* W1C */ 150 #define MSDC_INT_DMAQ_EMPTY BIT(6) /* W1C */ 151 #define MSDC_INT_SDIOIRQ BIT(7) /* W1C */ 152 #define MSDC_INT_CMDRDY BIT(8) /* W1C */ 153 #define MSDC_INT_CMDTMO BIT(9) /* W1C */ 154 #define MSDC_INT_RSPCRCERR BIT(10) /* W1C */ 155 #define MSDC_INT_CSTA BIT(11) /* R */ 156 #define MSDC_INT_XFER_COMPL BIT(12) /* W1C */ 157 #define MSDC_INT_DXFER_DONE BIT(13) /* W1C */ 158 #define MSDC_INT_DATTMO BIT(14) /* W1C */ 159 #define MSDC_INT_DATCRCERR BIT(15) /* W1C */ 160 #define MSDC_INT_ACMD19_DONE BIT(16) /* W1C */ 161 #define MSDC_INT_DMA_BDCSERR BIT(17) /* W1C */ 162 #define MSDC_INT_DMA_GPDCSERR BIT(18) /* W1C */ 163 #define MSDC_INT_DMA_PROTECT BIT(19) /* W1C */ 164 #define MSDC_INT_CMDQ BIT(28) /* W1C */ 165 166 /* MSDC_INTEN mask */ 167 #define MSDC_INTEN_MMCIRQ BIT(0) /* RW */ 168 #define MSDC_INTEN_CDSC BIT(1) /* RW */ 169 #define MSDC_INTEN_ACMDRDY BIT(3) /* RW */ 170 #define MSDC_INTEN_ACMDTMO BIT(4) /* RW */ 171 #define MSDC_INTEN_ACMDCRCERR BIT(5) /* RW */ 172 #define MSDC_INTEN_DMAQ_EMPTY BIT(6) /* RW */ 173 #define MSDC_INTEN_SDIOIRQ BIT(7) /* RW */ 174 #define MSDC_INTEN_CMDRDY BIT(8) /* RW */ 175 #define MSDC_INTEN_CMDTMO BIT(9) /* RW */ 176 #define MSDC_INTEN_RSPCRCERR BIT(10) /* RW */ 177 #define MSDC_INTEN_CSTA BIT(11) /* RW */ 178 #define MSDC_INTEN_XFER_COMPL BIT(12) /* RW */ 179 #define MSDC_INTEN_DXFER_DONE BIT(13) /* RW */ 180 #define MSDC_INTEN_DATTMO BIT(14) /* RW */ 181 #define MSDC_INTEN_DATCRCERR BIT(15) /* RW */ 182 #define MSDC_INTEN_ACMD19_DONE BIT(16) /* RW */ 183 #define MSDC_INTEN_DMA_BDCSERR BIT(17) /* RW */ 184 #define MSDC_INTEN_DMA_GPDCSERR BIT(18) /* RW */ 185 #define MSDC_INTEN_DMA_PROTECT BIT(19) /* RW */ 186 187 /* MSDC_FIFOCS mask */ 188 #define MSDC_FIFOCS_RXCNT GENMASK(7, 0) /* R */ 189 #define MSDC_FIFOCS_TXCNT GENMASK(23, 16) /* R */ 190 #define MSDC_FIFOCS_CLR BIT(31) /* RW */ 191 192 /* SDC_CFG mask */ 193 #define SDC_CFG_SDIOINTWKUP BIT(0) /* RW */ 194 #define SDC_CFG_INSWKUP BIT(1) /* RW */ 195 #define SDC_CFG_WRDTOC GENMASK(14, 2) /* RW */ 196 #define SDC_CFG_BUSWIDTH GENMASK(17, 16) /* RW */ 197 #define SDC_CFG_SDIO BIT(19) /* RW */ 198 #define SDC_CFG_SDIOIDE BIT(20) /* RW */ 199 #define SDC_CFG_INTATGAP BIT(21) /* RW */ 200 #define SDC_CFG_DTOC GENMASK(31, 24) /* RW */ 201 202 /* SDC_STS mask */ 203 #define SDC_STS_SDCBUSY BIT(0) /* RW */ 204 #define SDC_STS_CMDBUSY BIT(1) /* RW */ 205 #define SDC_STS_SWR_COMPL BIT(31) /* RW */ 206 207 #define SDC_DAT1_IRQ_TRIGGER BIT(19) /* RW */ 208 /* SDC_ADV_CFG0 mask */ 209 #define SDC_RX_ENHANCE_EN BIT(20) /* RW */ 210 211 /* DMA_SA_H4BIT mask */ 212 #define DMA_ADDR_HIGH_4BIT GENMASK(3, 0) /* RW */ 213 214 /* MSDC_DMA_CTRL mask */ 215 #define MSDC_DMA_CTRL_START BIT(0) /* W */ 216 #define MSDC_DMA_CTRL_STOP BIT(1) /* W */ 217 #define MSDC_DMA_CTRL_RESUME BIT(2) /* W */ 218 #define MSDC_DMA_CTRL_MODE BIT(8) /* RW */ 219 #define MSDC_DMA_CTRL_LASTBUF BIT(10) /* RW */ 220 #define MSDC_DMA_CTRL_BRUSTSZ GENMASK(14, 12) /* RW */ 221 222 /* MSDC_DMA_CFG mask */ 223 #define MSDC_DMA_CFG_STS BIT(0) /* R */ 224 #define MSDC_DMA_CFG_DECSEN BIT(1) /* RW */ 225 #define MSDC_DMA_CFG_AHBHPROT2 BIT(9) /* RW */ 226 #define MSDC_DMA_CFG_ACTIVEEN BIT(13) /* RW */ 227 #define MSDC_DMA_CFG_CS12B16B BIT(16) /* RW */ 228 229 /* MSDC_PATCH_BIT mask */ 230 #define MSDC_PATCH_BIT_ODDSUPP BIT(1) /* RW */ 231 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7) 232 #define MSDC_CKGEN_MSDC_DLY_SEL GENMASK(14, 10) 233 #define MSDC_PATCH_BIT_IODSSEL BIT(16) /* RW */ 234 #define MSDC_PATCH_BIT_IOINTSEL BIT(17) /* RW */ 235 #define MSDC_PATCH_BIT_BUSYDLY GENMASK(21, 18) /* RW */ 236 #define MSDC_PATCH_BIT_WDOD GENMASK(25, 22) /* RW */ 237 #define MSDC_PATCH_BIT_IDRTSEL BIT(26) /* RW */ 238 #define MSDC_PATCH_BIT_CMDFSEL BIT(27) /* RW */ 239 #define MSDC_PATCH_BIT_INTDLSEL BIT(28) /* RW */ 240 #define MSDC_PATCH_BIT_SPCPUSH BIT(29) /* RW */ 241 #define MSDC_PATCH_BIT_DECRCTMO BIT(30) /* RW */ 242 243 #define MSDC_PATCH_BIT1_CMDTA GENMASK(5, 3) /* RW */ 244 #define MSDC_PB1_BUSY_CHECK_SEL BIT(7) /* RW */ 245 #define MSDC_PATCH_BIT1_STOP_DLY GENMASK(11, 8) /* RW */ 246 247 #define MSDC_PATCH_BIT2_CFGRESP BIT(15) /* RW */ 248 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28) /* RW */ 249 #define MSDC_PB2_SUPPORT_64G BIT(1) /* RW */ 250 #define MSDC_PB2_RESPWAIT GENMASK(3, 2) /* RW */ 251 #define MSDC_PB2_RESPSTSENSEL GENMASK(18, 16) /* RW */ 252 #define MSDC_PB2_CRCSTSENSEL GENMASK(31, 29) /* RW */ 253 254 #define MSDC_PAD_TUNE_DATWRDLY GENMASK(4, 0) /* RW */ 255 #define MSDC_PAD_TUNE_DATRRDLY GENMASK(12, 8) /* RW */ 256 #define MSDC_PAD_TUNE_CMDRDLY GENMASK(20, 16) /* RW */ 257 #define MSDC_PAD_TUNE_CMDRRDLY GENMASK(26, 22) /* RW */ 258 #define MSDC_PAD_TUNE_CLKTDLY GENMASK(31, 27) /* RW */ 259 #define MSDC_PAD_TUNE_RXDLYSEL BIT(15) /* RW */ 260 #define MSDC_PAD_TUNE_RD_SEL BIT(13) /* RW */ 261 #define MSDC_PAD_TUNE_CMD_SEL BIT(21) /* RW */ 262 263 #define PAD_DS_TUNE_DLY_SEL BIT(0) /* RW */ 264 #define PAD_DS_TUNE_DLY1 GENMASK(6, 2) /* RW */ 265 #define PAD_DS_TUNE_DLY2 GENMASK(11, 7) /* RW */ 266 #define PAD_DS_TUNE_DLY3 GENMASK(16, 12) /* RW */ 267 268 #define PAD_CMD_TUNE_RX_DLY3 GENMASK(5, 1) /* RW */ 269 270 /* EMMC51_CFG0 mask */ 271 #define CMDQ_RDAT_CNT GENMASK(21, 12) /* RW */ 272 273 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0) /* RW */ 274 #define EMMC50_CFG_CRCSTS_EDGE BIT(3) /* RW */ 275 #define EMMC50_CFG_CFCSTS_SEL BIT(4) /* RW */ 276 #define EMMC50_CFG_CMD_RESP_SEL BIT(9) /* RW */ 277 278 /* EMMC50_CFG1 mask */ 279 #define EMMC50_CFG1_DS_CFG BIT(28) /* RW */ 280 281 #define EMMC50_CFG3_OUTS_WR GENMASK(4, 0) /* RW */ 282 283 #define SDC_FIFO_CFG_WRVALIDSEL BIT(24) /* RW */ 284 #define SDC_FIFO_CFG_RDVALIDSEL BIT(25) /* RW */ 285 286 /* CQHCI_SETTING */ 287 #define CQHCI_RD_CMD_WND_SEL BIT(14) /* RW */ 288 #define CQHCI_WR_CMD_WND_SEL BIT(15) /* RW */ 289 290 /* EMMC_TOP_CONTROL mask */ 291 #define PAD_RXDLY_SEL BIT(0) /* RW */ 292 #define DELAY_EN BIT(1) /* RW */ 293 #define PAD_DAT_RD_RXDLY2 GENMASK(6, 2) /* RW */ 294 #define PAD_DAT_RD_RXDLY GENMASK(11, 7) /* RW */ 295 #define PAD_DAT_RD_RXDLY2_SEL BIT(12) /* RW */ 296 #define PAD_DAT_RD_RXDLY_SEL BIT(13) /* RW */ 297 #define DATA_K_VALUE_SEL BIT(14) /* RW */ 298 #define SDC_RX_ENH_EN BIT(15) /* TW */ 299 300 /* EMMC_TOP_CMD mask */ 301 #define PAD_CMD_RXDLY2 GENMASK(4, 0) /* RW */ 302 #define PAD_CMD_RXDLY GENMASK(9, 5) /* RW */ 303 #define PAD_CMD_RD_RXDLY2_SEL BIT(10) /* RW */ 304 #define PAD_CMD_RD_RXDLY_SEL BIT(11) /* RW */ 305 #define PAD_CMD_TX_DLY GENMASK(16, 12) /* RW */ 306 307 /* EMMC50_PAD_DS_TUNE mask */ 308 #define PAD_DS_DLY_SEL BIT(16) /* RW */ 309 #define PAD_DS_DLY1 GENMASK(14, 10) /* RW */ 310 #define PAD_DS_DLY3 GENMASK(4, 0) /* RW */ 311 312 #define REQ_CMD_EIO BIT(0) 313 #define REQ_CMD_TMO BIT(1) 314 #define REQ_DAT_ERR BIT(2) 315 #define REQ_STOP_EIO BIT(3) 316 #define REQ_STOP_TMO BIT(4) 317 #define REQ_CMD_BUSY BIT(5) 318 319 #define MSDC_PREPARE_FLAG BIT(0) 320 #define MSDC_ASYNC_FLAG BIT(1) 321 #define MSDC_MMAP_FLAG BIT(2) 322 323 #define MTK_MMC_AUTOSUSPEND_DELAY 50 324 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 325 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 326 327 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 328 329 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 330 /*--------------------------------------------------------------------------*/ 331 /* Descriptor Structure */ 332 /*--------------------------------------------------------------------------*/ 333 struct mt_gpdma_desc { 334 u32 gpd_info; 335 #define GPDMA_DESC_HWO BIT(0) 336 #define GPDMA_DESC_BDP BIT(1) 337 #define GPDMA_DESC_CHECKSUM GENMASK(15, 8) 338 #define GPDMA_DESC_INT BIT(16) 339 #define GPDMA_DESC_NEXT_H4 GENMASK(27, 24) 340 #define GPDMA_DESC_PTR_H4 GENMASK(31, 28) 341 u32 next; 342 u32 ptr; 343 u32 gpd_data_len; 344 #define GPDMA_DESC_BUFLEN GENMASK(15, 0) 345 #define GPDMA_DESC_EXTLEN GENMASK(23, 16) 346 u32 arg; 347 u32 blknum; 348 u32 cmd; 349 }; 350 351 struct mt_bdma_desc { 352 u32 bd_info; 353 #define BDMA_DESC_EOL BIT(0) 354 #define BDMA_DESC_CHECKSUM GENMASK(15, 8) 355 #define BDMA_DESC_BLKPAD BIT(17) 356 #define BDMA_DESC_DWPAD BIT(18) 357 #define BDMA_DESC_NEXT_H4 GENMASK(27, 24) 358 #define BDMA_DESC_PTR_H4 GENMASK(31, 28) 359 u32 next; 360 u32 ptr; 361 u32 bd_data_len; 362 #define BDMA_DESC_BUFLEN GENMASK(15, 0) 363 #define BDMA_DESC_BUFLEN_EXT GENMASK(23, 0) 364 }; 365 366 struct msdc_dma { 367 struct scatterlist *sg; /* I/O scatter list */ 368 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 369 struct mt_bdma_desc *bd; /* pointer to bd array */ 370 dma_addr_t gpd_addr; /* the physical address of gpd array */ 371 dma_addr_t bd_addr; /* the physical address of bd array */ 372 }; 373 374 struct msdc_save_para { 375 u32 msdc_cfg; 376 u32 iocon; 377 u32 sdc_cfg; 378 u32 pad_tune; 379 u32 patch_bit0; 380 u32 patch_bit1; 381 u32 patch_bit2; 382 u32 pad_ds_tune; 383 u32 pad_cmd_tune; 384 u32 emmc50_cfg0; 385 u32 emmc50_cfg3; 386 u32 sdc_fifo_cfg; 387 u32 emmc_top_control; 388 u32 emmc_top_cmd; 389 u32 emmc50_pad_ds_tune; 390 }; 391 392 struct mtk_mmc_compatible { 393 u8 clk_div_bits; 394 bool recheck_sdio_irq; 395 bool hs400_tune; /* only used for MT8173 */ 396 u32 pad_tune_reg; 397 bool async_fifo; 398 bool data_tune; 399 bool busy_check; 400 bool stop_clk_fix; 401 bool enhance_rx; 402 bool support_64g; 403 bool use_internal_cd; 404 }; 405 406 struct msdc_tune_para { 407 u32 iocon; 408 u32 pad_tune; 409 u32 pad_cmd_tune; 410 u32 emmc_top_control; 411 u32 emmc_top_cmd; 412 }; 413 414 struct msdc_delay_phase { 415 u8 maxlen; 416 u8 start; 417 u8 final_phase; 418 }; 419 420 struct msdc_host { 421 struct device *dev; 422 const struct mtk_mmc_compatible *dev_comp; 423 int cmd_rsp; 424 425 spinlock_t lock; 426 struct mmc_request *mrq; 427 struct mmc_command *cmd; 428 struct mmc_data *data; 429 int error; 430 431 void __iomem *base; /* host base address */ 432 void __iomem *top_base; /* host top register base address */ 433 434 struct msdc_dma dma; /* dma channel */ 435 u64 dma_mask; 436 437 u32 timeout_ns; /* data timeout ns */ 438 u32 timeout_clks; /* data timeout clks */ 439 440 struct pinctrl *pinctrl; 441 struct pinctrl_state *pins_default; 442 struct pinctrl_state *pins_uhs; 443 struct delayed_work req_timeout; 444 int irq; /* host interrupt */ 445 struct reset_control *reset; 446 447 struct clk *src_clk; /* msdc source clock */ 448 struct clk *h_clk; /* msdc h_clk */ 449 struct clk *bus_clk; /* bus clock which used to access register */ 450 struct clk *src_clk_cg; /* msdc source clock control gate */ 451 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 452 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 453 u32 mclk; /* mmc subsystem clock frequency */ 454 u32 src_clk_freq; /* source clock frequency */ 455 unsigned char timing; 456 bool vqmmc_enabled; 457 u32 latch_ck; 458 u32 hs400_ds_delay; 459 u32 hs400_ds_dly3; 460 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 461 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 462 bool hs400_cmd_resp_sel_rising; 463 /* cmd response sample selection for HS400 */ 464 bool hs400_mode; /* current eMMC will run at hs400 mode */ 465 bool hs400_tuning; /* hs400 mode online tuning */ 466 bool internal_cd; /* Use internal card-detect logic */ 467 bool cqhci; /* support eMMC hw cmdq */ 468 struct msdc_save_para save_para; /* used when gate HCLK */ 469 struct msdc_tune_para def_tune_para; /* default tune setting */ 470 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 471 struct cqhci_host *cq_host; 472 }; 473 474 static const struct mtk_mmc_compatible mt8135_compat = { 475 .clk_div_bits = 8, 476 .recheck_sdio_irq = true, 477 .hs400_tune = false, 478 .pad_tune_reg = MSDC_PAD_TUNE, 479 .async_fifo = false, 480 .data_tune = false, 481 .busy_check = false, 482 .stop_clk_fix = false, 483 .enhance_rx = false, 484 .support_64g = false, 485 }; 486 487 static const struct mtk_mmc_compatible mt8173_compat = { 488 .clk_div_bits = 8, 489 .recheck_sdio_irq = true, 490 .hs400_tune = true, 491 .pad_tune_reg = MSDC_PAD_TUNE, 492 .async_fifo = false, 493 .data_tune = false, 494 .busy_check = false, 495 .stop_clk_fix = false, 496 .enhance_rx = false, 497 .support_64g = false, 498 }; 499 500 static const struct mtk_mmc_compatible mt8183_compat = { 501 .clk_div_bits = 12, 502 .recheck_sdio_irq = false, 503 .hs400_tune = false, 504 .pad_tune_reg = MSDC_PAD_TUNE0, 505 .async_fifo = true, 506 .data_tune = true, 507 .busy_check = true, 508 .stop_clk_fix = true, 509 .enhance_rx = true, 510 .support_64g = true, 511 }; 512 513 static const struct mtk_mmc_compatible mt2701_compat = { 514 .clk_div_bits = 12, 515 .recheck_sdio_irq = true, 516 .hs400_tune = false, 517 .pad_tune_reg = MSDC_PAD_TUNE0, 518 .async_fifo = true, 519 .data_tune = true, 520 .busy_check = false, 521 .stop_clk_fix = false, 522 .enhance_rx = false, 523 .support_64g = false, 524 }; 525 526 static const struct mtk_mmc_compatible mt2712_compat = { 527 .clk_div_bits = 12, 528 .recheck_sdio_irq = false, 529 .hs400_tune = false, 530 .pad_tune_reg = MSDC_PAD_TUNE0, 531 .async_fifo = true, 532 .data_tune = true, 533 .busy_check = true, 534 .stop_clk_fix = true, 535 .enhance_rx = true, 536 .support_64g = true, 537 }; 538 539 static const struct mtk_mmc_compatible mt7622_compat = { 540 .clk_div_bits = 12, 541 .recheck_sdio_irq = true, 542 .hs400_tune = false, 543 .pad_tune_reg = MSDC_PAD_TUNE0, 544 .async_fifo = true, 545 .data_tune = true, 546 .busy_check = true, 547 .stop_clk_fix = true, 548 .enhance_rx = true, 549 .support_64g = false, 550 }; 551 552 static const struct mtk_mmc_compatible mt8516_compat = { 553 .clk_div_bits = 12, 554 .recheck_sdio_irq = true, 555 .hs400_tune = false, 556 .pad_tune_reg = MSDC_PAD_TUNE0, 557 .async_fifo = true, 558 .data_tune = true, 559 .busy_check = true, 560 .stop_clk_fix = true, 561 }; 562 563 static const struct mtk_mmc_compatible mt7620_compat = { 564 .clk_div_bits = 8, 565 .recheck_sdio_irq = true, 566 .hs400_tune = false, 567 .pad_tune_reg = MSDC_PAD_TUNE, 568 .async_fifo = false, 569 .data_tune = false, 570 .busy_check = false, 571 .stop_clk_fix = false, 572 .enhance_rx = false, 573 .use_internal_cd = true, 574 }; 575 576 static const struct mtk_mmc_compatible mt6779_compat = { 577 .clk_div_bits = 12, 578 .recheck_sdio_irq = false, 579 .hs400_tune = false, 580 .pad_tune_reg = MSDC_PAD_TUNE0, 581 .async_fifo = true, 582 .data_tune = true, 583 .busy_check = true, 584 .stop_clk_fix = true, 585 .enhance_rx = true, 586 .support_64g = true, 587 }; 588 589 static const struct of_device_id msdc_of_ids[] = { 590 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 591 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 592 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 593 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 594 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 595 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 596 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 597 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 598 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 599 {} 600 }; 601 MODULE_DEVICE_TABLE(of, msdc_of_ids); 602 603 static void sdr_set_bits(void __iomem *reg, u32 bs) 604 { 605 u32 val = readl(reg); 606 607 val |= bs; 608 writel(val, reg); 609 } 610 611 static void sdr_clr_bits(void __iomem *reg, u32 bs) 612 { 613 u32 val = readl(reg); 614 615 val &= ~bs; 616 writel(val, reg); 617 } 618 619 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 620 { 621 unsigned int tv = readl(reg); 622 623 tv &= ~field; 624 tv |= ((val) << (ffs((unsigned int)field) - 1)); 625 writel(tv, reg); 626 } 627 628 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 629 { 630 unsigned int tv = readl(reg); 631 632 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 633 } 634 635 static void msdc_reset_hw(struct msdc_host *host) 636 { 637 u32 val; 638 639 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 640 readl_poll_timeout(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); 641 642 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 643 readl_poll_timeout(host->base + MSDC_FIFOCS, val, 644 !(val & MSDC_FIFOCS_CLR), 0, 0); 645 646 val = readl(host->base + MSDC_INT); 647 writel(val, host->base + MSDC_INT); 648 } 649 650 static void msdc_cmd_next(struct msdc_host *host, 651 struct mmc_request *mrq, struct mmc_command *cmd); 652 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 653 654 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 655 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 656 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 657 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 658 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 659 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 660 661 static u8 msdc_dma_calcs(u8 *buf, u32 len) 662 { 663 u32 i, sum = 0; 664 665 for (i = 0; i < len; i++) 666 sum += buf[i]; 667 return 0xff - (u8) sum; 668 } 669 670 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 671 struct mmc_data *data) 672 { 673 unsigned int j, dma_len; 674 dma_addr_t dma_address; 675 u32 dma_ctrl; 676 struct scatterlist *sg; 677 struct mt_gpdma_desc *gpd; 678 struct mt_bdma_desc *bd; 679 680 sg = data->sg; 681 682 gpd = dma->gpd; 683 bd = dma->bd; 684 685 /* modify gpd */ 686 gpd->gpd_info |= GPDMA_DESC_HWO; 687 gpd->gpd_info |= GPDMA_DESC_BDP; 688 /* need to clear first. use these bits to calc checksum */ 689 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 690 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 691 692 /* modify bd */ 693 for_each_sg(data->sg, sg, data->sg_count, j) { 694 dma_address = sg_dma_address(sg); 695 dma_len = sg_dma_len(sg); 696 697 /* init bd */ 698 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 699 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 700 bd[j].ptr = lower_32_bits(dma_address); 701 if (host->dev_comp->support_64g) { 702 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 703 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 704 << 28; 705 } 706 707 if (host->dev_comp->support_64g) { 708 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 709 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 710 } else { 711 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 712 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 713 } 714 715 if (j == data->sg_count - 1) /* the last bd */ 716 bd[j].bd_info |= BDMA_DESC_EOL; 717 else 718 bd[j].bd_info &= ~BDMA_DESC_EOL; 719 720 /* checksume need to clear first */ 721 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 722 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 723 } 724 725 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 726 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 727 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 728 dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8)); 729 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 730 if (host->dev_comp->support_64g) 731 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 732 upper_32_bits(dma->gpd_addr) & 0xf); 733 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 734 } 735 736 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 737 { 738 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 739 data->host_cookie |= MSDC_PREPARE_FLAG; 740 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 741 mmc_get_dma_dir(data)); 742 } 743 } 744 745 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 746 { 747 if (data->host_cookie & MSDC_ASYNC_FLAG) 748 return; 749 750 if (data->host_cookie & MSDC_PREPARE_FLAG) { 751 dma_unmap_sg(host->dev, data->sg, data->sg_len, 752 mmc_get_dma_dir(data)); 753 data->host_cookie &= ~MSDC_PREPARE_FLAG; 754 } 755 } 756 757 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 758 { 759 struct mmc_host *mmc = mmc_from_priv(host); 760 u64 timeout, clk_ns; 761 u32 mode = 0; 762 763 if (mmc->actual_clock == 0) { 764 timeout = 0; 765 } else { 766 clk_ns = 1000000000ULL; 767 do_div(clk_ns, mmc->actual_clock); 768 timeout = ns + clk_ns - 1; 769 do_div(timeout, clk_ns); 770 timeout += clks; 771 /* in 1048576 sclk cycle unit */ 772 timeout = DIV_ROUND_UP(timeout, BIT(20)); 773 if (host->dev_comp->clk_div_bits == 8) 774 sdr_get_field(host->base + MSDC_CFG, 775 MSDC_CFG_CKMOD, &mode); 776 else 777 sdr_get_field(host->base + MSDC_CFG, 778 MSDC_CFG_CKMOD_EXTRA, &mode); 779 /*DDR mode will double the clk cycles for data timeout */ 780 timeout = mode >= 2 ? timeout * 2 : timeout; 781 timeout = timeout > 1 ? timeout - 1 : 0; 782 } 783 return timeout; 784 } 785 786 /* clock control primitives */ 787 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 788 { 789 u64 timeout; 790 791 host->timeout_ns = ns; 792 host->timeout_clks = clks; 793 794 timeout = msdc_timeout_cal(host, ns, clks); 795 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 796 (u32)(timeout > 255 ? 255 : timeout)); 797 } 798 799 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 800 { 801 u64 timeout; 802 803 timeout = msdc_timeout_cal(host, ns, clks); 804 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 805 (u32)(timeout > 8191 ? 8191 : timeout)); 806 } 807 808 static void msdc_gate_clock(struct msdc_host *host) 809 { 810 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 811 clk_disable_unprepare(host->src_clk_cg); 812 clk_disable_unprepare(host->src_clk); 813 clk_disable_unprepare(host->bus_clk); 814 clk_disable_unprepare(host->h_clk); 815 } 816 817 static int msdc_ungate_clock(struct msdc_host *host) 818 { 819 u32 val; 820 int ret; 821 822 clk_prepare_enable(host->h_clk); 823 clk_prepare_enable(host->bus_clk); 824 clk_prepare_enable(host->src_clk); 825 clk_prepare_enable(host->src_clk_cg); 826 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 827 if (ret) { 828 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 829 return ret; 830 } 831 832 return readl_poll_timeout(host->base + MSDC_CFG, val, 833 (val & MSDC_CFG_CKSTB), 1, 20000); 834 } 835 836 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 837 { 838 struct mmc_host *mmc = mmc_from_priv(host); 839 u32 mode; 840 u32 flags; 841 u32 div; 842 u32 sclk; 843 u32 tune_reg = host->dev_comp->pad_tune_reg; 844 u32 val; 845 846 if (!hz) { 847 dev_dbg(host->dev, "set mclk to 0\n"); 848 host->mclk = 0; 849 mmc->actual_clock = 0; 850 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 851 return; 852 } 853 854 flags = readl(host->base + MSDC_INTEN); 855 sdr_clr_bits(host->base + MSDC_INTEN, flags); 856 if (host->dev_comp->clk_div_bits == 8) 857 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 858 else 859 sdr_clr_bits(host->base + MSDC_CFG, 860 MSDC_CFG_HS400_CK_MODE_EXTRA); 861 if (timing == MMC_TIMING_UHS_DDR50 || 862 timing == MMC_TIMING_MMC_DDR52 || 863 timing == MMC_TIMING_MMC_HS400) { 864 if (timing == MMC_TIMING_MMC_HS400) 865 mode = 0x3; 866 else 867 mode = 0x2; /* ddr mode and use divisor */ 868 869 if (hz >= (host->src_clk_freq >> 2)) { 870 div = 0; /* mean div = 1/4 */ 871 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 872 } else { 873 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 874 sclk = (host->src_clk_freq >> 2) / div; 875 div = (div >> 1); 876 } 877 878 if (timing == MMC_TIMING_MMC_HS400 && 879 hz >= (host->src_clk_freq >> 1)) { 880 if (host->dev_comp->clk_div_bits == 8) 881 sdr_set_bits(host->base + MSDC_CFG, 882 MSDC_CFG_HS400_CK_MODE); 883 else 884 sdr_set_bits(host->base + MSDC_CFG, 885 MSDC_CFG_HS400_CK_MODE_EXTRA); 886 sclk = host->src_clk_freq >> 1; 887 div = 0; /* div is ignore when bit18 is set */ 888 } 889 } else if (hz >= host->src_clk_freq) { 890 mode = 0x1; /* no divisor */ 891 div = 0; 892 sclk = host->src_clk_freq; 893 } else { 894 mode = 0x0; /* use divisor */ 895 if (hz >= (host->src_clk_freq >> 1)) { 896 div = 0; /* mean div = 1/2 */ 897 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 898 } else { 899 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 900 sclk = (host->src_clk_freq >> 2) / div; 901 } 902 } 903 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 904 /* 905 * As src_clk/HCLK use the same bit to gate/ungate, 906 * So if want to only gate src_clk, need gate its parent(mux). 907 */ 908 if (host->src_clk_cg) 909 clk_disable_unprepare(host->src_clk_cg); 910 else 911 clk_disable_unprepare(clk_get_parent(host->src_clk)); 912 if (host->dev_comp->clk_div_bits == 8) 913 sdr_set_field(host->base + MSDC_CFG, 914 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 915 (mode << 8) | div); 916 else 917 sdr_set_field(host->base + MSDC_CFG, 918 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 919 (mode << 12) | div); 920 if (host->src_clk_cg) 921 clk_prepare_enable(host->src_clk_cg); 922 else 923 clk_prepare_enable(clk_get_parent(host->src_clk)); 924 925 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); 926 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 927 mmc->actual_clock = sclk; 928 host->mclk = hz; 929 host->timing = timing; 930 /* need because clk changed. */ 931 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 932 sdr_set_bits(host->base + MSDC_INTEN, flags); 933 934 /* 935 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 936 * tune result of hs200/200Mhz is not suitable for 50Mhz 937 */ 938 if (mmc->actual_clock <= 52000000) { 939 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 940 if (host->top_base) { 941 writel(host->def_tune_para.emmc_top_control, 942 host->top_base + EMMC_TOP_CONTROL); 943 writel(host->def_tune_para.emmc_top_cmd, 944 host->top_base + EMMC_TOP_CMD); 945 } else { 946 writel(host->def_tune_para.pad_tune, 947 host->base + tune_reg); 948 } 949 } else { 950 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 951 writel(host->saved_tune_para.pad_cmd_tune, 952 host->base + PAD_CMD_TUNE); 953 if (host->top_base) { 954 writel(host->saved_tune_para.emmc_top_control, 955 host->top_base + EMMC_TOP_CONTROL); 956 writel(host->saved_tune_para.emmc_top_cmd, 957 host->top_base + EMMC_TOP_CMD); 958 } else { 959 writel(host->saved_tune_para.pad_tune, 960 host->base + tune_reg); 961 } 962 } 963 964 if (timing == MMC_TIMING_MMC_HS400 && 965 host->dev_comp->hs400_tune) 966 sdr_set_field(host->base + tune_reg, 967 MSDC_PAD_TUNE_CMDRRDLY, 968 host->hs400_cmd_int_delay); 969 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 970 timing); 971 } 972 973 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 974 struct mmc_command *cmd) 975 { 976 u32 resp; 977 978 switch (mmc_resp_type(cmd)) { 979 /* Actually, R1, R5, R6, R7 are the same */ 980 case MMC_RSP_R1: 981 resp = 0x1; 982 break; 983 case MMC_RSP_R1B: 984 resp = 0x7; 985 break; 986 case MMC_RSP_R2: 987 resp = 0x2; 988 break; 989 case MMC_RSP_R3: 990 resp = 0x3; 991 break; 992 case MMC_RSP_NONE: 993 default: 994 resp = 0x0; 995 break; 996 } 997 998 return resp; 999 } 1000 1001 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 1002 struct mmc_request *mrq, struct mmc_command *cmd) 1003 { 1004 struct mmc_host *mmc = mmc_from_priv(host); 1005 /* rawcmd : 1006 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 1007 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 1008 */ 1009 u32 opcode = cmd->opcode; 1010 u32 resp = msdc_cmd_find_resp(host, cmd); 1011 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1012 1013 host->cmd_rsp = resp; 1014 1015 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1016 opcode == MMC_STOP_TRANSMISSION) 1017 rawcmd |= BIT(14); 1018 else if (opcode == SD_SWITCH_VOLTAGE) 1019 rawcmd |= BIT(30); 1020 else if (opcode == SD_APP_SEND_SCR || 1021 opcode == SD_APP_SEND_NUM_WR_BLKS || 1022 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1023 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1024 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1025 rawcmd |= BIT(11); 1026 1027 if (cmd->data) { 1028 struct mmc_data *data = cmd->data; 1029 1030 if (mmc_op_multi(opcode)) { 1031 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1032 !(mrq->sbc->arg & 0xFFFF0000)) 1033 rawcmd |= BIT(29); /* AutoCMD23 */ 1034 } 1035 1036 rawcmd |= ((data->blksz & 0xFFF) << 16); 1037 if (data->flags & MMC_DATA_WRITE) 1038 rawcmd |= BIT(13); 1039 if (data->blocks > 1) 1040 rawcmd |= BIT(12); 1041 else 1042 rawcmd |= BIT(11); 1043 /* Always use dma mode */ 1044 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1045 1046 if (host->timeout_ns != data->timeout_ns || 1047 host->timeout_clks != data->timeout_clks) 1048 msdc_set_timeout(host, data->timeout_ns, 1049 data->timeout_clks); 1050 1051 writel(data->blocks, host->base + SDC_BLK_NUM); 1052 } 1053 return rawcmd; 1054 } 1055 1056 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, 1057 struct mmc_data *data) 1058 { 1059 bool read; 1060 1061 WARN_ON(host->data); 1062 host->data = data; 1063 read = data->flags & MMC_DATA_READ; 1064 1065 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1066 msdc_dma_setup(host, &host->dma, data); 1067 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1068 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1069 dev_dbg(host->dev, "DMA start\n"); 1070 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1071 __func__, cmd->opcode, data->blocks, read); 1072 } 1073 1074 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1075 struct mmc_command *cmd) 1076 { 1077 u32 *rsp = cmd->resp; 1078 1079 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1080 1081 if (events & MSDC_INT_ACMDRDY) { 1082 cmd->error = 0; 1083 } else { 1084 msdc_reset_hw(host); 1085 if (events & MSDC_INT_ACMDCRCERR) { 1086 cmd->error = -EILSEQ; 1087 host->error |= REQ_STOP_EIO; 1088 } else if (events & MSDC_INT_ACMDTMO) { 1089 cmd->error = -ETIMEDOUT; 1090 host->error |= REQ_STOP_TMO; 1091 } 1092 dev_err(host->dev, 1093 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1094 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1095 } 1096 return cmd->error; 1097 } 1098 1099 /* 1100 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1101 * 1102 * Host controller may lost interrupt in some special case. 1103 * Add SDIO irq recheck mechanism to make sure all interrupts 1104 * can be processed immediately 1105 */ 1106 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1107 { 1108 struct mmc_host *mmc = mmc_from_priv(host); 1109 u32 reg_int, reg_inten, reg_ps; 1110 1111 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1112 reg_inten = readl(host->base + MSDC_INTEN); 1113 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1114 reg_int = readl(host->base + MSDC_INT); 1115 reg_ps = readl(host->base + MSDC_PS); 1116 if (!(reg_int & MSDC_INT_SDIOIRQ || 1117 reg_ps & MSDC_PS_DATA1)) { 1118 __msdc_enable_sdio_irq(host, 0); 1119 sdio_signal_irq(mmc); 1120 } 1121 } 1122 } 1123 } 1124 1125 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) 1126 { 1127 if (host->error) 1128 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1129 __func__, cmd->opcode, cmd->arg, host->error); 1130 } 1131 1132 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1133 { 1134 unsigned long flags; 1135 1136 /* 1137 * No need check the return value of cancel_delayed_work, as only ONE 1138 * path will go here! 1139 */ 1140 cancel_delayed_work(&host->req_timeout); 1141 1142 spin_lock_irqsave(&host->lock, flags); 1143 host->mrq = NULL; 1144 spin_unlock_irqrestore(&host->lock, flags); 1145 1146 msdc_track_cmd_data(host, mrq->cmd); 1147 if (mrq->data) 1148 msdc_unprepare_data(host, mrq->data); 1149 if (host->error) 1150 msdc_reset_hw(host); 1151 mmc_request_done(mmc_from_priv(host), mrq); 1152 if (host->dev_comp->recheck_sdio_irq) 1153 msdc_recheck_sdio_irq(host); 1154 } 1155 1156 /* returns true if command is fully handled; returns false otherwise */ 1157 static bool msdc_cmd_done(struct msdc_host *host, int events, 1158 struct mmc_request *mrq, struct mmc_command *cmd) 1159 { 1160 bool done = false; 1161 bool sbc_error; 1162 unsigned long flags; 1163 u32 *rsp; 1164 1165 if (mrq->sbc && cmd == mrq->cmd && 1166 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1167 | MSDC_INT_ACMDTMO))) 1168 msdc_auto_cmd_done(host, events, mrq->sbc); 1169 1170 sbc_error = mrq->sbc && mrq->sbc->error; 1171 1172 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1173 | MSDC_INT_RSPCRCERR 1174 | MSDC_INT_CMDTMO))) 1175 return done; 1176 1177 spin_lock_irqsave(&host->lock, flags); 1178 done = !host->cmd; 1179 host->cmd = NULL; 1180 spin_unlock_irqrestore(&host->lock, flags); 1181 1182 if (done) 1183 return true; 1184 rsp = cmd->resp; 1185 1186 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1187 1188 if (cmd->flags & MMC_RSP_PRESENT) { 1189 if (cmd->flags & MMC_RSP_136) { 1190 rsp[0] = readl(host->base + SDC_RESP3); 1191 rsp[1] = readl(host->base + SDC_RESP2); 1192 rsp[2] = readl(host->base + SDC_RESP1); 1193 rsp[3] = readl(host->base + SDC_RESP0); 1194 } else { 1195 rsp[0] = readl(host->base + SDC_RESP0); 1196 } 1197 } 1198 1199 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1200 if (events & MSDC_INT_CMDTMO || 1201 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1202 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200 && 1203 !host->hs400_tuning)) 1204 /* 1205 * should not clear fifo/interrupt as the tune data 1206 * may have alreay come when cmd19/cmd21 gets response 1207 * CRC error. 1208 */ 1209 msdc_reset_hw(host); 1210 if (events & MSDC_INT_RSPCRCERR) { 1211 cmd->error = -EILSEQ; 1212 host->error |= REQ_CMD_EIO; 1213 } else if (events & MSDC_INT_CMDTMO) { 1214 cmd->error = -ETIMEDOUT; 1215 host->error |= REQ_CMD_TMO; 1216 } 1217 } 1218 if (cmd->error) 1219 dev_dbg(host->dev, 1220 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1221 __func__, cmd->opcode, cmd->arg, rsp[0], 1222 cmd->error); 1223 1224 msdc_cmd_next(host, mrq, cmd); 1225 return true; 1226 } 1227 1228 /* It is the core layer's responsibility to ensure card status 1229 * is correct before issue a request. but host design do below 1230 * checks recommended. 1231 */ 1232 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1233 struct mmc_request *mrq, struct mmc_command *cmd) 1234 { 1235 u32 val; 1236 int ret; 1237 1238 /* The max busy time we can endure is 20ms */ 1239 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1240 !(val & SDC_STS_CMDBUSY), 1, 20000); 1241 if (ret) { 1242 dev_err(host->dev, "CMD bus busy detected\n"); 1243 host->error |= REQ_CMD_BUSY; 1244 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1245 return false; 1246 } 1247 1248 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1249 /* R1B or with data, should check SDCBUSY */ 1250 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, 1251 !(val & SDC_STS_SDCBUSY), 1, 20000); 1252 if (ret) { 1253 dev_err(host->dev, "Controller busy detected\n"); 1254 host->error |= REQ_CMD_BUSY; 1255 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1256 return false; 1257 } 1258 } 1259 return true; 1260 } 1261 1262 static void msdc_start_command(struct msdc_host *host, 1263 struct mmc_request *mrq, struct mmc_command *cmd) 1264 { 1265 u32 rawcmd; 1266 unsigned long flags; 1267 1268 WARN_ON(host->cmd); 1269 host->cmd = cmd; 1270 1271 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1272 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1273 return; 1274 1275 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1276 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1277 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1278 msdc_reset_hw(host); 1279 } 1280 1281 cmd->error = 0; 1282 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1283 1284 spin_lock_irqsave(&host->lock, flags); 1285 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1286 spin_unlock_irqrestore(&host->lock, flags); 1287 1288 writel(cmd->arg, host->base + SDC_ARG); 1289 writel(rawcmd, host->base + SDC_CMD); 1290 } 1291 1292 static void msdc_cmd_next(struct msdc_host *host, 1293 struct mmc_request *mrq, struct mmc_command *cmd) 1294 { 1295 if ((cmd->error && 1296 !(cmd->error == -EILSEQ && 1297 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1298 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200 || 1299 host->hs400_tuning))) || 1300 (mrq->sbc && mrq->sbc->error)) 1301 msdc_request_done(host, mrq); 1302 else if (cmd == mrq->sbc) 1303 msdc_start_command(host, mrq, mrq->cmd); 1304 else if (!cmd->data) 1305 msdc_request_done(host, mrq); 1306 else 1307 msdc_start_data(host, cmd, cmd->data); 1308 } 1309 1310 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1311 { 1312 struct msdc_host *host = mmc_priv(mmc); 1313 1314 host->error = 0; 1315 WARN_ON(host->mrq); 1316 host->mrq = mrq; 1317 1318 if (mrq->data) 1319 msdc_prepare_data(host, mrq->data); 1320 1321 /* if SBC is required, we have HW option and SW option. 1322 * if HW option is enabled, and SBC does not have "special" flags, 1323 * use HW option, otherwise use SW option 1324 */ 1325 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1326 (mrq->sbc->arg & 0xFFFF0000))) 1327 msdc_start_command(host, mrq, mrq->sbc); 1328 else 1329 msdc_start_command(host, mrq, mrq->cmd); 1330 } 1331 1332 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1333 { 1334 struct msdc_host *host = mmc_priv(mmc); 1335 struct mmc_data *data = mrq->data; 1336 1337 if (!data) 1338 return; 1339 1340 msdc_prepare_data(host, data); 1341 data->host_cookie |= MSDC_ASYNC_FLAG; 1342 } 1343 1344 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1345 int err) 1346 { 1347 struct msdc_host *host = mmc_priv(mmc); 1348 struct mmc_data *data = mrq->data; 1349 1350 if (!data) 1351 return; 1352 1353 if (data->host_cookie) { 1354 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1355 msdc_unprepare_data(host, data); 1356 } 1357 } 1358 1359 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 1360 { 1361 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1362 !mrq->sbc) 1363 msdc_start_command(host, mrq, mrq->stop); 1364 else 1365 msdc_request_done(host, mrq); 1366 } 1367 1368 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1369 struct mmc_request *mrq, struct mmc_data *data) 1370 { 1371 struct mmc_command *stop; 1372 unsigned long flags; 1373 bool done; 1374 unsigned int check_data = events & 1375 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1376 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1377 | MSDC_INT_DMA_PROTECT); 1378 u32 val; 1379 int ret; 1380 1381 spin_lock_irqsave(&host->lock, flags); 1382 done = !host->data; 1383 if (check_data) 1384 host->data = NULL; 1385 spin_unlock_irqrestore(&host->lock, flags); 1386 1387 if (done) 1388 return true; 1389 stop = data->stop; 1390 1391 if (check_data || (stop && stop->error)) { 1392 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1393 readl(host->base + MSDC_DMA_CFG)); 1394 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1395 1); 1396 1397 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, 1398 !(val & MSDC_DMA_CFG_STS), 1, 20000); 1399 if (ret) { 1400 dev_dbg(host->dev, "DMA stop timed out\n"); 1401 return false; 1402 } 1403 1404 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1405 dev_dbg(host->dev, "DMA stop\n"); 1406 1407 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1408 data->bytes_xfered = data->blocks * data->blksz; 1409 } else { 1410 dev_dbg(host->dev, "interrupt events: %x\n", events); 1411 msdc_reset_hw(host); 1412 host->error |= REQ_DAT_ERR; 1413 data->bytes_xfered = 0; 1414 1415 if (events & MSDC_INT_DATTMO) 1416 data->error = -ETIMEDOUT; 1417 else if (events & MSDC_INT_DATCRCERR) 1418 data->error = -EILSEQ; 1419 1420 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1421 __func__, mrq->cmd->opcode, data->blocks); 1422 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1423 (int)data->error, data->bytes_xfered); 1424 } 1425 1426 msdc_data_xfer_next(host, mrq); 1427 done = true; 1428 } 1429 return done; 1430 } 1431 1432 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1433 { 1434 u32 val = readl(host->base + SDC_CFG); 1435 1436 val &= ~SDC_CFG_BUSWIDTH; 1437 1438 switch (width) { 1439 default: 1440 case MMC_BUS_WIDTH_1: 1441 val |= (MSDC_BUS_1BITS << 16); 1442 break; 1443 case MMC_BUS_WIDTH_4: 1444 val |= (MSDC_BUS_4BITS << 16); 1445 break; 1446 case MMC_BUS_WIDTH_8: 1447 val |= (MSDC_BUS_8BITS << 16); 1448 break; 1449 } 1450 1451 writel(val, host->base + SDC_CFG); 1452 dev_dbg(host->dev, "Bus Width = %d", width); 1453 } 1454 1455 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1456 { 1457 struct msdc_host *host = mmc_priv(mmc); 1458 int ret; 1459 1460 if (!IS_ERR(mmc->supply.vqmmc)) { 1461 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1462 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1463 dev_err(host->dev, "Unsupported signal voltage!\n"); 1464 return -EINVAL; 1465 } 1466 1467 ret = mmc_regulator_set_vqmmc(mmc, ios); 1468 if (ret < 0) { 1469 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1470 ret, ios->signal_voltage); 1471 return ret; 1472 } 1473 1474 /* Apply different pinctrl settings for different signal voltage */ 1475 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1476 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1477 else 1478 pinctrl_select_state(host->pinctrl, host->pins_default); 1479 } 1480 return 0; 1481 } 1482 1483 static int msdc_card_busy(struct mmc_host *mmc) 1484 { 1485 struct msdc_host *host = mmc_priv(mmc); 1486 u32 status = readl(host->base + MSDC_PS); 1487 1488 /* only check if data0 is low */ 1489 return !(status & BIT(16)); 1490 } 1491 1492 static void msdc_request_timeout(struct work_struct *work) 1493 { 1494 struct msdc_host *host = container_of(work, struct msdc_host, 1495 req_timeout.work); 1496 1497 /* simulate HW timeout status */ 1498 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1499 if (host->mrq) { 1500 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1501 host->mrq, host->mrq->cmd->opcode); 1502 if (host->cmd) { 1503 dev_err(host->dev, "%s: aborting cmd=%d\n", 1504 __func__, host->cmd->opcode); 1505 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1506 host->cmd); 1507 } else if (host->data) { 1508 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1509 __func__, host->mrq->cmd->opcode, 1510 host->data->blocks); 1511 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1512 host->data); 1513 } 1514 } 1515 } 1516 1517 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1518 { 1519 if (enb) { 1520 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1521 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1522 if (host->dev_comp->recheck_sdio_irq) 1523 msdc_recheck_sdio_irq(host); 1524 } else { 1525 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1526 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1527 } 1528 } 1529 1530 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1531 { 1532 unsigned long flags; 1533 struct msdc_host *host = mmc_priv(mmc); 1534 1535 spin_lock_irqsave(&host->lock, flags); 1536 __msdc_enable_sdio_irq(host, enb); 1537 spin_unlock_irqrestore(&host->lock, flags); 1538 1539 if (enb) 1540 pm_runtime_get_noresume(host->dev); 1541 else 1542 pm_runtime_put_noidle(host->dev); 1543 } 1544 1545 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1546 { 1547 struct mmc_host *mmc = mmc_from_priv(host); 1548 int cmd_err = 0, dat_err = 0; 1549 1550 if (intsts & MSDC_INT_RSPCRCERR) { 1551 cmd_err = -EILSEQ; 1552 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1553 } else if (intsts & MSDC_INT_CMDTMO) { 1554 cmd_err = -ETIMEDOUT; 1555 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1556 } 1557 1558 if (intsts & MSDC_INT_DATCRCERR) { 1559 dat_err = -EILSEQ; 1560 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1561 } else if (intsts & MSDC_INT_DATTMO) { 1562 dat_err = -ETIMEDOUT; 1563 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1564 } 1565 1566 if (cmd_err || dat_err) { 1567 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1568 cmd_err, dat_err, intsts); 1569 } 1570 1571 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1572 } 1573 1574 static irqreturn_t msdc_irq(int irq, void *dev_id) 1575 { 1576 struct msdc_host *host = (struct msdc_host *) dev_id; 1577 struct mmc_host *mmc = mmc_from_priv(host); 1578 1579 while (true) { 1580 struct mmc_request *mrq; 1581 struct mmc_command *cmd; 1582 struct mmc_data *data; 1583 u32 events, event_mask; 1584 1585 spin_lock(&host->lock); 1586 events = readl(host->base + MSDC_INT); 1587 event_mask = readl(host->base + MSDC_INTEN); 1588 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1589 __msdc_enable_sdio_irq(host, 0); 1590 /* clear interrupts */ 1591 writel(events & event_mask, host->base + MSDC_INT); 1592 1593 mrq = host->mrq; 1594 cmd = host->cmd; 1595 data = host->data; 1596 spin_unlock(&host->lock); 1597 1598 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1599 sdio_signal_irq(mmc); 1600 1601 if ((events & event_mask) & MSDC_INT_CDSC) { 1602 if (host->internal_cd) 1603 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1604 events &= ~MSDC_INT_CDSC; 1605 } 1606 1607 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1608 break; 1609 1610 if ((mmc->caps2 & MMC_CAP2_CQE) && 1611 (events & MSDC_INT_CMDQ)) { 1612 msdc_cmdq_irq(host, events); 1613 /* clear interrupts */ 1614 writel(events, host->base + MSDC_INT); 1615 return IRQ_HANDLED; 1616 } 1617 1618 if (!mrq) { 1619 dev_err(host->dev, 1620 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1621 __func__, events, event_mask); 1622 WARN_ON(1); 1623 break; 1624 } 1625 1626 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1627 1628 if (cmd) 1629 msdc_cmd_done(host, events, mrq, cmd); 1630 else if (data) 1631 msdc_data_xfer_done(host, events, mrq, data); 1632 } 1633 1634 return IRQ_HANDLED; 1635 } 1636 1637 static void msdc_init_hw(struct msdc_host *host) 1638 { 1639 u32 val; 1640 u32 tune_reg = host->dev_comp->pad_tune_reg; 1641 1642 if (host->reset) { 1643 reset_control_assert(host->reset); 1644 usleep_range(10, 50); 1645 reset_control_deassert(host->reset); 1646 } 1647 1648 /* Configure to MMC/SD mode, clock free running */ 1649 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1650 1651 /* Reset */ 1652 msdc_reset_hw(host); 1653 1654 /* Disable and clear all interrupts */ 1655 writel(0, host->base + MSDC_INTEN); 1656 val = readl(host->base + MSDC_INT); 1657 writel(val, host->base + MSDC_INT); 1658 1659 /* Configure card detection */ 1660 if (host->internal_cd) { 1661 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1662 DEFAULT_DEBOUNCE); 1663 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1664 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1665 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1666 } else { 1667 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1668 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1669 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1670 } 1671 1672 if (host->top_base) { 1673 writel(0, host->top_base + EMMC_TOP_CONTROL); 1674 writel(0, host->top_base + EMMC_TOP_CMD); 1675 } else { 1676 writel(0, host->base + tune_reg); 1677 } 1678 writel(0, host->base + MSDC_IOCON); 1679 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1680 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1681 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1682 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1683 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1684 1685 if (host->dev_comp->stop_clk_fix) { 1686 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1687 MSDC_PATCH_BIT1_STOP_DLY, 3); 1688 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1689 SDC_FIFO_CFG_WRVALIDSEL); 1690 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1691 SDC_FIFO_CFG_RDVALIDSEL); 1692 } 1693 1694 if (host->dev_comp->busy_check) 1695 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); 1696 1697 if (host->dev_comp->async_fifo) { 1698 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1699 MSDC_PB2_RESPWAIT, 3); 1700 if (host->dev_comp->enhance_rx) { 1701 if (host->top_base) 1702 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1703 SDC_RX_ENH_EN); 1704 else 1705 sdr_set_bits(host->base + SDC_ADV_CFG0, 1706 SDC_RX_ENHANCE_EN); 1707 } else { 1708 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1709 MSDC_PB2_RESPSTSENSEL, 2); 1710 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1711 MSDC_PB2_CRCSTSENSEL, 2); 1712 } 1713 /* use async fifo, then no need tune internal delay */ 1714 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1715 MSDC_PATCH_BIT2_CFGRESP); 1716 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1717 MSDC_PATCH_BIT2_CFGCRCSTS); 1718 } 1719 1720 if (host->dev_comp->support_64g) 1721 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1722 MSDC_PB2_SUPPORT_64G); 1723 if (host->dev_comp->data_tune) { 1724 if (host->top_base) { 1725 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1726 PAD_DAT_RD_RXDLY_SEL); 1727 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1728 DATA_K_VALUE_SEL); 1729 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1730 PAD_CMD_RD_RXDLY_SEL); 1731 } else { 1732 sdr_set_bits(host->base + tune_reg, 1733 MSDC_PAD_TUNE_RD_SEL | 1734 MSDC_PAD_TUNE_CMD_SEL); 1735 } 1736 } else { 1737 /* choose clock tune */ 1738 if (host->top_base) 1739 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1740 PAD_RXDLY_SEL); 1741 else 1742 sdr_set_bits(host->base + tune_reg, 1743 MSDC_PAD_TUNE_RXDLYSEL); 1744 } 1745 1746 /* Configure to enable SDIO mode. 1747 * it's must otherwise sdio cmd5 failed 1748 */ 1749 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1750 1751 /* Config SDIO device detect interrupt function */ 1752 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1753 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1754 1755 /* Configure to default data timeout */ 1756 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1757 1758 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1759 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1760 if (host->top_base) { 1761 host->def_tune_para.emmc_top_control = 1762 readl(host->top_base + EMMC_TOP_CONTROL); 1763 host->def_tune_para.emmc_top_cmd = 1764 readl(host->top_base + EMMC_TOP_CMD); 1765 host->saved_tune_para.emmc_top_control = 1766 readl(host->top_base + EMMC_TOP_CONTROL); 1767 host->saved_tune_para.emmc_top_cmd = 1768 readl(host->top_base + EMMC_TOP_CMD); 1769 } else { 1770 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1771 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1772 } 1773 dev_dbg(host->dev, "init hardware done!"); 1774 } 1775 1776 static void msdc_deinit_hw(struct msdc_host *host) 1777 { 1778 u32 val; 1779 1780 if (host->internal_cd) { 1781 /* Disabled card-detect */ 1782 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1783 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1784 } 1785 1786 /* Disable and clear all interrupts */ 1787 writel(0, host->base + MSDC_INTEN); 1788 1789 val = readl(host->base + MSDC_INT); 1790 writel(val, host->base + MSDC_INT); 1791 } 1792 1793 /* init gpd and bd list in msdc_drv_probe */ 1794 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1795 { 1796 struct mt_gpdma_desc *gpd = dma->gpd; 1797 struct mt_bdma_desc *bd = dma->bd; 1798 dma_addr_t dma_addr; 1799 int i; 1800 1801 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1802 1803 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1804 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1805 /* gpd->next is must set for desc DMA 1806 * That's why must alloc 2 gpd structure. 1807 */ 1808 gpd->next = lower_32_bits(dma_addr); 1809 if (host->dev_comp->support_64g) 1810 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1811 1812 dma_addr = dma->bd_addr; 1813 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1814 if (host->dev_comp->support_64g) 1815 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1816 1817 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1818 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1819 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1820 bd[i].next = lower_32_bits(dma_addr); 1821 if (host->dev_comp->support_64g) 1822 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1823 } 1824 } 1825 1826 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1827 { 1828 struct msdc_host *host = mmc_priv(mmc); 1829 int ret; 1830 1831 msdc_set_buswidth(host, ios->bus_width); 1832 1833 /* Suspend/Resume will do power off/on */ 1834 switch (ios->power_mode) { 1835 case MMC_POWER_UP: 1836 if (!IS_ERR(mmc->supply.vmmc)) { 1837 msdc_init_hw(host); 1838 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1839 ios->vdd); 1840 if (ret) { 1841 dev_err(host->dev, "Failed to set vmmc power!\n"); 1842 return; 1843 } 1844 } 1845 break; 1846 case MMC_POWER_ON: 1847 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1848 ret = regulator_enable(mmc->supply.vqmmc); 1849 if (ret) 1850 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1851 else 1852 host->vqmmc_enabled = true; 1853 } 1854 break; 1855 case MMC_POWER_OFF: 1856 if (!IS_ERR(mmc->supply.vmmc)) 1857 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1858 1859 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1860 regulator_disable(mmc->supply.vqmmc); 1861 host->vqmmc_enabled = false; 1862 } 1863 break; 1864 default: 1865 break; 1866 } 1867 1868 if (host->mclk != ios->clock || host->timing != ios->timing) 1869 msdc_set_mclk(host, ios->timing, ios->clock); 1870 } 1871 1872 static u32 test_delay_bit(u32 delay, u32 bit) 1873 { 1874 bit %= PAD_DELAY_MAX; 1875 return delay & BIT(bit); 1876 } 1877 1878 static int get_delay_len(u32 delay, u32 start_bit) 1879 { 1880 int i; 1881 1882 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1883 if (test_delay_bit(delay, start_bit + i) == 0) 1884 return i; 1885 } 1886 return PAD_DELAY_MAX - start_bit; 1887 } 1888 1889 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1890 { 1891 int start = 0, len = 0; 1892 int start_final = 0, len_final = 0; 1893 u8 final_phase = 0xff; 1894 struct msdc_delay_phase delay_phase = { 0, }; 1895 1896 if (delay == 0) { 1897 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1898 delay_phase.final_phase = final_phase; 1899 return delay_phase; 1900 } 1901 1902 while (start < PAD_DELAY_MAX) { 1903 len = get_delay_len(delay, start); 1904 if (len_final < len) { 1905 start_final = start; 1906 len_final = len; 1907 } 1908 start += len ? len : 1; 1909 if (len >= 12 && start_final < 4) 1910 break; 1911 } 1912 1913 /* The rule is that to find the smallest delay cell */ 1914 if (start_final == 0) 1915 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1916 else 1917 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1918 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1919 delay, len_final, final_phase); 1920 1921 delay_phase.maxlen = len_final; 1922 delay_phase.start = start_final; 1923 delay_phase.final_phase = final_phase; 1924 return delay_phase; 1925 } 1926 1927 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1928 { 1929 u32 tune_reg = host->dev_comp->pad_tune_reg; 1930 1931 if (host->top_base) 1932 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1933 value); 1934 else 1935 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1936 value); 1937 } 1938 1939 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1940 { 1941 u32 tune_reg = host->dev_comp->pad_tune_reg; 1942 1943 if (host->top_base) 1944 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1945 PAD_DAT_RD_RXDLY, value); 1946 else 1947 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1948 value); 1949 } 1950 1951 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1952 { 1953 struct msdc_host *host = mmc_priv(mmc); 1954 u32 rise_delay = 0, fall_delay = 0; 1955 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1956 struct msdc_delay_phase internal_delay_phase; 1957 u8 final_delay, final_maxlen; 1958 u32 internal_delay = 0; 1959 u32 tune_reg = host->dev_comp->pad_tune_reg; 1960 int cmd_err; 1961 int i, j; 1962 1963 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1964 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1965 sdr_set_field(host->base + tune_reg, 1966 MSDC_PAD_TUNE_CMDRRDLY, 1967 host->hs200_cmd_int_delay); 1968 1969 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1970 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1971 msdc_set_cmd_delay(host, i); 1972 /* 1973 * Using the same parameters, it may sometimes pass the test, 1974 * but sometimes it may fail. To make sure the parameters are 1975 * more stable, we test each set of parameters 3 times. 1976 */ 1977 for (j = 0; j < 3; j++) { 1978 mmc_send_tuning(mmc, opcode, &cmd_err); 1979 if (!cmd_err) { 1980 rise_delay |= BIT(i); 1981 } else { 1982 rise_delay &= ~BIT(i); 1983 break; 1984 } 1985 } 1986 } 1987 final_rise_delay = get_best_delay(host, rise_delay); 1988 /* if rising edge has enough margin, then do not scan falling edge */ 1989 if (final_rise_delay.maxlen >= 12 || 1990 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1991 goto skip_fall; 1992 1993 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1994 for (i = 0; i < PAD_DELAY_MAX; i++) { 1995 msdc_set_cmd_delay(host, i); 1996 /* 1997 * Using the same parameters, it may sometimes pass the test, 1998 * but sometimes it may fail. To make sure the parameters are 1999 * more stable, we test each set of parameters 3 times. 2000 */ 2001 for (j = 0; j < 3; j++) { 2002 mmc_send_tuning(mmc, opcode, &cmd_err); 2003 if (!cmd_err) { 2004 fall_delay |= BIT(i); 2005 } else { 2006 fall_delay &= ~BIT(i); 2007 break; 2008 } 2009 } 2010 } 2011 final_fall_delay = get_best_delay(host, fall_delay); 2012 2013 skip_fall: 2014 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2015 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 2016 final_maxlen = final_fall_delay.maxlen; 2017 if (final_maxlen == final_rise_delay.maxlen) { 2018 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2019 final_delay = final_rise_delay.final_phase; 2020 } else { 2021 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2022 final_delay = final_fall_delay.final_phase; 2023 } 2024 msdc_set_cmd_delay(host, final_delay); 2025 2026 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2027 goto skip_internal; 2028 2029 for (i = 0; i < PAD_DELAY_MAX; i++) { 2030 sdr_set_field(host->base + tune_reg, 2031 MSDC_PAD_TUNE_CMDRRDLY, i); 2032 mmc_send_tuning(mmc, opcode, &cmd_err); 2033 if (!cmd_err) 2034 internal_delay |= BIT(i); 2035 } 2036 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2037 internal_delay_phase = get_best_delay(host, internal_delay); 2038 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2039 internal_delay_phase.final_phase); 2040 skip_internal: 2041 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2042 return final_delay == 0xff ? -EIO : 0; 2043 } 2044 2045 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2046 { 2047 struct msdc_host *host = mmc_priv(mmc); 2048 u32 cmd_delay = 0; 2049 struct msdc_delay_phase final_cmd_delay = { 0,}; 2050 u8 final_delay; 2051 int cmd_err; 2052 int i, j; 2053 2054 /* select EMMC50 PAD CMD tune */ 2055 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2056 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2057 2058 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2059 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2060 sdr_set_field(host->base + MSDC_PAD_TUNE, 2061 MSDC_PAD_TUNE_CMDRRDLY, 2062 host->hs200_cmd_int_delay); 2063 2064 if (host->hs400_cmd_resp_sel_rising) 2065 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2066 else 2067 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2068 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2069 sdr_set_field(host->base + PAD_CMD_TUNE, 2070 PAD_CMD_TUNE_RX_DLY3, i); 2071 /* 2072 * Using the same parameters, it may sometimes pass the test, 2073 * but sometimes it may fail. To make sure the parameters are 2074 * more stable, we test each set of parameters 3 times. 2075 */ 2076 for (j = 0; j < 3; j++) { 2077 mmc_send_tuning(mmc, opcode, &cmd_err); 2078 if (!cmd_err) { 2079 cmd_delay |= BIT(i); 2080 } else { 2081 cmd_delay &= ~BIT(i); 2082 break; 2083 } 2084 } 2085 } 2086 final_cmd_delay = get_best_delay(host, cmd_delay); 2087 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2088 final_cmd_delay.final_phase); 2089 final_delay = final_cmd_delay.final_phase; 2090 2091 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2092 return final_delay == 0xff ? -EIO : 0; 2093 } 2094 2095 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2096 { 2097 struct msdc_host *host = mmc_priv(mmc); 2098 u32 rise_delay = 0, fall_delay = 0; 2099 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2100 u8 final_delay, final_maxlen; 2101 int i, ret; 2102 2103 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2104 host->latch_ck); 2105 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2106 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2107 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2108 msdc_set_data_delay(host, i); 2109 ret = mmc_send_tuning(mmc, opcode, NULL); 2110 if (!ret) 2111 rise_delay |= BIT(i); 2112 } 2113 final_rise_delay = get_best_delay(host, rise_delay); 2114 /* if rising edge has enough margin, then do not scan falling edge */ 2115 if (final_rise_delay.maxlen >= 12 || 2116 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2117 goto skip_fall; 2118 2119 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2120 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2121 for (i = 0; i < PAD_DELAY_MAX; i++) { 2122 msdc_set_data_delay(host, i); 2123 ret = mmc_send_tuning(mmc, opcode, NULL); 2124 if (!ret) 2125 fall_delay |= BIT(i); 2126 } 2127 final_fall_delay = get_best_delay(host, fall_delay); 2128 2129 skip_fall: 2130 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2131 if (final_maxlen == final_rise_delay.maxlen) { 2132 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2133 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2134 final_delay = final_rise_delay.final_phase; 2135 } else { 2136 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2137 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2138 final_delay = final_fall_delay.final_phase; 2139 } 2140 msdc_set_data_delay(host, final_delay); 2141 2142 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2143 return final_delay == 0xff ? -EIO : 0; 2144 } 2145 2146 /* 2147 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2148 * together, which can save the tuning time. 2149 */ 2150 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2151 { 2152 struct msdc_host *host = mmc_priv(mmc); 2153 u32 rise_delay = 0, fall_delay = 0; 2154 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2155 u8 final_delay, final_maxlen; 2156 int i, ret; 2157 2158 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2159 host->latch_ck); 2160 2161 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2162 sdr_clr_bits(host->base + MSDC_IOCON, 2163 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2164 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2165 msdc_set_cmd_delay(host, i); 2166 msdc_set_data_delay(host, i); 2167 ret = mmc_send_tuning(mmc, opcode, NULL); 2168 if (!ret) 2169 rise_delay |= BIT(i); 2170 } 2171 final_rise_delay = get_best_delay(host, rise_delay); 2172 /* if rising edge has enough margin, then do not scan falling edge */ 2173 if (final_rise_delay.maxlen >= 12 || 2174 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2175 goto skip_fall; 2176 2177 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2178 sdr_set_bits(host->base + MSDC_IOCON, 2179 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2180 for (i = 0; i < PAD_DELAY_MAX; i++) { 2181 msdc_set_cmd_delay(host, i); 2182 msdc_set_data_delay(host, i); 2183 ret = mmc_send_tuning(mmc, opcode, NULL); 2184 if (!ret) 2185 fall_delay |= BIT(i); 2186 } 2187 final_fall_delay = get_best_delay(host, fall_delay); 2188 2189 skip_fall: 2190 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2191 if (final_maxlen == final_rise_delay.maxlen) { 2192 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2193 sdr_clr_bits(host->base + MSDC_IOCON, 2194 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2195 final_delay = final_rise_delay.final_phase; 2196 } else { 2197 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2198 sdr_set_bits(host->base + MSDC_IOCON, 2199 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2200 final_delay = final_fall_delay.final_phase; 2201 } 2202 2203 msdc_set_cmd_delay(host, final_delay); 2204 msdc_set_data_delay(host, final_delay); 2205 2206 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2207 return final_delay == 0xff ? -EIO : 0; 2208 } 2209 2210 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2211 { 2212 struct msdc_host *host = mmc_priv(mmc); 2213 int ret; 2214 u32 tune_reg = host->dev_comp->pad_tune_reg; 2215 2216 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2217 ret = msdc_tune_together(mmc, opcode); 2218 if (host->hs400_mode) { 2219 sdr_clr_bits(host->base + MSDC_IOCON, 2220 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2221 msdc_set_data_delay(host, 0); 2222 } 2223 goto tune_done; 2224 } 2225 if (host->hs400_mode && 2226 host->dev_comp->hs400_tune) 2227 ret = hs400_tune_response(mmc, opcode); 2228 else 2229 ret = msdc_tune_response(mmc, opcode); 2230 if (ret == -EIO) { 2231 dev_err(host->dev, "Tune response fail!\n"); 2232 return ret; 2233 } 2234 if (host->hs400_mode == false) { 2235 ret = msdc_tune_data(mmc, opcode); 2236 if (ret == -EIO) 2237 dev_err(host->dev, "Tune data fail!\n"); 2238 } 2239 2240 tune_done: 2241 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2242 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2243 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2244 if (host->top_base) { 2245 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2246 EMMC_TOP_CONTROL); 2247 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2248 EMMC_TOP_CMD); 2249 } 2250 return ret; 2251 } 2252 2253 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2254 { 2255 struct msdc_host *host = mmc_priv(mmc); 2256 host->hs400_mode = true; 2257 2258 if (host->top_base) 2259 writel(host->hs400_ds_delay, 2260 host->top_base + EMMC50_PAD_DS_TUNE); 2261 else 2262 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2263 /* hs400 mode must set it to 0 */ 2264 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2265 /* to improve read performance, set outstanding to 2 */ 2266 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2267 2268 return 0; 2269 } 2270 2271 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) 2272 { 2273 struct msdc_host *host = mmc_priv(mmc); 2274 struct msdc_delay_phase dly1_delay; 2275 u32 val, result_dly1 = 0; 2276 u8 *ext_csd; 2277 int i, ret; 2278 2279 if (host->top_base) { 2280 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, 2281 PAD_DS_DLY_SEL); 2282 if (host->hs400_ds_dly3) 2283 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2284 PAD_DS_DLY3, host->hs400_ds_dly3); 2285 } else { 2286 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); 2287 if (host->hs400_ds_dly3) 2288 sdr_set_field(host->base + PAD_DS_TUNE, 2289 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); 2290 } 2291 2292 host->hs400_tuning = true; 2293 for (i = 0; i < PAD_DELAY_MAX; i++) { 2294 if (host->top_base) 2295 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2296 PAD_DS_DLY1, i); 2297 else 2298 sdr_set_field(host->base + PAD_DS_TUNE, 2299 PAD_DS_TUNE_DLY1, i); 2300 ret = mmc_get_ext_csd(card, &ext_csd); 2301 if (!ret) { 2302 result_dly1 |= BIT(i); 2303 kfree(ext_csd); 2304 } 2305 } 2306 host->hs400_tuning = false; 2307 2308 dly1_delay = get_best_delay(host, result_dly1); 2309 if (dly1_delay.maxlen == 0) { 2310 dev_err(host->dev, "Failed to get DLY1 delay!\n"); 2311 goto fail; 2312 } 2313 if (host->top_base) 2314 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, 2315 PAD_DS_DLY1, dly1_delay.final_phase); 2316 else 2317 sdr_set_field(host->base + PAD_DS_TUNE, 2318 PAD_DS_TUNE_DLY1, dly1_delay.final_phase); 2319 2320 if (host->top_base) 2321 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); 2322 else 2323 val = readl(host->base + PAD_DS_TUNE); 2324 2325 dev_info(host->dev, "Fianl PAD_DS_TUNE: 0x%x\n", val); 2326 2327 return 0; 2328 2329 fail: 2330 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); 2331 return -EIO; 2332 } 2333 2334 static void msdc_hw_reset(struct mmc_host *mmc) 2335 { 2336 struct msdc_host *host = mmc_priv(mmc); 2337 2338 sdr_set_bits(host->base + EMMC_IOCON, 1); 2339 udelay(10); /* 10us is enough */ 2340 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2341 } 2342 2343 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2344 { 2345 unsigned long flags; 2346 struct msdc_host *host = mmc_priv(mmc); 2347 2348 spin_lock_irqsave(&host->lock, flags); 2349 __msdc_enable_sdio_irq(host, 1); 2350 spin_unlock_irqrestore(&host->lock, flags); 2351 } 2352 2353 static int msdc_get_cd(struct mmc_host *mmc) 2354 { 2355 struct msdc_host *host = mmc_priv(mmc); 2356 int val; 2357 2358 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2359 return 1; 2360 2361 if (!host->internal_cd) 2362 return mmc_gpio_get_cd(mmc); 2363 2364 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2365 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2366 return !!val; 2367 else 2368 return !val; 2369 } 2370 2371 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2372 struct mmc_ios *ios) 2373 { 2374 struct msdc_host *host = mmc_priv(mmc); 2375 2376 if (ios->enhanced_strobe) { 2377 msdc_prepare_hs400_tuning(mmc, ios); 2378 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2379 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2380 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2381 2382 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2383 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2384 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2385 } else { 2386 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2387 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2388 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2389 2390 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2391 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2392 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2393 } 2394 } 2395 2396 static void msdc_cqe_enable(struct mmc_host *mmc) 2397 { 2398 struct msdc_host *host = mmc_priv(mmc); 2399 2400 /* enable cmdq irq */ 2401 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2402 /* enable busy check */ 2403 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2404 /* default write data / busy timeout 20s */ 2405 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2406 /* default read data timeout 1s */ 2407 msdc_set_timeout(host, 1000000000ULL, 0); 2408 } 2409 2410 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2411 { 2412 struct msdc_host *host = mmc_priv(mmc); 2413 unsigned int val = 0; 2414 2415 /* disable cmdq irq */ 2416 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2417 /* disable busy check */ 2418 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2419 2420 if (recovery) { 2421 sdr_set_field(host->base + MSDC_DMA_CTRL, 2422 MSDC_DMA_CTRL_STOP, 1); 2423 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, 2424 !(val & MSDC_DMA_CFG_STS), 1, 3000))) 2425 return; 2426 msdc_reset_hw(host); 2427 } 2428 } 2429 2430 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2431 { 2432 struct cqhci_host *cq_host = mmc->cqe_private; 2433 u32 reg; 2434 2435 reg = cqhci_readl(cq_host, CQHCI_CFG); 2436 reg |= CQHCI_ENABLE; 2437 cqhci_writel(cq_host, reg, CQHCI_CFG); 2438 } 2439 2440 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2441 { 2442 struct cqhci_host *cq_host = mmc->cqe_private; 2443 u32 reg; 2444 2445 reg = cqhci_readl(cq_host, CQHCI_CFG); 2446 reg &= ~CQHCI_ENABLE; 2447 cqhci_writel(cq_host, reg, CQHCI_CFG); 2448 } 2449 2450 static const struct mmc_host_ops mt_msdc_ops = { 2451 .post_req = msdc_post_req, 2452 .pre_req = msdc_pre_req, 2453 .request = msdc_ops_request, 2454 .set_ios = msdc_ops_set_ios, 2455 .get_ro = mmc_gpio_get_ro, 2456 .get_cd = msdc_get_cd, 2457 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2458 .enable_sdio_irq = msdc_enable_sdio_irq, 2459 .ack_sdio_irq = msdc_ack_sdio_irq, 2460 .start_signal_voltage_switch = msdc_ops_switch_volt, 2461 .card_busy = msdc_card_busy, 2462 .execute_tuning = msdc_execute_tuning, 2463 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2464 .execute_hs400_tuning = msdc_execute_hs400_tuning, 2465 .hw_reset = msdc_hw_reset, 2466 }; 2467 2468 static const struct cqhci_host_ops msdc_cmdq_ops = { 2469 .enable = msdc_cqe_enable, 2470 .disable = msdc_cqe_disable, 2471 .pre_enable = msdc_cqe_pre_enable, 2472 .post_disable = msdc_cqe_post_disable, 2473 }; 2474 2475 static void msdc_of_property_parse(struct platform_device *pdev, 2476 struct msdc_host *host) 2477 { 2478 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2479 &host->latch_ck); 2480 2481 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2482 &host->hs400_ds_delay); 2483 2484 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", 2485 &host->hs400_ds_dly3); 2486 2487 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2488 &host->hs200_cmd_int_delay); 2489 2490 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2491 &host->hs400_cmd_int_delay); 2492 2493 if (of_property_read_bool(pdev->dev.of_node, 2494 "mediatek,hs400-cmd-resp-sel-rising")) 2495 host->hs400_cmd_resp_sel_rising = true; 2496 else 2497 host->hs400_cmd_resp_sel_rising = false; 2498 2499 if (of_property_read_bool(pdev->dev.of_node, 2500 "supports-cqe")) 2501 host->cqhci = true; 2502 else 2503 host->cqhci = false; 2504 } 2505 2506 static int msdc_of_clock_parse(struct platform_device *pdev, 2507 struct msdc_host *host) 2508 { 2509 int ret; 2510 2511 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2512 if (IS_ERR(host->src_clk)) 2513 return PTR_ERR(host->src_clk); 2514 2515 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2516 if (IS_ERR(host->h_clk)) 2517 return PTR_ERR(host->h_clk); 2518 2519 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2520 if (IS_ERR(host->bus_clk)) 2521 host->bus_clk = NULL; 2522 2523 /*source clock control gate is optional clock*/ 2524 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2525 if (IS_ERR(host->src_clk_cg)) 2526 host->src_clk_cg = NULL; 2527 2528 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2529 if (IS_ERR(host->sys_clk_cg)) 2530 host->sys_clk_cg = NULL; 2531 2532 /* If present, always enable for this clock gate */ 2533 clk_prepare_enable(host->sys_clk_cg); 2534 2535 host->bulk_clks[0].id = "pclk_cg"; 2536 host->bulk_clks[1].id = "axi_cg"; 2537 host->bulk_clks[2].id = "ahb_cg"; 2538 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2539 host->bulk_clks); 2540 if (ret) { 2541 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2542 return ret; 2543 } 2544 2545 return 0; 2546 } 2547 2548 static int msdc_drv_probe(struct platform_device *pdev) 2549 { 2550 struct mmc_host *mmc; 2551 struct msdc_host *host; 2552 struct resource *res; 2553 int ret; 2554 2555 if (!pdev->dev.of_node) { 2556 dev_err(&pdev->dev, "No DT found\n"); 2557 return -EINVAL; 2558 } 2559 2560 /* Allocate MMC host for this device */ 2561 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2562 if (!mmc) 2563 return -ENOMEM; 2564 2565 host = mmc_priv(mmc); 2566 ret = mmc_of_parse(mmc); 2567 if (ret) 2568 goto host_free; 2569 2570 host->base = devm_platform_ioremap_resource(pdev, 0); 2571 if (IS_ERR(host->base)) { 2572 ret = PTR_ERR(host->base); 2573 goto host_free; 2574 } 2575 2576 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2577 if (res) { 2578 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2579 if (IS_ERR(host->top_base)) 2580 host->top_base = NULL; 2581 } 2582 2583 ret = mmc_regulator_get_supply(mmc); 2584 if (ret) 2585 goto host_free; 2586 2587 ret = msdc_of_clock_parse(pdev, host); 2588 if (ret) 2589 goto host_free; 2590 2591 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2592 "hrst"); 2593 if (IS_ERR(host->reset)) { 2594 ret = PTR_ERR(host->reset); 2595 goto host_free; 2596 } 2597 2598 host->irq = platform_get_irq(pdev, 0); 2599 if (host->irq < 0) { 2600 ret = -EINVAL; 2601 goto host_free; 2602 } 2603 2604 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2605 if (IS_ERR(host->pinctrl)) { 2606 ret = PTR_ERR(host->pinctrl); 2607 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2608 goto host_free; 2609 } 2610 2611 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2612 if (IS_ERR(host->pins_default)) { 2613 ret = PTR_ERR(host->pins_default); 2614 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2615 goto host_free; 2616 } 2617 2618 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2619 if (IS_ERR(host->pins_uhs)) { 2620 ret = PTR_ERR(host->pins_uhs); 2621 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2622 goto host_free; 2623 } 2624 2625 msdc_of_property_parse(pdev, host); 2626 2627 host->dev = &pdev->dev; 2628 host->dev_comp = of_device_get_match_data(&pdev->dev); 2629 host->src_clk_freq = clk_get_rate(host->src_clk); 2630 /* Set host parameters to mmc */ 2631 mmc->ops = &mt_msdc_ops; 2632 if (host->dev_comp->clk_div_bits == 8) 2633 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2634 else 2635 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2636 2637 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2638 !mmc_can_gpio_cd(mmc) && 2639 host->dev_comp->use_internal_cd) { 2640 /* 2641 * Is removable but no GPIO declared, so 2642 * use internal functionality. 2643 */ 2644 host->internal_cd = true; 2645 } 2646 2647 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2648 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2649 2650 mmc->caps |= MMC_CAP_CMD23; 2651 if (host->cqhci) 2652 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2653 /* MMC core transfer sizes tunable parameters */ 2654 mmc->max_segs = MAX_BD_NUM; 2655 if (host->dev_comp->support_64g) 2656 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2657 else 2658 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2659 mmc->max_blk_size = 2048; 2660 mmc->max_req_size = 512 * 1024; 2661 mmc->max_blk_count = mmc->max_req_size / 512; 2662 if (host->dev_comp->support_64g) 2663 host->dma_mask = DMA_BIT_MASK(36); 2664 else 2665 host->dma_mask = DMA_BIT_MASK(32); 2666 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2667 2668 host->timeout_clks = 3 * 1048576; 2669 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2670 2 * sizeof(struct mt_gpdma_desc), 2671 &host->dma.gpd_addr, GFP_KERNEL); 2672 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2673 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2674 &host->dma.bd_addr, GFP_KERNEL); 2675 if (!host->dma.gpd || !host->dma.bd) { 2676 ret = -ENOMEM; 2677 goto release_mem; 2678 } 2679 msdc_init_gpd_bd(host, &host->dma); 2680 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2681 spin_lock_init(&host->lock); 2682 2683 platform_set_drvdata(pdev, mmc); 2684 ret = msdc_ungate_clock(host); 2685 if (ret) { 2686 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); 2687 goto release_mem; 2688 } 2689 msdc_init_hw(host); 2690 2691 if (mmc->caps2 & MMC_CAP2_CQE) { 2692 host->cq_host = devm_kzalloc(mmc->parent, 2693 sizeof(*host->cq_host), 2694 GFP_KERNEL); 2695 if (!host->cq_host) { 2696 ret = -ENOMEM; 2697 goto host_free; 2698 } 2699 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2700 host->cq_host->mmio = host->base + 0x800; 2701 host->cq_host->ops = &msdc_cmdq_ops; 2702 ret = cqhci_init(host->cq_host, mmc, true); 2703 if (ret) 2704 goto host_free; 2705 mmc->max_segs = 128; 2706 /* cqhci 16bit length */ 2707 /* 0 size, means 65536 so we don't have to -1 here */ 2708 mmc->max_seg_size = 64 * 1024; 2709 } 2710 2711 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2712 IRQF_TRIGGER_NONE, pdev->name, host); 2713 if (ret) 2714 goto release; 2715 2716 pm_runtime_set_active(host->dev); 2717 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2718 pm_runtime_use_autosuspend(host->dev); 2719 pm_runtime_enable(host->dev); 2720 ret = mmc_add_host(mmc); 2721 2722 if (ret) 2723 goto end; 2724 2725 return 0; 2726 end: 2727 pm_runtime_disable(host->dev); 2728 release: 2729 platform_set_drvdata(pdev, NULL); 2730 msdc_deinit_hw(host); 2731 msdc_gate_clock(host); 2732 release_mem: 2733 if (host->dma.gpd) 2734 dma_free_coherent(&pdev->dev, 2735 2 * sizeof(struct mt_gpdma_desc), 2736 host->dma.gpd, host->dma.gpd_addr); 2737 if (host->dma.bd) 2738 dma_free_coherent(&pdev->dev, 2739 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2740 host->dma.bd, host->dma.bd_addr); 2741 host_free: 2742 mmc_free_host(mmc); 2743 2744 return ret; 2745 } 2746 2747 static int msdc_drv_remove(struct platform_device *pdev) 2748 { 2749 struct mmc_host *mmc; 2750 struct msdc_host *host; 2751 2752 mmc = platform_get_drvdata(pdev); 2753 host = mmc_priv(mmc); 2754 2755 pm_runtime_get_sync(host->dev); 2756 2757 platform_set_drvdata(pdev, NULL); 2758 mmc_remove_host(mmc); 2759 msdc_deinit_hw(host); 2760 msdc_gate_clock(host); 2761 2762 pm_runtime_disable(host->dev); 2763 pm_runtime_put_noidle(host->dev); 2764 dma_free_coherent(&pdev->dev, 2765 2 * sizeof(struct mt_gpdma_desc), 2766 host->dma.gpd, host->dma.gpd_addr); 2767 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2768 host->dma.bd, host->dma.bd_addr); 2769 2770 mmc_free_host(mmc); 2771 2772 return 0; 2773 } 2774 2775 static void msdc_save_reg(struct msdc_host *host) 2776 { 2777 u32 tune_reg = host->dev_comp->pad_tune_reg; 2778 2779 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2780 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2781 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2782 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2783 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2784 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2785 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2786 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2787 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2788 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2789 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2790 if (host->top_base) { 2791 host->save_para.emmc_top_control = 2792 readl(host->top_base + EMMC_TOP_CONTROL); 2793 host->save_para.emmc_top_cmd = 2794 readl(host->top_base + EMMC_TOP_CMD); 2795 host->save_para.emmc50_pad_ds_tune = 2796 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2797 } else { 2798 host->save_para.pad_tune = readl(host->base + tune_reg); 2799 } 2800 } 2801 2802 static void msdc_restore_reg(struct msdc_host *host) 2803 { 2804 struct mmc_host *mmc = mmc_from_priv(host); 2805 u32 tune_reg = host->dev_comp->pad_tune_reg; 2806 2807 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2808 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2809 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2810 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2811 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2812 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2813 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2814 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2815 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2816 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2817 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2818 if (host->top_base) { 2819 writel(host->save_para.emmc_top_control, 2820 host->top_base + EMMC_TOP_CONTROL); 2821 writel(host->save_para.emmc_top_cmd, 2822 host->top_base + EMMC_TOP_CMD); 2823 writel(host->save_para.emmc50_pad_ds_tune, 2824 host->top_base + EMMC50_PAD_DS_TUNE); 2825 } else { 2826 writel(host->save_para.pad_tune, host->base + tune_reg); 2827 } 2828 2829 if (sdio_irq_claimed(mmc)) 2830 __msdc_enable_sdio_irq(host, 1); 2831 } 2832 2833 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2834 { 2835 struct mmc_host *mmc = dev_get_drvdata(dev); 2836 struct msdc_host *host = mmc_priv(mmc); 2837 2838 msdc_save_reg(host); 2839 msdc_gate_clock(host); 2840 return 0; 2841 } 2842 2843 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2844 { 2845 struct mmc_host *mmc = dev_get_drvdata(dev); 2846 struct msdc_host *host = mmc_priv(mmc); 2847 int ret; 2848 2849 ret = msdc_ungate_clock(host); 2850 if (ret) 2851 return ret; 2852 2853 msdc_restore_reg(host); 2854 return 0; 2855 } 2856 2857 static int __maybe_unused msdc_suspend(struct device *dev) 2858 { 2859 struct mmc_host *mmc = dev_get_drvdata(dev); 2860 int ret; 2861 2862 if (mmc->caps2 & MMC_CAP2_CQE) { 2863 ret = cqhci_suspend(mmc); 2864 if (ret) 2865 return ret; 2866 } 2867 2868 return pm_runtime_force_suspend(dev); 2869 } 2870 2871 static int __maybe_unused msdc_resume(struct device *dev) 2872 { 2873 return pm_runtime_force_resume(dev); 2874 } 2875 2876 static const struct dev_pm_ops msdc_dev_pm_ops = { 2877 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2878 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2879 }; 2880 2881 static struct platform_driver mt_msdc_driver = { 2882 .probe = msdc_drv_probe, 2883 .remove = msdc_drv_remove, 2884 .driver = { 2885 .name = "mtk-msdc", 2886 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2887 .of_match_table = msdc_of_ids, 2888 .pm = &msdc_dev_pm_ops, 2889 }, 2890 }; 2891 2892 module_platform_driver(mt_msdc_driver); 2893 MODULE_LICENSE("GPL v2"); 2894 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2895