xref: /linux/drivers/mmc/host/mtk-sd.c (revision 4b132aacb0768ac1e652cf517097ea6f237214b9)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2014-2015, 2022 MediaTek Inc.
4  * Author: Chaotian.Jing <chaotian.jing@mediatek.com>
5  */
6 
7 #include <linux/module.h>
8 #include <linux/bitops.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/iopoll.h>
13 #include <linux/ioport.h>
14 #include <linux/irq.h>
15 #include <linux/of.h>
16 #include <linux/pinctrl/consumer.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm.h>
19 #include <linux/pm_runtime.h>
20 #include <linux/pm_wakeirq.h>
21 #include <linux/regulator/consumer.h>
22 #include <linux/slab.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/reset.h>
26 
27 #include <linux/mmc/card.h>
28 #include <linux/mmc/core.h>
29 #include <linux/mmc/host.h>
30 #include <linux/mmc/mmc.h>
31 #include <linux/mmc/sd.h>
32 #include <linux/mmc/sdio.h>
33 #include <linux/mmc/slot-gpio.h>
34 
35 #include "cqhci.h"
36 
37 #define MAX_BD_NUM          1024
38 #define MSDC_NR_CLOCKS      3
39 
40 /*--------------------------------------------------------------------------*/
41 /* Common Definition                                                        */
42 /*--------------------------------------------------------------------------*/
43 #define MSDC_BUS_1BITS          0x0
44 #define MSDC_BUS_4BITS          0x1
45 #define MSDC_BUS_8BITS          0x2
46 
47 #define MSDC_BURST_64B          0x6
48 
49 /*--------------------------------------------------------------------------*/
50 /* Register Offset                                                          */
51 /*--------------------------------------------------------------------------*/
52 #define MSDC_CFG         0x0
53 #define MSDC_IOCON       0x04
54 #define MSDC_PS          0x08
55 #define MSDC_INT         0x0c
56 #define MSDC_INTEN       0x10
57 #define MSDC_FIFOCS      0x14
58 #define SDC_CFG          0x30
59 #define SDC_CMD          0x34
60 #define SDC_ARG          0x38
61 #define SDC_STS          0x3c
62 #define SDC_RESP0        0x40
63 #define SDC_RESP1        0x44
64 #define SDC_RESP2        0x48
65 #define SDC_RESP3        0x4c
66 #define SDC_BLK_NUM      0x50
67 #define SDC_ADV_CFG0     0x64
68 #define EMMC_IOCON       0x7c
69 #define SDC_ACMD_RESP    0x80
70 #define DMA_SA_H4BIT     0x8c
71 #define MSDC_DMA_SA      0x90
72 #define MSDC_DMA_CTRL    0x98
73 #define MSDC_DMA_CFG     0x9c
74 #define MSDC_PATCH_BIT   0xb0
75 #define MSDC_PATCH_BIT1  0xb4
76 #define MSDC_PATCH_BIT2  0xb8
77 #define MSDC_PAD_TUNE    0xec
78 #define MSDC_PAD_TUNE0   0xf0
79 #define PAD_DS_TUNE      0x188
80 #define PAD_CMD_TUNE     0x18c
81 #define EMMC51_CFG0	 0x204
82 #define EMMC50_CFG0      0x208
83 #define EMMC50_CFG1      0x20c
84 #define EMMC50_CFG3      0x220
85 #define SDC_FIFO_CFG     0x228
86 #define CQHCI_SETTING	 0x7fc
87 
88 /*--------------------------------------------------------------------------*/
89 /* Top Pad Register Offset                                                  */
90 /*--------------------------------------------------------------------------*/
91 #define EMMC_TOP_CONTROL	0x00
92 #define EMMC_TOP_CMD		0x04
93 #define EMMC50_PAD_DS_TUNE	0x0c
94 
95 /*--------------------------------------------------------------------------*/
96 /* Register Mask                                                            */
97 /*--------------------------------------------------------------------------*/
98 
99 /* MSDC_CFG mask */
100 #define MSDC_CFG_MODE           BIT(0)	/* RW */
101 #define MSDC_CFG_CKPDN          BIT(1)	/* RW */
102 #define MSDC_CFG_RST            BIT(2)	/* RW */
103 #define MSDC_CFG_PIO            BIT(3)	/* RW */
104 #define MSDC_CFG_CKDRVEN        BIT(4)	/* RW */
105 #define MSDC_CFG_BV18SDT        BIT(5)	/* RW */
106 #define MSDC_CFG_BV18PSS        BIT(6)	/* R  */
107 #define MSDC_CFG_CKSTB          BIT(7)	/* R  */
108 #define MSDC_CFG_CKDIV          GENMASK(15, 8)	/* RW */
109 #define MSDC_CFG_CKMOD          GENMASK(17, 16)	/* RW */
110 #define MSDC_CFG_HS400_CK_MODE  BIT(18)	/* RW */
111 #define MSDC_CFG_HS400_CK_MODE_EXTRA  BIT(22)	/* RW */
112 #define MSDC_CFG_CKDIV_EXTRA    GENMASK(19, 8)	/* RW */
113 #define MSDC_CFG_CKMOD_EXTRA    GENMASK(21, 20)	/* RW */
114 
115 /* MSDC_IOCON mask */
116 #define MSDC_IOCON_SDR104CKS    BIT(0)	/* RW */
117 #define MSDC_IOCON_RSPL         BIT(1)	/* RW */
118 #define MSDC_IOCON_DSPL         BIT(2)	/* RW */
119 #define MSDC_IOCON_DDLSEL       BIT(3)	/* RW */
120 #define MSDC_IOCON_DDR50CKD     BIT(4)	/* RW */
121 #define MSDC_IOCON_DSPLSEL      BIT(5)	/* RW */
122 #define MSDC_IOCON_W_DSPL       BIT(8)	/* RW */
123 #define MSDC_IOCON_D0SPL        BIT(16)	/* RW */
124 #define MSDC_IOCON_D1SPL        BIT(17)	/* RW */
125 #define MSDC_IOCON_D2SPL        BIT(18)	/* RW */
126 #define MSDC_IOCON_D3SPL        BIT(19)	/* RW */
127 #define MSDC_IOCON_D4SPL        BIT(20)	/* RW */
128 #define MSDC_IOCON_D5SPL        BIT(21)	/* RW */
129 #define MSDC_IOCON_D6SPL        BIT(22)	/* RW */
130 #define MSDC_IOCON_D7SPL        BIT(23)	/* RW */
131 #define MSDC_IOCON_RISCSZ       GENMASK(25, 24)	/* RW */
132 
133 /* MSDC_PS mask */
134 #define MSDC_PS_CDEN            BIT(0)	/* RW */
135 #define MSDC_PS_CDSTS           BIT(1)	/* R  */
136 #define MSDC_PS_CDDEBOUNCE      GENMASK(15, 12)	/* RW */
137 #define MSDC_PS_DAT             GENMASK(23, 16)	/* R  */
138 #define MSDC_PS_DATA1           BIT(17)	/* R  */
139 #define MSDC_PS_CMD             BIT(24)	/* R  */
140 #define MSDC_PS_WP              BIT(31)	/* R  */
141 
142 /* MSDC_INT mask */
143 #define MSDC_INT_MMCIRQ         BIT(0)	/* W1C */
144 #define MSDC_INT_CDSC           BIT(1)	/* W1C */
145 #define MSDC_INT_ACMDRDY        BIT(3)	/* W1C */
146 #define MSDC_INT_ACMDTMO        BIT(4)	/* W1C */
147 #define MSDC_INT_ACMDCRCERR     BIT(5)	/* W1C */
148 #define MSDC_INT_DMAQ_EMPTY     BIT(6)	/* W1C */
149 #define MSDC_INT_SDIOIRQ        BIT(7)	/* W1C */
150 #define MSDC_INT_CMDRDY         BIT(8)	/* W1C */
151 #define MSDC_INT_CMDTMO         BIT(9)	/* W1C */
152 #define MSDC_INT_RSPCRCERR      BIT(10)	/* W1C */
153 #define MSDC_INT_CSTA           BIT(11)	/* R */
154 #define MSDC_INT_XFER_COMPL     BIT(12)	/* W1C */
155 #define MSDC_INT_DXFER_DONE     BIT(13)	/* W1C */
156 #define MSDC_INT_DATTMO         BIT(14)	/* W1C */
157 #define MSDC_INT_DATCRCERR      BIT(15)	/* W1C */
158 #define MSDC_INT_ACMD19_DONE    BIT(16)	/* W1C */
159 #define MSDC_INT_DMA_BDCSERR    BIT(17)	/* W1C */
160 #define MSDC_INT_DMA_GPDCSERR   BIT(18)	/* W1C */
161 #define MSDC_INT_DMA_PROTECT    BIT(19)	/* W1C */
162 #define MSDC_INT_CMDQ           BIT(28)	/* W1C */
163 
164 /* MSDC_INTEN mask */
165 #define MSDC_INTEN_MMCIRQ       BIT(0)	/* RW */
166 #define MSDC_INTEN_CDSC         BIT(1)	/* RW */
167 #define MSDC_INTEN_ACMDRDY      BIT(3)	/* RW */
168 #define MSDC_INTEN_ACMDTMO      BIT(4)	/* RW */
169 #define MSDC_INTEN_ACMDCRCERR   BIT(5)	/* RW */
170 #define MSDC_INTEN_DMAQ_EMPTY   BIT(6)	/* RW */
171 #define MSDC_INTEN_SDIOIRQ      BIT(7)	/* RW */
172 #define MSDC_INTEN_CMDRDY       BIT(8)	/* RW */
173 #define MSDC_INTEN_CMDTMO       BIT(9)	/* RW */
174 #define MSDC_INTEN_RSPCRCERR    BIT(10)	/* RW */
175 #define MSDC_INTEN_CSTA         BIT(11)	/* RW */
176 #define MSDC_INTEN_XFER_COMPL   BIT(12)	/* RW */
177 #define MSDC_INTEN_DXFER_DONE   BIT(13)	/* RW */
178 #define MSDC_INTEN_DATTMO       BIT(14)	/* RW */
179 #define MSDC_INTEN_DATCRCERR    BIT(15)	/* RW */
180 #define MSDC_INTEN_ACMD19_DONE  BIT(16)	/* RW */
181 #define MSDC_INTEN_DMA_BDCSERR  BIT(17)	/* RW */
182 #define MSDC_INTEN_DMA_GPDCSERR BIT(18)	/* RW */
183 #define MSDC_INTEN_DMA_PROTECT  BIT(19)	/* RW */
184 
185 /* MSDC_FIFOCS mask */
186 #define MSDC_FIFOCS_RXCNT       GENMASK(7, 0)	/* R */
187 #define MSDC_FIFOCS_TXCNT       GENMASK(23, 16)	/* R */
188 #define MSDC_FIFOCS_CLR         BIT(31)	/* RW */
189 
190 /* SDC_CFG mask */
191 #define SDC_CFG_SDIOINTWKUP     BIT(0)	/* RW */
192 #define SDC_CFG_INSWKUP         BIT(1)	/* RW */
193 #define SDC_CFG_WRDTOC          GENMASK(14, 2)  /* RW */
194 #define SDC_CFG_BUSWIDTH        GENMASK(17, 16)	/* RW */
195 #define SDC_CFG_SDIO            BIT(19)	/* RW */
196 #define SDC_CFG_SDIOIDE         BIT(20)	/* RW */
197 #define SDC_CFG_INTATGAP        BIT(21)	/* RW */
198 #define SDC_CFG_DTOC            GENMASK(31, 24)	/* RW */
199 
200 /* SDC_STS mask */
201 #define SDC_STS_SDCBUSY         BIT(0)	/* RW */
202 #define SDC_STS_CMDBUSY         BIT(1)	/* RW */
203 #define SDC_STS_SWR_COMPL       BIT(31)	/* RW */
204 
205 #define SDC_DAT1_IRQ_TRIGGER	BIT(19)	/* RW */
206 /* SDC_ADV_CFG0 mask */
207 #define SDC_RX_ENHANCE_EN	BIT(20)	/* RW */
208 
209 /* DMA_SA_H4BIT mask */
210 #define DMA_ADDR_HIGH_4BIT      GENMASK(3, 0)	/* RW */
211 
212 /* MSDC_DMA_CTRL mask */
213 #define MSDC_DMA_CTRL_START     BIT(0)	/* W */
214 #define MSDC_DMA_CTRL_STOP      BIT(1)	/* W */
215 #define MSDC_DMA_CTRL_RESUME    BIT(2)	/* W */
216 #define MSDC_DMA_CTRL_MODE      BIT(8)	/* RW */
217 #define MSDC_DMA_CTRL_LASTBUF   BIT(10)	/* RW */
218 #define MSDC_DMA_CTRL_BRUSTSZ   GENMASK(14, 12)	/* RW */
219 
220 /* MSDC_DMA_CFG mask */
221 #define MSDC_DMA_CFG_STS        BIT(0)	/* R */
222 #define MSDC_DMA_CFG_DECSEN     BIT(1)	/* RW */
223 #define MSDC_DMA_CFG_AHBHPROT2  BIT(9)	/* RW */
224 #define MSDC_DMA_CFG_ACTIVEEN   BIT(13)	/* RW */
225 #define MSDC_DMA_CFG_CS12B16B   BIT(16)	/* RW */
226 
227 /* MSDC_PATCH_BIT mask */
228 #define MSDC_PATCH_BIT_ODDSUPP    BIT(1)	/* RW */
229 #define MSDC_INT_DAT_LATCH_CK_SEL GENMASK(9, 7)
230 #define MSDC_CKGEN_MSDC_DLY_SEL   GENMASK(14, 10)
231 #define MSDC_PATCH_BIT_IODSSEL    BIT(16)	/* RW */
232 #define MSDC_PATCH_BIT_IOINTSEL   BIT(17)	/* RW */
233 #define MSDC_PATCH_BIT_BUSYDLY    GENMASK(21, 18)	/* RW */
234 #define MSDC_PATCH_BIT_WDOD       GENMASK(25, 22)	/* RW */
235 #define MSDC_PATCH_BIT_IDRTSEL    BIT(26)	/* RW */
236 #define MSDC_PATCH_BIT_CMDFSEL    BIT(27)	/* RW */
237 #define MSDC_PATCH_BIT_INTDLSEL   BIT(28)	/* RW */
238 #define MSDC_PATCH_BIT_SPCPUSH    BIT(29)	/* RW */
239 #define MSDC_PATCH_BIT_DECRCTMO   BIT(30)	/* RW */
240 
241 #define MSDC_PATCH_BIT1_CMDTA     GENMASK(5, 3)    /* RW */
242 #define MSDC_PB1_BUSY_CHECK_SEL   BIT(7)    /* RW */
243 #define MSDC_PATCH_BIT1_STOP_DLY  GENMASK(11, 8)    /* RW */
244 
245 #define MSDC_PATCH_BIT2_CFGRESP   BIT(15)   /* RW */
246 #define MSDC_PATCH_BIT2_CFGCRCSTS BIT(28)   /* RW */
247 #define MSDC_PB2_SUPPORT_64G      BIT(1)    /* RW */
248 #define MSDC_PB2_RESPWAIT         GENMASK(3, 2)   /* RW */
249 #define MSDC_PB2_RESPSTSENSEL     GENMASK(18, 16) /* RW */
250 #define MSDC_PB2_CRCSTSENSEL      GENMASK(31, 29) /* RW */
251 
252 #define MSDC_PAD_TUNE_DATWRDLY	  GENMASK(4, 0)		/* RW */
253 #define MSDC_PAD_TUNE_DATRRDLY	  GENMASK(12, 8)	/* RW */
254 #define MSDC_PAD_TUNE_DATRRDLY2	  GENMASK(12, 8)	/* RW */
255 #define MSDC_PAD_TUNE_CMDRDLY	  GENMASK(20, 16)	/* RW */
256 #define MSDC_PAD_TUNE_CMDRDLY2	  GENMASK(20, 16)	/* RW */
257 #define MSDC_PAD_TUNE_CMDRRDLY	  GENMASK(26, 22)	/* RW */
258 #define MSDC_PAD_TUNE_CLKTDLY	  GENMASK(31, 27)	/* RW */
259 #define MSDC_PAD_TUNE_RXDLYSEL	  BIT(15)   /* RW */
260 #define MSDC_PAD_TUNE_RD_SEL	  BIT(13)   /* RW */
261 #define MSDC_PAD_TUNE_CMD_SEL	  BIT(21)   /* RW */
262 #define MSDC_PAD_TUNE_RD2_SEL	  BIT(13)   /* RW */
263 #define MSDC_PAD_TUNE_CMD2_SEL	  BIT(21)   /* RW */
264 
265 #define PAD_DS_TUNE_DLY_SEL       BIT(0)	  /* RW */
266 #define PAD_DS_TUNE_DLY1	  GENMASK(6, 2)   /* RW */
267 #define PAD_DS_TUNE_DLY2	  GENMASK(11, 7)  /* RW */
268 #define PAD_DS_TUNE_DLY3	  GENMASK(16, 12) /* RW */
269 
270 #define PAD_CMD_TUNE_RX_DLY3	  GENMASK(5, 1)   /* RW */
271 
272 /* EMMC51_CFG0 mask */
273 #define CMDQ_RDAT_CNT		  GENMASK(21, 12) /* RW */
274 
275 #define EMMC50_CFG_PADCMD_LATCHCK BIT(0)   /* RW */
276 #define EMMC50_CFG_CRCSTS_EDGE    BIT(3)   /* RW */
277 #define EMMC50_CFG_CFCSTS_SEL     BIT(4)   /* RW */
278 #define EMMC50_CFG_CMD_RESP_SEL   BIT(9)   /* RW */
279 
280 /* EMMC50_CFG1 mask */
281 #define EMMC50_CFG1_DS_CFG        BIT(28)  /* RW */
282 
283 #define EMMC50_CFG3_OUTS_WR       GENMASK(4, 0)  /* RW */
284 
285 #define SDC_FIFO_CFG_WRVALIDSEL   BIT(24)  /* RW */
286 #define SDC_FIFO_CFG_RDVALIDSEL   BIT(25)  /* RW */
287 
288 /* CQHCI_SETTING */
289 #define CQHCI_RD_CMD_WND_SEL	  BIT(14) /* RW */
290 #define CQHCI_WR_CMD_WND_SEL	  BIT(15) /* RW */
291 
292 /* EMMC_TOP_CONTROL mask */
293 #define PAD_RXDLY_SEL           BIT(0)      /* RW */
294 #define DELAY_EN                BIT(1)      /* RW */
295 #define PAD_DAT_RD_RXDLY2       GENMASK(6, 2)     /* RW */
296 #define PAD_DAT_RD_RXDLY        GENMASK(11, 7)    /* RW */
297 #define PAD_DAT_RD_RXDLY2_SEL   BIT(12)     /* RW */
298 #define PAD_DAT_RD_RXDLY_SEL    BIT(13)     /* RW */
299 #define DATA_K_VALUE_SEL        BIT(14)     /* RW */
300 #define SDC_RX_ENH_EN           BIT(15)     /* TW */
301 
302 /* EMMC_TOP_CMD mask */
303 #define PAD_CMD_RXDLY2          GENMASK(4, 0)	/* RW */
304 #define PAD_CMD_RXDLY           GENMASK(9, 5)	/* RW */
305 #define PAD_CMD_RD_RXDLY2_SEL   BIT(10)		/* RW */
306 #define PAD_CMD_RD_RXDLY_SEL    BIT(11)		/* RW */
307 #define PAD_CMD_TX_DLY          GENMASK(16, 12)	/* RW */
308 
309 /* EMMC50_PAD_DS_TUNE mask */
310 #define PAD_DS_DLY_SEL		BIT(16)	/* RW */
311 #define PAD_DS_DLY1		GENMASK(14, 10)	/* RW */
312 #define PAD_DS_DLY3		GENMASK(4, 0)	/* RW */
313 
314 #define REQ_CMD_EIO  BIT(0)
315 #define REQ_CMD_TMO  BIT(1)
316 #define REQ_DAT_ERR  BIT(2)
317 #define REQ_STOP_EIO BIT(3)
318 #define REQ_STOP_TMO BIT(4)
319 #define REQ_CMD_BUSY BIT(5)
320 
321 #define MSDC_PREPARE_FLAG BIT(0)
322 #define MSDC_ASYNC_FLAG BIT(1)
323 #define MSDC_MMAP_FLAG BIT(2)
324 
325 #define MTK_MMC_AUTOSUSPEND_DELAY	50
326 #define CMD_TIMEOUT         (HZ/10 * 5)	/* 100ms x5 */
327 #define DAT_TIMEOUT         (HZ    * 5)	/* 1000ms x5 */
328 
329 #define DEFAULT_DEBOUNCE	(8)	/* 8 cycles CD debounce */
330 
331 #define TUNING_REG2_FIXED_OFFEST	4
332 #define PAD_DELAY_HALF	32 /* PAD delay cells */
333 #define PAD_DELAY_FULL	64
334 /*--------------------------------------------------------------------------*/
335 /* Descriptor Structure                                                     */
336 /*--------------------------------------------------------------------------*/
337 struct mt_gpdma_desc {
338 	u32 gpd_info;
339 #define GPDMA_DESC_HWO		BIT(0)
340 #define GPDMA_DESC_BDP		BIT(1)
341 #define GPDMA_DESC_CHECKSUM	GENMASK(15, 8)
342 #define GPDMA_DESC_INT		BIT(16)
343 #define GPDMA_DESC_NEXT_H4	GENMASK(27, 24)
344 #define GPDMA_DESC_PTR_H4	GENMASK(31, 28)
345 	u32 next;
346 	u32 ptr;
347 	u32 gpd_data_len;
348 #define GPDMA_DESC_BUFLEN	GENMASK(15, 0)
349 #define GPDMA_DESC_EXTLEN	GENMASK(23, 16)
350 	u32 arg;
351 	u32 blknum;
352 	u32 cmd;
353 };
354 
355 struct mt_bdma_desc {
356 	u32 bd_info;
357 #define BDMA_DESC_EOL		BIT(0)
358 #define BDMA_DESC_CHECKSUM	GENMASK(15, 8)
359 #define BDMA_DESC_BLKPAD	BIT(17)
360 #define BDMA_DESC_DWPAD		BIT(18)
361 #define BDMA_DESC_NEXT_H4	GENMASK(27, 24)
362 #define BDMA_DESC_PTR_H4	GENMASK(31, 28)
363 	u32 next;
364 	u32 ptr;
365 	u32 bd_data_len;
366 #define BDMA_DESC_BUFLEN	GENMASK(15, 0)
367 #define BDMA_DESC_BUFLEN_EXT	GENMASK(23, 0)
368 };
369 
370 struct msdc_dma {
371 	struct scatterlist *sg;	/* I/O scatter list */
372 	struct mt_gpdma_desc *gpd;		/* pointer to gpd array */
373 	struct mt_bdma_desc *bd;		/* pointer to bd array */
374 	dma_addr_t gpd_addr;	/* the physical address of gpd array */
375 	dma_addr_t bd_addr;	/* the physical address of bd array */
376 };
377 
378 struct msdc_save_para {
379 	u32 msdc_cfg;
380 	u32 iocon;
381 	u32 sdc_cfg;
382 	u32 pad_tune;
383 	u32 patch_bit0;
384 	u32 patch_bit1;
385 	u32 patch_bit2;
386 	u32 pad_ds_tune;
387 	u32 pad_cmd_tune;
388 	u32 emmc50_cfg0;
389 	u32 emmc50_cfg3;
390 	u32 sdc_fifo_cfg;
391 	u32 emmc_top_control;
392 	u32 emmc_top_cmd;
393 	u32 emmc50_pad_ds_tune;
394 };
395 
396 struct mtk_mmc_compatible {
397 	u8 clk_div_bits;
398 	bool recheck_sdio_irq;
399 	bool hs400_tune; /* only used for MT8173 */
400 	u32 pad_tune_reg;
401 	bool async_fifo;
402 	bool data_tune;
403 	bool busy_check;
404 	bool stop_clk_fix;
405 	bool enhance_rx;
406 	bool support_64g;
407 	bool use_internal_cd;
408 };
409 
410 struct msdc_tune_para {
411 	u32 iocon;
412 	u32 pad_tune;
413 	u32 pad_cmd_tune;
414 	u32 emmc_top_control;
415 	u32 emmc_top_cmd;
416 };
417 
418 struct msdc_delay_phase {
419 	u8 maxlen;
420 	u8 start;
421 	u8 final_phase;
422 };
423 
424 struct msdc_host {
425 	struct device *dev;
426 	const struct mtk_mmc_compatible *dev_comp;
427 	int cmd_rsp;
428 
429 	spinlock_t lock;
430 	struct mmc_request *mrq;
431 	struct mmc_command *cmd;
432 	struct mmc_data *data;
433 	int error;
434 
435 	void __iomem *base;		/* host base address */
436 	void __iomem *top_base;		/* host top register base address */
437 
438 	struct msdc_dma dma;	/* dma channel */
439 	u64 dma_mask;
440 
441 	u32 timeout_ns;		/* data timeout ns */
442 	u32 timeout_clks;	/* data timeout clks */
443 
444 	struct pinctrl *pinctrl;
445 	struct pinctrl_state *pins_default;
446 	struct pinctrl_state *pins_uhs;
447 	struct pinctrl_state *pins_eint;
448 	struct delayed_work req_timeout;
449 	int irq;		/* host interrupt */
450 	int eint_irq;		/* interrupt from sdio device for waking up system */
451 	struct reset_control *reset;
452 
453 	struct clk *src_clk;	/* msdc source clock */
454 	struct clk *h_clk;      /* msdc h_clk */
455 	struct clk *bus_clk;	/* bus clock which used to access register */
456 	struct clk *src_clk_cg; /* msdc source clock control gate */
457 	struct clk *sys_clk_cg;	/* msdc subsys clock control gate */
458 	struct clk *crypto_clk; /* msdc crypto clock control gate */
459 	struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS];
460 	u32 mclk;		/* mmc subsystem clock frequency */
461 	u32 src_clk_freq;	/* source clock frequency */
462 	unsigned char timing;
463 	bool vqmmc_enabled;
464 	u32 latch_ck;
465 	u32 hs400_ds_delay;
466 	u32 hs400_ds_dly3;
467 	u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */
468 	u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */
469 	u32 tuning_step;
470 	bool hs400_cmd_resp_sel_rising;
471 				 /* cmd response sample selection for HS400 */
472 	bool hs400_mode;	/* current eMMC will run at hs400 mode */
473 	bool hs400_tuning;	/* hs400 mode online tuning */
474 	bool internal_cd;	/* Use internal card-detect logic */
475 	bool cqhci;		/* support eMMC hw cmdq */
476 	struct msdc_save_para save_para; /* used when gate HCLK */
477 	struct msdc_tune_para def_tune_para; /* default tune setting */
478 	struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */
479 	struct cqhci_host *cq_host;
480 	u32 cq_ssc1_time;
481 };
482 
483 static const struct mtk_mmc_compatible mt2701_compat = {
484 	.clk_div_bits = 12,
485 	.recheck_sdio_irq = true,
486 	.hs400_tune = false,
487 	.pad_tune_reg = MSDC_PAD_TUNE0,
488 	.async_fifo = true,
489 	.data_tune = true,
490 	.busy_check = false,
491 	.stop_clk_fix = false,
492 	.enhance_rx = false,
493 	.support_64g = false,
494 };
495 
496 static const struct mtk_mmc_compatible mt2712_compat = {
497 	.clk_div_bits = 12,
498 	.recheck_sdio_irq = false,
499 	.hs400_tune = false,
500 	.pad_tune_reg = MSDC_PAD_TUNE0,
501 	.async_fifo = true,
502 	.data_tune = true,
503 	.busy_check = true,
504 	.stop_clk_fix = true,
505 	.enhance_rx = true,
506 	.support_64g = true,
507 };
508 
509 static const struct mtk_mmc_compatible mt6779_compat = {
510 	.clk_div_bits = 12,
511 	.recheck_sdio_irq = false,
512 	.hs400_tune = false,
513 	.pad_tune_reg = MSDC_PAD_TUNE0,
514 	.async_fifo = true,
515 	.data_tune = true,
516 	.busy_check = true,
517 	.stop_clk_fix = true,
518 	.enhance_rx = true,
519 	.support_64g = true,
520 };
521 
522 static const struct mtk_mmc_compatible mt6795_compat = {
523 	.clk_div_bits = 8,
524 	.recheck_sdio_irq = false,
525 	.hs400_tune = true,
526 	.pad_tune_reg = MSDC_PAD_TUNE,
527 	.async_fifo = false,
528 	.data_tune = false,
529 	.busy_check = false,
530 	.stop_clk_fix = false,
531 	.enhance_rx = false,
532 	.support_64g = false,
533 };
534 
535 static const struct mtk_mmc_compatible mt7620_compat = {
536 	.clk_div_bits = 8,
537 	.recheck_sdio_irq = true,
538 	.hs400_tune = false,
539 	.pad_tune_reg = MSDC_PAD_TUNE,
540 	.async_fifo = false,
541 	.data_tune = false,
542 	.busy_check = false,
543 	.stop_clk_fix = false,
544 	.enhance_rx = false,
545 	.use_internal_cd = true,
546 };
547 
548 static const struct mtk_mmc_compatible mt7622_compat = {
549 	.clk_div_bits = 12,
550 	.recheck_sdio_irq = true,
551 	.hs400_tune = false,
552 	.pad_tune_reg = MSDC_PAD_TUNE0,
553 	.async_fifo = true,
554 	.data_tune = true,
555 	.busy_check = true,
556 	.stop_clk_fix = true,
557 	.enhance_rx = true,
558 	.support_64g = false,
559 };
560 
561 static const struct mtk_mmc_compatible mt7986_compat = {
562 	.clk_div_bits = 12,
563 	.recheck_sdio_irq = true,
564 	.hs400_tune = false,
565 	.pad_tune_reg = MSDC_PAD_TUNE0,
566 	.async_fifo = true,
567 	.data_tune = true,
568 	.busy_check = true,
569 	.stop_clk_fix = true,
570 	.enhance_rx = true,
571 	.support_64g = true,
572 };
573 
574 static const struct mtk_mmc_compatible mt8135_compat = {
575 	.clk_div_bits = 8,
576 	.recheck_sdio_irq = true,
577 	.hs400_tune = false,
578 	.pad_tune_reg = MSDC_PAD_TUNE,
579 	.async_fifo = false,
580 	.data_tune = false,
581 	.busy_check = false,
582 	.stop_clk_fix = false,
583 	.enhance_rx = false,
584 	.support_64g = false,
585 };
586 
587 static const struct mtk_mmc_compatible mt8173_compat = {
588 	.clk_div_bits = 8,
589 	.recheck_sdio_irq = true,
590 	.hs400_tune = true,
591 	.pad_tune_reg = MSDC_PAD_TUNE,
592 	.async_fifo = false,
593 	.data_tune = false,
594 	.busy_check = false,
595 	.stop_clk_fix = false,
596 	.enhance_rx = false,
597 	.support_64g = false,
598 };
599 
600 static const struct mtk_mmc_compatible mt8183_compat = {
601 	.clk_div_bits = 12,
602 	.recheck_sdio_irq = false,
603 	.hs400_tune = false,
604 	.pad_tune_reg = MSDC_PAD_TUNE0,
605 	.async_fifo = true,
606 	.data_tune = true,
607 	.busy_check = true,
608 	.stop_clk_fix = true,
609 	.enhance_rx = true,
610 	.support_64g = true,
611 };
612 
613 static const struct mtk_mmc_compatible mt8516_compat = {
614 	.clk_div_bits = 12,
615 	.recheck_sdio_irq = true,
616 	.hs400_tune = false,
617 	.pad_tune_reg = MSDC_PAD_TUNE0,
618 	.async_fifo = true,
619 	.data_tune = true,
620 	.busy_check = true,
621 	.stop_clk_fix = true,
622 };
623 
624 static const struct of_device_id msdc_of_ids[] = {
625 	{ .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
626 	{ .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
627 	{ .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
628 	{ .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
629 	{ .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
630 	{ .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
631 	{ .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
632 	{ .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
633 	{ .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
634 	{ .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
635 	{ .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
636 
637 	{}
638 };
639 MODULE_DEVICE_TABLE(of, msdc_of_ids);
640 
641 static void sdr_set_bits(void __iomem *reg, u32 bs)
642 {
643 	u32 val = readl(reg);
644 
645 	val |= bs;
646 	writel(val, reg);
647 }
648 
649 static void sdr_clr_bits(void __iomem *reg, u32 bs)
650 {
651 	u32 val = readl(reg);
652 
653 	val &= ~bs;
654 	writel(val, reg);
655 }
656 
657 static void sdr_set_field(void __iomem *reg, u32 field, u32 val)
658 {
659 	unsigned int tv = readl(reg);
660 
661 	tv &= ~field;
662 	tv |= ((val) << (ffs((unsigned int)field) - 1));
663 	writel(tv, reg);
664 }
665 
666 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val)
667 {
668 	unsigned int tv = readl(reg);
669 
670 	*val = ((tv & field) >> (ffs((unsigned int)field) - 1));
671 }
672 
673 static void msdc_reset_hw(struct msdc_host *host)
674 {
675 	u32 val;
676 
677 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST);
678 	readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0);
679 
680 	sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR);
681 	readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val,
682 				  !(val & MSDC_FIFOCS_CLR), 0, 0);
683 
684 	val = readl(host->base + MSDC_INT);
685 	writel(val, host->base + MSDC_INT);
686 }
687 
688 static void msdc_cmd_next(struct msdc_host *host,
689 		struct mmc_request *mrq, struct mmc_command *cmd);
690 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
691 
692 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR |
693 			MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY |
694 			MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO;
695 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO |
696 			MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR |
697 			MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT;
698 
699 static u8 msdc_dma_calcs(u8 *buf, u32 len)
700 {
701 	u32 i, sum = 0;
702 
703 	for (i = 0; i < len; i++)
704 		sum += buf[i];
705 	return 0xff - (u8) sum;
706 }
707 
708 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma,
709 		struct mmc_data *data)
710 {
711 	unsigned int j, dma_len;
712 	dma_addr_t dma_address;
713 	u32 dma_ctrl;
714 	struct scatterlist *sg;
715 	struct mt_gpdma_desc *gpd;
716 	struct mt_bdma_desc *bd;
717 
718 	sg = data->sg;
719 
720 	gpd = dma->gpd;
721 	bd = dma->bd;
722 
723 	/* modify gpd */
724 	gpd->gpd_info |= GPDMA_DESC_HWO;
725 	gpd->gpd_info |= GPDMA_DESC_BDP;
726 	/* need to clear first. use these bits to calc checksum */
727 	gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM;
728 	gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8;
729 
730 	/* modify bd */
731 	for_each_sg(data->sg, sg, data->sg_count, j) {
732 		dma_address = sg_dma_address(sg);
733 		dma_len = sg_dma_len(sg);
734 
735 		/* init bd */
736 		bd[j].bd_info &= ~BDMA_DESC_BLKPAD;
737 		bd[j].bd_info &= ~BDMA_DESC_DWPAD;
738 		bd[j].ptr = lower_32_bits(dma_address);
739 		if (host->dev_comp->support_64g) {
740 			bd[j].bd_info &= ~BDMA_DESC_PTR_H4;
741 			bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf)
742 					 << 28;
743 		}
744 
745 		if (host->dev_comp->support_64g) {
746 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT;
747 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT);
748 		} else {
749 			bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN;
750 			bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN);
751 		}
752 
753 		if (j == data->sg_count - 1) /* the last bd */
754 			bd[j].bd_info |= BDMA_DESC_EOL;
755 		else
756 			bd[j].bd_info &= ~BDMA_DESC_EOL;
757 
758 		/* checksum need to clear first */
759 		bd[j].bd_info &= ~BDMA_DESC_CHECKSUM;
760 		bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8;
761 	}
762 
763 	sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1);
764 	dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL);
765 	dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE);
766 	dma_ctrl |= (MSDC_BURST_64B << 12 | BIT(8));
767 	writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL);
768 	if (host->dev_comp->support_64g)
769 		sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT,
770 			      upper_32_bits(dma->gpd_addr) & 0xf);
771 	writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA);
772 }
773 
774 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data)
775 {
776 	if (!(data->host_cookie & MSDC_PREPARE_FLAG)) {
777 		data->host_cookie |= MSDC_PREPARE_FLAG;
778 		data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len,
779 					    mmc_get_dma_dir(data));
780 	}
781 }
782 
783 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data)
784 {
785 	if (data->host_cookie & MSDC_ASYNC_FLAG)
786 		return;
787 
788 	if (data->host_cookie & MSDC_PREPARE_FLAG) {
789 		dma_unmap_sg(host->dev, data->sg, data->sg_len,
790 			     mmc_get_dma_dir(data));
791 		data->host_cookie &= ~MSDC_PREPARE_FLAG;
792 	}
793 }
794 
795 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks)
796 {
797 	struct mmc_host *mmc = mmc_from_priv(host);
798 	u64 timeout, clk_ns;
799 	u32 mode = 0;
800 
801 	if (mmc->actual_clock == 0) {
802 		timeout = 0;
803 	} else {
804 		clk_ns  = 1000000000ULL;
805 		do_div(clk_ns, mmc->actual_clock);
806 		timeout = ns + clk_ns - 1;
807 		do_div(timeout, clk_ns);
808 		timeout += clks;
809 		/* in 1048576 sclk cycle unit */
810 		timeout = DIV_ROUND_UP(timeout, BIT(20));
811 		if (host->dev_comp->clk_div_bits == 8)
812 			sdr_get_field(host->base + MSDC_CFG,
813 				      MSDC_CFG_CKMOD, &mode);
814 		else
815 			sdr_get_field(host->base + MSDC_CFG,
816 				      MSDC_CFG_CKMOD_EXTRA, &mode);
817 		/*DDR mode will double the clk cycles for data timeout */
818 		timeout = mode >= 2 ? timeout * 2 : timeout;
819 		timeout = timeout > 1 ? timeout - 1 : 0;
820 	}
821 	return timeout;
822 }
823 
824 /* clock control primitives */
825 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks)
826 {
827 	u64 timeout;
828 
829 	host->timeout_ns = ns;
830 	host->timeout_clks = clks;
831 
832 	timeout = msdc_timeout_cal(host, ns, clks);
833 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC,
834 		      (u32)(timeout > 255 ? 255 : timeout));
835 }
836 
837 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks)
838 {
839 	u64 timeout;
840 
841 	timeout = msdc_timeout_cal(host, ns, clks);
842 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC,
843 		      (u32)(timeout > 8191 ? 8191 : timeout));
844 }
845 
846 static void msdc_gate_clock(struct msdc_host *host)
847 {
848 	clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks);
849 	clk_disable_unprepare(host->crypto_clk);
850 	clk_disable_unprepare(host->src_clk_cg);
851 	clk_disable_unprepare(host->src_clk);
852 	clk_disable_unprepare(host->bus_clk);
853 	clk_disable_unprepare(host->h_clk);
854 }
855 
856 static int msdc_ungate_clock(struct msdc_host *host)
857 {
858 	u32 val;
859 	int ret;
860 
861 	clk_prepare_enable(host->h_clk);
862 	clk_prepare_enable(host->bus_clk);
863 	clk_prepare_enable(host->src_clk);
864 	clk_prepare_enable(host->src_clk_cg);
865 	clk_prepare_enable(host->crypto_clk);
866 	ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks);
867 	if (ret) {
868 		dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n");
869 		return ret;
870 	}
871 
872 	return readl_poll_timeout(host->base + MSDC_CFG, val,
873 				  (val & MSDC_CFG_CKSTB), 1, 20000);
874 }
875 
876 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz)
877 {
878 	struct mmc_host *mmc = mmc_from_priv(host);
879 	u32 mode;
880 	u32 flags;
881 	u32 div;
882 	u32 sclk;
883 	u32 tune_reg = host->dev_comp->pad_tune_reg;
884 	u32 val;
885 
886 	if (!hz) {
887 		dev_dbg(host->dev, "set mclk to 0\n");
888 		host->mclk = 0;
889 		mmc->actual_clock = 0;
890 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
891 		return;
892 	}
893 
894 	flags = readl(host->base + MSDC_INTEN);
895 	sdr_clr_bits(host->base + MSDC_INTEN, flags);
896 	if (host->dev_comp->clk_div_bits == 8)
897 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE);
898 	else
899 		sdr_clr_bits(host->base + MSDC_CFG,
900 			     MSDC_CFG_HS400_CK_MODE_EXTRA);
901 	if (timing == MMC_TIMING_UHS_DDR50 ||
902 	    timing == MMC_TIMING_MMC_DDR52 ||
903 	    timing == MMC_TIMING_MMC_HS400) {
904 		if (timing == MMC_TIMING_MMC_HS400)
905 			mode = 0x3;
906 		else
907 			mode = 0x2; /* ddr mode and use divisor */
908 
909 		if (hz >= (host->src_clk_freq >> 2)) {
910 			div = 0; /* mean div = 1/4 */
911 			sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
912 		} else {
913 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
914 			sclk = (host->src_clk_freq >> 2) / div;
915 			div = (div >> 1);
916 		}
917 
918 		if (timing == MMC_TIMING_MMC_HS400 &&
919 		    hz >= (host->src_clk_freq >> 1)) {
920 			if (host->dev_comp->clk_div_bits == 8)
921 				sdr_set_bits(host->base + MSDC_CFG,
922 					     MSDC_CFG_HS400_CK_MODE);
923 			else
924 				sdr_set_bits(host->base + MSDC_CFG,
925 					     MSDC_CFG_HS400_CK_MODE_EXTRA);
926 			sclk = host->src_clk_freq >> 1;
927 			div = 0; /* div is ignore when bit18 is set */
928 		}
929 	} else if (hz >= host->src_clk_freq) {
930 		mode = 0x1; /* no divisor */
931 		div = 0;
932 		sclk = host->src_clk_freq;
933 	} else {
934 		mode = 0x0; /* use divisor */
935 		if (hz >= (host->src_clk_freq >> 1)) {
936 			div = 0; /* mean div = 1/2 */
937 			sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */
938 		} else {
939 			div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2);
940 			sclk = (host->src_clk_freq >> 2) / div;
941 		}
942 	}
943 	sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
944 
945 	clk_disable_unprepare(host->src_clk_cg);
946 	if (host->dev_comp->clk_div_bits == 8)
947 		sdr_set_field(host->base + MSDC_CFG,
948 			      MSDC_CFG_CKMOD | MSDC_CFG_CKDIV,
949 			      (mode << 8) | div);
950 	else
951 		sdr_set_field(host->base + MSDC_CFG,
952 			      MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA,
953 			      (mode << 12) | div);
954 
955 	clk_prepare_enable(host->src_clk_cg);
956 	readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0);
957 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN);
958 	mmc->actual_clock = sclk;
959 	host->mclk = hz;
960 	host->timing = timing;
961 	/* need because clk changed. */
962 	msdc_set_timeout(host, host->timeout_ns, host->timeout_clks);
963 	sdr_set_bits(host->base + MSDC_INTEN, flags);
964 
965 	/*
966 	 * mmc_select_hs400() will drop to 50Mhz and High speed mode,
967 	 * tune result of hs200/200Mhz is not suitable for 50Mhz
968 	 */
969 	if (mmc->actual_clock <= 52000000) {
970 		writel(host->def_tune_para.iocon, host->base + MSDC_IOCON);
971 		if (host->top_base) {
972 			writel(host->def_tune_para.emmc_top_control,
973 			       host->top_base + EMMC_TOP_CONTROL);
974 			writel(host->def_tune_para.emmc_top_cmd,
975 			       host->top_base + EMMC_TOP_CMD);
976 		} else {
977 			writel(host->def_tune_para.pad_tune,
978 			       host->base + tune_reg);
979 		}
980 	} else {
981 		writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON);
982 		writel(host->saved_tune_para.pad_cmd_tune,
983 		       host->base + PAD_CMD_TUNE);
984 		if (host->top_base) {
985 			writel(host->saved_tune_para.emmc_top_control,
986 			       host->top_base + EMMC_TOP_CONTROL);
987 			writel(host->saved_tune_para.emmc_top_cmd,
988 			       host->top_base + EMMC_TOP_CMD);
989 		} else {
990 			writel(host->saved_tune_para.pad_tune,
991 			       host->base + tune_reg);
992 		}
993 	}
994 
995 	if (timing == MMC_TIMING_MMC_HS400 &&
996 	    host->dev_comp->hs400_tune)
997 		sdr_set_field(host->base + tune_reg,
998 			      MSDC_PAD_TUNE_CMDRRDLY,
999 			      host->hs400_cmd_int_delay);
1000 	dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock,
1001 		timing);
1002 }
1003 
1004 static inline u32 msdc_cmd_find_resp(struct msdc_host *host,
1005 		struct mmc_command *cmd)
1006 {
1007 	u32 resp;
1008 
1009 	switch (mmc_resp_type(cmd)) {
1010 		/* Actually, R1, R5, R6, R7 are the same */
1011 	case MMC_RSP_R1:
1012 		resp = 0x1;
1013 		break;
1014 	case MMC_RSP_R1B:
1015 		resp = 0x7;
1016 		break;
1017 	case MMC_RSP_R2:
1018 		resp = 0x2;
1019 		break;
1020 	case MMC_RSP_R3:
1021 		resp = 0x3;
1022 		break;
1023 	case MMC_RSP_NONE:
1024 	default:
1025 		resp = 0x0;
1026 		break;
1027 	}
1028 
1029 	return resp;
1030 }
1031 
1032 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host,
1033 		struct mmc_request *mrq, struct mmc_command *cmd)
1034 {
1035 	struct mmc_host *mmc = mmc_from_priv(host);
1036 	/* rawcmd :
1037 	 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 |
1038 	 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode
1039 	 */
1040 	u32 opcode = cmd->opcode;
1041 	u32 resp = msdc_cmd_find_resp(host, cmd);
1042 	u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7);
1043 
1044 	host->cmd_rsp = resp;
1045 
1046 	if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) ||
1047 	    opcode == MMC_STOP_TRANSMISSION)
1048 		rawcmd |= BIT(14);
1049 	else if (opcode == SD_SWITCH_VOLTAGE)
1050 		rawcmd |= BIT(30);
1051 	else if (opcode == SD_APP_SEND_SCR ||
1052 		 opcode == SD_APP_SEND_NUM_WR_BLKS ||
1053 		 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1054 		 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) ||
1055 		 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC))
1056 		rawcmd |= BIT(11);
1057 
1058 	if (cmd->data) {
1059 		struct mmc_data *data = cmd->data;
1060 
1061 		if (mmc_op_multi(opcode)) {
1062 			if (mmc_card_mmc(mmc->card) && mrq->sbc &&
1063 			    !(mrq->sbc->arg & 0xFFFF0000))
1064 				rawcmd |= BIT(29); /* AutoCMD23 */
1065 		}
1066 
1067 		rawcmd |= ((data->blksz & 0xFFF) << 16);
1068 		if (data->flags & MMC_DATA_WRITE)
1069 			rawcmd |= BIT(13);
1070 		if (data->blocks > 1)
1071 			rawcmd |= BIT(12);
1072 		else
1073 			rawcmd |= BIT(11);
1074 		/* Always use dma mode */
1075 		sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO);
1076 
1077 		if (host->timeout_ns != data->timeout_ns ||
1078 		    host->timeout_clks != data->timeout_clks)
1079 			msdc_set_timeout(host, data->timeout_ns,
1080 					data->timeout_clks);
1081 
1082 		writel(data->blocks, host->base + SDC_BLK_NUM);
1083 	}
1084 	return rawcmd;
1085 }
1086 
1087 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd,
1088 		struct mmc_data *data)
1089 {
1090 	bool read;
1091 
1092 	WARN_ON(host->data);
1093 	host->data = data;
1094 	read = data->flags & MMC_DATA_READ;
1095 
1096 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1097 	msdc_dma_setup(host, &host->dma, data);
1098 	sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask);
1099 	sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1);
1100 	dev_dbg(host->dev, "DMA start\n");
1101 	dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n",
1102 			__func__, cmd->opcode, data->blocks, read);
1103 }
1104 
1105 static int msdc_auto_cmd_done(struct msdc_host *host, int events,
1106 		struct mmc_command *cmd)
1107 {
1108 	u32 *rsp = cmd->resp;
1109 
1110 	rsp[0] = readl(host->base + SDC_ACMD_RESP);
1111 
1112 	if (events & MSDC_INT_ACMDRDY) {
1113 		cmd->error = 0;
1114 	} else {
1115 		msdc_reset_hw(host);
1116 		if (events & MSDC_INT_ACMDCRCERR) {
1117 			cmd->error = -EILSEQ;
1118 			host->error |= REQ_STOP_EIO;
1119 		} else if (events & MSDC_INT_ACMDTMO) {
1120 			cmd->error = -ETIMEDOUT;
1121 			host->error |= REQ_STOP_TMO;
1122 		}
1123 		dev_err(host->dev,
1124 			"%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n",
1125 			__func__, cmd->opcode, cmd->arg, rsp[0], cmd->error);
1126 	}
1127 	return cmd->error;
1128 }
1129 
1130 /*
1131  * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1132  *
1133  * Host controller may lost interrupt in some special case.
1134  * Add SDIO irq recheck mechanism to make sure all interrupts
1135  * can be processed immediately
1136  */
1137 static void msdc_recheck_sdio_irq(struct msdc_host *host)
1138 {
1139 	struct mmc_host *mmc = mmc_from_priv(host);
1140 	u32 reg_int, reg_inten, reg_ps;
1141 
1142 	if (mmc->caps & MMC_CAP_SDIO_IRQ) {
1143 		reg_inten = readl(host->base + MSDC_INTEN);
1144 		if (reg_inten & MSDC_INTEN_SDIOIRQ) {
1145 			reg_int = readl(host->base + MSDC_INT);
1146 			reg_ps = readl(host->base + MSDC_PS);
1147 			if (!(reg_int & MSDC_INT_SDIOIRQ ||
1148 			      reg_ps & MSDC_PS_DATA1)) {
1149 				__msdc_enable_sdio_irq(host, 0);
1150 				sdio_signal_irq(mmc);
1151 			}
1152 		}
1153 	}
1154 }
1155 
1156 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd)
1157 {
1158 	if (host->error &&
1159 	    ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) ||
1160 	     cmd->error == -ETIMEDOUT))
1161 		dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n",
1162 			 __func__, cmd->opcode, cmd->arg, host->error);
1163 }
1164 
1165 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq)
1166 {
1167 	unsigned long flags;
1168 
1169 	/*
1170 	 * No need check the return value of cancel_delayed_work, as only ONE
1171 	 * path will go here!
1172 	 */
1173 	cancel_delayed_work(&host->req_timeout);
1174 
1175 	spin_lock_irqsave(&host->lock, flags);
1176 	host->mrq = NULL;
1177 	spin_unlock_irqrestore(&host->lock, flags);
1178 
1179 	msdc_track_cmd_data(host, mrq->cmd);
1180 	if (mrq->data)
1181 		msdc_unprepare_data(host, mrq->data);
1182 	if (host->error)
1183 		msdc_reset_hw(host);
1184 	mmc_request_done(mmc_from_priv(host), mrq);
1185 	if (host->dev_comp->recheck_sdio_irq)
1186 		msdc_recheck_sdio_irq(host);
1187 }
1188 
1189 /* returns true if command is fully handled; returns false otherwise */
1190 static bool msdc_cmd_done(struct msdc_host *host, int events,
1191 			  struct mmc_request *mrq, struct mmc_command *cmd)
1192 {
1193 	bool done = false;
1194 	bool sbc_error;
1195 	unsigned long flags;
1196 	u32 *rsp;
1197 
1198 	if (mrq->sbc && cmd == mrq->cmd &&
1199 	    (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR
1200 				   | MSDC_INT_ACMDTMO)))
1201 		msdc_auto_cmd_done(host, events, mrq->sbc);
1202 
1203 	sbc_error = mrq->sbc && mrq->sbc->error;
1204 
1205 	if (!sbc_error && !(events & (MSDC_INT_CMDRDY
1206 					| MSDC_INT_RSPCRCERR
1207 					| MSDC_INT_CMDTMO)))
1208 		return done;
1209 
1210 	spin_lock_irqsave(&host->lock, flags);
1211 	done = !host->cmd;
1212 	host->cmd = NULL;
1213 	spin_unlock_irqrestore(&host->lock, flags);
1214 
1215 	if (done)
1216 		return true;
1217 	rsp = cmd->resp;
1218 
1219 	sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1220 
1221 	if (cmd->flags & MMC_RSP_PRESENT) {
1222 		if (cmd->flags & MMC_RSP_136) {
1223 			rsp[0] = readl(host->base + SDC_RESP3);
1224 			rsp[1] = readl(host->base + SDC_RESP2);
1225 			rsp[2] = readl(host->base + SDC_RESP1);
1226 			rsp[3] = readl(host->base + SDC_RESP0);
1227 		} else {
1228 			rsp[0] = readl(host->base + SDC_RESP0);
1229 		}
1230 	}
1231 
1232 	if (!sbc_error && !(events & MSDC_INT_CMDRDY)) {
1233 		if ((events & MSDC_INT_CMDTMO && !host->hs400_tuning) ||
1234 		    (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning))
1235 			/*
1236 			 * should not clear fifo/interrupt as the tune data
1237 			 * may have already come when cmd19/cmd21 gets response
1238 			 * CRC error.
1239 			 */
1240 			msdc_reset_hw(host);
1241 		if (events & MSDC_INT_RSPCRCERR) {
1242 			cmd->error = -EILSEQ;
1243 			host->error |= REQ_CMD_EIO;
1244 		} else if (events & MSDC_INT_CMDTMO) {
1245 			cmd->error = -ETIMEDOUT;
1246 			host->error |= REQ_CMD_TMO;
1247 		}
1248 	}
1249 	if (cmd->error)
1250 		dev_dbg(host->dev,
1251 				"%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n",
1252 				__func__, cmd->opcode, cmd->arg, rsp[0],
1253 				cmd->error);
1254 
1255 	msdc_cmd_next(host, mrq, cmd);
1256 	return true;
1257 }
1258 
1259 /* It is the core layer's responsibility to ensure card status
1260  * is correct before issue a request. but host design do below
1261  * checks recommended.
1262  */
1263 static inline bool msdc_cmd_is_ready(struct msdc_host *host,
1264 		struct mmc_request *mrq, struct mmc_command *cmd)
1265 {
1266 	u32 val;
1267 	int ret;
1268 
1269 	/* The max busy time we can endure is 20ms */
1270 	ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1271 					!(val & SDC_STS_CMDBUSY), 1, 20000);
1272 	if (ret) {
1273 		dev_err(host->dev, "CMD bus busy detected\n");
1274 		host->error |= REQ_CMD_BUSY;
1275 		msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1276 		return false;
1277 	}
1278 
1279 	if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) {
1280 		/* R1B or with data, should check SDCBUSY */
1281 		ret = readl_poll_timeout_atomic(host->base + SDC_STS, val,
1282 						!(val & SDC_STS_SDCBUSY), 1, 20000);
1283 		if (ret) {
1284 			dev_err(host->dev, "Controller busy detected\n");
1285 			host->error |= REQ_CMD_BUSY;
1286 			msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd);
1287 			return false;
1288 		}
1289 	}
1290 	return true;
1291 }
1292 
1293 static void msdc_start_command(struct msdc_host *host,
1294 		struct mmc_request *mrq, struct mmc_command *cmd)
1295 {
1296 	u32 rawcmd;
1297 	unsigned long flags;
1298 
1299 	WARN_ON(host->cmd);
1300 	host->cmd = cmd;
1301 
1302 	mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT);
1303 	if (!msdc_cmd_is_ready(host, mrq, cmd))
1304 		return;
1305 
1306 	if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 ||
1307 	    readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) {
1308 		dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n");
1309 		msdc_reset_hw(host);
1310 	}
1311 
1312 	cmd->error = 0;
1313 	rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd);
1314 
1315 	spin_lock_irqsave(&host->lock, flags);
1316 	sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask);
1317 	spin_unlock_irqrestore(&host->lock, flags);
1318 
1319 	writel(cmd->arg, host->base + SDC_ARG);
1320 	writel(rawcmd, host->base + SDC_CMD);
1321 }
1322 
1323 static void msdc_cmd_next(struct msdc_host *host,
1324 		struct mmc_request *mrq, struct mmc_command *cmd)
1325 {
1326 	if ((cmd->error && !host->hs400_tuning &&
1327 	     !(cmd->error == -EILSEQ &&
1328 	     mmc_op_tuning(cmd->opcode))) ||
1329 	    (mrq->sbc && mrq->sbc->error))
1330 		msdc_request_done(host, mrq);
1331 	else if (cmd == mrq->sbc)
1332 		msdc_start_command(host, mrq, mrq->cmd);
1333 	else if (!cmd->data)
1334 		msdc_request_done(host, mrq);
1335 	else
1336 		msdc_start_data(host, cmd, cmd->data);
1337 }
1338 
1339 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq)
1340 {
1341 	struct msdc_host *host = mmc_priv(mmc);
1342 
1343 	host->error = 0;
1344 	WARN_ON(host->mrq);
1345 	host->mrq = mrq;
1346 
1347 	if (mrq->data)
1348 		msdc_prepare_data(host, mrq->data);
1349 
1350 	/* if SBC is required, we have HW option and SW option.
1351 	 * if HW option is enabled, and SBC does not have "special" flags,
1352 	 * use HW option,  otherwise use SW option
1353 	 */
1354 	if (mrq->sbc && (!mmc_card_mmc(mmc->card) ||
1355 	    (mrq->sbc->arg & 0xFFFF0000)))
1356 		msdc_start_command(host, mrq, mrq->sbc);
1357 	else
1358 		msdc_start_command(host, mrq, mrq->cmd);
1359 }
1360 
1361 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
1362 {
1363 	struct msdc_host *host = mmc_priv(mmc);
1364 	struct mmc_data *data = mrq->data;
1365 
1366 	if (!data)
1367 		return;
1368 
1369 	msdc_prepare_data(host, data);
1370 	data->host_cookie |= MSDC_ASYNC_FLAG;
1371 }
1372 
1373 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
1374 		int err)
1375 {
1376 	struct msdc_host *host = mmc_priv(mmc);
1377 	struct mmc_data *data = mrq->data;
1378 
1379 	if (!data)
1380 		return;
1381 
1382 	if (data->host_cookie) {
1383 		data->host_cookie &= ~MSDC_ASYNC_FLAG;
1384 		msdc_unprepare_data(host, data);
1385 	}
1386 }
1387 
1388 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq)
1389 {
1390 	if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error &&
1391 	    !mrq->sbc)
1392 		msdc_start_command(host, mrq, mrq->stop);
1393 	else
1394 		msdc_request_done(host, mrq);
1395 }
1396 
1397 static void msdc_data_xfer_done(struct msdc_host *host, u32 events,
1398 				struct mmc_request *mrq, struct mmc_data *data)
1399 {
1400 	struct mmc_command *stop;
1401 	unsigned long flags;
1402 	bool done;
1403 	unsigned int check_data = events &
1404 	    (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO
1405 	     | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR
1406 	     | MSDC_INT_DMA_PROTECT);
1407 	u32 val;
1408 	int ret;
1409 
1410 	spin_lock_irqsave(&host->lock, flags);
1411 	done = !host->data;
1412 	if (check_data)
1413 		host->data = NULL;
1414 	spin_unlock_irqrestore(&host->lock, flags);
1415 
1416 	if (done)
1417 		return;
1418 	stop = data->stop;
1419 
1420 	if (check_data || (stop && stop->error)) {
1421 		dev_dbg(host->dev, "DMA status: 0x%8X\n",
1422 				readl(host->base + MSDC_DMA_CFG));
1423 		sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP,
1424 				1);
1425 
1426 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val,
1427 						!(val & MSDC_DMA_CTRL_STOP), 1, 20000);
1428 		if (ret)
1429 			dev_dbg(host->dev, "DMA stop timed out\n");
1430 
1431 		ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val,
1432 						!(val & MSDC_DMA_CFG_STS), 1, 20000);
1433 		if (ret)
1434 			dev_dbg(host->dev, "DMA inactive timed out\n");
1435 
1436 		sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask);
1437 		dev_dbg(host->dev, "DMA stop\n");
1438 
1439 		if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) {
1440 			data->bytes_xfered = data->blocks * data->blksz;
1441 		} else {
1442 			dev_dbg(host->dev, "interrupt events: %x\n", events);
1443 			msdc_reset_hw(host);
1444 			host->error |= REQ_DAT_ERR;
1445 			data->bytes_xfered = 0;
1446 
1447 			if (events & MSDC_INT_DATTMO)
1448 				data->error = -ETIMEDOUT;
1449 			else if (events & MSDC_INT_DATCRCERR)
1450 				data->error = -EILSEQ;
1451 
1452 			dev_dbg(host->dev, "%s: cmd=%d; blocks=%d",
1453 				__func__, mrq->cmd->opcode, data->blocks);
1454 			dev_dbg(host->dev, "data_error=%d xfer_size=%d\n",
1455 				(int)data->error, data->bytes_xfered);
1456 		}
1457 
1458 		msdc_data_xfer_next(host, mrq);
1459 	}
1460 }
1461 
1462 static void msdc_set_buswidth(struct msdc_host *host, u32 width)
1463 {
1464 	u32 val = readl(host->base + SDC_CFG);
1465 
1466 	val &= ~SDC_CFG_BUSWIDTH;
1467 
1468 	switch (width) {
1469 	default:
1470 	case MMC_BUS_WIDTH_1:
1471 		val |= (MSDC_BUS_1BITS << 16);
1472 		break;
1473 	case MMC_BUS_WIDTH_4:
1474 		val |= (MSDC_BUS_4BITS << 16);
1475 		break;
1476 	case MMC_BUS_WIDTH_8:
1477 		val |= (MSDC_BUS_8BITS << 16);
1478 		break;
1479 	}
1480 
1481 	writel(val, host->base + SDC_CFG);
1482 	dev_dbg(host->dev, "Bus Width = %d", width);
1483 }
1484 
1485 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios)
1486 {
1487 	struct msdc_host *host = mmc_priv(mmc);
1488 	int ret;
1489 
1490 	if (!IS_ERR(mmc->supply.vqmmc)) {
1491 		if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 &&
1492 		    ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) {
1493 			dev_err(host->dev, "Unsupported signal voltage!\n");
1494 			return -EINVAL;
1495 		}
1496 
1497 		ret = mmc_regulator_set_vqmmc(mmc, ios);
1498 		if (ret < 0) {
1499 			dev_dbg(host->dev, "Regulator set error %d (%d)\n",
1500 				ret, ios->signal_voltage);
1501 			return ret;
1502 		}
1503 
1504 		/* Apply different pinctrl settings for different signal voltage */
1505 		if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)
1506 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1507 		else
1508 			pinctrl_select_state(host->pinctrl, host->pins_default);
1509 	}
1510 	return 0;
1511 }
1512 
1513 static int msdc_card_busy(struct mmc_host *mmc)
1514 {
1515 	struct msdc_host *host = mmc_priv(mmc);
1516 	u32 status = readl(host->base + MSDC_PS);
1517 
1518 	/* only check if data0 is low */
1519 	return !(status & BIT(16));
1520 }
1521 
1522 static void msdc_request_timeout(struct work_struct *work)
1523 {
1524 	struct msdc_host *host = container_of(work, struct msdc_host,
1525 			req_timeout.work);
1526 
1527 	/* simulate HW timeout status */
1528 	dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__);
1529 	if (host->mrq) {
1530 		dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__,
1531 				host->mrq, host->mrq->cmd->opcode);
1532 		if (host->cmd) {
1533 			dev_err(host->dev, "%s: aborting cmd=%d\n",
1534 					__func__, host->cmd->opcode);
1535 			msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq,
1536 					host->cmd);
1537 		} else if (host->data) {
1538 			dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n",
1539 					__func__, host->mrq->cmd->opcode,
1540 					host->data->blocks);
1541 			msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq,
1542 					host->data);
1543 		}
1544 	}
1545 }
1546 
1547 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb)
1548 {
1549 	if (enb) {
1550 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1551 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1552 		if (host->dev_comp->recheck_sdio_irq)
1553 			msdc_recheck_sdio_irq(host);
1554 	} else {
1555 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1556 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1557 	}
1558 }
1559 
1560 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb)
1561 {
1562 	struct msdc_host *host = mmc_priv(mmc);
1563 	unsigned long flags;
1564 	int ret;
1565 
1566 	spin_lock_irqsave(&host->lock, flags);
1567 	__msdc_enable_sdio_irq(host, enb);
1568 	spin_unlock_irqrestore(&host->lock, flags);
1569 
1570 	if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) {
1571 		if (enb) {
1572 			/*
1573 			 * In dev_pm_set_dedicated_wake_irq_reverse(), eint pin will be set to
1574 			 * GPIO mode. We need to restore it to SDIO DAT1 mode after that.
1575 			 * Since the current pinstate is pins_uhs, to ensure pinctrl select take
1576 			 * affect successfully, we change the pinstate to pins_eint firstly.
1577 			 */
1578 			pinctrl_select_state(host->pinctrl, host->pins_eint);
1579 			ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq);
1580 
1581 			if (ret) {
1582 				dev_err(host->dev, "Failed to register SDIO wakeup irq!\n");
1583 				host->pins_eint = NULL;
1584 				pm_runtime_get_noresume(host->dev);
1585 			} else {
1586 				dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq);
1587 			}
1588 
1589 			pinctrl_select_state(host->pinctrl, host->pins_uhs);
1590 		} else {
1591 			dev_pm_clear_wake_irq(host->dev);
1592 		}
1593 	} else {
1594 		if (enb) {
1595 			/* Ensure host->pins_eint is NULL */
1596 			host->pins_eint = NULL;
1597 			pm_runtime_get_noresume(host->dev);
1598 		} else {
1599 			pm_runtime_put_noidle(host->dev);
1600 		}
1601 	}
1602 }
1603 
1604 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts)
1605 {
1606 	struct mmc_host *mmc = mmc_from_priv(host);
1607 	int cmd_err = 0, dat_err = 0;
1608 
1609 	if (intsts & MSDC_INT_RSPCRCERR) {
1610 		cmd_err = -EILSEQ;
1611 		dev_err(host->dev, "%s: CMD CRC ERR", __func__);
1612 	} else if (intsts & MSDC_INT_CMDTMO) {
1613 		cmd_err = -ETIMEDOUT;
1614 		dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__);
1615 	}
1616 
1617 	if (intsts & MSDC_INT_DATCRCERR) {
1618 		dat_err = -EILSEQ;
1619 		dev_err(host->dev, "%s: DATA CRC ERR", __func__);
1620 	} else if (intsts & MSDC_INT_DATTMO) {
1621 		dat_err = -ETIMEDOUT;
1622 		dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__);
1623 	}
1624 
1625 	if (cmd_err || dat_err) {
1626 		dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x",
1627 			cmd_err, dat_err, intsts);
1628 	}
1629 
1630 	return cqhci_irq(mmc, 0, cmd_err, dat_err);
1631 }
1632 
1633 static irqreturn_t msdc_irq(int irq, void *dev_id)
1634 {
1635 	struct msdc_host *host = (struct msdc_host *) dev_id;
1636 	struct mmc_host *mmc = mmc_from_priv(host);
1637 
1638 	while (true) {
1639 		struct mmc_request *mrq;
1640 		struct mmc_command *cmd;
1641 		struct mmc_data *data;
1642 		u32 events, event_mask;
1643 
1644 		spin_lock(&host->lock);
1645 		events = readl(host->base + MSDC_INT);
1646 		event_mask = readl(host->base + MSDC_INTEN);
1647 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1648 			__msdc_enable_sdio_irq(host, 0);
1649 		/* clear interrupts */
1650 		writel(events & event_mask, host->base + MSDC_INT);
1651 
1652 		mrq = host->mrq;
1653 		cmd = host->cmd;
1654 		data = host->data;
1655 		spin_unlock(&host->lock);
1656 
1657 		if ((events & event_mask) & MSDC_INT_SDIOIRQ)
1658 			sdio_signal_irq(mmc);
1659 
1660 		if ((events & event_mask) & MSDC_INT_CDSC) {
1661 			if (host->internal_cd)
1662 				mmc_detect_change(mmc, msecs_to_jiffies(20));
1663 			events &= ~MSDC_INT_CDSC;
1664 		}
1665 
1666 		if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ)))
1667 			break;
1668 
1669 		if ((mmc->caps2 & MMC_CAP2_CQE) &&
1670 		    (events & MSDC_INT_CMDQ)) {
1671 			msdc_cmdq_irq(host, events);
1672 			/* clear interrupts */
1673 			writel(events, host->base + MSDC_INT);
1674 			return IRQ_HANDLED;
1675 		}
1676 
1677 		if (!mrq) {
1678 			dev_err(host->dev,
1679 				"%s: MRQ=NULL; events=%08X; event_mask=%08X\n",
1680 				__func__, events, event_mask);
1681 			WARN_ON(1);
1682 			break;
1683 		}
1684 
1685 		dev_dbg(host->dev, "%s: events=%08X\n", __func__, events);
1686 
1687 		if (cmd)
1688 			msdc_cmd_done(host, events, mrq, cmd);
1689 		else if (data)
1690 			msdc_data_xfer_done(host, events, mrq, data);
1691 	}
1692 
1693 	return IRQ_HANDLED;
1694 }
1695 
1696 static void msdc_init_hw(struct msdc_host *host)
1697 {
1698 	u32 val;
1699 	u32 tune_reg = host->dev_comp->pad_tune_reg;
1700 	struct mmc_host *mmc = mmc_from_priv(host);
1701 
1702 	if (host->reset) {
1703 		reset_control_assert(host->reset);
1704 		usleep_range(10, 50);
1705 		reset_control_deassert(host->reset);
1706 	}
1707 
1708 	/* Configure to MMC/SD mode, clock free running */
1709 	sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN);
1710 
1711 	/* Reset */
1712 	msdc_reset_hw(host);
1713 
1714 	/* Disable and clear all interrupts */
1715 	writel(0, host->base + MSDC_INTEN);
1716 	val = readl(host->base + MSDC_INT);
1717 	writel(val, host->base + MSDC_INT);
1718 
1719 	/* Configure card detection */
1720 	if (host->internal_cd) {
1721 		sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE,
1722 			      DEFAULT_DEBOUNCE);
1723 		sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1724 		sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1725 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1726 	} else {
1727 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1728 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1729 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC);
1730 	}
1731 
1732 	if (host->top_base) {
1733 		writel(0, host->top_base + EMMC_TOP_CONTROL);
1734 		writel(0, host->top_base + EMMC_TOP_CMD);
1735 	} else {
1736 		writel(0, host->base + tune_reg);
1737 	}
1738 	writel(0, host->base + MSDC_IOCON);
1739 	sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0);
1740 	writel(0x403c0046, host->base + MSDC_PATCH_BIT);
1741 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1);
1742 	writel(0xffff4089, host->base + MSDC_PATCH_BIT1);
1743 	sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL);
1744 
1745 	if (host->dev_comp->stop_clk_fix) {
1746 		sdr_set_field(host->base + MSDC_PATCH_BIT1,
1747 			      MSDC_PATCH_BIT1_STOP_DLY, 3);
1748 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1749 			     SDC_FIFO_CFG_WRVALIDSEL);
1750 		sdr_clr_bits(host->base + SDC_FIFO_CFG,
1751 			     SDC_FIFO_CFG_RDVALIDSEL);
1752 	}
1753 
1754 	if (host->dev_comp->busy_check)
1755 		sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7));
1756 
1757 	if (host->dev_comp->async_fifo) {
1758 		sdr_set_field(host->base + MSDC_PATCH_BIT2,
1759 			      MSDC_PB2_RESPWAIT, 3);
1760 		if (host->dev_comp->enhance_rx) {
1761 			if (host->top_base)
1762 				sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1763 					     SDC_RX_ENH_EN);
1764 			else
1765 				sdr_set_bits(host->base + SDC_ADV_CFG0,
1766 					     SDC_RX_ENHANCE_EN);
1767 		} else {
1768 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1769 				      MSDC_PB2_RESPSTSENSEL, 2);
1770 			sdr_set_field(host->base + MSDC_PATCH_BIT2,
1771 				      MSDC_PB2_CRCSTSENSEL, 2);
1772 		}
1773 		/* use async fifo, then no need tune internal delay */
1774 		sdr_clr_bits(host->base + MSDC_PATCH_BIT2,
1775 			     MSDC_PATCH_BIT2_CFGRESP);
1776 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1777 			     MSDC_PATCH_BIT2_CFGCRCSTS);
1778 	}
1779 
1780 	if (host->dev_comp->support_64g)
1781 		sdr_set_bits(host->base + MSDC_PATCH_BIT2,
1782 			     MSDC_PB2_SUPPORT_64G);
1783 	if (host->dev_comp->data_tune) {
1784 		if (host->top_base) {
1785 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1786 				     PAD_DAT_RD_RXDLY_SEL);
1787 			sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL,
1788 				     DATA_K_VALUE_SEL);
1789 			sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1790 				     PAD_CMD_RD_RXDLY_SEL);
1791 			if (host->tuning_step > PAD_DELAY_HALF) {
1792 				sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1793 					     PAD_DAT_RD_RXDLY2_SEL);
1794 				sdr_set_bits(host->top_base + EMMC_TOP_CMD,
1795 					     PAD_CMD_RD_RXDLY2_SEL);
1796 			}
1797 		} else {
1798 			sdr_set_bits(host->base + tune_reg,
1799 				     MSDC_PAD_TUNE_RD_SEL |
1800 				     MSDC_PAD_TUNE_CMD_SEL);
1801 			if (host->tuning_step > PAD_DELAY_HALF)
1802 				sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
1803 					     MSDC_PAD_TUNE_RD2_SEL |
1804 					     MSDC_PAD_TUNE_CMD2_SEL);
1805 		}
1806 	} else {
1807 		/* choose clock tune */
1808 		if (host->top_base)
1809 			sdr_set_bits(host->top_base + EMMC_TOP_CONTROL,
1810 				     PAD_RXDLY_SEL);
1811 		else
1812 			sdr_set_bits(host->base + tune_reg,
1813 				     MSDC_PAD_TUNE_RXDLYSEL);
1814 	}
1815 
1816 	if (mmc->caps2 & MMC_CAP2_NO_SDIO) {
1817 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1818 		sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ);
1819 		sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1820 	} else {
1821 		/* Configure to enable SDIO mode, otherwise SDIO CMD5 fails */
1822 		sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO);
1823 
1824 		/* Config SDIO device detect interrupt function */
1825 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE);
1826 		sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER);
1827 	}
1828 
1829 	/* Configure to default data timeout */
1830 	sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3);
1831 
1832 	host->def_tune_para.iocon = readl(host->base + MSDC_IOCON);
1833 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
1834 	if (host->top_base) {
1835 		host->def_tune_para.emmc_top_control =
1836 			readl(host->top_base + EMMC_TOP_CONTROL);
1837 		host->def_tune_para.emmc_top_cmd =
1838 			readl(host->top_base + EMMC_TOP_CMD);
1839 		host->saved_tune_para.emmc_top_control =
1840 			readl(host->top_base + EMMC_TOP_CONTROL);
1841 		host->saved_tune_para.emmc_top_cmd =
1842 			readl(host->top_base + EMMC_TOP_CMD);
1843 	} else {
1844 		host->def_tune_para.pad_tune = readl(host->base + tune_reg);
1845 		host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
1846 	}
1847 	dev_dbg(host->dev, "init hardware done!");
1848 }
1849 
1850 static void msdc_deinit_hw(struct msdc_host *host)
1851 {
1852 	u32 val;
1853 
1854 	if (host->internal_cd) {
1855 		/* Disabled card-detect */
1856 		sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN);
1857 		sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP);
1858 	}
1859 
1860 	/* Disable and clear all interrupts */
1861 	writel(0, host->base + MSDC_INTEN);
1862 
1863 	val = readl(host->base + MSDC_INT);
1864 	writel(val, host->base + MSDC_INT);
1865 }
1866 
1867 /* init gpd and bd list in msdc_drv_probe */
1868 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma)
1869 {
1870 	struct mt_gpdma_desc *gpd = dma->gpd;
1871 	struct mt_bdma_desc *bd = dma->bd;
1872 	dma_addr_t dma_addr;
1873 	int i;
1874 
1875 	memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2);
1876 
1877 	dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc);
1878 	gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */
1879 	/* gpd->next is must set for desc DMA
1880 	 * That's why must alloc 2 gpd structure.
1881 	 */
1882 	gpd->next = lower_32_bits(dma_addr);
1883 	if (host->dev_comp->support_64g)
1884 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1885 
1886 	dma_addr = dma->bd_addr;
1887 	gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */
1888 	if (host->dev_comp->support_64g)
1889 		gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28;
1890 
1891 	memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM);
1892 	for (i = 0; i < (MAX_BD_NUM - 1); i++) {
1893 		dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1);
1894 		bd[i].next = lower_32_bits(dma_addr);
1895 		if (host->dev_comp->support_64g)
1896 			bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24;
1897 	}
1898 }
1899 
1900 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1901 {
1902 	struct msdc_host *host = mmc_priv(mmc);
1903 	int ret;
1904 
1905 	msdc_set_buswidth(host, ios->bus_width);
1906 
1907 	/* Suspend/Resume will do power off/on */
1908 	switch (ios->power_mode) {
1909 	case MMC_POWER_UP:
1910 		if (!IS_ERR(mmc->supply.vmmc)) {
1911 			msdc_init_hw(host);
1912 			ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc,
1913 					ios->vdd);
1914 			if (ret) {
1915 				dev_err(host->dev, "Failed to set vmmc power!\n");
1916 				return;
1917 			}
1918 		}
1919 		break;
1920 	case MMC_POWER_ON:
1921 		if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1922 			ret = regulator_enable(mmc->supply.vqmmc);
1923 			if (ret)
1924 				dev_err(host->dev, "Failed to set vqmmc power!\n");
1925 			else
1926 				host->vqmmc_enabled = true;
1927 		}
1928 		break;
1929 	case MMC_POWER_OFF:
1930 		if (!IS_ERR(mmc->supply.vmmc))
1931 			mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1932 
1933 		if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1934 			regulator_disable(mmc->supply.vqmmc);
1935 			host->vqmmc_enabled = false;
1936 		}
1937 		break;
1938 	default:
1939 		break;
1940 	}
1941 
1942 	if (host->mclk != ios->clock || host->timing != ios->timing)
1943 		msdc_set_mclk(host, ios->timing, ios->clock);
1944 }
1945 
1946 static u64 test_delay_bit(u64 delay, u32 bit)
1947 {
1948 	bit %= PAD_DELAY_FULL;
1949 	return delay & BIT_ULL(bit);
1950 }
1951 
1952 static int get_delay_len(u64 delay, u32 start_bit)
1953 {
1954 	int i;
1955 
1956 	for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) {
1957 		if (test_delay_bit(delay, start_bit + i) == 0)
1958 			return i;
1959 	}
1960 	return PAD_DELAY_FULL - start_bit;
1961 }
1962 
1963 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay)
1964 {
1965 	int start = 0, len = 0;
1966 	int start_final = 0, len_final = 0;
1967 	u8 final_phase = 0xff;
1968 	struct msdc_delay_phase delay_phase = { 0, };
1969 
1970 	if (delay == 0) {
1971 		dev_err(host->dev, "phase error: [map:%016llx]\n", delay);
1972 		delay_phase.final_phase = final_phase;
1973 		return delay_phase;
1974 	}
1975 
1976 	while (start < PAD_DELAY_FULL) {
1977 		len = get_delay_len(delay, start);
1978 		if (len_final < len) {
1979 			start_final = start;
1980 			len_final = len;
1981 		}
1982 		start += len ? len : 1;
1983 		if (!upper_32_bits(delay) && len >= 12 && start_final < 4)
1984 			break;
1985 	}
1986 
1987 	/* The rule is that to find the smallest delay cell */
1988 	if (start_final == 0)
1989 		final_phase = (start_final + len_final / 3) % PAD_DELAY_FULL;
1990 	else
1991 		final_phase = (start_final + len_final / 2) % PAD_DELAY_FULL;
1992 	dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n",
1993 		delay, len_final, final_phase);
1994 
1995 	delay_phase.maxlen = len_final;
1996 	delay_phase.start = start_final;
1997 	delay_phase.final_phase = final_phase;
1998 	return delay_phase;
1999 }
2000 
2001 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value)
2002 {
2003 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2004 
2005 	if (host->top_base) {
2006 		if (value < PAD_DELAY_HALF) {
2007 			sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value);
2008 			sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0);
2009 		} else {
2010 			sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY,
2011 				      PAD_DELAY_HALF - 1);
2012 			sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2,
2013 				      value - PAD_DELAY_HALF);
2014 		}
2015 	} else {
2016 		if (value < PAD_DELAY_HALF) {
2017 			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value);
2018 			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2019 				      MSDC_PAD_TUNE_CMDRDLY2, 0);
2020 		} else {
2021 			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY,
2022 				      PAD_DELAY_HALF - 1);
2023 			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2024 				      MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF);
2025 		}
2026 	}
2027 }
2028 
2029 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value)
2030 {
2031 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2032 
2033 	if (host->top_base) {
2034 		if (value < PAD_DELAY_HALF) {
2035 			sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2036 				      PAD_DAT_RD_RXDLY, value);
2037 			sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2038 				      PAD_DAT_RD_RXDLY2, 0);
2039 		} else {
2040 			sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2041 				      PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1);
2042 			sdr_set_field(host->top_base + EMMC_TOP_CONTROL,
2043 				      PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF);
2044 		}
2045 	} else {
2046 		if (value < PAD_DELAY_HALF) {
2047 			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value);
2048 			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2049 				      MSDC_PAD_TUNE_DATRRDLY2, 0);
2050 		} else {
2051 			sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY,
2052 				      PAD_DELAY_HALF - 1);
2053 			sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST,
2054 				      MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF);
2055 		}
2056 	}
2057 }
2058 
2059 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode)
2060 {
2061 	struct msdc_host *host = mmc_priv(mmc);
2062 	u64 rise_delay = 0, fall_delay = 0;
2063 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2064 	struct msdc_delay_phase internal_delay_phase;
2065 	u8 final_delay, final_maxlen;
2066 	u32 internal_delay = 0;
2067 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2068 	int cmd_err;
2069 	int i, j;
2070 
2071 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2072 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2073 		sdr_set_field(host->base + tune_reg,
2074 			      MSDC_PAD_TUNE_CMDRRDLY,
2075 			      host->hs200_cmd_int_delay);
2076 
2077 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2078 	for (i = 0; i < host->tuning_step; i++) {
2079 		msdc_set_cmd_delay(host, i);
2080 		/*
2081 		 * Using the same parameters, it may sometimes pass the test,
2082 		 * but sometimes it may fail. To make sure the parameters are
2083 		 * more stable, we test each set of parameters 3 times.
2084 		 */
2085 		for (j = 0; j < 3; j++) {
2086 			mmc_send_tuning(mmc, opcode, &cmd_err);
2087 			if (!cmd_err) {
2088 				rise_delay |= BIT_ULL(i);
2089 			} else {
2090 				rise_delay &= ~BIT_ULL(i);
2091 				break;
2092 			}
2093 		}
2094 	}
2095 	final_rise_delay = get_best_delay(host, rise_delay);
2096 	/* if rising edge has enough margin, then do not scan falling edge */
2097 	if (final_rise_delay.maxlen >= 12 ||
2098 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2099 		goto skip_fall;
2100 
2101 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2102 	for (i = 0; i < host->tuning_step; i++) {
2103 		msdc_set_cmd_delay(host, i);
2104 		/*
2105 		 * Using the same parameters, it may sometimes pass the test,
2106 		 * but sometimes it may fail. To make sure the parameters are
2107 		 * more stable, we test each set of parameters 3 times.
2108 		 */
2109 		for (j = 0; j < 3; j++) {
2110 			mmc_send_tuning(mmc, opcode, &cmd_err);
2111 			if (!cmd_err) {
2112 				fall_delay |= BIT_ULL(i);
2113 			} else {
2114 				fall_delay &= ~BIT_ULL(i);
2115 				break;
2116 			}
2117 		}
2118 	}
2119 	final_fall_delay = get_best_delay(host, fall_delay);
2120 
2121 skip_fall:
2122 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2123 	if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4)
2124 		final_maxlen = final_fall_delay.maxlen;
2125 	if (final_maxlen == final_rise_delay.maxlen) {
2126 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2127 		final_delay = final_rise_delay.final_phase;
2128 	} else {
2129 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2130 		final_delay = final_fall_delay.final_phase;
2131 	}
2132 	msdc_set_cmd_delay(host, final_delay);
2133 
2134 	if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay)
2135 		goto skip_internal;
2136 
2137 	for (i = 0; i < host->tuning_step; i++) {
2138 		sdr_set_field(host->base + tune_reg,
2139 			      MSDC_PAD_TUNE_CMDRRDLY, i);
2140 		mmc_send_tuning(mmc, opcode, &cmd_err);
2141 		if (!cmd_err)
2142 			internal_delay |= BIT_ULL(i);
2143 	}
2144 	dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay);
2145 	internal_delay_phase = get_best_delay(host, internal_delay);
2146 	sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY,
2147 		      internal_delay_phase.final_phase);
2148 skip_internal:
2149 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2150 	return final_delay == 0xff ? -EIO : 0;
2151 }
2152 
2153 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode)
2154 {
2155 	struct msdc_host *host = mmc_priv(mmc);
2156 	u32 cmd_delay = 0;
2157 	struct msdc_delay_phase final_cmd_delay = { 0,};
2158 	u8 final_delay;
2159 	int cmd_err;
2160 	int i, j;
2161 
2162 	/* select EMMC50 PAD CMD tune */
2163 	sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0));
2164 	sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2);
2165 
2166 	if (mmc->ios.timing == MMC_TIMING_MMC_HS200 ||
2167 	    mmc->ios.timing == MMC_TIMING_UHS_SDR104)
2168 		sdr_set_field(host->base + MSDC_PAD_TUNE,
2169 			      MSDC_PAD_TUNE_CMDRRDLY,
2170 			      host->hs200_cmd_int_delay);
2171 
2172 	if (host->hs400_cmd_resp_sel_rising)
2173 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2174 	else
2175 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2176 
2177 	for (i = 0; i < PAD_DELAY_HALF; i++) {
2178 		sdr_set_field(host->base + PAD_CMD_TUNE,
2179 			      PAD_CMD_TUNE_RX_DLY3, i);
2180 		/*
2181 		 * Using the same parameters, it may sometimes pass the test,
2182 		 * but sometimes it may fail. To make sure the parameters are
2183 		 * more stable, we test each set of parameters 3 times.
2184 		 */
2185 		for (j = 0; j < 3; j++) {
2186 			mmc_send_tuning(mmc, opcode, &cmd_err);
2187 			if (!cmd_err) {
2188 				cmd_delay |= BIT(i);
2189 			} else {
2190 				cmd_delay &= ~BIT(i);
2191 				break;
2192 			}
2193 		}
2194 	}
2195 	final_cmd_delay = get_best_delay(host, cmd_delay);
2196 	sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3,
2197 		      final_cmd_delay.final_phase);
2198 	final_delay = final_cmd_delay.final_phase;
2199 
2200 	dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay);
2201 	return final_delay == 0xff ? -EIO : 0;
2202 }
2203 
2204 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode)
2205 {
2206 	struct msdc_host *host = mmc_priv(mmc);
2207 	u64 rise_delay = 0, fall_delay = 0;
2208 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2209 	u8 final_delay, final_maxlen;
2210 	int i, ret;
2211 
2212 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2213 		      host->latch_ck);
2214 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2215 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2216 	for (i = 0; i < host->tuning_step; i++) {
2217 		msdc_set_data_delay(host, i);
2218 		ret = mmc_send_tuning(mmc, opcode, NULL);
2219 		if (!ret)
2220 			rise_delay |= BIT_ULL(i);
2221 	}
2222 	final_rise_delay = get_best_delay(host, rise_delay);
2223 	/* if rising edge has enough margin, then do not scan falling edge */
2224 	if (final_rise_delay.maxlen >= 12 ||
2225 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2226 		goto skip_fall;
2227 
2228 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2229 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2230 	for (i = 0; i < host->tuning_step; i++) {
2231 		msdc_set_data_delay(host, i);
2232 		ret = mmc_send_tuning(mmc, opcode, NULL);
2233 		if (!ret)
2234 			fall_delay |= BIT_ULL(i);
2235 	}
2236 	final_fall_delay = get_best_delay(host, fall_delay);
2237 
2238 skip_fall:
2239 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2240 	if (final_maxlen == final_rise_delay.maxlen) {
2241 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2242 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2243 		final_delay = final_rise_delay.final_phase;
2244 	} else {
2245 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL);
2246 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL);
2247 		final_delay = final_fall_delay.final_phase;
2248 	}
2249 	msdc_set_data_delay(host, final_delay);
2250 
2251 	dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay);
2252 	return final_delay == 0xff ? -EIO : 0;
2253 }
2254 
2255 /*
2256  * MSDC IP which supports data tune + async fifo can do CMD/DAT tune
2257  * together, which can save the tuning time.
2258  */
2259 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode)
2260 {
2261 	struct msdc_host *host = mmc_priv(mmc);
2262 	u64 rise_delay = 0, fall_delay = 0;
2263 	struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,};
2264 	u8 final_delay, final_maxlen;
2265 	int i, ret;
2266 
2267 	sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL,
2268 		      host->latch_ck);
2269 
2270 	sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2271 	sdr_clr_bits(host->base + MSDC_IOCON,
2272 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2273 	for (i = 0; i < host->tuning_step; i++) {
2274 		msdc_set_cmd_delay(host, i);
2275 		msdc_set_data_delay(host, i);
2276 		ret = mmc_send_tuning(mmc, opcode, NULL);
2277 		if (!ret)
2278 			rise_delay |= BIT_ULL(i);
2279 	}
2280 	final_rise_delay = get_best_delay(host, rise_delay);
2281 	/* if rising edge has enough margin, then do not scan falling edge */
2282 	if (final_rise_delay.maxlen >= 12 ||
2283 	    (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4))
2284 		goto skip_fall;
2285 
2286 	sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2287 	sdr_set_bits(host->base + MSDC_IOCON,
2288 		     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2289 	for (i = 0; i < host->tuning_step; i++) {
2290 		msdc_set_cmd_delay(host, i);
2291 		msdc_set_data_delay(host, i);
2292 		ret = mmc_send_tuning(mmc, opcode, NULL);
2293 		if (!ret)
2294 			fall_delay |= BIT_ULL(i);
2295 	}
2296 	final_fall_delay = get_best_delay(host, fall_delay);
2297 
2298 skip_fall:
2299 	final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen);
2300 	if (final_maxlen == final_rise_delay.maxlen) {
2301 		sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2302 		sdr_clr_bits(host->base + MSDC_IOCON,
2303 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2304 		final_delay = final_rise_delay.final_phase;
2305 	} else {
2306 		sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL);
2307 		sdr_set_bits(host->base + MSDC_IOCON,
2308 			     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2309 		final_delay = final_fall_delay.final_phase;
2310 	}
2311 
2312 	msdc_set_cmd_delay(host, final_delay);
2313 	msdc_set_data_delay(host, final_delay);
2314 
2315 	dev_dbg(host->dev, "Final pad delay: %x\n", final_delay);
2316 	return final_delay == 0xff ? -EIO : 0;
2317 }
2318 
2319 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode)
2320 {
2321 	struct msdc_host *host = mmc_priv(mmc);
2322 	int ret;
2323 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2324 
2325 	if (host->dev_comp->data_tune && host->dev_comp->async_fifo) {
2326 		ret = msdc_tune_together(mmc, opcode);
2327 		if (host->hs400_mode) {
2328 			sdr_clr_bits(host->base + MSDC_IOCON,
2329 				     MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL);
2330 			msdc_set_data_delay(host, 0);
2331 		}
2332 		goto tune_done;
2333 	}
2334 	if (host->hs400_mode &&
2335 	    host->dev_comp->hs400_tune)
2336 		ret = hs400_tune_response(mmc, opcode);
2337 	else
2338 		ret = msdc_tune_response(mmc, opcode);
2339 	if (ret == -EIO) {
2340 		dev_err(host->dev, "Tune response fail!\n");
2341 		return ret;
2342 	}
2343 	if (host->hs400_mode == false) {
2344 		ret = msdc_tune_data(mmc, opcode);
2345 		if (ret == -EIO)
2346 			dev_err(host->dev, "Tune data fail!\n");
2347 	}
2348 
2349 tune_done:
2350 	host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON);
2351 	host->saved_tune_para.pad_tune = readl(host->base + tune_reg);
2352 	host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2353 	if (host->top_base) {
2354 		host->saved_tune_para.emmc_top_control = readl(host->top_base +
2355 				EMMC_TOP_CONTROL);
2356 		host->saved_tune_para.emmc_top_cmd = readl(host->top_base +
2357 				EMMC_TOP_CMD);
2358 	}
2359 	return ret;
2360 }
2361 
2362 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios)
2363 {
2364 	struct msdc_host *host = mmc_priv(mmc);
2365 	host->hs400_mode = true;
2366 
2367 	if (host->top_base)
2368 		writel(host->hs400_ds_delay,
2369 		       host->top_base + EMMC50_PAD_DS_TUNE);
2370 	else
2371 		writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE);
2372 	/* hs400 mode must set it to 0 */
2373 	sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS);
2374 	/* to improve read performance, set outstanding to 2 */
2375 	sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2);
2376 
2377 	return 0;
2378 }
2379 
2380 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card)
2381 {
2382 	struct msdc_host *host = mmc_priv(mmc);
2383 	struct msdc_delay_phase dly1_delay;
2384 	u32 val, result_dly1 = 0;
2385 	u8 *ext_csd;
2386 	int i, ret;
2387 
2388 	if (host->top_base) {
2389 		sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE,
2390 			     PAD_DS_DLY_SEL);
2391 		if (host->hs400_ds_dly3)
2392 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2393 				      PAD_DS_DLY3, host->hs400_ds_dly3);
2394 	} else {
2395 		sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL);
2396 		if (host->hs400_ds_dly3)
2397 			sdr_set_field(host->base + PAD_DS_TUNE,
2398 				      PAD_DS_TUNE_DLY3, host->hs400_ds_dly3);
2399 	}
2400 
2401 	host->hs400_tuning = true;
2402 	for (i = 0; i < PAD_DELAY_HALF; i++) {
2403 		if (host->top_base)
2404 			sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2405 				      PAD_DS_DLY1, i);
2406 		else
2407 			sdr_set_field(host->base + PAD_DS_TUNE,
2408 				      PAD_DS_TUNE_DLY1, i);
2409 		ret = mmc_get_ext_csd(card, &ext_csd);
2410 		if (!ret) {
2411 			result_dly1 |= BIT(i);
2412 			kfree(ext_csd);
2413 		}
2414 	}
2415 	host->hs400_tuning = false;
2416 
2417 	dly1_delay = get_best_delay(host, result_dly1);
2418 	if (dly1_delay.maxlen == 0) {
2419 		dev_err(host->dev, "Failed to get DLY1 delay!\n");
2420 		goto fail;
2421 	}
2422 	if (host->top_base)
2423 		sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE,
2424 			      PAD_DS_DLY1, dly1_delay.final_phase);
2425 	else
2426 		sdr_set_field(host->base + PAD_DS_TUNE,
2427 			      PAD_DS_TUNE_DLY1, dly1_delay.final_phase);
2428 
2429 	if (host->top_base)
2430 		val = readl(host->top_base + EMMC50_PAD_DS_TUNE);
2431 	else
2432 		val = readl(host->base + PAD_DS_TUNE);
2433 
2434 	dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val);
2435 
2436 	return 0;
2437 
2438 fail:
2439 	dev_err(host->dev, "Failed to tuning DS pin delay!\n");
2440 	return -EIO;
2441 }
2442 
2443 static void msdc_hw_reset(struct mmc_host *mmc)
2444 {
2445 	struct msdc_host *host = mmc_priv(mmc);
2446 
2447 	sdr_set_bits(host->base + EMMC_IOCON, 1);
2448 	udelay(10); /* 10us is enough */
2449 	sdr_clr_bits(host->base + EMMC_IOCON, 1);
2450 }
2451 
2452 static void msdc_ack_sdio_irq(struct mmc_host *mmc)
2453 {
2454 	unsigned long flags;
2455 	struct msdc_host *host = mmc_priv(mmc);
2456 
2457 	spin_lock_irqsave(&host->lock, flags);
2458 	__msdc_enable_sdio_irq(host, 1);
2459 	spin_unlock_irqrestore(&host->lock, flags);
2460 }
2461 
2462 static int msdc_get_cd(struct mmc_host *mmc)
2463 {
2464 	struct msdc_host *host = mmc_priv(mmc);
2465 	int val;
2466 
2467 	if (mmc->caps & MMC_CAP_NONREMOVABLE)
2468 		return 1;
2469 
2470 	if (!host->internal_cd)
2471 		return mmc_gpio_get_cd(mmc);
2472 
2473 	val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS;
2474 	if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH)
2475 		return !!val;
2476 	else
2477 		return !val;
2478 }
2479 
2480 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc,
2481 				       struct mmc_ios *ios)
2482 {
2483 	struct msdc_host *host = mmc_priv(mmc);
2484 
2485 	if (ios->enhanced_strobe) {
2486 		msdc_prepare_hs400_tuning(mmc, ios);
2487 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1);
2488 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1);
2489 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1);
2490 
2491 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2492 		sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2493 		sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT);
2494 	} else {
2495 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0);
2496 		sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0);
2497 		sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0);
2498 
2499 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL);
2500 		sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL);
2501 		sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4);
2502 	}
2503 }
2504 
2505 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns)
2506 {
2507 	struct mmc_host *mmc = mmc_from_priv(host);
2508 	struct cqhci_host *cq_host = mmc->cqe_private;
2509 	u8 itcfmul;
2510 	u64 hclk_freq, value;
2511 
2512 	/*
2513 	 * On MediaTek SoCs the MSDC controller's CQE uses msdc_hclk as ITCFVAL
2514 	 * so we multiply/divide the HCLK frequency by ITCFMUL to calculate the
2515 	 * Send Status Command Idle Timer (CIT) value.
2516 	 */
2517 	hclk_freq = (u64)clk_get_rate(host->h_clk);
2518 	itcfmul = CQHCI_ITCFMUL(cqhci_readl(cq_host, CQHCI_CAP));
2519 	switch (itcfmul) {
2520 	case 0x0:
2521 		do_div(hclk_freq, 1000);
2522 		break;
2523 	case 0x1:
2524 		do_div(hclk_freq, 100);
2525 		break;
2526 	case 0x2:
2527 		do_div(hclk_freq, 10);
2528 		break;
2529 	case 0x3:
2530 		break;
2531 	case 0x4:
2532 		hclk_freq = hclk_freq * 10;
2533 		break;
2534 	default:
2535 		host->cq_ssc1_time = 0x40;
2536 		return;
2537 	}
2538 
2539 	value = hclk_freq * timer_ns;
2540 	do_div(value, 1000000000);
2541 	host->cq_ssc1_time = value;
2542 }
2543 
2544 static void msdc_cqe_enable(struct mmc_host *mmc)
2545 {
2546 	struct msdc_host *host = mmc_priv(mmc);
2547 	struct cqhci_host *cq_host = mmc->cqe_private;
2548 
2549 	/* enable cmdq irq */
2550 	writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN);
2551 	/* enable busy check */
2552 	sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2553 	/* default write data / busy timeout 20s */
2554 	msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0);
2555 	/* default read data timeout 1s */
2556 	msdc_set_timeout(host, 1000000000ULL, 0);
2557 
2558 	/* Set the send status command idle timer */
2559 	cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1);
2560 }
2561 
2562 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery)
2563 {
2564 	struct msdc_host *host = mmc_priv(mmc);
2565 	unsigned int val = 0;
2566 
2567 	/* disable cmdq irq */
2568 	sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ);
2569 	/* disable busy check */
2570 	sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL);
2571 
2572 	val = readl(host->base + MSDC_INT);
2573 	writel(val, host->base + MSDC_INT);
2574 
2575 	if (recovery) {
2576 		sdr_set_field(host->base + MSDC_DMA_CTRL,
2577 			      MSDC_DMA_CTRL_STOP, 1);
2578 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val,
2579 			!(val & MSDC_DMA_CTRL_STOP), 1, 3000)))
2580 			return;
2581 		if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val,
2582 			!(val & MSDC_DMA_CFG_STS), 1, 3000)))
2583 			return;
2584 		msdc_reset_hw(host);
2585 	}
2586 }
2587 
2588 static void msdc_cqe_pre_enable(struct mmc_host *mmc)
2589 {
2590 	struct cqhci_host *cq_host = mmc->cqe_private;
2591 	u32 reg;
2592 
2593 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2594 	reg |= CQHCI_ENABLE;
2595 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2596 }
2597 
2598 static void msdc_cqe_post_disable(struct mmc_host *mmc)
2599 {
2600 	struct cqhci_host *cq_host = mmc->cqe_private;
2601 	u32 reg;
2602 
2603 	reg = cqhci_readl(cq_host, CQHCI_CFG);
2604 	reg &= ~CQHCI_ENABLE;
2605 	cqhci_writel(cq_host, reg, CQHCI_CFG);
2606 }
2607 
2608 static const struct mmc_host_ops mt_msdc_ops = {
2609 	.post_req = msdc_post_req,
2610 	.pre_req = msdc_pre_req,
2611 	.request = msdc_ops_request,
2612 	.set_ios = msdc_ops_set_ios,
2613 	.get_ro = mmc_gpio_get_ro,
2614 	.get_cd = msdc_get_cd,
2615 	.hs400_enhanced_strobe = msdc_hs400_enhanced_strobe,
2616 	.enable_sdio_irq = msdc_enable_sdio_irq,
2617 	.ack_sdio_irq = msdc_ack_sdio_irq,
2618 	.start_signal_voltage_switch = msdc_ops_switch_volt,
2619 	.card_busy = msdc_card_busy,
2620 	.execute_tuning = msdc_execute_tuning,
2621 	.prepare_hs400_tuning = msdc_prepare_hs400_tuning,
2622 	.execute_hs400_tuning = msdc_execute_hs400_tuning,
2623 	.card_hw_reset = msdc_hw_reset,
2624 };
2625 
2626 static const struct cqhci_host_ops msdc_cmdq_ops = {
2627 	.enable         = msdc_cqe_enable,
2628 	.disable        = msdc_cqe_disable,
2629 	.pre_enable = msdc_cqe_pre_enable,
2630 	.post_disable = msdc_cqe_post_disable,
2631 };
2632 
2633 static void msdc_of_property_parse(struct platform_device *pdev,
2634 				   struct msdc_host *host)
2635 {
2636 	struct mmc_host *mmc = mmc_from_priv(host);
2637 
2638 	of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck",
2639 			     &host->latch_ck);
2640 
2641 	of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay",
2642 			     &host->hs400_ds_delay);
2643 
2644 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3",
2645 			     &host->hs400_ds_dly3);
2646 
2647 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay",
2648 			     &host->hs200_cmd_int_delay);
2649 
2650 	of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay",
2651 			     &host->hs400_cmd_int_delay);
2652 
2653 	if (of_property_read_bool(pdev->dev.of_node,
2654 				  "mediatek,hs400-cmd-resp-sel-rising"))
2655 		host->hs400_cmd_resp_sel_rising = true;
2656 	else
2657 		host->hs400_cmd_resp_sel_rising = false;
2658 
2659 	if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step",
2660 				 &host->tuning_step)) {
2661 		if (mmc->caps2 & MMC_CAP2_NO_MMC)
2662 			host->tuning_step = PAD_DELAY_FULL;
2663 		else
2664 			host->tuning_step = PAD_DELAY_HALF;
2665 	}
2666 
2667 	if (of_property_read_bool(pdev->dev.of_node,
2668 				  "supports-cqe"))
2669 		host->cqhci = true;
2670 	else
2671 		host->cqhci = false;
2672 }
2673 
2674 static int msdc_of_clock_parse(struct platform_device *pdev,
2675 			       struct msdc_host *host)
2676 {
2677 	int ret;
2678 
2679 	host->src_clk = devm_clk_get(&pdev->dev, "source");
2680 	if (IS_ERR(host->src_clk))
2681 		return PTR_ERR(host->src_clk);
2682 
2683 	host->h_clk = devm_clk_get(&pdev->dev, "hclk");
2684 	if (IS_ERR(host->h_clk))
2685 		return PTR_ERR(host->h_clk);
2686 
2687 	host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk");
2688 	if (IS_ERR(host->bus_clk))
2689 		host->bus_clk = NULL;
2690 
2691 	/*source clock control gate is optional clock*/
2692 	host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg");
2693 	if (IS_ERR(host->src_clk_cg))
2694 		return PTR_ERR(host->src_clk_cg);
2695 
2696 	/*
2697 	 * Fallback for legacy device-trees: src_clk and HCLK use the same
2698 	 * bit to control gating but they are parented to a different mux,
2699 	 * hence if our intention is to gate only the source, required
2700 	 * during a clk mode switch to avoid hw hangs, we need to gate
2701 	 * its parent (specified as a different clock only on new DTs).
2702 	 */
2703 	if (!host->src_clk_cg) {
2704 		host->src_clk_cg = clk_get_parent(host->src_clk);
2705 		if (IS_ERR(host->src_clk_cg))
2706 			return PTR_ERR(host->src_clk_cg);
2707 	}
2708 
2709 	/* If present, always enable for this clock gate */
2710 	host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg");
2711 	if (IS_ERR(host->sys_clk_cg))
2712 		host->sys_clk_cg = NULL;
2713 
2714 	host->bulk_clks[0].id = "pclk_cg";
2715 	host->bulk_clks[1].id = "axi_cg";
2716 	host->bulk_clks[2].id = "ahb_cg";
2717 	ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS,
2718 					 host->bulk_clks);
2719 	if (ret) {
2720 		dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n");
2721 		return ret;
2722 	}
2723 
2724 	return 0;
2725 }
2726 
2727 static int msdc_drv_probe(struct platform_device *pdev)
2728 {
2729 	struct mmc_host *mmc;
2730 	struct msdc_host *host;
2731 	struct resource *res;
2732 	int ret;
2733 
2734 	if (!pdev->dev.of_node) {
2735 		dev_err(&pdev->dev, "No DT found\n");
2736 		return -EINVAL;
2737 	}
2738 
2739 	/* Allocate MMC host for this device */
2740 	mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev);
2741 	if (!mmc)
2742 		return -ENOMEM;
2743 
2744 	host = mmc_priv(mmc);
2745 	ret = mmc_of_parse(mmc);
2746 	if (ret)
2747 		goto host_free;
2748 
2749 	host->base = devm_platform_ioremap_resource(pdev, 0);
2750 	if (IS_ERR(host->base)) {
2751 		ret = PTR_ERR(host->base);
2752 		goto host_free;
2753 	}
2754 
2755 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2756 	if (res) {
2757 		host->top_base = devm_ioremap_resource(&pdev->dev, res);
2758 		if (IS_ERR(host->top_base))
2759 			host->top_base = NULL;
2760 	}
2761 
2762 	ret = mmc_regulator_get_supply(mmc);
2763 	if (ret)
2764 		goto host_free;
2765 
2766 	ret = msdc_of_clock_parse(pdev, host);
2767 	if (ret)
2768 		goto host_free;
2769 
2770 	host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
2771 								"hrst");
2772 	if (IS_ERR(host->reset)) {
2773 		ret = PTR_ERR(host->reset);
2774 		goto host_free;
2775 	}
2776 
2777 	/* only eMMC has crypto property */
2778 	if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) {
2779 		host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto");
2780 		if (IS_ERR(host->crypto_clk))
2781 			host->crypto_clk = NULL;
2782 		else
2783 			mmc->caps2 |= MMC_CAP2_CRYPTO;
2784 	}
2785 
2786 	host->irq = platform_get_irq(pdev, 0);
2787 	if (host->irq < 0) {
2788 		ret = host->irq;
2789 		goto host_free;
2790 	}
2791 
2792 	host->pinctrl = devm_pinctrl_get(&pdev->dev);
2793 	if (IS_ERR(host->pinctrl)) {
2794 		ret = PTR_ERR(host->pinctrl);
2795 		dev_err(&pdev->dev, "Cannot find pinctrl!\n");
2796 		goto host_free;
2797 	}
2798 
2799 	host->pins_default = pinctrl_lookup_state(host->pinctrl, "default");
2800 	if (IS_ERR(host->pins_default)) {
2801 		ret = PTR_ERR(host->pins_default);
2802 		dev_err(&pdev->dev, "Cannot find pinctrl default!\n");
2803 		goto host_free;
2804 	}
2805 
2806 	host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs");
2807 	if (IS_ERR(host->pins_uhs)) {
2808 		ret = PTR_ERR(host->pins_uhs);
2809 		dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n");
2810 		goto host_free;
2811 	}
2812 
2813 	/* Support for SDIO eint irq ? */
2814 	if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) {
2815 		host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup");
2816 		if (host->eint_irq > 0) {
2817 			host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint");
2818 			if (IS_ERR(host->pins_eint)) {
2819 				dev_err(&pdev->dev, "Cannot find pinctrl eint!\n");
2820 				host->pins_eint = NULL;
2821 			} else {
2822 				device_init_wakeup(&pdev->dev, true);
2823 			}
2824 		}
2825 	}
2826 
2827 	msdc_of_property_parse(pdev, host);
2828 
2829 	host->dev = &pdev->dev;
2830 	host->dev_comp = of_device_get_match_data(&pdev->dev);
2831 	host->src_clk_freq = clk_get_rate(host->src_clk);
2832 	/* Set host parameters to mmc */
2833 	mmc->ops = &mt_msdc_ops;
2834 	if (host->dev_comp->clk_div_bits == 8)
2835 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255);
2836 	else
2837 		mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095);
2838 
2839 	if (!(mmc->caps & MMC_CAP_NONREMOVABLE) &&
2840 	    !mmc_can_gpio_cd(mmc) &&
2841 	    host->dev_comp->use_internal_cd) {
2842 		/*
2843 		 * Is removable but no GPIO declared, so
2844 		 * use internal functionality.
2845 		 */
2846 		host->internal_cd = true;
2847 	}
2848 
2849 	if (mmc->caps & MMC_CAP_SDIO_IRQ)
2850 		mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD;
2851 
2852 	mmc->caps |= MMC_CAP_CMD23;
2853 	if (host->cqhci)
2854 		mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD;
2855 	/* MMC core transfer sizes tunable parameters */
2856 	mmc->max_segs = MAX_BD_NUM;
2857 	if (host->dev_comp->support_64g)
2858 		mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT;
2859 	else
2860 		mmc->max_seg_size = BDMA_DESC_BUFLEN;
2861 	mmc->max_blk_size = 2048;
2862 	mmc->max_req_size = 512 * 1024;
2863 	mmc->max_blk_count = mmc->max_req_size / 512;
2864 	if (host->dev_comp->support_64g)
2865 		host->dma_mask = DMA_BIT_MASK(36);
2866 	else
2867 		host->dma_mask = DMA_BIT_MASK(32);
2868 	mmc_dev(mmc)->dma_mask = &host->dma_mask;
2869 
2870 	host->timeout_clks = 3 * 1048576;
2871 	host->dma.gpd = dma_alloc_coherent(&pdev->dev,
2872 				2 * sizeof(struct mt_gpdma_desc),
2873 				&host->dma.gpd_addr, GFP_KERNEL);
2874 	host->dma.bd = dma_alloc_coherent(&pdev->dev,
2875 				MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2876 				&host->dma.bd_addr, GFP_KERNEL);
2877 	if (!host->dma.gpd || !host->dma.bd) {
2878 		ret = -ENOMEM;
2879 		goto release_mem;
2880 	}
2881 	msdc_init_gpd_bd(host, &host->dma);
2882 	INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout);
2883 	spin_lock_init(&host->lock);
2884 
2885 	platform_set_drvdata(pdev, mmc);
2886 	ret = msdc_ungate_clock(host);
2887 	if (ret) {
2888 		dev_err(&pdev->dev, "Cannot ungate clocks!\n");
2889 		goto release_mem;
2890 	}
2891 	msdc_init_hw(host);
2892 
2893 	if (mmc->caps2 & MMC_CAP2_CQE) {
2894 		host->cq_host = devm_kzalloc(mmc->parent,
2895 					     sizeof(*host->cq_host),
2896 					     GFP_KERNEL);
2897 		if (!host->cq_host) {
2898 			ret = -ENOMEM;
2899 			goto host_free;
2900 		}
2901 		host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128;
2902 		host->cq_host->mmio = host->base + 0x800;
2903 		host->cq_host->ops = &msdc_cmdq_ops;
2904 		ret = cqhci_init(host->cq_host, mmc, true);
2905 		if (ret)
2906 			goto host_free;
2907 		mmc->max_segs = 128;
2908 		/* cqhci 16bit length */
2909 		/* 0 size, means 65536 so we don't have to -1 here */
2910 		mmc->max_seg_size = 64 * 1024;
2911 		/* Reduce CIT to 0x40 that corresponds to 2.35us */
2912 		msdc_cqe_cit_cal(host, 2350);
2913 	}
2914 
2915 	ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq,
2916 			       IRQF_TRIGGER_NONE, pdev->name, host);
2917 	if (ret)
2918 		goto release;
2919 
2920 	pm_runtime_set_active(host->dev);
2921 	pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY);
2922 	pm_runtime_use_autosuspend(host->dev);
2923 	pm_runtime_enable(host->dev);
2924 	ret = mmc_add_host(mmc);
2925 
2926 	if (ret)
2927 		goto end;
2928 
2929 	return 0;
2930 end:
2931 	pm_runtime_disable(host->dev);
2932 release:
2933 	platform_set_drvdata(pdev, NULL);
2934 	msdc_deinit_hw(host);
2935 	msdc_gate_clock(host);
2936 release_mem:
2937 	if (host->dma.gpd)
2938 		dma_free_coherent(&pdev->dev,
2939 			2 * sizeof(struct mt_gpdma_desc),
2940 			host->dma.gpd, host->dma.gpd_addr);
2941 	if (host->dma.bd)
2942 		dma_free_coherent(&pdev->dev,
2943 			MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2944 			host->dma.bd, host->dma.bd_addr);
2945 host_free:
2946 	mmc_free_host(mmc);
2947 
2948 	return ret;
2949 }
2950 
2951 static void msdc_drv_remove(struct platform_device *pdev)
2952 {
2953 	struct mmc_host *mmc;
2954 	struct msdc_host *host;
2955 
2956 	mmc = platform_get_drvdata(pdev);
2957 	host = mmc_priv(mmc);
2958 
2959 	pm_runtime_get_sync(host->dev);
2960 
2961 	platform_set_drvdata(pdev, NULL);
2962 	mmc_remove_host(mmc);
2963 	msdc_deinit_hw(host);
2964 	msdc_gate_clock(host);
2965 
2966 	pm_runtime_disable(host->dev);
2967 	pm_runtime_put_noidle(host->dev);
2968 	dma_free_coherent(&pdev->dev,
2969 			2 * sizeof(struct mt_gpdma_desc),
2970 			host->dma.gpd, host->dma.gpd_addr);
2971 	dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc),
2972 			host->dma.bd, host->dma.bd_addr);
2973 
2974 	mmc_free_host(mmc);
2975 }
2976 
2977 static void msdc_save_reg(struct msdc_host *host)
2978 {
2979 	u32 tune_reg = host->dev_comp->pad_tune_reg;
2980 
2981 	host->save_para.msdc_cfg = readl(host->base + MSDC_CFG);
2982 	host->save_para.iocon = readl(host->base + MSDC_IOCON);
2983 	host->save_para.sdc_cfg = readl(host->base + SDC_CFG);
2984 	host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT);
2985 	host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1);
2986 	host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2);
2987 	host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE);
2988 	host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE);
2989 	host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0);
2990 	host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3);
2991 	host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG);
2992 	if (host->top_base) {
2993 		host->save_para.emmc_top_control =
2994 			readl(host->top_base + EMMC_TOP_CONTROL);
2995 		host->save_para.emmc_top_cmd =
2996 			readl(host->top_base + EMMC_TOP_CMD);
2997 		host->save_para.emmc50_pad_ds_tune =
2998 			readl(host->top_base + EMMC50_PAD_DS_TUNE);
2999 	} else {
3000 		host->save_para.pad_tune = readl(host->base + tune_reg);
3001 	}
3002 }
3003 
3004 static void msdc_restore_reg(struct msdc_host *host)
3005 {
3006 	struct mmc_host *mmc = mmc_from_priv(host);
3007 	u32 tune_reg = host->dev_comp->pad_tune_reg;
3008 
3009 	writel(host->save_para.msdc_cfg, host->base + MSDC_CFG);
3010 	writel(host->save_para.iocon, host->base + MSDC_IOCON);
3011 	writel(host->save_para.sdc_cfg, host->base + SDC_CFG);
3012 	writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT);
3013 	writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1);
3014 	writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2);
3015 	writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE);
3016 	writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE);
3017 	writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0);
3018 	writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3);
3019 	writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG);
3020 	if (host->top_base) {
3021 		writel(host->save_para.emmc_top_control,
3022 		       host->top_base + EMMC_TOP_CONTROL);
3023 		writel(host->save_para.emmc_top_cmd,
3024 		       host->top_base + EMMC_TOP_CMD);
3025 		writel(host->save_para.emmc50_pad_ds_tune,
3026 		       host->top_base + EMMC50_PAD_DS_TUNE);
3027 	} else {
3028 		writel(host->save_para.pad_tune, host->base + tune_reg);
3029 	}
3030 
3031 	if (sdio_irq_claimed(mmc))
3032 		__msdc_enable_sdio_irq(host, 1);
3033 }
3034 
3035 static int __maybe_unused msdc_runtime_suspend(struct device *dev)
3036 {
3037 	struct mmc_host *mmc = dev_get_drvdata(dev);
3038 	struct msdc_host *host = mmc_priv(mmc);
3039 
3040 	msdc_save_reg(host);
3041 
3042 	if (sdio_irq_claimed(mmc)) {
3043 		if (host->pins_eint) {
3044 			disable_irq(host->irq);
3045 			pinctrl_select_state(host->pinctrl, host->pins_eint);
3046 		}
3047 
3048 		__msdc_enable_sdio_irq(host, 0);
3049 	}
3050 	msdc_gate_clock(host);
3051 	return 0;
3052 }
3053 
3054 static int __maybe_unused msdc_runtime_resume(struct device *dev)
3055 {
3056 	struct mmc_host *mmc = dev_get_drvdata(dev);
3057 	struct msdc_host *host = mmc_priv(mmc);
3058 	int ret;
3059 
3060 	ret = msdc_ungate_clock(host);
3061 	if (ret)
3062 		return ret;
3063 
3064 	msdc_restore_reg(host);
3065 
3066 	if (sdio_irq_claimed(mmc) && host->pins_eint) {
3067 		pinctrl_select_state(host->pinctrl, host->pins_uhs);
3068 		enable_irq(host->irq);
3069 	}
3070 	return 0;
3071 }
3072 
3073 static int __maybe_unused msdc_suspend(struct device *dev)
3074 {
3075 	struct mmc_host *mmc = dev_get_drvdata(dev);
3076 	struct msdc_host *host = mmc_priv(mmc);
3077 	int ret;
3078 	u32 val;
3079 
3080 	if (mmc->caps2 & MMC_CAP2_CQE) {
3081 		ret = cqhci_suspend(mmc);
3082 		if (ret)
3083 			return ret;
3084 		val = readl(host->base + MSDC_INT);
3085 		writel(val, host->base + MSDC_INT);
3086 	}
3087 
3088 	/*
3089 	 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will
3090 	 * not be marked as 1, pm_runtime_force_resume() will go out directly.
3091 	 */
3092 	if (sdio_irq_claimed(mmc) && host->pins_eint)
3093 		pm_runtime_get_noresume(dev);
3094 
3095 	return pm_runtime_force_suspend(dev);
3096 }
3097 
3098 static int __maybe_unused msdc_resume(struct device *dev)
3099 {
3100 	struct mmc_host *mmc = dev_get_drvdata(dev);
3101 	struct msdc_host *host = mmc_priv(mmc);
3102 
3103 	if (sdio_irq_claimed(mmc) && host->pins_eint)
3104 		pm_runtime_put_noidle(dev);
3105 
3106 	return pm_runtime_force_resume(dev);
3107 }
3108 
3109 static const struct dev_pm_ops msdc_dev_pm_ops = {
3110 	SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume)
3111 	SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL)
3112 };
3113 
3114 static struct platform_driver mt_msdc_driver = {
3115 	.probe = msdc_drv_probe,
3116 	.remove_new = msdc_drv_remove,
3117 	.driver = {
3118 		.name = "mtk-msdc",
3119 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
3120 		.of_match_table = msdc_of_ids,
3121 		.pm = &msdc_dev_pm_ops,
3122 	},
3123 };
3124 
3125 module_platform_driver(mt_msdc_driver);
3126 MODULE_LICENSE("GPL v2");
3127 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");
3128