1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014-2015 MediaTek Inc. 4 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/ioport.h> 12 #include <linux/irq.h> 13 #include <linux/of_address.h> 14 #include <linux/of_device.h> 15 #include <linux/of_irq.h> 16 #include <linux/of_gpio.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/regulator/consumer.h> 22 #include <linux/slab.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/reset.h> 26 27 #include <linux/mmc/card.h> 28 #include <linux/mmc/core.h> 29 #include <linux/mmc/host.h> 30 #include <linux/mmc/mmc.h> 31 #include <linux/mmc/sd.h> 32 #include <linux/mmc/sdio.h> 33 #include <linux/mmc/slot-gpio.h> 34 35 #include "cqhci.h" 36 37 #define MAX_BD_NUM 1024 38 #define MSDC_NR_CLOCKS 3 39 40 /*--------------------------------------------------------------------------*/ 41 /* Common Definition */ 42 /*--------------------------------------------------------------------------*/ 43 #define MSDC_BUS_1BITS 0x0 44 #define MSDC_BUS_4BITS 0x1 45 #define MSDC_BUS_8BITS 0x2 46 47 #define MSDC_BURST_64B 0x6 48 49 /*--------------------------------------------------------------------------*/ 50 /* Register Offset */ 51 /*--------------------------------------------------------------------------*/ 52 #define MSDC_CFG 0x0 53 #define MSDC_IOCON 0x04 54 #define MSDC_PS 0x08 55 #define MSDC_INT 0x0c 56 #define MSDC_INTEN 0x10 57 #define MSDC_FIFOCS 0x14 58 #define SDC_CFG 0x30 59 #define SDC_CMD 0x34 60 #define SDC_ARG 0x38 61 #define SDC_STS 0x3c 62 #define SDC_RESP0 0x40 63 #define SDC_RESP1 0x44 64 #define SDC_RESP2 0x48 65 #define SDC_RESP3 0x4c 66 #define SDC_BLK_NUM 0x50 67 #define SDC_ADV_CFG0 0x64 68 #define EMMC_IOCON 0x7c 69 #define SDC_ACMD_RESP 0x80 70 #define DMA_SA_H4BIT 0x8c 71 #define MSDC_DMA_SA 0x90 72 #define MSDC_DMA_CTRL 0x98 73 #define MSDC_DMA_CFG 0x9c 74 #define MSDC_PATCH_BIT 0xb0 75 #define MSDC_PATCH_BIT1 0xb4 76 #define MSDC_PATCH_BIT2 0xb8 77 #define MSDC_PAD_TUNE 0xec 78 #define MSDC_PAD_TUNE0 0xf0 79 #define PAD_DS_TUNE 0x188 80 #define PAD_CMD_TUNE 0x18c 81 #define EMMC51_CFG0 0x204 82 #define EMMC50_CFG0 0x208 83 #define EMMC50_CFG1 0x20c 84 #define EMMC50_CFG3 0x220 85 #define SDC_FIFO_CFG 0x228 86 #define CQHCI_SETTING 0x7fc 87 88 /*--------------------------------------------------------------------------*/ 89 /* Top Pad Register Offset */ 90 /*--------------------------------------------------------------------------*/ 91 #define EMMC_TOP_CONTROL 0x00 92 #define EMMC_TOP_CMD 0x04 93 #define EMMC50_PAD_DS_TUNE 0x0c 94 95 /*--------------------------------------------------------------------------*/ 96 /* Register Mask */ 97 /*--------------------------------------------------------------------------*/ 98 99 /* MSDC_CFG mask */ 100 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 101 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 102 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 103 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 104 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 105 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 106 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 107 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 108 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 109 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 110 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 111 #define MSDC_CFG_HS400_CK_MODE_EXTRA (0x1 << 22) /* RW */ 112 #define MSDC_CFG_CKDIV_EXTRA (0xfff << 8) /* RW */ 113 #define MSDC_CFG_CKMOD_EXTRA (0x3 << 20) /* RW */ 114 115 /* MSDC_IOCON mask */ 116 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 117 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 118 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 119 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 120 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 121 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 122 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 123 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 124 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 125 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 126 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 127 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 128 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 129 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 130 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 131 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 132 133 /* MSDC_PS mask */ 134 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 135 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 136 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 137 #define MSDC_PS_DAT (0xff << 16) /* R */ 138 #define MSDC_PS_DATA1 (0x1 << 17) /* R */ 139 #define MSDC_PS_CMD (0x1 << 24) /* R */ 140 #define MSDC_PS_WP (0x1 << 31) /* R */ 141 142 /* MSDC_INT mask */ 143 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 144 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 145 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 146 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 147 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 148 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 149 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 150 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 151 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 152 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 153 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 154 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 155 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 156 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 157 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 158 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 159 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 160 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 161 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 162 #define MSDC_INT_CMDQ (0x1 << 28) /* W1C */ 163 164 /* MSDC_INTEN mask */ 165 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 166 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 167 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 168 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 169 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 170 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 171 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 172 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 173 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 174 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 175 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 176 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 177 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 178 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 179 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 180 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 181 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 182 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 183 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 184 185 /* MSDC_FIFOCS mask */ 186 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 187 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 188 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 189 190 /* SDC_CFG mask */ 191 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 192 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 193 #define SDC_CFG_WRDTOC (0x1fff << 2) /* RW */ 194 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 195 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 196 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 197 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 198 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 199 200 /* SDC_STS mask */ 201 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 202 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 203 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 204 205 #define SDC_DAT1_IRQ_TRIGGER (0x1 << 19) /* RW */ 206 /* SDC_ADV_CFG0 mask */ 207 #define SDC_RX_ENHANCE_EN (0x1 << 20) /* RW */ 208 209 /* DMA_SA_H4BIT mask */ 210 #define DMA_ADDR_HIGH_4BIT (0xf << 0) /* RW */ 211 212 /* MSDC_DMA_CTRL mask */ 213 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 214 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 215 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 216 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 217 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 218 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 219 220 /* MSDC_DMA_CFG mask */ 221 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 222 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 223 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 224 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 225 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 226 227 /* MSDC_PATCH_BIT mask */ 228 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 229 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 230 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 231 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 232 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 233 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 234 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 235 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 236 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 237 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 238 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 239 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 240 241 #define MSDC_PATCH_BIT1_CMDTA (0x7 << 3) /* RW */ 242 #define MSDC_PB1_BUSY_CHECK_SEL (0x1 << 7) /* RW */ 243 #define MSDC_PATCH_BIT1_STOP_DLY (0xf << 8) /* RW */ 244 245 #define MSDC_PATCH_BIT2_CFGRESP (0x1 << 15) /* RW */ 246 #define MSDC_PATCH_BIT2_CFGCRCSTS (0x1 << 28) /* RW */ 247 #define MSDC_PB2_SUPPORT_64G (0x1 << 1) /* RW */ 248 #define MSDC_PB2_RESPWAIT (0x3 << 2) /* RW */ 249 #define MSDC_PB2_RESPSTSENSEL (0x7 << 16) /* RW */ 250 #define MSDC_PB2_CRCSTSENSEL (0x7 << 29) /* RW */ 251 252 #define MSDC_PAD_TUNE_DATWRDLY (0x1f << 0) /* RW */ 253 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 254 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 255 #define MSDC_PAD_TUNE_CMDRRDLY (0x1f << 22) /* RW */ 256 #define MSDC_PAD_TUNE_CLKTDLY (0x1f << 27) /* RW */ 257 #define MSDC_PAD_TUNE_RXDLYSEL (0x1 << 15) /* RW */ 258 #define MSDC_PAD_TUNE_RD_SEL (0x1 << 13) /* RW */ 259 #define MSDC_PAD_TUNE_CMD_SEL (0x1 << 21) /* RW */ 260 261 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 262 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 263 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 264 265 #define PAD_CMD_TUNE_RX_DLY3 (0x1f << 1) /* RW */ 266 267 /* EMMC51_CFG0 mask */ 268 #define CMDQ_RDAT_CNT (0x3ff << 12) /* RW */ 269 270 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 271 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 272 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 273 #define EMMC50_CFG_CMD_RESP_SEL (0x1 << 9) /* RW */ 274 275 /* EMMC50_CFG1 mask */ 276 #define EMMC50_CFG1_DS_CFG (0x1 << 28) /* RW */ 277 278 #define EMMC50_CFG3_OUTS_WR (0x1f << 0) /* RW */ 279 280 #define SDC_FIFO_CFG_WRVALIDSEL (0x1 << 24) /* RW */ 281 #define SDC_FIFO_CFG_RDVALIDSEL (0x1 << 25) /* RW */ 282 283 /* CQHCI_SETTING */ 284 #define CQHCI_RD_CMD_WND_SEL (0x1 << 14) /* RW */ 285 #define CQHCI_WR_CMD_WND_SEL (0x1 << 15) /* RW */ 286 287 /* EMMC_TOP_CONTROL mask */ 288 #define PAD_RXDLY_SEL (0x1 << 0) /* RW */ 289 #define DELAY_EN (0x1 << 1) /* RW */ 290 #define PAD_DAT_RD_RXDLY2 (0x1f << 2) /* RW */ 291 #define PAD_DAT_RD_RXDLY (0x1f << 7) /* RW */ 292 #define PAD_DAT_RD_RXDLY2_SEL (0x1 << 12) /* RW */ 293 #define PAD_DAT_RD_RXDLY_SEL (0x1 << 13) /* RW */ 294 #define DATA_K_VALUE_SEL (0x1 << 14) /* RW */ 295 #define SDC_RX_ENH_EN (0x1 << 15) /* TW */ 296 297 /* EMMC_TOP_CMD mask */ 298 #define PAD_CMD_RXDLY2 (0x1f << 0) /* RW */ 299 #define PAD_CMD_RXDLY (0x1f << 5) /* RW */ 300 #define PAD_CMD_RD_RXDLY2_SEL (0x1 << 10) /* RW */ 301 #define PAD_CMD_RD_RXDLY_SEL (0x1 << 11) /* RW */ 302 #define PAD_CMD_TX_DLY (0x1f << 12) /* RW */ 303 304 #define REQ_CMD_EIO (0x1 << 0) 305 #define REQ_CMD_TMO (0x1 << 1) 306 #define REQ_DAT_ERR (0x1 << 2) 307 #define REQ_STOP_EIO (0x1 << 3) 308 #define REQ_STOP_TMO (0x1 << 4) 309 #define REQ_CMD_BUSY (0x1 << 5) 310 311 #define MSDC_PREPARE_FLAG (0x1 << 0) 312 #define MSDC_ASYNC_FLAG (0x1 << 1) 313 #define MSDC_MMAP_FLAG (0x1 << 2) 314 315 #define MTK_MMC_AUTOSUSPEND_DELAY 50 316 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 317 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 318 319 #define DEFAULT_DEBOUNCE (8) /* 8 cycles CD debounce */ 320 321 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 322 /*--------------------------------------------------------------------------*/ 323 /* Descriptor Structure */ 324 /*--------------------------------------------------------------------------*/ 325 struct mt_gpdma_desc { 326 u32 gpd_info; 327 #define GPDMA_DESC_HWO (0x1 << 0) 328 #define GPDMA_DESC_BDP (0x1 << 1) 329 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 330 #define GPDMA_DESC_INT (0x1 << 16) 331 #define GPDMA_DESC_NEXT_H4 (0xf << 24) 332 #define GPDMA_DESC_PTR_H4 (0xf << 28) 333 u32 next; 334 u32 ptr; 335 u32 gpd_data_len; 336 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 337 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 338 u32 arg; 339 u32 blknum; 340 u32 cmd; 341 }; 342 343 struct mt_bdma_desc { 344 u32 bd_info; 345 #define BDMA_DESC_EOL (0x1 << 0) 346 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 347 #define BDMA_DESC_BLKPAD (0x1 << 17) 348 #define BDMA_DESC_DWPAD (0x1 << 18) 349 #define BDMA_DESC_NEXT_H4 (0xf << 24) 350 #define BDMA_DESC_PTR_H4 (0xf << 28) 351 u32 next; 352 u32 ptr; 353 u32 bd_data_len; 354 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 355 #define BDMA_DESC_BUFLEN_EXT (0xffffff) /* bit0 ~ bit23 */ 356 }; 357 358 struct msdc_dma { 359 struct scatterlist *sg; /* I/O scatter list */ 360 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 361 struct mt_bdma_desc *bd; /* pointer to bd array */ 362 dma_addr_t gpd_addr; /* the physical address of gpd array */ 363 dma_addr_t bd_addr; /* the physical address of bd array */ 364 }; 365 366 struct msdc_save_para { 367 u32 msdc_cfg; 368 u32 iocon; 369 u32 sdc_cfg; 370 u32 pad_tune; 371 u32 patch_bit0; 372 u32 patch_bit1; 373 u32 patch_bit2; 374 u32 pad_ds_tune; 375 u32 pad_cmd_tune; 376 u32 emmc50_cfg0; 377 u32 emmc50_cfg3; 378 u32 sdc_fifo_cfg; 379 u32 emmc_top_control; 380 u32 emmc_top_cmd; 381 u32 emmc50_pad_ds_tune; 382 }; 383 384 struct mtk_mmc_compatible { 385 u8 clk_div_bits; 386 bool recheck_sdio_irq; 387 bool hs400_tune; /* only used for MT8173 */ 388 u32 pad_tune_reg; 389 bool async_fifo; 390 bool data_tune; 391 bool busy_check; 392 bool stop_clk_fix; 393 bool enhance_rx; 394 bool support_64g; 395 bool use_internal_cd; 396 }; 397 398 struct msdc_tune_para { 399 u32 iocon; 400 u32 pad_tune; 401 u32 pad_cmd_tune; 402 u32 emmc_top_control; 403 u32 emmc_top_cmd; 404 }; 405 406 struct msdc_delay_phase { 407 u8 maxlen; 408 u8 start; 409 u8 final_phase; 410 }; 411 412 struct msdc_host { 413 struct device *dev; 414 const struct mtk_mmc_compatible *dev_comp; 415 int cmd_rsp; 416 417 spinlock_t lock; 418 struct mmc_request *mrq; 419 struct mmc_command *cmd; 420 struct mmc_data *data; 421 int error; 422 423 void __iomem *base; /* host base address */ 424 void __iomem *top_base; /* host top register base address */ 425 426 struct msdc_dma dma; /* dma channel */ 427 u64 dma_mask; 428 429 u32 timeout_ns; /* data timeout ns */ 430 u32 timeout_clks; /* data timeout clks */ 431 432 struct pinctrl *pinctrl; 433 struct pinctrl_state *pins_default; 434 struct pinctrl_state *pins_uhs; 435 struct delayed_work req_timeout; 436 int irq; /* host interrupt */ 437 struct reset_control *reset; 438 439 struct clk *src_clk; /* msdc source clock */ 440 struct clk *h_clk; /* msdc h_clk */ 441 struct clk *bus_clk; /* bus clock which used to access register */ 442 struct clk *src_clk_cg; /* msdc source clock control gate */ 443 struct clk *sys_clk_cg; /* msdc subsys clock control gate */ 444 struct clk_bulk_data bulk_clks[MSDC_NR_CLOCKS]; 445 u32 mclk; /* mmc subsystem clock frequency */ 446 u32 src_clk_freq; /* source clock frequency */ 447 unsigned char timing; 448 bool vqmmc_enabled; 449 u32 latch_ck; 450 u32 hs400_ds_delay; 451 u32 hs200_cmd_int_delay; /* cmd internal delay for HS200/SDR104 */ 452 u32 hs400_cmd_int_delay; /* cmd internal delay for HS400 */ 453 bool hs400_cmd_resp_sel_rising; 454 /* cmd response sample selection for HS400 */ 455 bool hs400_mode; /* current eMMC will run at hs400 mode */ 456 bool internal_cd; /* Use internal card-detect logic */ 457 bool cqhci; /* support eMMC hw cmdq */ 458 struct msdc_save_para save_para; /* used when gate HCLK */ 459 struct msdc_tune_para def_tune_para; /* default tune setting */ 460 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 461 struct cqhci_host *cq_host; 462 }; 463 464 static const struct mtk_mmc_compatible mt8135_compat = { 465 .clk_div_bits = 8, 466 .recheck_sdio_irq = true, 467 .hs400_tune = false, 468 .pad_tune_reg = MSDC_PAD_TUNE, 469 .async_fifo = false, 470 .data_tune = false, 471 .busy_check = false, 472 .stop_clk_fix = false, 473 .enhance_rx = false, 474 .support_64g = false, 475 }; 476 477 static const struct mtk_mmc_compatible mt8173_compat = { 478 .clk_div_bits = 8, 479 .recheck_sdio_irq = true, 480 .hs400_tune = true, 481 .pad_tune_reg = MSDC_PAD_TUNE, 482 .async_fifo = false, 483 .data_tune = false, 484 .busy_check = false, 485 .stop_clk_fix = false, 486 .enhance_rx = false, 487 .support_64g = false, 488 }; 489 490 static const struct mtk_mmc_compatible mt8183_compat = { 491 .clk_div_bits = 12, 492 .recheck_sdio_irq = false, 493 .hs400_tune = false, 494 .pad_tune_reg = MSDC_PAD_TUNE0, 495 .async_fifo = true, 496 .data_tune = true, 497 .busy_check = true, 498 .stop_clk_fix = true, 499 .enhance_rx = true, 500 .support_64g = true, 501 }; 502 503 static const struct mtk_mmc_compatible mt2701_compat = { 504 .clk_div_bits = 12, 505 .recheck_sdio_irq = true, 506 .hs400_tune = false, 507 .pad_tune_reg = MSDC_PAD_TUNE0, 508 .async_fifo = true, 509 .data_tune = true, 510 .busy_check = false, 511 .stop_clk_fix = false, 512 .enhance_rx = false, 513 .support_64g = false, 514 }; 515 516 static const struct mtk_mmc_compatible mt2712_compat = { 517 .clk_div_bits = 12, 518 .recheck_sdio_irq = false, 519 .hs400_tune = false, 520 .pad_tune_reg = MSDC_PAD_TUNE0, 521 .async_fifo = true, 522 .data_tune = true, 523 .busy_check = true, 524 .stop_clk_fix = true, 525 .enhance_rx = true, 526 .support_64g = true, 527 }; 528 529 static const struct mtk_mmc_compatible mt7622_compat = { 530 .clk_div_bits = 12, 531 .recheck_sdio_irq = true, 532 .hs400_tune = false, 533 .pad_tune_reg = MSDC_PAD_TUNE0, 534 .async_fifo = true, 535 .data_tune = true, 536 .busy_check = true, 537 .stop_clk_fix = true, 538 .enhance_rx = true, 539 .support_64g = false, 540 }; 541 542 static const struct mtk_mmc_compatible mt8516_compat = { 543 .clk_div_bits = 12, 544 .recheck_sdio_irq = true, 545 .hs400_tune = false, 546 .pad_tune_reg = MSDC_PAD_TUNE0, 547 .async_fifo = true, 548 .data_tune = true, 549 .busy_check = true, 550 .stop_clk_fix = true, 551 }; 552 553 static const struct mtk_mmc_compatible mt7620_compat = { 554 .clk_div_bits = 8, 555 .recheck_sdio_irq = true, 556 .hs400_tune = false, 557 .pad_tune_reg = MSDC_PAD_TUNE, 558 .async_fifo = false, 559 .data_tune = false, 560 .busy_check = false, 561 .stop_clk_fix = false, 562 .enhance_rx = false, 563 .use_internal_cd = true, 564 }; 565 566 static const struct mtk_mmc_compatible mt6779_compat = { 567 .clk_div_bits = 12, 568 .recheck_sdio_irq = false, 569 .hs400_tune = false, 570 .pad_tune_reg = MSDC_PAD_TUNE0, 571 .async_fifo = true, 572 .data_tune = true, 573 .busy_check = true, 574 .stop_clk_fix = true, 575 .enhance_rx = true, 576 .support_64g = true, 577 }; 578 579 static const struct of_device_id msdc_of_ids[] = { 580 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat}, 581 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat}, 582 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat}, 583 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat}, 584 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat}, 585 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat}, 586 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat}, 587 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat}, 588 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat}, 589 {} 590 }; 591 MODULE_DEVICE_TABLE(of, msdc_of_ids); 592 593 static void sdr_set_bits(void __iomem *reg, u32 bs) 594 { 595 u32 val = readl(reg); 596 597 val |= bs; 598 writel(val, reg); 599 } 600 601 static void sdr_clr_bits(void __iomem *reg, u32 bs) 602 { 603 u32 val = readl(reg); 604 605 val &= ~bs; 606 writel(val, reg); 607 } 608 609 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 610 { 611 unsigned int tv = readl(reg); 612 613 tv &= ~field; 614 tv |= ((val) << (ffs((unsigned int)field) - 1)); 615 writel(tv, reg); 616 } 617 618 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 619 { 620 unsigned int tv = readl(reg); 621 622 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 623 } 624 625 static void msdc_reset_hw(struct msdc_host *host) 626 { 627 u32 val; 628 629 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 630 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 631 cpu_relax(); 632 633 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 634 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 635 cpu_relax(); 636 637 val = readl(host->base + MSDC_INT); 638 writel(val, host->base + MSDC_INT); 639 } 640 641 static void msdc_cmd_next(struct msdc_host *host, 642 struct mmc_request *mrq, struct mmc_command *cmd); 643 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb); 644 645 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 646 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 647 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 648 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 649 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 650 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 651 652 static u8 msdc_dma_calcs(u8 *buf, u32 len) 653 { 654 u32 i, sum = 0; 655 656 for (i = 0; i < len; i++) 657 sum += buf[i]; 658 return 0xff - (u8) sum; 659 } 660 661 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 662 struct mmc_data *data) 663 { 664 unsigned int j, dma_len; 665 dma_addr_t dma_address; 666 u32 dma_ctrl; 667 struct scatterlist *sg; 668 struct mt_gpdma_desc *gpd; 669 struct mt_bdma_desc *bd; 670 671 sg = data->sg; 672 673 gpd = dma->gpd; 674 bd = dma->bd; 675 676 /* modify gpd */ 677 gpd->gpd_info |= GPDMA_DESC_HWO; 678 gpd->gpd_info |= GPDMA_DESC_BDP; 679 /* need to clear first. use these bits to calc checksum */ 680 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 681 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 682 683 /* modify bd */ 684 for_each_sg(data->sg, sg, data->sg_count, j) { 685 dma_address = sg_dma_address(sg); 686 dma_len = sg_dma_len(sg); 687 688 /* init bd */ 689 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 690 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 691 bd[j].ptr = lower_32_bits(dma_address); 692 if (host->dev_comp->support_64g) { 693 bd[j].bd_info &= ~BDMA_DESC_PTR_H4; 694 bd[j].bd_info |= (upper_32_bits(dma_address) & 0xf) 695 << 28; 696 } 697 698 if (host->dev_comp->support_64g) { 699 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN_EXT; 700 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN_EXT); 701 } else { 702 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 703 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 704 } 705 706 if (j == data->sg_count - 1) /* the last bd */ 707 bd[j].bd_info |= BDMA_DESC_EOL; 708 else 709 bd[j].bd_info &= ~BDMA_DESC_EOL; 710 711 /* checksume need to clear first */ 712 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 713 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 714 } 715 716 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 717 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 718 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 719 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 720 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 721 if (host->dev_comp->support_64g) 722 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, 723 upper_32_bits(dma->gpd_addr) & 0xf); 724 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); 725 } 726 727 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) 728 { 729 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 730 data->host_cookie |= MSDC_PREPARE_FLAG; 731 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 732 mmc_get_dma_dir(data)); 733 } 734 } 735 736 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) 737 { 738 if (data->host_cookie & MSDC_ASYNC_FLAG) 739 return; 740 741 if (data->host_cookie & MSDC_PREPARE_FLAG) { 742 dma_unmap_sg(host->dev, data->sg, data->sg_len, 743 mmc_get_dma_dir(data)); 744 data->host_cookie &= ~MSDC_PREPARE_FLAG; 745 } 746 } 747 748 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) 749 { 750 struct mmc_host *mmc = mmc_from_priv(host); 751 u64 timeout, clk_ns; 752 u32 mode = 0; 753 754 if (mmc->actual_clock == 0) { 755 timeout = 0; 756 } else { 757 clk_ns = 1000000000ULL; 758 do_div(clk_ns, mmc->actual_clock); 759 timeout = ns + clk_ns - 1; 760 do_div(timeout, clk_ns); 761 timeout += clks; 762 /* in 1048576 sclk cycle unit */ 763 timeout = DIV_ROUND_UP(timeout, (0x1 << 20)); 764 if (host->dev_comp->clk_div_bits == 8) 765 sdr_get_field(host->base + MSDC_CFG, 766 MSDC_CFG_CKMOD, &mode); 767 else 768 sdr_get_field(host->base + MSDC_CFG, 769 MSDC_CFG_CKMOD_EXTRA, &mode); 770 /*DDR mode will double the clk cycles for data timeout */ 771 timeout = mode >= 2 ? timeout * 2 : timeout; 772 timeout = timeout > 1 ? timeout - 1 : 0; 773 } 774 return timeout; 775 } 776 777 /* clock control primitives */ 778 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) 779 { 780 u64 timeout; 781 782 host->timeout_ns = ns; 783 host->timeout_clks = clks; 784 785 timeout = msdc_timeout_cal(host, ns, clks); 786 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 787 (u32)(timeout > 255 ? 255 : timeout)); 788 } 789 790 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) 791 { 792 u64 timeout; 793 794 timeout = msdc_timeout_cal(host, ns, clks); 795 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, 796 (u32)(timeout > 8191 ? 8191 : timeout)); 797 } 798 799 static void msdc_gate_clock(struct msdc_host *host) 800 { 801 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); 802 clk_disable_unprepare(host->src_clk_cg); 803 clk_disable_unprepare(host->src_clk); 804 clk_disable_unprepare(host->bus_clk); 805 clk_disable_unprepare(host->h_clk); 806 } 807 808 static void msdc_ungate_clock(struct msdc_host *host) 809 { 810 int ret; 811 812 clk_prepare_enable(host->h_clk); 813 clk_prepare_enable(host->bus_clk); 814 clk_prepare_enable(host->src_clk); 815 clk_prepare_enable(host->src_clk_cg); 816 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); 817 if (ret) { 818 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); 819 return; 820 } 821 822 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 823 cpu_relax(); 824 } 825 826 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 827 { 828 struct mmc_host *mmc = mmc_from_priv(host); 829 u32 mode; 830 u32 flags; 831 u32 div; 832 u32 sclk; 833 u32 tune_reg = host->dev_comp->pad_tune_reg; 834 835 if (!hz) { 836 dev_dbg(host->dev, "set mclk to 0\n"); 837 host->mclk = 0; 838 mmc->actual_clock = 0; 839 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 840 return; 841 } 842 843 flags = readl(host->base + MSDC_INTEN); 844 sdr_clr_bits(host->base + MSDC_INTEN, flags); 845 if (host->dev_comp->clk_div_bits == 8) 846 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 847 else 848 sdr_clr_bits(host->base + MSDC_CFG, 849 MSDC_CFG_HS400_CK_MODE_EXTRA); 850 if (timing == MMC_TIMING_UHS_DDR50 || 851 timing == MMC_TIMING_MMC_DDR52 || 852 timing == MMC_TIMING_MMC_HS400) { 853 if (timing == MMC_TIMING_MMC_HS400) 854 mode = 0x3; 855 else 856 mode = 0x2; /* ddr mode and use divisor */ 857 858 if (hz >= (host->src_clk_freq >> 2)) { 859 div = 0; /* mean div = 1/4 */ 860 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 861 } else { 862 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 863 sclk = (host->src_clk_freq >> 2) / div; 864 div = (div >> 1); 865 } 866 867 if (timing == MMC_TIMING_MMC_HS400 && 868 hz >= (host->src_clk_freq >> 1)) { 869 if (host->dev_comp->clk_div_bits == 8) 870 sdr_set_bits(host->base + MSDC_CFG, 871 MSDC_CFG_HS400_CK_MODE); 872 else 873 sdr_set_bits(host->base + MSDC_CFG, 874 MSDC_CFG_HS400_CK_MODE_EXTRA); 875 sclk = host->src_clk_freq >> 1; 876 div = 0; /* div is ignore when bit18 is set */ 877 } 878 } else if (hz >= host->src_clk_freq) { 879 mode = 0x1; /* no divisor */ 880 div = 0; 881 sclk = host->src_clk_freq; 882 } else { 883 mode = 0x0; /* use divisor */ 884 if (hz >= (host->src_clk_freq >> 1)) { 885 div = 0; /* mean div = 1/2 */ 886 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 887 } else { 888 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 889 sclk = (host->src_clk_freq >> 2) / div; 890 } 891 } 892 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 893 /* 894 * As src_clk/HCLK use the same bit to gate/ungate, 895 * So if want to only gate src_clk, need gate its parent(mux). 896 */ 897 if (host->src_clk_cg) 898 clk_disable_unprepare(host->src_clk_cg); 899 else 900 clk_disable_unprepare(clk_get_parent(host->src_clk)); 901 if (host->dev_comp->clk_div_bits == 8) 902 sdr_set_field(host->base + MSDC_CFG, 903 MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 904 (mode << 8) | div); 905 else 906 sdr_set_field(host->base + MSDC_CFG, 907 MSDC_CFG_CKMOD_EXTRA | MSDC_CFG_CKDIV_EXTRA, 908 (mode << 12) | div); 909 if (host->src_clk_cg) 910 clk_prepare_enable(host->src_clk_cg); 911 else 912 clk_prepare_enable(clk_get_parent(host->src_clk)); 913 914 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 915 cpu_relax(); 916 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 917 mmc->actual_clock = sclk; 918 host->mclk = hz; 919 host->timing = timing; 920 /* need because clk changed. */ 921 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 922 sdr_set_bits(host->base + MSDC_INTEN, flags); 923 924 /* 925 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 926 * tune result of hs200/200Mhz is not suitable for 50Mhz 927 */ 928 if (mmc->actual_clock <= 52000000) { 929 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 930 if (host->top_base) { 931 writel(host->def_tune_para.emmc_top_control, 932 host->top_base + EMMC_TOP_CONTROL); 933 writel(host->def_tune_para.emmc_top_cmd, 934 host->top_base + EMMC_TOP_CMD); 935 } else { 936 writel(host->def_tune_para.pad_tune, 937 host->base + tune_reg); 938 } 939 } else { 940 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 941 writel(host->saved_tune_para.pad_cmd_tune, 942 host->base + PAD_CMD_TUNE); 943 if (host->top_base) { 944 writel(host->saved_tune_para.emmc_top_control, 945 host->top_base + EMMC_TOP_CONTROL); 946 writel(host->saved_tune_para.emmc_top_cmd, 947 host->top_base + EMMC_TOP_CMD); 948 } else { 949 writel(host->saved_tune_para.pad_tune, 950 host->base + tune_reg); 951 } 952 } 953 954 if (timing == MMC_TIMING_MMC_HS400 && 955 host->dev_comp->hs400_tune) 956 sdr_set_field(host->base + tune_reg, 957 MSDC_PAD_TUNE_CMDRRDLY, 958 host->hs400_cmd_int_delay); 959 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, 960 timing); 961 } 962 963 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 964 struct mmc_request *mrq, struct mmc_command *cmd) 965 { 966 u32 resp; 967 968 switch (mmc_resp_type(cmd)) { 969 /* Actually, R1, R5, R6, R7 are the same */ 970 case MMC_RSP_R1: 971 resp = 0x1; 972 break; 973 case MMC_RSP_R1B: 974 resp = 0x7; 975 break; 976 case MMC_RSP_R2: 977 resp = 0x2; 978 break; 979 case MMC_RSP_R3: 980 resp = 0x3; 981 break; 982 case MMC_RSP_NONE: 983 default: 984 resp = 0x0; 985 break; 986 } 987 988 return resp; 989 } 990 991 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 992 struct mmc_request *mrq, struct mmc_command *cmd) 993 { 994 struct mmc_host *mmc = mmc_from_priv(host); 995 /* rawcmd : 996 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 997 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 998 */ 999 u32 opcode = cmd->opcode; 1000 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 1001 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 1002 1003 host->cmd_rsp = resp; 1004 1005 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 1006 opcode == MMC_STOP_TRANSMISSION) 1007 rawcmd |= (0x1 << 14); 1008 else if (opcode == SD_SWITCH_VOLTAGE) 1009 rawcmd |= (0x1 << 30); 1010 else if (opcode == SD_APP_SEND_SCR || 1011 opcode == SD_APP_SEND_NUM_WR_BLKS || 1012 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1013 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 1014 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 1015 rawcmd |= (0x1 << 11); 1016 1017 if (cmd->data) { 1018 struct mmc_data *data = cmd->data; 1019 1020 if (mmc_op_multi(opcode)) { 1021 if (mmc_card_mmc(mmc->card) && mrq->sbc && 1022 !(mrq->sbc->arg & 0xFFFF0000)) 1023 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 1024 } 1025 1026 rawcmd |= ((data->blksz & 0xFFF) << 16); 1027 if (data->flags & MMC_DATA_WRITE) 1028 rawcmd |= (0x1 << 13); 1029 if (data->blocks > 1) 1030 rawcmd |= (0x2 << 11); 1031 else 1032 rawcmd |= (0x1 << 11); 1033 /* Always use dma mode */ 1034 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 1035 1036 if (host->timeout_ns != data->timeout_ns || 1037 host->timeout_clks != data->timeout_clks) 1038 msdc_set_timeout(host, data->timeout_ns, 1039 data->timeout_clks); 1040 1041 writel(data->blocks, host->base + SDC_BLK_NUM); 1042 } 1043 return rawcmd; 1044 } 1045 1046 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 1047 struct mmc_command *cmd, struct mmc_data *data) 1048 { 1049 bool read; 1050 1051 WARN_ON(host->data); 1052 host->data = data; 1053 read = data->flags & MMC_DATA_READ; 1054 1055 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1056 msdc_dma_setup(host, &host->dma, data); 1057 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 1058 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 1059 dev_dbg(host->dev, "DMA start\n"); 1060 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 1061 __func__, cmd->opcode, data->blocks, read); 1062 } 1063 1064 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 1065 struct mmc_command *cmd) 1066 { 1067 u32 *rsp = cmd->resp; 1068 1069 rsp[0] = readl(host->base + SDC_ACMD_RESP); 1070 1071 if (events & MSDC_INT_ACMDRDY) { 1072 cmd->error = 0; 1073 } else { 1074 msdc_reset_hw(host); 1075 if (events & MSDC_INT_ACMDCRCERR) { 1076 cmd->error = -EILSEQ; 1077 host->error |= REQ_STOP_EIO; 1078 } else if (events & MSDC_INT_ACMDTMO) { 1079 cmd->error = -ETIMEDOUT; 1080 host->error |= REQ_STOP_TMO; 1081 } 1082 dev_err(host->dev, 1083 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 1084 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 1085 } 1086 return cmd->error; 1087 } 1088 1089 /* 1090 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost 1091 * 1092 * Host controller may lost interrupt in some special case. 1093 * Add SDIO irq recheck mechanism to make sure all interrupts 1094 * can be processed immediately 1095 */ 1096 static void msdc_recheck_sdio_irq(struct msdc_host *host) 1097 { 1098 struct mmc_host *mmc = mmc_from_priv(host); 1099 u32 reg_int, reg_inten, reg_ps; 1100 1101 if (mmc->caps & MMC_CAP_SDIO_IRQ) { 1102 reg_inten = readl(host->base + MSDC_INTEN); 1103 if (reg_inten & MSDC_INTEN_SDIOIRQ) { 1104 reg_int = readl(host->base + MSDC_INT); 1105 reg_ps = readl(host->base + MSDC_PS); 1106 if (!(reg_int & MSDC_INT_SDIOIRQ || 1107 reg_ps & MSDC_PS_DATA1)) { 1108 __msdc_enable_sdio_irq(host, 0); 1109 sdio_signal_irq(mmc); 1110 } 1111 } 1112 } 1113 } 1114 1115 static void msdc_track_cmd_data(struct msdc_host *host, 1116 struct mmc_command *cmd, struct mmc_data *data) 1117 { 1118 if (host->error) 1119 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 1120 __func__, cmd->opcode, cmd->arg, host->error); 1121 } 1122 1123 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 1124 { 1125 unsigned long flags; 1126 1127 /* 1128 * No need check the return value of cancel_delayed_work, as only ONE 1129 * path will go here! 1130 */ 1131 cancel_delayed_work(&host->req_timeout); 1132 1133 spin_lock_irqsave(&host->lock, flags); 1134 host->mrq = NULL; 1135 spin_unlock_irqrestore(&host->lock, flags); 1136 1137 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 1138 if (mrq->data) 1139 msdc_unprepare_data(host, mrq->data); 1140 if (host->error) 1141 msdc_reset_hw(host); 1142 mmc_request_done(mmc_from_priv(host), mrq); 1143 if (host->dev_comp->recheck_sdio_irq) 1144 msdc_recheck_sdio_irq(host); 1145 } 1146 1147 /* returns true if command is fully handled; returns false otherwise */ 1148 static bool msdc_cmd_done(struct msdc_host *host, int events, 1149 struct mmc_request *mrq, struct mmc_command *cmd) 1150 { 1151 bool done = false; 1152 bool sbc_error; 1153 unsigned long flags; 1154 u32 *rsp; 1155 1156 if (mrq->sbc && cmd == mrq->cmd && 1157 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 1158 | MSDC_INT_ACMDTMO))) 1159 msdc_auto_cmd_done(host, events, mrq->sbc); 1160 1161 sbc_error = mrq->sbc && mrq->sbc->error; 1162 1163 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 1164 | MSDC_INT_RSPCRCERR 1165 | MSDC_INT_CMDTMO))) 1166 return done; 1167 1168 spin_lock_irqsave(&host->lock, flags); 1169 done = !host->cmd; 1170 host->cmd = NULL; 1171 spin_unlock_irqrestore(&host->lock, flags); 1172 1173 if (done) 1174 return true; 1175 rsp = cmd->resp; 1176 1177 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1178 1179 if (cmd->flags & MMC_RSP_PRESENT) { 1180 if (cmd->flags & MMC_RSP_136) { 1181 rsp[0] = readl(host->base + SDC_RESP3); 1182 rsp[1] = readl(host->base + SDC_RESP2); 1183 rsp[2] = readl(host->base + SDC_RESP1); 1184 rsp[3] = readl(host->base + SDC_RESP0); 1185 } else { 1186 rsp[0] = readl(host->base + SDC_RESP0); 1187 } 1188 } 1189 1190 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 1191 if (events & MSDC_INT_CMDTMO || 1192 (cmd->opcode != MMC_SEND_TUNING_BLOCK && 1193 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200)) 1194 /* 1195 * should not clear fifo/interrupt as the tune data 1196 * may have alreay come when cmd19/cmd21 gets response 1197 * CRC error. 1198 */ 1199 msdc_reset_hw(host); 1200 if (events & MSDC_INT_RSPCRCERR) { 1201 cmd->error = -EILSEQ; 1202 host->error |= REQ_CMD_EIO; 1203 } else if (events & MSDC_INT_CMDTMO) { 1204 cmd->error = -ETIMEDOUT; 1205 host->error |= REQ_CMD_TMO; 1206 } 1207 } 1208 if (cmd->error) 1209 dev_dbg(host->dev, 1210 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 1211 __func__, cmd->opcode, cmd->arg, rsp[0], 1212 cmd->error); 1213 1214 msdc_cmd_next(host, mrq, cmd); 1215 return true; 1216 } 1217 1218 /* It is the core layer's responsibility to ensure card status 1219 * is correct before issue a request. but host design do below 1220 * checks recommended. 1221 */ 1222 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 1223 struct mmc_request *mrq, struct mmc_command *cmd) 1224 { 1225 /* The max busy time we can endure is 20ms */ 1226 unsigned long tmo = jiffies + msecs_to_jiffies(20); 1227 1228 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 1229 time_before(jiffies, tmo)) 1230 cpu_relax(); 1231 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 1232 dev_err(host->dev, "CMD bus busy detected\n"); 1233 host->error |= REQ_CMD_BUSY; 1234 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1235 return false; 1236 } 1237 1238 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 1239 tmo = jiffies + msecs_to_jiffies(20); 1240 /* R1B or with data, should check SDCBUSY */ 1241 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 1242 time_before(jiffies, tmo)) 1243 cpu_relax(); 1244 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 1245 dev_err(host->dev, "Controller busy detected\n"); 1246 host->error |= REQ_CMD_BUSY; 1247 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 1248 return false; 1249 } 1250 } 1251 return true; 1252 } 1253 1254 static void msdc_start_command(struct msdc_host *host, 1255 struct mmc_request *mrq, struct mmc_command *cmd) 1256 { 1257 u32 rawcmd; 1258 unsigned long flags; 1259 1260 WARN_ON(host->cmd); 1261 host->cmd = cmd; 1262 1263 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 1264 if (!msdc_cmd_is_ready(host, mrq, cmd)) 1265 return; 1266 1267 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 1268 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 1269 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 1270 msdc_reset_hw(host); 1271 } 1272 1273 cmd->error = 0; 1274 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 1275 1276 spin_lock_irqsave(&host->lock, flags); 1277 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 1278 spin_unlock_irqrestore(&host->lock, flags); 1279 1280 writel(cmd->arg, host->base + SDC_ARG); 1281 writel(rawcmd, host->base + SDC_CMD); 1282 } 1283 1284 static void msdc_cmd_next(struct msdc_host *host, 1285 struct mmc_request *mrq, struct mmc_command *cmd) 1286 { 1287 if ((cmd->error && 1288 !(cmd->error == -EILSEQ && 1289 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 1290 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 1291 (mrq->sbc && mrq->sbc->error)) 1292 msdc_request_done(host, mrq); 1293 else if (cmd == mrq->sbc) 1294 msdc_start_command(host, mrq, mrq->cmd); 1295 else if (!cmd->data) 1296 msdc_request_done(host, mrq); 1297 else 1298 msdc_start_data(host, mrq, cmd, cmd->data); 1299 } 1300 1301 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 1302 { 1303 struct msdc_host *host = mmc_priv(mmc); 1304 1305 host->error = 0; 1306 WARN_ON(host->mrq); 1307 host->mrq = mrq; 1308 1309 if (mrq->data) 1310 msdc_prepare_data(host, mrq->data); 1311 1312 /* if SBC is required, we have HW option and SW option. 1313 * if HW option is enabled, and SBC does not have "special" flags, 1314 * use HW option, otherwise use SW option 1315 */ 1316 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 1317 (mrq->sbc->arg & 0xFFFF0000))) 1318 msdc_start_command(host, mrq, mrq->sbc); 1319 else 1320 msdc_start_command(host, mrq, mrq->cmd); 1321 } 1322 1323 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 1324 { 1325 struct msdc_host *host = mmc_priv(mmc); 1326 struct mmc_data *data = mrq->data; 1327 1328 if (!data) 1329 return; 1330 1331 msdc_prepare_data(host, data); 1332 data->host_cookie |= MSDC_ASYNC_FLAG; 1333 } 1334 1335 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 1336 int err) 1337 { 1338 struct msdc_host *host = mmc_priv(mmc); 1339 struct mmc_data *data = mrq->data; 1340 1341 if (!data) 1342 return; 1343 1344 if (data->host_cookie) { 1345 data->host_cookie &= ~MSDC_ASYNC_FLAG; 1346 msdc_unprepare_data(host, data); 1347 } 1348 } 1349 1350 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) 1351 { 1352 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 1353 !mrq->sbc) 1354 msdc_start_command(host, mrq, mrq->stop); 1355 else 1356 msdc_request_done(host, mrq); 1357 } 1358 1359 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 1360 struct mmc_request *mrq, struct mmc_data *data) 1361 { 1362 struct mmc_command *stop; 1363 unsigned long flags; 1364 bool done; 1365 unsigned int check_data = events & 1366 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 1367 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 1368 | MSDC_INT_DMA_PROTECT); 1369 1370 spin_lock_irqsave(&host->lock, flags); 1371 done = !host->data; 1372 if (check_data) 1373 host->data = NULL; 1374 spin_unlock_irqrestore(&host->lock, flags); 1375 1376 if (done) 1377 return true; 1378 stop = data->stop; 1379 1380 if (check_data || (stop && stop->error)) { 1381 dev_dbg(host->dev, "DMA status: 0x%8X\n", 1382 readl(host->base + MSDC_DMA_CFG)); 1383 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 1384 1); 1385 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 1386 cpu_relax(); 1387 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 1388 dev_dbg(host->dev, "DMA stop\n"); 1389 1390 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 1391 data->bytes_xfered = data->blocks * data->blksz; 1392 } else { 1393 dev_dbg(host->dev, "interrupt events: %x\n", events); 1394 msdc_reset_hw(host); 1395 host->error |= REQ_DAT_ERR; 1396 data->bytes_xfered = 0; 1397 1398 if (events & MSDC_INT_DATTMO) 1399 data->error = -ETIMEDOUT; 1400 else if (events & MSDC_INT_DATCRCERR) 1401 data->error = -EILSEQ; 1402 1403 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1404 __func__, mrq->cmd->opcode, data->blocks); 1405 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1406 (int)data->error, data->bytes_xfered); 1407 } 1408 1409 msdc_data_xfer_next(host, mrq); 1410 done = true; 1411 } 1412 return done; 1413 } 1414 1415 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1416 { 1417 u32 val = readl(host->base + SDC_CFG); 1418 1419 val &= ~SDC_CFG_BUSWIDTH; 1420 1421 switch (width) { 1422 default: 1423 case MMC_BUS_WIDTH_1: 1424 val |= (MSDC_BUS_1BITS << 16); 1425 break; 1426 case MMC_BUS_WIDTH_4: 1427 val |= (MSDC_BUS_4BITS << 16); 1428 break; 1429 case MMC_BUS_WIDTH_8: 1430 val |= (MSDC_BUS_8BITS << 16); 1431 break; 1432 } 1433 1434 writel(val, host->base + SDC_CFG); 1435 dev_dbg(host->dev, "Bus Width = %d", width); 1436 } 1437 1438 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1439 { 1440 struct msdc_host *host = mmc_priv(mmc); 1441 int ret; 1442 1443 if (!IS_ERR(mmc->supply.vqmmc)) { 1444 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1445 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1446 dev_err(host->dev, "Unsupported signal voltage!\n"); 1447 return -EINVAL; 1448 } 1449 1450 ret = mmc_regulator_set_vqmmc(mmc, ios); 1451 if (ret < 0) { 1452 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1453 ret, ios->signal_voltage); 1454 return ret; 1455 } 1456 1457 /* Apply different pinctrl settings for different signal voltage */ 1458 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1459 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1460 else 1461 pinctrl_select_state(host->pinctrl, host->pins_default); 1462 } 1463 return 0; 1464 } 1465 1466 static int msdc_card_busy(struct mmc_host *mmc) 1467 { 1468 struct msdc_host *host = mmc_priv(mmc); 1469 u32 status = readl(host->base + MSDC_PS); 1470 1471 /* only check if data0 is low */ 1472 return !(status & BIT(16)); 1473 } 1474 1475 static void msdc_request_timeout(struct work_struct *work) 1476 { 1477 struct msdc_host *host = container_of(work, struct msdc_host, 1478 req_timeout.work); 1479 1480 /* simulate HW timeout status */ 1481 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1482 if (host->mrq) { 1483 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1484 host->mrq, host->mrq->cmd->opcode); 1485 if (host->cmd) { 1486 dev_err(host->dev, "%s: aborting cmd=%d\n", 1487 __func__, host->cmd->opcode); 1488 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1489 host->cmd); 1490 } else if (host->data) { 1491 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1492 __func__, host->mrq->cmd->opcode, 1493 host->data->blocks); 1494 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1495 host->data); 1496 } 1497 } 1498 } 1499 1500 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) 1501 { 1502 if (enb) { 1503 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1504 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1505 if (host->dev_comp->recheck_sdio_irq) 1506 msdc_recheck_sdio_irq(host); 1507 } else { 1508 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); 1509 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1510 } 1511 } 1512 1513 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) 1514 { 1515 unsigned long flags; 1516 struct msdc_host *host = mmc_priv(mmc); 1517 1518 spin_lock_irqsave(&host->lock, flags); 1519 __msdc_enable_sdio_irq(host, enb); 1520 spin_unlock_irqrestore(&host->lock, flags); 1521 1522 if (enb) 1523 pm_runtime_get_noresume(host->dev); 1524 else 1525 pm_runtime_put_noidle(host->dev); 1526 } 1527 1528 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) 1529 { 1530 struct mmc_host *mmc = mmc_from_priv(host); 1531 int cmd_err = 0, dat_err = 0; 1532 1533 if (intsts & MSDC_INT_RSPCRCERR) { 1534 cmd_err = -EILSEQ; 1535 dev_err(host->dev, "%s: CMD CRC ERR", __func__); 1536 } else if (intsts & MSDC_INT_CMDTMO) { 1537 cmd_err = -ETIMEDOUT; 1538 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); 1539 } 1540 1541 if (intsts & MSDC_INT_DATCRCERR) { 1542 dat_err = -EILSEQ; 1543 dev_err(host->dev, "%s: DATA CRC ERR", __func__); 1544 } else if (intsts & MSDC_INT_DATTMO) { 1545 dat_err = -ETIMEDOUT; 1546 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); 1547 } 1548 1549 if (cmd_err || dat_err) { 1550 dev_err(host->dev, "cmd_err = %d, dat_err =%d, intsts = 0x%x", 1551 cmd_err, dat_err, intsts); 1552 } 1553 1554 return cqhci_irq(mmc, 0, cmd_err, dat_err); 1555 } 1556 1557 static irqreturn_t msdc_irq(int irq, void *dev_id) 1558 { 1559 struct msdc_host *host = (struct msdc_host *) dev_id; 1560 struct mmc_host *mmc = mmc_from_priv(host); 1561 1562 while (true) { 1563 struct mmc_request *mrq; 1564 struct mmc_command *cmd; 1565 struct mmc_data *data; 1566 u32 events, event_mask; 1567 1568 spin_lock(&host->lock); 1569 events = readl(host->base + MSDC_INT); 1570 event_mask = readl(host->base + MSDC_INTEN); 1571 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1572 __msdc_enable_sdio_irq(host, 0); 1573 /* clear interrupts */ 1574 writel(events & event_mask, host->base + MSDC_INT); 1575 1576 mrq = host->mrq; 1577 cmd = host->cmd; 1578 data = host->data; 1579 spin_unlock(&host->lock); 1580 1581 if ((events & event_mask) & MSDC_INT_SDIOIRQ) 1582 sdio_signal_irq(mmc); 1583 1584 if ((events & event_mask) & MSDC_INT_CDSC) { 1585 if (host->internal_cd) 1586 mmc_detect_change(mmc, msecs_to_jiffies(20)); 1587 events &= ~MSDC_INT_CDSC; 1588 } 1589 1590 if (!(events & (event_mask & ~MSDC_INT_SDIOIRQ))) 1591 break; 1592 1593 if ((mmc->caps2 & MMC_CAP2_CQE) && 1594 (events & MSDC_INT_CMDQ)) { 1595 msdc_cmdq_irq(host, events); 1596 /* clear interrupts */ 1597 writel(events, host->base + MSDC_INT); 1598 return IRQ_HANDLED; 1599 } 1600 1601 if (!mrq) { 1602 dev_err(host->dev, 1603 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1604 __func__, events, event_mask); 1605 WARN_ON(1); 1606 break; 1607 } 1608 1609 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1610 1611 if (cmd) 1612 msdc_cmd_done(host, events, mrq, cmd); 1613 else if (data) 1614 msdc_data_xfer_done(host, events, mrq, data); 1615 } 1616 1617 return IRQ_HANDLED; 1618 } 1619 1620 static void msdc_init_hw(struct msdc_host *host) 1621 { 1622 u32 val; 1623 u32 tune_reg = host->dev_comp->pad_tune_reg; 1624 1625 if (host->reset) { 1626 reset_control_assert(host->reset); 1627 usleep_range(10, 50); 1628 reset_control_deassert(host->reset); 1629 } 1630 1631 /* Configure to MMC/SD mode, clock free running */ 1632 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1633 1634 /* Reset */ 1635 msdc_reset_hw(host); 1636 1637 /* Disable and clear all interrupts */ 1638 writel(0, host->base + MSDC_INTEN); 1639 val = readl(host->base + MSDC_INT); 1640 writel(val, host->base + MSDC_INT); 1641 1642 /* Configure card detection */ 1643 if (host->internal_cd) { 1644 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, 1645 DEFAULT_DEBOUNCE); 1646 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1647 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1648 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1649 } else { 1650 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1651 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1652 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); 1653 } 1654 1655 if (host->top_base) { 1656 writel(0, host->top_base + EMMC_TOP_CONTROL); 1657 writel(0, host->top_base + EMMC_TOP_CMD); 1658 } else { 1659 writel(0, host->base + tune_reg); 1660 } 1661 writel(0, host->base + MSDC_IOCON); 1662 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1663 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1664 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1665 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); 1666 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1667 1668 if (host->dev_comp->stop_clk_fix) { 1669 sdr_set_field(host->base + MSDC_PATCH_BIT1, 1670 MSDC_PATCH_BIT1_STOP_DLY, 3); 1671 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1672 SDC_FIFO_CFG_WRVALIDSEL); 1673 sdr_clr_bits(host->base + SDC_FIFO_CFG, 1674 SDC_FIFO_CFG_RDVALIDSEL); 1675 } 1676 1677 if (host->dev_comp->busy_check) 1678 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, (1 << 7)); 1679 1680 if (host->dev_comp->async_fifo) { 1681 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1682 MSDC_PB2_RESPWAIT, 3); 1683 if (host->dev_comp->enhance_rx) { 1684 if (host->top_base) 1685 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1686 SDC_RX_ENH_EN); 1687 else 1688 sdr_set_bits(host->base + SDC_ADV_CFG0, 1689 SDC_RX_ENHANCE_EN); 1690 } else { 1691 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1692 MSDC_PB2_RESPSTSENSEL, 2); 1693 sdr_set_field(host->base + MSDC_PATCH_BIT2, 1694 MSDC_PB2_CRCSTSENSEL, 2); 1695 } 1696 /* use async fifo, then no need tune internal delay */ 1697 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, 1698 MSDC_PATCH_BIT2_CFGRESP); 1699 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1700 MSDC_PATCH_BIT2_CFGCRCSTS); 1701 } 1702 1703 if (host->dev_comp->support_64g) 1704 sdr_set_bits(host->base + MSDC_PATCH_BIT2, 1705 MSDC_PB2_SUPPORT_64G); 1706 if (host->dev_comp->data_tune) { 1707 if (host->top_base) { 1708 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1709 PAD_DAT_RD_RXDLY_SEL); 1710 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, 1711 DATA_K_VALUE_SEL); 1712 sdr_set_bits(host->top_base + EMMC_TOP_CMD, 1713 PAD_CMD_RD_RXDLY_SEL); 1714 } else { 1715 sdr_set_bits(host->base + tune_reg, 1716 MSDC_PAD_TUNE_RD_SEL | 1717 MSDC_PAD_TUNE_CMD_SEL); 1718 } 1719 } else { 1720 /* choose clock tune */ 1721 if (host->top_base) 1722 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, 1723 PAD_RXDLY_SEL); 1724 else 1725 sdr_set_bits(host->base + tune_reg, 1726 MSDC_PAD_TUNE_RXDLYSEL); 1727 } 1728 1729 /* Configure to enable SDIO mode. 1730 * it's must otherwise sdio cmd5 failed 1731 */ 1732 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1733 1734 /* Config SDIO device detect interrupt function */ 1735 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1736 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); 1737 1738 /* Configure to default data timeout */ 1739 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1740 1741 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1742 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1743 if (host->top_base) { 1744 host->def_tune_para.emmc_top_control = 1745 readl(host->top_base + EMMC_TOP_CONTROL); 1746 host->def_tune_para.emmc_top_cmd = 1747 readl(host->top_base + EMMC_TOP_CMD); 1748 host->saved_tune_para.emmc_top_control = 1749 readl(host->top_base + EMMC_TOP_CONTROL); 1750 host->saved_tune_para.emmc_top_cmd = 1751 readl(host->top_base + EMMC_TOP_CMD); 1752 } else { 1753 host->def_tune_para.pad_tune = readl(host->base + tune_reg); 1754 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 1755 } 1756 dev_dbg(host->dev, "init hardware done!"); 1757 } 1758 1759 static void msdc_deinit_hw(struct msdc_host *host) 1760 { 1761 u32 val; 1762 1763 if (host->internal_cd) { 1764 /* Disabled card-detect */ 1765 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1766 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); 1767 } 1768 1769 /* Disable and clear all interrupts */ 1770 writel(0, host->base + MSDC_INTEN); 1771 1772 val = readl(host->base + MSDC_INT); 1773 writel(val, host->base + MSDC_INT); 1774 } 1775 1776 /* init gpd and bd list in msdc_drv_probe */ 1777 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1778 { 1779 struct mt_gpdma_desc *gpd = dma->gpd; 1780 struct mt_bdma_desc *bd = dma->bd; 1781 dma_addr_t dma_addr; 1782 int i; 1783 1784 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1785 1786 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1787 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1788 /* gpd->next is must set for desc DMA 1789 * That's why must alloc 2 gpd structure. 1790 */ 1791 gpd->next = lower_32_bits(dma_addr); 1792 if (host->dev_comp->support_64g) 1793 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1794 1795 dma_addr = dma->bd_addr; 1796 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ 1797 if (host->dev_comp->support_64g) 1798 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; 1799 1800 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1801 for (i = 0; i < (MAX_BD_NUM - 1); i++) { 1802 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); 1803 bd[i].next = lower_32_bits(dma_addr); 1804 if (host->dev_comp->support_64g) 1805 bd[i].bd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; 1806 } 1807 } 1808 1809 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1810 { 1811 struct msdc_host *host = mmc_priv(mmc); 1812 int ret; 1813 1814 msdc_set_buswidth(host, ios->bus_width); 1815 1816 /* Suspend/Resume will do power off/on */ 1817 switch (ios->power_mode) { 1818 case MMC_POWER_UP: 1819 if (!IS_ERR(mmc->supply.vmmc)) { 1820 msdc_init_hw(host); 1821 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1822 ios->vdd); 1823 if (ret) { 1824 dev_err(host->dev, "Failed to set vmmc power!\n"); 1825 return; 1826 } 1827 } 1828 break; 1829 case MMC_POWER_ON: 1830 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1831 ret = regulator_enable(mmc->supply.vqmmc); 1832 if (ret) 1833 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1834 else 1835 host->vqmmc_enabled = true; 1836 } 1837 break; 1838 case MMC_POWER_OFF: 1839 if (!IS_ERR(mmc->supply.vmmc)) 1840 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1841 1842 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1843 regulator_disable(mmc->supply.vqmmc); 1844 host->vqmmc_enabled = false; 1845 } 1846 break; 1847 default: 1848 break; 1849 } 1850 1851 if (host->mclk != ios->clock || host->timing != ios->timing) 1852 msdc_set_mclk(host, ios->timing, ios->clock); 1853 } 1854 1855 static u32 test_delay_bit(u32 delay, u32 bit) 1856 { 1857 bit %= PAD_DELAY_MAX; 1858 return delay & (1 << bit); 1859 } 1860 1861 static int get_delay_len(u32 delay, u32 start_bit) 1862 { 1863 int i; 1864 1865 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1866 if (test_delay_bit(delay, start_bit + i) == 0) 1867 return i; 1868 } 1869 return PAD_DELAY_MAX - start_bit; 1870 } 1871 1872 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1873 { 1874 int start = 0, len = 0; 1875 int start_final = 0, len_final = 0; 1876 u8 final_phase = 0xff; 1877 struct msdc_delay_phase delay_phase = { 0, }; 1878 1879 if (delay == 0) { 1880 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1881 delay_phase.final_phase = final_phase; 1882 return delay_phase; 1883 } 1884 1885 while (start < PAD_DELAY_MAX) { 1886 len = get_delay_len(delay, start); 1887 if (len_final < len) { 1888 start_final = start; 1889 len_final = len; 1890 } 1891 start += len ? len : 1; 1892 if (len >= 12 && start_final < 4) 1893 break; 1894 } 1895 1896 /* The rule is that to find the smallest delay cell */ 1897 if (start_final == 0) 1898 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1899 else 1900 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1901 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1902 delay, len_final, final_phase); 1903 1904 delay_phase.maxlen = len_final; 1905 delay_phase.start = start_final; 1906 delay_phase.final_phase = final_phase; 1907 return delay_phase; 1908 } 1909 1910 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) 1911 { 1912 u32 tune_reg = host->dev_comp->pad_tune_reg; 1913 1914 if (host->top_base) 1915 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, 1916 value); 1917 else 1918 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, 1919 value); 1920 } 1921 1922 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) 1923 { 1924 u32 tune_reg = host->dev_comp->pad_tune_reg; 1925 1926 if (host->top_base) 1927 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, 1928 PAD_DAT_RD_RXDLY, value); 1929 else 1930 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, 1931 value); 1932 } 1933 1934 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1935 { 1936 struct msdc_host *host = mmc_priv(mmc); 1937 u32 rise_delay = 0, fall_delay = 0; 1938 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1939 struct msdc_delay_phase internal_delay_phase; 1940 u8 final_delay, final_maxlen; 1941 u32 internal_delay = 0; 1942 u32 tune_reg = host->dev_comp->pad_tune_reg; 1943 int cmd_err; 1944 int i, j; 1945 1946 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 1947 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 1948 sdr_set_field(host->base + tune_reg, 1949 MSDC_PAD_TUNE_CMDRRDLY, 1950 host->hs200_cmd_int_delay); 1951 1952 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1953 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1954 msdc_set_cmd_delay(host, i); 1955 /* 1956 * Using the same parameters, it may sometimes pass the test, 1957 * but sometimes it may fail. To make sure the parameters are 1958 * more stable, we test each set of parameters 3 times. 1959 */ 1960 for (j = 0; j < 3; j++) { 1961 mmc_send_tuning(mmc, opcode, &cmd_err); 1962 if (!cmd_err) { 1963 rise_delay |= (1 << i); 1964 } else { 1965 rise_delay &= ~(1 << i); 1966 break; 1967 } 1968 } 1969 } 1970 final_rise_delay = get_best_delay(host, rise_delay); 1971 /* if rising edge has enough margin, then do not scan falling edge */ 1972 if (final_rise_delay.maxlen >= 12 || 1973 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1974 goto skip_fall; 1975 1976 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1977 for (i = 0; i < PAD_DELAY_MAX; i++) { 1978 msdc_set_cmd_delay(host, i); 1979 /* 1980 * Using the same parameters, it may sometimes pass the test, 1981 * but sometimes it may fail. To make sure the parameters are 1982 * more stable, we test each set of parameters 3 times. 1983 */ 1984 for (j = 0; j < 3; j++) { 1985 mmc_send_tuning(mmc, opcode, &cmd_err); 1986 if (!cmd_err) { 1987 fall_delay |= (1 << i); 1988 } else { 1989 fall_delay &= ~(1 << i); 1990 break; 1991 } 1992 } 1993 } 1994 final_fall_delay = get_best_delay(host, fall_delay); 1995 1996 skip_fall: 1997 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1998 if (final_fall_delay.maxlen >= 12 && final_fall_delay.start < 4) 1999 final_maxlen = final_fall_delay.maxlen; 2000 if (final_maxlen == final_rise_delay.maxlen) { 2001 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2002 final_delay = final_rise_delay.final_phase; 2003 } else { 2004 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2005 final_delay = final_fall_delay.final_phase; 2006 } 2007 msdc_set_cmd_delay(host, final_delay); 2008 2009 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) 2010 goto skip_internal; 2011 2012 for (i = 0; i < PAD_DELAY_MAX; i++) { 2013 sdr_set_field(host->base + tune_reg, 2014 MSDC_PAD_TUNE_CMDRRDLY, i); 2015 mmc_send_tuning(mmc, opcode, &cmd_err); 2016 if (!cmd_err) 2017 internal_delay |= (1 << i); 2018 } 2019 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); 2020 internal_delay_phase = get_best_delay(host, internal_delay); 2021 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, 2022 internal_delay_phase.final_phase); 2023 skip_internal: 2024 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2025 return final_delay == 0xff ? -EIO : 0; 2026 } 2027 2028 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) 2029 { 2030 struct msdc_host *host = mmc_priv(mmc); 2031 u32 cmd_delay = 0; 2032 struct msdc_delay_phase final_cmd_delay = { 0,}; 2033 u8 final_delay; 2034 int cmd_err; 2035 int i, j; 2036 2037 /* select EMMC50 PAD CMD tune */ 2038 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); 2039 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); 2040 2041 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || 2042 mmc->ios.timing == MMC_TIMING_UHS_SDR104) 2043 sdr_set_field(host->base + MSDC_PAD_TUNE, 2044 MSDC_PAD_TUNE_CMDRRDLY, 2045 host->hs200_cmd_int_delay); 2046 2047 if (host->hs400_cmd_resp_sel_rising) 2048 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2049 else 2050 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2051 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2052 sdr_set_field(host->base + PAD_CMD_TUNE, 2053 PAD_CMD_TUNE_RX_DLY3, i); 2054 /* 2055 * Using the same parameters, it may sometimes pass the test, 2056 * but sometimes it may fail. To make sure the parameters are 2057 * more stable, we test each set of parameters 3 times. 2058 */ 2059 for (j = 0; j < 3; j++) { 2060 mmc_send_tuning(mmc, opcode, &cmd_err); 2061 if (!cmd_err) { 2062 cmd_delay |= (1 << i); 2063 } else { 2064 cmd_delay &= ~(1 << i); 2065 break; 2066 } 2067 } 2068 } 2069 final_cmd_delay = get_best_delay(host, cmd_delay); 2070 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, 2071 final_cmd_delay.final_phase); 2072 final_delay = final_cmd_delay.final_phase; 2073 2074 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); 2075 return final_delay == 0xff ? -EIO : 0; 2076 } 2077 2078 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 2079 { 2080 struct msdc_host *host = mmc_priv(mmc); 2081 u32 rise_delay = 0, fall_delay = 0; 2082 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2083 u8 final_delay, final_maxlen; 2084 int i, ret; 2085 2086 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2087 host->latch_ck); 2088 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2089 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2090 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2091 msdc_set_data_delay(host, i); 2092 ret = mmc_send_tuning(mmc, opcode, NULL); 2093 if (!ret) 2094 rise_delay |= (1 << i); 2095 } 2096 final_rise_delay = get_best_delay(host, rise_delay); 2097 /* if rising edge has enough margin, then do not scan falling edge */ 2098 if (final_rise_delay.maxlen >= 12 || 2099 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2100 goto skip_fall; 2101 2102 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2103 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2104 for (i = 0; i < PAD_DELAY_MAX; i++) { 2105 msdc_set_data_delay(host, i); 2106 ret = mmc_send_tuning(mmc, opcode, NULL); 2107 if (!ret) 2108 fall_delay |= (1 << i); 2109 } 2110 final_fall_delay = get_best_delay(host, fall_delay); 2111 2112 skip_fall: 2113 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2114 if (final_maxlen == final_rise_delay.maxlen) { 2115 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2116 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2117 final_delay = final_rise_delay.final_phase; 2118 } else { 2119 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 2120 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 2121 final_delay = final_fall_delay.final_phase; 2122 } 2123 msdc_set_data_delay(host, final_delay); 2124 2125 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); 2126 return final_delay == 0xff ? -EIO : 0; 2127 } 2128 2129 /* 2130 * MSDC IP which supports data tune + async fifo can do CMD/DAT tune 2131 * together, which can save the tuning time. 2132 */ 2133 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) 2134 { 2135 struct msdc_host *host = mmc_priv(mmc); 2136 u32 rise_delay = 0, fall_delay = 0; 2137 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 2138 u8 final_delay, final_maxlen; 2139 int i, ret; 2140 2141 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, 2142 host->latch_ck); 2143 2144 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2145 sdr_clr_bits(host->base + MSDC_IOCON, 2146 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2147 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 2148 msdc_set_cmd_delay(host, i); 2149 msdc_set_data_delay(host, i); 2150 ret = mmc_send_tuning(mmc, opcode, NULL); 2151 if (!ret) 2152 rise_delay |= (1 << i); 2153 } 2154 final_rise_delay = get_best_delay(host, rise_delay); 2155 /* if rising edge has enough margin, then do not scan falling edge */ 2156 if (final_rise_delay.maxlen >= 12 || 2157 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 2158 goto skip_fall; 2159 2160 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2161 sdr_set_bits(host->base + MSDC_IOCON, 2162 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2163 for (i = 0; i < PAD_DELAY_MAX; i++) { 2164 msdc_set_cmd_delay(host, i); 2165 msdc_set_data_delay(host, i); 2166 ret = mmc_send_tuning(mmc, opcode, NULL); 2167 if (!ret) 2168 fall_delay |= (1 << i); 2169 } 2170 final_fall_delay = get_best_delay(host, fall_delay); 2171 2172 skip_fall: 2173 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 2174 if (final_maxlen == final_rise_delay.maxlen) { 2175 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2176 sdr_clr_bits(host->base + MSDC_IOCON, 2177 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2178 final_delay = final_rise_delay.final_phase; 2179 } else { 2180 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 2181 sdr_set_bits(host->base + MSDC_IOCON, 2182 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2183 final_delay = final_fall_delay.final_phase; 2184 } 2185 2186 msdc_set_cmd_delay(host, final_delay); 2187 msdc_set_data_delay(host, final_delay); 2188 2189 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); 2190 return final_delay == 0xff ? -EIO : 0; 2191 } 2192 2193 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 2194 { 2195 struct msdc_host *host = mmc_priv(mmc); 2196 int ret; 2197 u32 tune_reg = host->dev_comp->pad_tune_reg; 2198 2199 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { 2200 ret = msdc_tune_together(mmc, opcode); 2201 if (host->hs400_mode) { 2202 sdr_clr_bits(host->base + MSDC_IOCON, 2203 MSDC_IOCON_DSPL | MSDC_IOCON_W_DSPL); 2204 msdc_set_data_delay(host, 0); 2205 } 2206 goto tune_done; 2207 } 2208 if (host->hs400_mode && 2209 host->dev_comp->hs400_tune) 2210 ret = hs400_tune_response(mmc, opcode); 2211 else 2212 ret = msdc_tune_response(mmc, opcode); 2213 if (ret == -EIO) { 2214 dev_err(host->dev, "Tune response fail!\n"); 2215 return ret; 2216 } 2217 if (host->hs400_mode == false) { 2218 ret = msdc_tune_data(mmc, opcode); 2219 if (ret == -EIO) 2220 dev_err(host->dev, "Tune data fail!\n"); 2221 } 2222 2223 tune_done: 2224 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 2225 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); 2226 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2227 if (host->top_base) { 2228 host->saved_tune_para.emmc_top_control = readl(host->top_base + 2229 EMMC_TOP_CONTROL); 2230 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + 2231 EMMC_TOP_CMD); 2232 } 2233 return ret; 2234 } 2235 2236 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 2237 { 2238 struct msdc_host *host = mmc_priv(mmc); 2239 host->hs400_mode = true; 2240 2241 if (host->top_base) 2242 writel(host->hs400_ds_delay, 2243 host->top_base + EMMC50_PAD_DS_TUNE); 2244 else 2245 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 2246 /* hs400 mode must set it to 0 */ 2247 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); 2248 /* to improve read performance, set outstanding to 2 */ 2249 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); 2250 2251 return 0; 2252 } 2253 2254 static void msdc_hw_reset(struct mmc_host *mmc) 2255 { 2256 struct msdc_host *host = mmc_priv(mmc); 2257 2258 sdr_set_bits(host->base + EMMC_IOCON, 1); 2259 udelay(10); /* 10us is enough */ 2260 sdr_clr_bits(host->base + EMMC_IOCON, 1); 2261 } 2262 2263 static void msdc_ack_sdio_irq(struct mmc_host *mmc) 2264 { 2265 unsigned long flags; 2266 struct msdc_host *host = mmc_priv(mmc); 2267 2268 spin_lock_irqsave(&host->lock, flags); 2269 __msdc_enable_sdio_irq(host, 1); 2270 spin_unlock_irqrestore(&host->lock, flags); 2271 } 2272 2273 static int msdc_get_cd(struct mmc_host *mmc) 2274 { 2275 struct msdc_host *host = mmc_priv(mmc); 2276 int val; 2277 2278 if (mmc->caps & MMC_CAP_NONREMOVABLE) 2279 return 1; 2280 2281 if (!host->internal_cd) 2282 return mmc_gpio_get_cd(mmc); 2283 2284 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; 2285 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) 2286 return !!val; 2287 else 2288 return !val; 2289 } 2290 2291 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, 2292 struct mmc_ios *ios) 2293 { 2294 struct msdc_host *host = mmc_priv(mmc); 2295 2296 if (ios->enhanced_strobe) { 2297 msdc_prepare_hs400_tuning(mmc, ios); 2298 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); 2299 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); 2300 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); 2301 2302 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2303 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2304 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); 2305 } else { 2306 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); 2307 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); 2308 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); 2309 2310 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); 2311 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); 2312 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); 2313 } 2314 } 2315 2316 static void msdc_cqe_enable(struct mmc_host *mmc) 2317 { 2318 struct msdc_host *host = mmc_priv(mmc); 2319 2320 /* enable cmdq irq */ 2321 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); 2322 /* enable busy check */ 2323 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2324 /* default write data / busy timeout 20s */ 2325 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); 2326 /* default read data timeout 1s */ 2327 msdc_set_timeout(host, 1000000000ULL, 0); 2328 } 2329 2330 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) 2331 { 2332 struct msdc_host *host = mmc_priv(mmc); 2333 2334 /* disable cmdq irq */ 2335 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); 2336 /* disable busy check */ 2337 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); 2338 2339 if (recovery) { 2340 sdr_set_field(host->base + MSDC_DMA_CTRL, 2341 MSDC_DMA_CTRL_STOP, 1); 2342 msdc_reset_hw(host); 2343 } 2344 } 2345 2346 static void msdc_cqe_pre_enable(struct mmc_host *mmc) 2347 { 2348 struct cqhci_host *cq_host = mmc->cqe_private; 2349 u32 reg; 2350 2351 reg = cqhci_readl(cq_host, CQHCI_CFG); 2352 reg |= CQHCI_ENABLE; 2353 cqhci_writel(cq_host, reg, CQHCI_CFG); 2354 } 2355 2356 static void msdc_cqe_post_disable(struct mmc_host *mmc) 2357 { 2358 struct cqhci_host *cq_host = mmc->cqe_private; 2359 u32 reg; 2360 2361 reg = cqhci_readl(cq_host, CQHCI_CFG); 2362 reg &= ~CQHCI_ENABLE; 2363 cqhci_writel(cq_host, reg, CQHCI_CFG); 2364 } 2365 2366 static const struct mmc_host_ops mt_msdc_ops = { 2367 .post_req = msdc_post_req, 2368 .pre_req = msdc_pre_req, 2369 .request = msdc_ops_request, 2370 .set_ios = msdc_ops_set_ios, 2371 .get_ro = mmc_gpio_get_ro, 2372 .get_cd = msdc_get_cd, 2373 .hs400_enhanced_strobe = msdc_hs400_enhanced_strobe, 2374 .enable_sdio_irq = msdc_enable_sdio_irq, 2375 .ack_sdio_irq = msdc_ack_sdio_irq, 2376 .start_signal_voltage_switch = msdc_ops_switch_volt, 2377 .card_busy = msdc_card_busy, 2378 .execute_tuning = msdc_execute_tuning, 2379 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 2380 .hw_reset = msdc_hw_reset, 2381 }; 2382 2383 static const struct cqhci_host_ops msdc_cmdq_ops = { 2384 .enable = msdc_cqe_enable, 2385 .disable = msdc_cqe_disable, 2386 .pre_enable = msdc_cqe_pre_enable, 2387 .post_disable = msdc_cqe_post_disable, 2388 }; 2389 2390 static void msdc_of_property_parse(struct platform_device *pdev, 2391 struct msdc_host *host) 2392 { 2393 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", 2394 &host->latch_ck); 2395 2396 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 2397 &host->hs400_ds_delay); 2398 2399 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", 2400 &host->hs200_cmd_int_delay); 2401 2402 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", 2403 &host->hs400_cmd_int_delay); 2404 2405 if (of_property_read_bool(pdev->dev.of_node, 2406 "mediatek,hs400-cmd-resp-sel-rising")) 2407 host->hs400_cmd_resp_sel_rising = true; 2408 else 2409 host->hs400_cmd_resp_sel_rising = false; 2410 2411 if (of_property_read_bool(pdev->dev.of_node, 2412 "supports-cqe")) 2413 host->cqhci = true; 2414 else 2415 host->cqhci = false; 2416 } 2417 2418 static int msdc_of_clock_parse(struct platform_device *pdev, 2419 struct msdc_host *host) 2420 { 2421 int ret; 2422 2423 host->src_clk = devm_clk_get(&pdev->dev, "source"); 2424 if (IS_ERR(host->src_clk)) 2425 return PTR_ERR(host->src_clk); 2426 2427 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 2428 if (IS_ERR(host->h_clk)) 2429 return PTR_ERR(host->h_clk); 2430 2431 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); 2432 if (IS_ERR(host->bus_clk)) 2433 host->bus_clk = NULL; 2434 2435 /*source clock control gate is optional clock*/ 2436 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); 2437 if (IS_ERR(host->src_clk_cg)) 2438 host->src_clk_cg = NULL; 2439 2440 host->sys_clk_cg = devm_clk_get_optional(&pdev->dev, "sys_cg"); 2441 if (IS_ERR(host->sys_clk_cg)) 2442 host->sys_clk_cg = NULL; 2443 2444 /* If present, always enable for this clock gate */ 2445 clk_prepare_enable(host->sys_clk_cg); 2446 2447 host->bulk_clks[0].id = "pclk_cg"; 2448 host->bulk_clks[1].id = "axi_cg"; 2449 host->bulk_clks[2].id = "ahb_cg"; 2450 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, 2451 host->bulk_clks); 2452 if (ret) { 2453 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); 2454 return ret; 2455 } 2456 2457 return 0; 2458 } 2459 2460 static int msdc_drv_probe(struct platform_device *pdev) 2461 { 2462 struct mmc_host *mmc; 2463 struct msdc_host *host; 2464 struct resource *res; 2465 int ret; 2466 2467 if (!pdev->dev.of_node) { 2468 dev_err(&pdev->dev, "No DT found\n"); 2469 return -EINVAL; 2470 } 2471 2472 /* Allocate MMC host for this device */ 2473 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 2474 if (!mmc) 2475 return -ENOMEM; 2476 2477 host = mmc_priv(mmc); 2478 ret = mmc_of_parse(mmc); 2479 if (ret) 2480 goto host_free; 2481 2482 host->base = devm_platform_ioremap_resource(pdev, 0); 2483 if (IS_ERR(host->base)) { 2484 ret = PTR_ERR(host->base); 2485 goto host_free; 2486 } 2487 2488 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 2489 if (res) { 2490 host->top_base = devm_ioremap_resource(&pdev->dev, res); 2491 if (IS_ERR(host->top_base)) 2492 host->top_base = NULL; 2493 } 2494 2495 ret = mmc_regulator_get_supply(mmc); 2496 if (ret) 2497 goto host_free; 2498 2499 ret = msdc_of_clock_parse(pdev, host); 2500 if (ret) 2501 goto host_free; 2502 2503 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 2504 "hrst"); 2505 if (IS_ERR(host->reset)) { 2506 ret = PTR_ERR(host->reset); 2507 goto host_free; 2508 } 2509 2510 host->irq = platform_get_irq(pdev, 0); 2511 if (host->irq < 0) { 2512 ret = -EINVAL; 2513 goto host_free; 2514 } 2515 2516 host->pinctrl = devm_pinctrl_get(&pdev->dev); 2517 if (IS_ERR(host->pinctrl)) { 2518 ret = PTR_ERR(host->pinctrl); 2519 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 2520 goto host_free; 2521 } 2522 2523 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 2524 if (IS_ERR(host->pins_default)) { 2525 ret = PTR_ERR(host->pins_default); 2526 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 2527 goto host_free; 2528 } 2529 2530 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 2531 if (IS_ERR(host->pins_uhs)) { 2532 ret = PTR_ERR(host->pins_uhs); 2533 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 2534 goto host_free; 2535 } 2536 2537 msdc_of_property_parse(pdev, host); 2538 2539 host->dev = &pdev->dev; 2540 host->dev_comp = of_device_get_match_data(&pdev->dev); 2541 host->src_clk_freq = clk_get_rate(host->src_clk); 2542 /* Set host parameters to mmc */ 2543 mmc->ops = &mt_msdc_ops; 2544 if (host->dev_comp->clk_div_bits == 8) 2545 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); 2546 else 2547 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); 2548 2549 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && 2550 !mmc_can_gpio_cd(mmc) && 2551 host->dev_comp->use_internal_cd) { 2552 /* 2553 * Is removable but no GPIO declared, so 2554 * use internal functionality. 2555 */ 2556 host->internal_cd = true; 2557 } 2558 2559 if (mmc->caps & MMC_CAP_SDIO_IRQ) 2560 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; 2561 2562 mmc->caps |= MMC_CAP_CMD23; 2563 if (host->cqhci) 2564 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; 2565 /* MMC core transfer sizes tunable parameters */ 2566 mmc->max_segs = MAX_BD_NUM; 2567 if (host->dev_comp->support_64g) 2568 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; 2569 else 2570 mmc->max_seg_size = BDMA_DESC_BUFLEN; 2571 mmc->max_blk_size = 2048; 2572 mmc->max_req_size = 512 * 1024; 2573 mmc->max_blk_count = mmc->max_req_size / 512; 2574 if (host->dev_comp->support_64g) 2575 host->dma_mask = DMA_BIT_MASK(36); 2576 else 2577 host->dma_mask = DMA_BIT_MASK(32); 2578 mmc_dev(mmc)->dma_mask = &host->dma_mask; 2579 2580 if (mmc->caps2 & MMC_CAP2_CQE) { 2581 host->cq_host = devm_kzalloc(mmc->parent, 2582 sizeof(*host->cq_host), 2583 GFP_KERNEL); 2584 if (!host->cq_host) { 2585 ret = -ENOMEM; 2586 goto host_free; 2587 } 2588 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 2589 host->cq_host->mmio = host->base + 0x800; 2590 host->cq_host->ops = &msdc_cmdq_ops; 2591 ret = cqhci_init(host->cq_host, mmc, true); 2592 if (ret) 2593 goto host_free; 2594 mmc->max_segs = 128; 2595 /* cqhci 16bit length */ 2596 /* 0 size, means 65536 so we don't have to -1 here */ 2597 mmc->max_seg_size = 64 * 1024; 2598 } 2599 2600 host->timeout_clks = 3 * 1048576; 2601 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 2602 2 * sizeof(struct mt_gpdma_desc), 2603 &host->dma.gpd_addr, GFP_KERNEL); 2604 host->dma.bd = dma_alloc_coherent(&pdev->dev, 2605 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2606 &host->dma.bd_addr, GFP_KERNEL); 2607 if (!host->dma.gpd || !host->dma.bd) { 2608 ret = -ENOMEM; 2609 goto release_mem; 2610 } 2611 msdc_init_gpd_bd(host, &host->dma); 2612 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 2613 spin_lock_init(&host->lock); 2614 2615 platform_set_drvdata(pdev, mmc); 2616 msdc_ungate_clock(host); 2617 msdc_init_hw(host); 2618 2619 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 2620 IRQF_TRIGGER_NONE, pdev->name, host); 2621 if (ret) 2622 goto release; 2623 2624 pm_runtime_set_active(host->dev); 2625 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 2626 pm_runtime_use_autosuspend(host->dev); 2627 pm_runtime_enable(host->dev); 2628 ret = mmc_add_host(mmc); 2629 2630 if (ret) 2631 goto end; 2632 2633 return 0; 2634 end: 2635 pm_runtime_disable(host->dev); 2636 release: 2637 platform_set_drvdata(pdev, NULL); 2638 msdc_deinit_hw(host); 2639 msdc_gate_clock(host); 2640 release_mem: 2641 if (host->dma.gpd) 2642 dma_free_coherent(&pdev->dev, 2643 2 * sizeof(struct mt_gpdma_desc), 2644 host->dma.gpd, host->dma.gpd_addr); 2645 if (host->dma.bd) 2646 dma_free_coherent(&pdev->dev, 2647 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2648 host->dma.bd, host->dma.bd_addr); 2649 host_free: 2650 mmc_free_host(mmc); 2651 2652 return ret; 2653 } 2654 2655 static int msdc_drv_remove(struct platform_device *pdev) 2656 { 2657 struct mmc_host *mmc; 2658 struct msdc_host *host; 2659 2660 mmc = platform_get_drvdata(pdev); 2661 host = mmc_priv(mmc); 2662 2663 pm_runtime_get_sync(host->dev); 2664 2665 platform_set_drvdata(pdev, NULL); 2666 mmc_remove_host(mmc); 2667 msdc_deinit_hw(host); 2668 msdc_gate_clock(host); 2669 2670 pm_runtime_disable(host->dev); 2671 pm_runtime_put_noidle(host->dev); 2672 dma_free_coherent(&pdev->dev, 2673 2 * sizeof(struct mt_gpdma_desc), 2674 host->dma.gpd, host->dma.gpd_addr); 2675 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 2676 host->dma.bd, host->dma.bd_addr); 2677 2678 mmc_free_host(mmc); 2679 2680 return 0; 2681 } 2682 2683 static void msdc_save_reg(struct msdc_host *host) 2684 { 2685 u32 tune_reg = host->dev_comp->pad_tune_reg; 2686 2687 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 2688 host->save_para.iocon = readl(host->base + MSDC_IOCON); 2689 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 2690 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 2691 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 2692 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); 2693 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 2694 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); 2695 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 2696 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); 2697 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); 2698 if (host->top_base) { 2699 host->save_para.emmc_top_control = 2700 readl(host->top_base + EMMC_TOP_CONTROL); 2701 host->save_para.emmc_top_cmd = 2702 readl(host->top_base + EMMC_TOP_CMD); 2703 host->save_para.emmc50_pad_ds_tune = 2704 readl(host->top_base + EMMC50_PAD_DS_TUNE); 2705 } else { 2706 host->save_para.pad_tune = readl(host->base + tune_reg); 2707 } 2708 } 2709 2710 static void msdc_restore_reg(struct msdc_host *host) 2711 { 2712 struct mmc_host *mmc = mmc_from_priv(host); 2713 u32 tune_reg = host->dev_comp->pad_tune_reg; 2714 2715 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 2716 writel(host->save_para.iocon, host->base + MSDC_IOCON); 2717 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 2718 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 2719 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 2720 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); 2721 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 2722 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); 2723 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 2724 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); 2725 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); 2726 if (host->top_base) { 2727 writel(host->save_para.emmc_top_control, 2728 host->top_base + EMMC_TOP_CONTROL); 2729 writel(host->save_para.emmc_top_cmd, 2730 host->top_base + EMMC_TOP_CMD); 2731 writel(host->save_para.emmc50_pad_ds_tune, 2732 host->top_base + EMMC50_PAD_DS_TUNE); 2733 } else { 2734 writel(host->save_para.pad_tune, host->base + tune_reg); 2735 } 2736 2737 if (sdio_irq_claimed(mmc)) 2738 __msdc_enable_sdio_irq(host, 1); 2739 } 2740 2741 static int __maybe_unused msdc_runtime_suspend(struct device *dev) 2742 { 2743 struct mmc_host *mmc = dev_get_drvdata(dev); 2744 struct msdc_host *host = mmc_priv(mmc); 2745 2746 msdc_save_reg(host); 2747 msdc_gate_clock(host); 2748 return 0; 2749 } 2750 2751 static int __maybe_unused msdc_runtime_resume(struct device *dev) 2752 { 2753 struct mmc_host *mmc = dev_get_drvdata(dev); 2754 struct msdc_host *host = mmc_priv(mmc); 2755 2756 msdc_ungate_clock(host); 2757 msdc_restore_reg(host); 2758 return 0; 2759 } 2760 2761 static int __maybe_unused msdc_suspend(struct device *dev) 2762 { 2763 struct mmc_host *mmc = dev_get_drvdata(dev); 2764 int ret; 2765 2766 if (mmc->caps2 & MMC_CAP2_CQE) { 2767 ret = cqhci_suspend(mmc); 2768 if (ret) 2769 return ret; 2770 } 2771 2772 return pm_runtime_force_suspend(dev); 2773 } 2774 2775 static int __maybe_unused msdc_resume(struct device *dev) 2776 { 2777 return pm_runtime_force_resume(dev); 2778 } 2779 2780 static const struct dev_pm_ops msdc_dev_pm_ops = { 2781 SET_SYSTEM_SLEEP_PM_OPS(msdc_suspend, msdc_resume) 2782 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 2783 }; 2784 2785 static struct platform_driver mt_msdc_driver = { 2786 .probe = msdc_drv_probe, 2787 .remove = msdc_drv_remove, 2788 .driver = { 2789 .name = "mtk-msdc", 2790 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 2791 .of_match_table = msdc_of_ids, 2792 .pm = &msdc_dev_pm_ops, 2793 }, 2794 }; 2795 2796 module_platform_driver(mt_msdc_driver); 2797 MODULE_LICENSE("GPL v2"); 2798 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 2799