1 /* 2 * Copyright (c) 2014-2015 MediaTek Inc. 3 * Author: Chaotian.Jing <chaotian.jing@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 15 #include <linux/module.h> 16 #include <linux/clk.h> 17 #include <linux/delay.h> 18 #include <linux/dma-mapping.h> 19 #include <linux/ioport.h> 20 #include <linux/irq.h> 21 #include <linux/of_address.h> 22 #include <linux/of_irq.h> 23 #include <linux/of_gpio.h> 24 #include <linux/pinctrl/consumer.h> 25 #include <linux/platform_device.h> 26 #include <linux/pm.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/regulator/consumer.h> 29 #include <linux/slab.h> 30 #include <linux/spinlock.h> 31 32 #include <linux/mmc/card.h> 33 #include <linux/mmc/core.h> 34 #include <linux/mmc/host.h> 35 #include <linux/mmc/mmc.h> 36 #include <linux/mmc/sd.h> 37 #include <linux/mmc/sdio.h> 38 #include <linux/mmc/slot-gpio.h> 39 40 #define MAX_BD_NUM 1024 41 42 /*--------------------------------------------------------------------------*/ 43 /* Common Definition */ 44 /*--------------------------------------------------------------------------*/ 45 #define MSDC_BUS_1BITS 0x0 46 #define MSDC_BUS_4BITS 0x1 47 #define MSDC_BUS_8BITS 0x2 48 49 #define MSDC_BURST_64B 0x6 50 51 /*--------------------------------------------------------------------------*/ 52 /* Register Offset */ 53 /*--------------------------------------------------------------------------*/ 54 #define MSDC_CFG 0x0 55 #define MSDC_IOCON 0x04 56 #define MSDC_PS 0x08 57 #define MSDC_INT 0x0c 58 #define MSDC_INTEN 0x10 59 #define MSDC_FIFOCS 0x14 60 #define SDC_CFG 0x30 61 #define SDC_CMD 0x34 62 #define SDC_ARG 0x38 63 #define SDC_STS 0x3c 64 #define SDC_RESP0 0x40 65 #define SDC_RESP1 0x44 66 #define SDC_RESP2 0x48 67 #define SDC_RESP3 0x4c 68 #define SDC_BLK_NUM 0x50 69 #define EMMC_IOCON 0x7c 70 #define SDC_ACMD_RESP 0x80 71 #define MSDC_DMA_SA 0x90 72 #define MSDC_DMA_CTRL 0x98 73 #define MSDC_DMA_CFG 0x9c 74 #define MSDC_PATCH_BIT 0xb0 75 #define MSDC_PATCH_BIT1 0xb4 76 #define MSDC_PAD_TUNE 0xec 77 #define PAD_DS_TUNE 0x188 78 #define EMMC50_CFG0 0x208 79 80 /*--------------------------------------------------------------------------*/ 81 /* Register Mask */ 82 /*--------------------------------------------------------------------------*/ 83 84 /* MSDC_CFG mask */ 85 #define MSDC_CFG_MODE (0x1 << 0) /* RW */ 86 #define MSDC_CFG_CKPDN (0x1 << 1) /* RW */ 87 #define MSDC_CFG_RST (0x1 << 2) /* RW */ 88 #define MSDC_CFG_PIO (0x1 << 3) /* RW */ 89 #define MSDC_CFG_CKDRVEN (0x1 << 4) /* RW */ 90 #define MSDC_CFG_BV18SDT (0x1 << 5) /* RW */ 91 #define MSDC_CFG_BV18PSS (0x1 << 6) /* R */ 92 #define MSDC_CFG_CKSTB (0x1 << 7) /* R */ 93 #define MSDC_CFG_CKDIV (0xff << 8) /* RW */ 94 #define MSDC_CFG_CKMOD (0x3 << 16) /* RW */ 95 #define MSDC_CFG_HS400_CK_MODE (0x1 << 18) /* RW */ 96 97 /* MSDC_IOCON mask */ 98 #define MSDC_IOCON_SDR104CKS (0x1 << 0) /* RW */ 99 #define MSDC_IOCON_RSPL (0x1 << 1) /* RW */ 100 #define MSDC_IOCON_DSPL (0x1 << 2) /* RW */ 101 #define MSDC_IOCON_DDLSEL (0x1 << 3) /* RW */ 102 #define MSDC_IOCON_DDR50CKD (0x1 << 4) /* RW */ 103 #define MSDC_IOCON_DSPLSEL (0x1 << 5) /* RW */ 104 #define MSDC_IOCON_W_DSPL (0x1 << 8) /* RW */ 105 #define MSDC_IOCON_D0SPL (0x1 << 16) /* RW */ 106 #define MSDC_IOCON_D1SPL (0x1 << 17) /* RW */ 107 #define MSDC_IOCON_D2SPL (0x1 << 18) /* RW */ 108 #define MSDC_IOCON_D3SPL (0x1 << 19) /* RW */ 109 #define MSDC_IOCON_D4SPL (0x1 << 20) /* RW */ 110 #define MSDC_IOCON_D5SPL (0x1 << 21) /* RW */ 111 #define MSDC_IOCON_D6SPL (0x1 << 22) /* RW */ 112 #define MSDC_IOCON_D7SPL (0x1 << 23) /* RW */ 113 #define MSDC_IOCON_RISCSZ (0x3 << 24) /* RW */ 114 115 /* MSDC_PS mask */ 116 #define MSDC_PS_CDEN (0x1 << 0) /* RW */ 117 #define MSDC_PS_CDSTS (0x1 << 1) /* R */ 118 #define MSDC_PS_CDDEBOUNCE (0xf << 12) /* RW */ 119 #define MSDC_PS_DAT (0xff << 16) /* R */ 120 #define MSDC_PS_CMD (0x1 << 24) /* R */ 121 #define MSDC_PS_WP (0x1 << 31) /* R */ 122 123 /* MSDC_INT mask */ 124 #define MSDC_INT_MMCIRQ (0x1 << 0) /* W1C */ 125 #define MSDC_INT_CDSC (0x1 << 1) /* W1C */ 126 #define MSDC_INT_ACMDRDY (0x1 << 3) /* W1C */ 127 #define MSDC_INT_ACMDTMO (0x1 << 4) /* W1C */ 128 #define MSDC_INT_ACMDCRCERR (0x1 << 5) /* W1C */ 129 #define MSDC_INT_DMAQ_EMPTY (0x1 << 6) /* W1C */ 130 #define MSDC_INT_SDIOIRQ (0x1 << 7) /* W1C */ 131 #define MSDC_INT_CMDRDY (0x1 << 8) /* W1C */ 132 #define MSDC_INT_CMDTMO (0x1 << 9) /* W1C */ 133 #define MSDC_INT_RSPCRCERR (0x1 << 10) /* W1C */ 134 #define MSDC_INT_CSTA (0x1 << 11) /* R */ 135 #define MSDC_INT_XFER_COMPL (0x1 << 12) /* W1C */ 136 #define MSDC_INT_DXFER_DONE (0x1 << 13) /* W1C */ 137 #define MSDC_INT_DATTMO (0x1 << 14) /* W1C */ 138 #define MSDC_INT_DATCRCERR (0x1 << 15) /* W1C */ 139 #define MSDC_INT_ACMD19_DONE (0x1 << 16) /* W1C */ 140 #define MSDC_INT_DMA_BDCSERR (0x1 << 17) /* W1C */ 141 #define MSDC_INT_DMA_GPDCSERR (0x1 << 18) /* W1C */ 142 #define MSDC_INT_DMA_PROTECT (0x1 << 19) /* W1C */ 143 144 /* MSDC_INTEN mask */ 145 #define MSDC_INTEN_MMCIRQ (0x1 << 0) /* RW */ 146 #define MSDC_INTEN_CDSC (0x1 << 1) /* RW */ 147 #define MSDC_INTEN_ACMDRDY (0x1 << 3) /* RW */ 148 #define MSDC_INTEN_ACMDTMO (0x1 << 4) /* RW */ 149 #define MSDC_INTEN_ACMDCRCERR (0x1 << 5) /* RW */ 150 #define MSDC_INTEN_DMAQ_EMPTY (0x1 << 6) /* RW */ 151 #define MSDC_INTEN_SDIOIRQ (0x1 << 7) /* RW */ 152 #define MSDC_INTEN_CMDRDY (0x1 << 8) /* RW */ 153 #define MSDC_INTEN_CMDTMO (0x1 << 9) /* RW */ 154 #define MSDC_INTEN_RSPCRCERR (0x1 << 10) /* RW */ 155 #define MSDC_INTEN_CSTA (0x1 << 11) /* RW */ 156 #define MSDC_INTEN_XFER_COMPL (0x1 << 12) /* RW */ 157 #define MSDC_INTEN_DXFER_DONE (0x1 << 13) /* RW */ 158 #define MSDC_INTEN_DATTMO (0x1 << 14) /* RW */ 159 #define MSDC_INTEN_DATCRCERR (0x1 << 15) /* RW */ 160 #define MSDC_INTEN_ACMD19_DONE (0x1 << 16) /* RW */ 161 #define MSDC_INTEN_DMA_BDCSERR (0x1 << 17) /* RW */ 162 #define MSDC_INTEN_DMA_GPDCSERR (0x1 << 18) /* RW */ 163 #define MSDC_INTEN_DMA_PROTECT (0x1 << 19) /* RW */ 164 165 /* MSDC_FIFOCS mask */ 166 #define MSDC_FIFOCS_RXCNT (0xff << 0) /* R */ 167 #define MSDC_FIFOCS_TXCNT (0xff << 16) /* R */ 168 #define MSDC_FIFOCS_CLR (0x1 << 31) /* RW */ 169 170 /* SDC_CFG mask */ 171 #define SDC_CFG_SDIOINTWKUP (0x1 << 0) /* RW */ 172 #define SDC_CFG_INSWKUP (0x1 << 1) /* RW */ 173 #define SDC_CFG_BUSWIDTH (0x3 << 16) /* RW */ 174 #define SDC_CFG_SDIO (0x1 << 19) /* RW */ 175 #define SDC_CFG_SDIOIDE (0x1 << 20) /* RW */ 176 #define SDC_CFG_INTATGAP (0x1 << 21) /* RW */ 177 #define SDC_CFG_DTOC (0xff << 24) /* RW */ 178 179 /* SDC_STS mask */ 180 #define SDC_STS_SDCBUSY (0x1 << 0) /* RW */ 181 #define SDC_STS_CMDBUSY (0x1 << 1) /* RW */ 182 #define SDC_STS_SWR_COMPL (0x1 << 31) /* RW */ 183 184 /* MSDC_DMA_CTRL mask */ 185 #define MSDC_DMA_CTRL_START (0x1 << 0) /* W */ 186 #define MSDC_DMA_CTRL_STOP (0x1 << 1) /* W */ 187 #define MSDC_DMA_CTRL_RESUME (0x1 << 2) /* W */ 188 #define MSDC_DMA_CTRL_MODE (0x1 << 8) /* RW */ 189 #define MSDC_DMA_CTRL_LASTBUF (0x1 << 10) /* RW */ 190 #define MSDC_DMA_CTRL_BRUSTSZ (0x7 << 12) /* RW */ 191 192 /* MSDC_DMA_CFG mask */ 193 #define MSDC_DMA_CFG_STS (0x1 << 0) /* R */ 194 #define MSDC_DMA_CFG_DECSEN (0x1 << 1) /* RW */ 195 #define MSDC_DMA_CFG_AHBHPROT2 (0x2 << 8) /* RW */ 196 #define MSDC_DMA_CFG_ACTIVEEN (0x2 << 12) /* RW */ 197 #define MSDC_DMA_CFG_CS12B16B (0x1 << 16) /* RW */ 198 199 /* MSDC_PATCH_BIT mask */ 200 #define MSDC_PATCH_BIT_ODDSUPP (0x1 << 1) /* RW */ 201 #define MSDC_INT_DAT_LATCH_CK_SEL (0x7 << 7) 202 #define MSDC_CKGEN_MSDC_DLY_SEL (0x1f << 10) 203 #define MSDC_PATCH_BIT_IODSSEL (0x1 << 16) /* RW */ 204 #define MSDC_PATCH_BIT_IOINTSEL (0x1 << 17) /* RW */ 205 #define MSDC_PATCH_BIT_BUSYDLY (0xf << 18) /* RW */ 206 #define MSDC_PATCH_BIT_WDOD (0xf << 22) /* RW */ 207 #define MSDC_PATCH_BIT_IDRTSEL (0x1 << 26) /* RW */ 208 #define MSDC_PATCH_BIT_CMDFSEL (0x1 << 27) /* RW */ 209 #define MSDC_PATCH_BIT_INTDLSEL (0x1 << 28) /* RW */ 210 #define MSDC_PATCH_BIT_SPCPUSH (0x1 << 29) /* RW */ 211 #define MSDC_PATCH_BIT_DECRCTMO (0x1 << 30) /* RW */ 212 213 #define MSDC_PAD_TUNE_DATRRDLY (0x1f << 8) /* RW */ 214 #define MSDC_PAD_TUNE_CMDRDLY (0x1f << 16) /* RW */ 215 216 #define PAD_DS_TUNE_DLY1 (0x1f << 2) /* RW */ 217 #define PAD_DS_TUNE_DLY2 (0x1f << 7) /* RW */ 218 #define PAD_DS_TUNE_DLY3 (0x1f << 12) /* RW */ 219 220 #define EMMC50_CFG_PADCMD_LATCHCK (0x1 << 0) /* RW */ 221 #define EMMC50_CFG_CRCSTS_EDGE (0x1 << 3) /* RW */ 222 #define EMMC50_CFG_CFCSTS_SEL (0x1 << 4) /* RW */ 223 224 #define REQ_CMD_EIO (0x1 << 0) 225 #define REQ_CMD_TMO (0x1 << 1) 226 #define REQ_DAT_ERR (0x1 << 2) 227 #define REQ_STOP_EIO (0x1 << 3) 228 #define REQ_STOP_TMO (0x1 << 4) 229 #define REQ_CMD_BUSY (0x1 << 5) 230 231 #define MSDC_PREPARE_FLAG (0x1 << 0) 232 #define MSDC_ASYNC_FLAG (0x1 << 1) 233 #define MSDC_MMAP_FLAG (0x1 << 2) 234 235 #define MTK_MMC_AUTOSUSPEND_DELAY 50 236 #define CMD_TIMEOUT (HZ/10 * 5) /* 100ms x5 */ 237 #define DAT_TIMEOUT (HZ * 5) /* 1000ms x5 */ 238 239 #define PAD_DELAY_MAX 32 /* PAD delay cells */ 240 /*--------------------------------------------------------------------------*/ 241 /* Descriptor Structure */ 242 /*--------------------------------------------------------------------------*/ 243 struct mt_gpdma_desc { 244 u32 gpd_info; 245 #define GPDMA_DESC_HWO (0x1 << 0) 246 #define GPDMA_DESC_BDP (0x1 << 1) 247 #define GPDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 248 #define GPDMA_DESC_INT (0x1 << 16) 249 u32 next; 250 u32 ptr; 251 u32 gpd_data_len; 252 #define GPDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 253 #define GPDMA_DESC_EXTLEN (0xff << 16) /* bit16 ~ bit23 */ 254 u32 arg; 255 u32 blknum; 256 u32 cmd; 257 }; 258 259 struct mt_bdma_desc { 260 u32 bd_info; 261 #define BDMA_DESC_EOL (0x1 << 0) 262 #define BDMA_DESC_CHECKSUM (0xff << 8) /* bit8 ~ bit15 */ 263 #define BDMA_DESC_BLKPAD (0x1 << 17) 264 #define BDMA_DESC_DWPAD (0x1 << 18) 265 u32 next; 266 u32 ptr; 267 u32 bd_data_len; 268 #define BDMA_DESC_BUFLEN (0xffff) /* bit0 ~ bit15 */ 269 }; 270 271 struct msdc_dma { 272 struct scatterlist *sg; /* I/O scatter list */ 273 struct mt_gpdma_desc *gpd; /* pointer to gpd array */ 274 struct mt_bdma_desc *bd; /* pointer to bd array */ 275 dma_addr_t gpd_addr; /* the physical address of gpd array */ 276 dma_addr_t bd_addr; /* the physical address of bd array */ 277 }; 278 279 struct msdc_save_para { 280 u32 msdc_cfg; 281 u32 iocon; 282 u32 sdc_cfg; 283 u32 pad_tune; 284 u32 patch_bit0; 285 u32 patch_bit1; 286 u32 pad_ds_tune; 287 u32 emmc50_cfg0; 288 }; 289 290 struct msdc_tune_para { 291 u32 iocon; 292 u32 pad_tune; 293 }; 294 295 struct msdc_delay_phase { 296 u8 maxlen; 297 u8 start; 298 u8 final_phase; 299 }; 300 301 struct msdc_host { 302 struct device *dev; 303 struct mmc_host *mmc; /* mmc structure */ 304 int cmd_rsp; 305 306 spinlock_t lock; 307 struct mmc_request *mrq; 308 struct mmc_command *cmd; 309 struct mmc_data *data; 310 int error; 311 312 void __iomem *base; /* host base address */ 313 314 struct msdc_dma dma; /* dma channel */ 315 u64 dma_mask; 316 317 u32 timeout_ns; /* data timeout ns */ 318 u32 timeout_clks; /* data timeout clks */ 319 320 struct pinctrl *pinctrl; 321 struct pinctrl_state *pins_default; 322 struct pinctrl_state *pins_uhs; 323 struct delayed_work req_timeout; 324 int irq; /* host interrupt */ 325 326 struct clk *src_clk; /* msdc source clock */ 327 struct clk *h_clk; /* msdc h_clk */ 328 u32 mclk; /* mmc subsystem clock frequency */ 329 u32 src_clk_freq; /* source clock frequency */ 330 u32 sclk; /* SD/MS bus clock frequency */ 331 unsigned char timing; 332 bool vqmmc_enabled; 333 u32 hs400_ds_delay; 334 bool hs400_mode; /* current eMMC will run at hs400 mode */ 335 struct msdc_save_para save_para; /* used when gate HCLK */ 336 struct msdc_tune_para def_tune_para; /* default tune setting */ 337 struct msdc_tune_para saved_tune_para; /* tune result of CMD21/CMD19 */ 338 }; 339 340 static void sdr_set_bits(void __iomem *reg, u32 bs) 341 { 342 u32 val = readl(reg); 343 344 val |= bs; 345 writel(val, reg); 346 } 347 348 static void sdr_clr_bits(void __iomem *reg, u32 bs) 349 { 350 u32 val = readl(reg); 351 352 val &= ~bs; 353 writel(val, reg); 354 } 355 356 static void sdr_set_field(void __iomem *reg, u32 field, u32 val) 357 { 358 unsigned int tv = readl(reg); 359 360 tv &= ~field; 361 tv |= ((val) << (ffs((unsigned int)field) - 1)); 362 writel(tv, reg); 363 } 364 365 static void sdr_get_field(void __iomem *reg, u32 field, u32 *val) 366 { 367 unsigned int tv = readl(reg); 368 369 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); 370 } 371 372 static void msdc_reset_hw(struct msdc_host *host) 373 { 374 u32 val; 375 376 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); 377 while (readl(host->base + MSDC_CFG) & MSDC_CFG_RST) 378 cpu_relax(); 379 380 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); 381 while (readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_CLR) 382 cpu_relax(); 383 384 val = readl(host->base + MSDC_INT); 385 writel(val, host->base + MSDC_INT); 386 } 387 388 static void msdc_cmd_next(struct msdc_host *host, 389 struct mmc_request *mrq, struct mmc_command *cmd); 390 391 static const u32 cmd_ints_mask = MSDC_INTEN_CMDRDY | MSDC_INTEN_RSPCRCERR | 392 MSDC_INTEN_CMDTMO | MSDC_INTEN_ACMDRDY | 393 MSDC_INTEN_ACMDCRCERR | MSDC_INTEN_ACMDTMO; 394 static const u32 data_ints_mask = MSDC_INTEN_XFER_COMPL | MSDC_INTEN_DATTMO | 395 MSDC_INTEN_DATCRCERR | MSDC_INTEN_DMA_BDCSERR | 396 MSDC_INTEN_DMA_GPDCSERR | MSDC_INTEN_DMA_PROTECT; 397 398 static u8 msdc_dma_calcs(u8 *buf, u32 len) 399 { 400 u32 i, sum = 0; 401 402 for (i = 0; i < len; i++) 403 sum += buf[i]; 404 return 0xff - (u8) sum; 405 } 406 407 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, 408 struct mmc_data *data) 409 { 410 unsigned int j, dma_len; 411 dma_addr_t dma_address; 412 u32 dma_ctrl; 413 struct scatterlist *sg; 414 struct mt_gpdma_desc *gpd; 415 struct mt_bdma_desc *bd; 416 417 sg = data->sg; 418 419 gpd = dma->gpd; 420 bd = dma->bd; 421 422 /* modify gpd */ 423 gpd->gpd_info |= GPDMA_DESC_HWO; 424 gpd->gpd_info |= GPDMA_DESC_BDP; 425 /* need to clear first. use these bits to calc checksum */ 426 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; 427 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; 428 429 /* modify bd */ 430 for_each_sg(data->sg, sg, data->sg_count, j) { 431 dma_address = sg_dma_address(sg); 432 dma_len = sg_dma_len(sg); 433 434 /* init bd */ 435 bd[j].bd_info &= ~BDMA_DESC_BLKPAD; 436 bd[j].bd_info &= ~BDMA_DESC_DWPAD; 437 bd[j].ptr = (u32)dma_address; 438 bd[j].bd_data_len &= ~BDMA_DESC_BUFLEN; 439 bd[j].bd_data_len |= (dma_len & BDMA_DESC_BUFLEN); 440 441 if (j == data->sg_count - 1) /* the last bd */ 442 bd[j].bd_info |= BDMA_DESC_EOL; 443 else 444 bd[j].bd_info &= ~BDMA_DESC_EOL; 445 446 /* checksume need to clear first */ 447 bd[j].bd_info &= ~BDMA_DESC_CHECKSUM; 448 bd[j].bd_info |= msdc_dma_calcs((u8 *)(&bd[j]), 16) << 8; 449 } 450 451 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); 452 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); 453 dma_ctrl &= ~(MSDC_DMA_CTRL_BRUSTSZ | MSDC_DMA_CTRL_MODE); 454 dma_ctrl |= (MSDC_BURST_64B << 12 | 1 << 8); 455 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); 456 writel((u32)dma->gpd_addr, host->base + MSDC_DMA_SA); 457 } 458 459 static void msdc_prepare_data(struct msdc_host *host, struct mmc_request *mrq) 460 { 461 struct mmc_data *data = mrq->data; 462 463 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { 464 bool read = (data->flags & MMC_DATA_READ) != 0; 465 466 data->host_cookie |= MSDC_PREPARE_FLAG; 467 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, 468 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 469 } 470 } 471 472 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_request *mrq) 473 { 474 struct mmc_data *data = mrq->data; 475 476 if (data->host_cookie & MSDC_ASYNC_FLAG) 477 return; 478 479 if (data->host_cookie & MSDC_PREPARE_FLAG) { 480 bool read = (data->flags & MMC_DATA_READ) != 0; 481 482 dma_unmap_sg(host->dev, data->sg, data->sg_len, 483 read ? DMA_FROM_DEVICE : DMA_TO_DEVICE); 484 data->host_cookie &= ~MSDC_PREPARE_FLAG; 485 } 486 } 487 488 /* clock control primitives */ 489 static void msdc_set_timeout(struct msdc_host *host, u32 ns, u32 clks) 490 { 491 u32 timeout, clk_ns; 492 u32 mode = 0; 493 494 host->timeout_ns = ns; 495 host->timeout_clks = clks; 496 if (host->sclk == 0) { 497 timeout = 0; 498 } else { 499 clk_ns = 1000000000UL / host->sclk; 500 timeout = (ns + clk_ns - 1) / clk_ns + clks; 501 /* in 1048576 sclk cycle unit */ 502 timeout = (timeout + (0x1 << 20) - 1) >> 20; 503 sdr_get_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD, &mode); 504 /*DDR mode will double the clk cycles for data timeout */ 505 timeout = mode >= 2 ? timeout * 2 : timeout; 506 timeout = timeout > 1 ? timeout - 1 : 0; 507 timeout = timeout > 255 ? 255 : timeout; 508 } 509 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, timeout); 510 } 511 512 static void msdc_gate_clock(struct msdc_host *host) 513 { 514 clk_disable_unprepare(host->src_clk); 515 clk_disable_unprepare(host->h_clk); 516 } 517 518 static void msdc_ungate_clock(struct msdc_host *host) 519 { 520 clk_prepare_enable(host->h_clk); 521 clk_prepare_enable(host->src_clk); 522 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 523 cpu_relax(); 524 } 525 526 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) 527 { 528 u32 mode; 529 u32 flags; 530 u32 div; 531 u32 sclk; 532 533 if (!hz) { 534 dev_dbg(host->dev, "set mclk to 0\n"); 535 host->mclk = 0; 536 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 537 return; 538 } 539 540 flags = readl(host->base + MSDC_INTEN); 541 sdr_clr_bits(host->base + MSDC_INTEN, flags); 542 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); 543 if (timing == MMC_TIMING_UHS_DDR50 || 544 timing == MMC_TIMING_MMC_DDR52 || 545 timing == MMC_TIMING_MMC_HS400) { 546 if (timing == MMC_TIMING_MMC_HS400) 547 mode = 0x3; 548 else 549 mode = 0x2; /* ddr mode and use divisor */ 550 551 if (hz >= (host->src_clk_freq >> 2)) { 552 div = 0; /* mean div = 1/4 */ 553 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ 554 } else { 555 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 556 sclk = (host->src_clk_freq >> 2) / div; 557 div = (div >> 1); 558 } 559 560 if (timing == MMC_TIMING_MMC_HS400 && 561 hz >= (host->src_clk_freq >> 1)) { 562 sdr_set_bits(host->base + MSDC_CFG, 563 MSDC_CFG_HS400_CK_MODE); 564 sclk = host->src_clk_freq >> 1; 565 div = 0; /* div is ignore when bit18 is set */ 566 } 567 } else if (hz >= host->src_clk_freq) { 568 mode = 0x1; /* no divisor */ 569 div = 0; 570 sclk = host->src_clk_freq; 571 } else { 572 mode = 0x0; /* use divisor */ 573 if (hz >= (host->src_clk_freq >> 1)) { 574 div = 0; /* mean div = 1/2 */ 575 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ 576 } else { 577 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); 578 sclk = (host->src_clk_freq >> 2) / div; 579 } 580 } 581 sdr_set_field(host->base + MSDC_CFG, MSDC_CFG_CKMOD | MSDC_CFG_CKDIV, 582 (mode << 8) | (div % 0xff)); 583 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); 584 while (!(readl(host->base + MSDC_CFG) & MSDC_CFG_CKSTB)) 585 cpu_relax(); 586 host->sclk = sclk; 587 host->mclk = hz; 588 host->timing = timing; 589 /* need because clk changed. */ 590 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); 591 sdr_set_bits(host->base + MSDC_INTEN, flags); 592 593 /* 594 * mmc_select_hs400() will drop to 50Mhz and High speed mode, 595 * tune result of hs200/200Mhz is not suitable for 50Mhz 596 */ 597 if (host->sclk <= 52000000) { 598 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); 599 writel(host->def_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 600 } else { 601 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); 602 writel(host->saved_tune_para.pad_tune, host->base + MSDC_PAD_TUNE); 603 } 604 605 dev_dbg(host->dev, "sclk: %d, timing: %d\n", host->sclk, timing); 606 } 607 608 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, 609 struct mmc_request *mrq, struct mmc_command *cmd) 610 { 611 u32 resp; 612 613 switch (mmc_resp_type(cmd)) { 614 /* Actually, R1, R5, R6, R7 are the same */ 615 case MMC_RSP_R1: 616 resp = 0x1; 617 break; 618 case MMC_RSP_R1B: 619 resp = 0x7; 620 break; 621 case MMC_RSP_R2: 622 resp = 0x2; 623 break; 624 case MMC_RSP_R3: 625 resp = 0x3; 626 break; 627 case MMC_RSP_NONE: 628 default: 629 resp = 0x0; 630 break; 631 } 632 633 return resp; 634 } 635 636 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, 637 struct mmc_request *mrq, struct mmc_command *cmd) 638 { 639 /* rawcmd : 640 * vol_swt << 30 | auto_cmd << 28 | blklen << 16 | go_irq << 15 | 641 * stop << 14 | rw << 13 | dtype << 11 | rsptyp << 7 | brk << 6 | opcode 642 */ 643 u32 opcode = cmd->opcode; 644 u32 resp = msdc_cmd_find_resp(host, mrq, cmd); 645 u32 rawcmd = (opcode & 0x3f) | ((resp & 0x7) << 7); 646 647 host->cmd_rsp = resp; 648 649 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || 650 opcode == MMC_STOP_TRANSMISSION) 651 rawcmd |= (0x1 << 14); 652 else if (opcode == SD_SWITCH_VOLTAGE) 653 rawcmd |= (0x1 << 30); 654 else if (opcode == SD_APP_SEND_SCR || 655 opcode == SD_APP_SEND_NUM_WR_BLKS || 656 (opcode == SD_SWITCH && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 657 (opcode == SD_APP_SD_STATUS && mmc_cmd_type(cmd) == MMC_CMD_ADTC) || 658 (opcode == MMC_SEND_EXT_CSD && mmc_cmd_type(cmd) == MMC_CMD_ADTC)) 659 rawcmd |= (0x1 << 11); 660 661 if (cmd->data) { 662 struct mmc_data *data = cmd->data; 663 664 if (mmc_op_multi(opcode)) { 665 if (mmc_card_mmc(host->mmc->card) && mrq->sbc && 666 !(mrq->sbc->arg & 0xFFFF0000)) 667 rawcmd |= 0x2 << 28; /* AutoCMD23 */ 668 } 669 670 rawcmd |= ((data->blksz & 0xFFF) << 16); 671 if (data->flags & MMC_DATA_WRITE) 672 rawcmd |= (0x1 << 13); 673 if (data->blocks > 1) 674 rawcmd |= (0x2 << 11); 675 else 676 rawcmd |= (0x1 << 11); 677 /* Always use dma mode */ 678 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); 679 680 if (host->timeout_ns != data->timeout_ns || 681 host->timeout_clks != data->timeout_clks) 682 msdc_set_timeout(host, data->timeout_ns, 683 data->timeout_clks); 684 685 writel(data->blocks, host->base + SDC_BLK_NUM); 686 } 687 return rawcmd; 688 } 689 690 static void msdc_start_data(struct msdc_host *host, struct mmc_request *mrq, 691 struct mmc_command *cmd, struct mmc_data *data) 692 { 693 bool read; 694 695 WARN_ON(host->data); 696 host->data = data; 697 read = data->flags & MMC_DATA_READ; 698 699 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 700 msdc_dma_setup(host, &host->dma, data); 701 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); 702 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); 703 dev_dbg(host->dev, "DMA start\n"); 704 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", 705 __func__, cmd->opcode, data->blocks, read); 706 } 707 708 static int msdc_auto_cmd_done(struct msdc_host *host, int events, 709 struct mmc_command *cmd) 710 { 711 u32 *rsp = cmd->resp; 712 713 rsp[0] = readl(host->base + SDC_ACMD_RESP); 714 715 if (events & MSDC_INT_ACMDRDY) { 716 cmd->error = 0; 717 } else { 718 msdc_reset_hw(host); 719 if (events & MSDC_INT_ACMDCRCERR) { 720 cmd->error = -EILSEQ; 721 host->error |= REQ_STOP_EIO; 722 } else if (events & MSDC_INT_ACMDTMO) { 723 cmd->error = -ETIMEDOUT; 724 host->error |= REQ_STOP_TMO; 725 } 726 dev_err(host->dev, 727 "%s: AUTO_CMD%d arg=%08X; rsp %08X; cmd_error=%d\n", 728 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); 729 } 730 return cmd->error; 731 } 732 733 static void msdc_track_cmd_data(struct msdc_host *host, 734 struct mmc_command *cmd, struct mmc_data *data) 735 { 736 if (host->error) 737 dev_dbg(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", 738 __func__, cmd->opcode, cmd->arg, host->error); 739 } 740 741 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) 742 { 743 unsigned long flags; 744 bool ret; 745 746 ret = cancel_delayed_work(&host->req_timeout); 747 if (!ret) { 748 /* delay work already running */ 749 return; 750 } 751 spin_lock_irqsave(&host->lock, flags); 752 host->mrq = NULL; 753 spin_unlock_irqrestore(&host->lock, flags); 754 755 msdc_track_cmd_data(host, mrq->cmd, mrq->data); 756 if (mrq->data) 757 msdc_unprepare_data(host, mrq); 758 mmc_request_done(host->mmc, mrq); 759 } 760 761 /* returns true if command is fully handled; returns false otherwise */ 762 static bool msdc_cmd_done(struct msdc_host *host, int events, 763 struct mmc_request *mrq, struct mmc_command *cmd) 764 { 765 bool done = false; 766 bool sbc_error; 767 unsigned long flags; 768 u32 *rsp = cmd->resp; 769 770 if (mrq->sbc && cmd == mrq->cmd && 771 (events & (MSDC_INT_ACMDRDY | MSDC_INT_ACMDCRCERR 772 | MSDC_INT_ACMDTMO))) 773 msdc_auto_cmd_done(host, events, mrq->sbc); 774 775 sbc_error = mrq->sbc && mrq->sbc->error; 776 777 if (!sbc_error && !(events & (MSDC_INT_CMDRDY 778 | MSDC_INT_RSPCRCERR 779 | MSDC_INT_CMDTMO))) 780 return done; 781 782 spin_lock_irqsave(&host->lock, flags); 783 done = !host->cmd; 784 host->cmd = NULL; 785 spin_unlock_irqrestore(&host->lock, flags); 786 787 if (done) 788 return true; 789 790 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); 791 792 if (cmd->flags & MMC_RSP_PRESENT) { 793 if (cmd->flags & MMC_RSP_136) { 794 rsp[0] = readl(host->base + SDC_RESP3); 795 rsp[1] = readl(host->base + SDC_RESP2); 796 rsp[2] = readl(host->base + SDC_RESP1); 797 rsp[3] = readl(host->base + SDC_RESP0); 798 } else { 799 rsp[0] = readl(host->base + SDC_RESP0); 800 } 801 } 802 803 if (!sbc_error && !(events & MSDC_INT_CMDRDY)) { 804 if (cmd->opcode != MMC_SEND_TUNING_BLOCK && 805 cmd->opcode != MMC_SEND_TUNING_BLOCK_HS200) 806 /* 807 * should not clear fifo/interrupt as the tune data 808 * may have alreay come. 809 */ 810 msdc_reset_hw(host); 811 if (events & MSDC_INT_RSPCRCERR) { 812 cmd->error = -EILSEQ; 813 host->error |= REQ_CMD_EIO; 814 } else if (events & MSDC_INT_CMDTMO) { 815 cmd->error = -ETIMEDOUT; 816 host->error |= REQ_CMD_TMO; 817 } 818 } 819 if (cmd->error) 820 dev_dbg(host->dev, 821 "%s: cmd=%d arg=%08X; rsp %08X; cmd_error=%d\n", 822 __func__, cmd->opcode, cmd->arg, rsp[0], 823 cmd->error); 824 825 msdc_cmd_next(host, mrq, cmd); 826 return true; 827 } 828 829 /* It is the core layer's responsibility to ensure card status 830 * is correct before issue a request. but host design do below 831 * checks recommended. 832 */ 833 static inline bool msdc_cmd_is_ready(struct msdc_host *host, 834 struct mmc_request *mrq, struct mmc_command *cmd) 835 { 836 /* The max busy time we can endure is 20ms */ 837 unsigned long tmo = jiffies + msecs_to_jiffies(20); 838 839 while ((readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) && 840 time_before(jiffies, tmo)) 841 cpu_relax(); 842 if (readl(host->base + SDC_STS) & SDC_STS_CMDBUSY) { 843 dev_err(host->dev, "CMD bus busy detected\n"); 844 host->error |= REQ_CMD_BUSY; 845 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 846 return false; 847 } 848 849 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { 850 tmo = jiffies + msecs_to_jiffies(20); 851 /* R1B or with data, should check SDCBUSY */ 852 while ((readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) && 853 time_before(jiffies, tmo)) 854 cpu_relax(); 855 if (readl(host->base + SDC_STS) & SDC_STS_SDCBUSY) { 856 dev_err(host->dev, "Controller busy detected\n"); 857 host->error |= REQ_CMD_BUSY; 858 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); 859 return false; 860 } 861 } 862 return true; 863 } 864 865 static void msdc_start_command(struct msdc_host *host, 866 struct mmc_request *mrq, struct mmc_command *cmd) 867 { 868 u32 rawcmd; 869 870 WARN_ON(host->cmd); 871 host->cmd = cmd; 872 873 if (!msdc_cmd_is_ready(host, mrq, cmd)) 874 return; 875 876 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || 877 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { 878 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); 879 msdc_reset_hw(host); 880 } 881 882 cmd->error = 0; 883 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); 884 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); 885 886 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); 887 writel(cmd->arg, host->base + SDC_ARG); 888 writel(rawcmd, host->base + SDC_CMD); 889 } 890 891 static void msdc_cmd_next(struct msdc_host *host, 892 struct mmc_request *mrq, struct mmc_command *cmd) 893 { 894 if ((cmd->error && 895 !(cmd->error == -EILSEQ && 896 (cmd->opcode == MMC_SEND_TUNING_BLOCK || 897 cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200))) || 898 (mrq->sbc && mrq->sbc->error)) 899 msdc_request_done(host, mrq); 900 else if (cmd == mrq->sbc) 901 msdc_start_command(host, mrq, mrq->cmd); 902 else if (!cmd->data) 903 msdc_request_done(host, mrq); 904 else 905 msdc_start_data(host, mrq, cmd, cmd->data); 906 } 907 908 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) 909 { 910 struct msdc_host *host = mmc_priv(mmc); 911 912 host->error = 0; 913 WARN_ON(host->mrq); 914 host->mrq = mrq; 915 916 if (mrq->data) 917 msdc_prepare_data(host, mrq); 918 919 /* if SBC is required, we have HW option and SW option. 920 * if HW option is enabled, and SBC does not have "special" flags, 921 * use HW option, otherwise use SW option 922 */ 923 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || 924 (mrq->sbc->arg & 0xFFFF0000))) 925 msdc_start_command(host, mrq, mrq->sbc); 926 else 927 msdc_start_command(host, mrq, mrq->cmd); 928 } 929 930 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) 931 { 932 struct msdc_host *host = mmc_priv(mmc); 933 struct mmc_data *data = mrq->data; 934 935 if (!data) 936 return; 937 938 msdc_prepare_data(host, mrq); 939 data->host_cookie |= MSDC_ASYNC_FLAG; 940 } 941 942 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, 943 int err) 944 { 945 struct msdc_host *host = mmc_priv(mmc); 946 struct mmc_data *data; 947 948 data = mrq->data; 949 if (!data) 950 return; 951 if (data->host_cookie) { 952 data->host_cookie &= ~MSDC_ASYNC_FLAG; 953 msdc_unprepare_data(host, mrq); 954 } 955 } 956 957 static void msdc_data_xfer_next(struct msdc_host *host, 958 struct mmc_request *mrq, struct mmc_data *data) 959 { 960 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && 961 !mrq->sbc) 962 msdc_start_command(host, mrq, mrq->stop); 963 else 964 msdc_request_done(host, mrq); 965 } 966 967 static bool msdc_data_xfer_done(struct msdc_host *host, u32 events, 968 struct mmc_request *mrq, struct mmc_data *data) 969 { 970 struct mmc_command *stop = data->stop; 971 unsigned long flags; 972 bool done; 973 unsigned int check_data = events & 974 (MSDC_INT_XFER_COMPL | MSDC_INT_DATCRCERR | MSDC_INT_DATTMO 975 | MSDC_INT_DMA_BDCSERR | MSDC_INT_DMA_GPDCSERR 976 | MSDC_INT_DMA_PROTECT); 977 978 spin_lock_irqsave(&host->lock, flags); 979 done = !host->data; 980 if (check_data) 981 host->data = NULL; 982 spin_unlock_irqrestore(&host->lock, flags); 983 984 if (done) 985 return true; 986 987 if (check_data || (stop && stop->error)) { 988 dev_dbg(host->dev, "DMA status: 0x%8X\n", 989 readl(host->base + MSDC_DMA_CFG)); 990 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, 991 1); 992 while (readl(host->base + MSDC_DMA_CFG) & MSDC_DMA_CFG_STS) 993 cpu_relax(); 994 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); 995 dev_dbg(host->dev, "DMA stop\n"); 996 997 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { 998 data->bytes_xfered = data->blocks * data->blksz; 999 } else { 1000 dev_dbg(host->dev, "interrupt events: %x\n", events); 1001 msdc_reset_hw(host); 1002 host->error |= REQ_DAT_ERR; 1003 data->bytes_xfered = 0; 1004 1005 if (events & MSDC_INT_DATTMO) 1006 data->error = -ETIMEDOUT; 1007 else if (events & MSDC_INT_DATCRCERR) 1008 data->error = -EILSEQ; 1009 1010 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", 1011 __func__, mrq->cmd->opcode, data->blocks); 1012 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", 1013 (int)data->error, data->bytes_xfered); 1014 } 1015 1016 msdc_data_xfer_next(host, mrq, data); 1017 done = true; 1018 } 1019 return done; 1020 } 1021 1022 static void msdc_set_buswidth(struct msdc_host *host, u32 width) 1023 { 1024 u32 val = readl(host->base + SDC_CFG); 1025 1026 val &= ~SDC_CFG_BUSWIDTH; 1027 1028 switch (width) { 1029 default: 1030 case MMC_BUS_WIDTH_1: 1031 val |= (MSDC_BUS_1BITS << 16); 1032 break; 1033 case MMC_BUS_WIDTH_4: 1034 val |= (MSDC_BUS_4BITS << 16); 1035 break; 1036 case MMC_BUS_WIDTH_8: 1037 val |= (MSDC_BUS_8BITS << 16); 1038 break; 1039 } 1040 1041 writel(val, host->base + SDC_CFG); 1042 dev_dbg(host->dev, "Bus Width = %d", width); 1043 } 1044 1045 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) 1046 { 1047 struct msdc_host *host = mmc_priv(mmc); 1048 int ret = 0; 1049 1050 if (!IS_ERR(mmc->supply.vqmmc)) { 1051 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && 1052 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { 1053 dev_err(host->dev, "Unsupported signal voltage!\n"); 1054 return -EINVAL; 1055 } 1056 1057 ret = mmc_regulator_set_vqmmc(mmc, ios); 1058 if (ret) { 1059 dev_dbg(host->dev, "Regulator set error %d (%d)\n", 1060 ret, ios->signal_voltage); 1061 } else { 1062 /* Apply different pinctrl settings for different signal voltage */ 1063 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) 1064 pinctrl_select_state(host->pinctrl, host->pins_uhs); 1065 else 1066 pinctrl_select_state(host->pinctrl, host->pins_default); 1067 } 1068 } 1069 return ret; 1070 } 1071 1072 static int msdc_card_busy(struct mmc_host *mmc) 1073 { 1074 struct msdc_host *host = mmc_priv(mmc); 1075 u32 status = readl(host->base + MSDC_PS); 1076 1077 /* check if any pin between dat[0:3] is low */ 1078 if (((status >> 16) & 0xf) != 0xf) 1079 return 1; 1080 1081 return 0; 1082 } 1083 1084 static void msdc_request_timeout(struct work_struct *work) 1085 { 1086 struct msdc_host *host = container_of(work, struct msdc_host, 1087 req_timeout.work); 1088 1089 /* simulate HW timeout status */ 1090 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); 1091 if (host->mrq) { 1092 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, 1093 host->mrq, host->mrq->cmd->opcode); 1094 if (host->cmd) { 1095 dev_err(host->dev, "%s: aborting cmd=%d\n", 1096 __func__, host->cmd->opcode); 1097 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, 1098 host->cmd); 1099 } else if (host->data) { 1100 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", 1101 __func__, host->mrq->cmd->opcode, 1102 host->data->blocks); 1103 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, 1104 host->data); 1105 } 1106 } 1107 } 1108 1109 static irqreturn_t msdc_irq(int irq, void *dev_id) 1110 { 1111 struct msdc_host *host = (struct msdc_host *) dev_id; 1112 1113 while (true) { 1114 unsigned long flags; 1115 struct mmc_request *mrq; 1116 struct mmc_command *cmd; 1117 struct mmc_data *data; 1118 u32 events, event_mask; 1119 1120 spin_lock_irqsave(&host->lock, flags); 1121 events = readl(host->base + MSDC_INT); 1122 event_mask = readl(host->base + MSDC_INTEN); 1123 /* clear interrupts */ 1124 writel(events & event_mask, host->base + MSDC_INT); 1125 1126 mrq = host->mrq; 1127 cmd = host->cmd; 1128 data = host->data; 1129 spin_unlock_irqrestore(&host->lock, flags); 1130 1131 if (!(events & event_mask)) 1132 break; 1133 1134 if (!mrq) { 1135 dev_err(host->dev, 1136 "%s: MRQ=NULL; events=%08X; event_mask=%08X\n", 1137 __func__, events, event_mask); 1138 WARN_ON(1); 1139 break; 1140 } 1141 1142 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); 1143 1144 if (cmd) 1145 msdc_cmd_done(host, events, mrq, cmd); 1146 else if (data) 1147 msdc_data_xfer_done(host, events, mrq, data); 1148 } 1149 1150 return IRQ_HANDLED; 1151 } 1152 1153 static void msdc_init_hw(struct msdc_host *host) 1154 { 1155 u32 val; 1156 1157 /* Configure to MMC/SD mode, clock free running */ 1158 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); 1159 1160 /* Reset */ 1161 msdc_reset_hw(host); 1162 1163 /* Disable card detection */ 1164 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); 1165 1166 /* Disable and clear all interrupts */ 1167 writel(0, host->base + MSDC_INTEN); 1168 val = readl(host->base + MSDC_INT); 1169 writel(val, host->base + MSDC_INT); 1170 1171 writel(0, host->base + MSDC_PAD_TUNE); 1172 writel(0, host->base + MSDC_IOCON); 1173 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); 1174 writel(0x403c0046, host->base + MSDC_PATCH_BIT); 1175 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); 1176 writel(0xffff0089, host->base + MSDC_PATCH_BIT1); 1177 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); 1178 1179 /* Configure to enable SDIO mode. 1180 * it's must otherwise sdio cmd5 failed 1181 */ 1182 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); 1183 1184 /* disable detect SDIO device interrupt function */ 1185 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); 1186 1187 /* Configure to default data timeout */ 1188 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); 1189 1190 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); 1191 host->def_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1192 dev_dbg(host->dev, "init hardware done!"); 1193 } 1194 1195 static void msdc_deinit_hw(struct msdc_host *host) 1196 { 1197 u32 val; 1198 /* Disable and clear all interrupts */ 1199 writel(0, host->base + MSDC_INTEN); 1200 1201 val = readl(host->base + MSDC_INT); 1202 writel(val, host->base + MSDC_INT); 1203 } 1204 1205 /* init gpd and bd list in msdc_drv_probe */ 1206 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) 1207 { 1208 struct mt_gpdma_desc *gpd = dma->gpd; 1209 struct mt_bdma_desc *bd = dma->bd; 1210 int i; 1211 1212 memset(gpd, 0, sizeof(struct mt_gpdma_desc) * 2); 1213 1214 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ 1215 gpd->ptr = (u32)dma->bd_addr; /* physical address */ 1216 /* gpd->next is must set for desc DMA 1217 * That's why must alloc 2 gpd structure. 1218 */ 1219 gpd->next = (u32)dma->gpd_addr + sizeof(struct mt_gpdma_desc); 1220 memset(bd, 0, sizeof(struct mt_bdma_desc) * MAX_BD_NUM); 1221 for (i = 0; i < (MAX_BD_NUM - 1); i++) 1222 bd[i].next = (u32)dma->bd_addr + sizeof(*bd) * (i + 1); 1223 } 1224 1225 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1226 { 1227 struct msdc_host *host = mmc_priv(mmc); 1228 int ret; 1229 1230 msdc_set_buswidth(host, ios->bus_width); 1231 1232 /* Suspend/Resume will do power off/on */ 1233 switch (ios->power_mode) { 1234 case MMC_POWER_UP: 1235 if (!IS_ERR(mmc->supply.vmmc)) { 1236 msdc_init_hw(host); 1237 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 1238 ios->vdd); 1239 if (ret) { 1240 dev_err(host->dev, "Failed to set vmmc power!\n"); 1241 return; 1242 } 1243 } 1244 break; 1245 case MMC_POWER_ON: 1246 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { 1247 ret = regulator_enable(mmc->supply.vqmmc); 1248 if (ret) 1249 dev_err(host->dev, "Failed to set vqmmc power!\n"); 1250 else 1251 host->vqmmc_enabled = true; 1252 } 1253 break; 1254 case MMC_POWER_OFF: 1255 if (!IS_ERR(mmc->supply.vmmc)) 1256 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1257 1258 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { 1259 regulator_disable(mmc->supply.vqmmc); 1260 host->vqmmc_enabled = false; 1261 } 1262 break; 1263 default: 1264 break; 1265 } 1266 1267 if (host->mclk != ios->clock || host->timing != ios->timing) 1268 msdc_set_mclk(host, ios->timing, ios->clock); 1269 } 1270 1271 static u32 test_delay_bit(u32 delay, u32 bit) 1272 { 1273 bit %= PAD_DELAY_MAX; 1274 return delay & (1 << bit); 1275 } 1276 1277 static int get_delay_len(u32 delay, u32 start_bit) 1278 { 1279 int i; 1280 1281 for (i = 0; i < (PAD_DELAY_MAX - start_bit); i++) { 1282 if (test_delay_bit(delay, start_bit + i) == 0) 1283 return i; 1284 } 1285 return PAD_DELAY_MAX - start_bit; 1286 } 1287 1288 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u32 delay) 1289 { 1290 int start = 0, len = 0; 1291 int start_final = 0, len_final = 0; 1292 u8 final_phase = 0xff; 1293 struct msdc_delay_phase delay_phase = { 0, }; 1294 1295 if (delay == 0) { 1296 dev_err(host->dev, "phase error: [map:%x]\n", delay); 1297 delay_phase.final_phase = final_phase; 1298 return delay_phase; 1299 } 1300 1301 while (start < PAD_DELAY_MAX) { 1302 len = get_delay_len(delay, start); 1303 if (len_final < len) { 1304 start_final = start; 1305 len_final = len; 1306 } 1307 start += len ? len : 1; 1308 if (len >= 8 && start_final < 4) 1309 break; 1310 } 1311 1312 /* The rule is that to find the smallest delay cell */ 1313 if (start_final == 0) 1314 final_phase = (start_final + len_final / 3) % PAD_DELAY_MAX; 1315 else 1316 final_phase = (start_final + len_final / 2) % PAD_DELAY_MAX; 1317 dev_info(host->dev, "phase: [map:%x] [maxlen:%d] [final:%d]\n", 1318 delay, len_final, final_phase); 1319 1320 delay_phase.maxlen = len_final; 1321 delay_phase.start = start_final; 1322 delay_phase.final_phase = final_phase; 1323 return delay_phase; 1324 } 1325 1326 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) 1327 { 1328 struct msdc_host *host = mmc_priv(mmc); 1329 u32 rise_delay = 0, fall_delay = 0; 1330 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1331 u8 final_delay, final_maxlen; 1332 int cmd_err; 1333 int i; 1334 1335 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1336 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1337 sdr_set_field(host->base + MSDC_PAD_TUNE, 1338 MSDC_PAD_TUNE_CMDRDLY, i); 1339 mmc_send_tuning(mmc, opcode, &cmd_err); 1340 if (!cmd_err) 1341 rise_delay |= (1 << i); 1342 } 1343 final_rise_delay = get_best_delay(host, rise_delay); 1344 /* if rising edge has enough margin, then do not scan falling edge */ 1345 if (final_rise_delay.maxlen >= 10 || 1346 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1347 goto skip_fall; 1348 1349 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1350 for (i = 0; i < PAD_DELAY_MAX; i++) { 1351 sdr_set_field(host->base + MSDC_PAD_TUNE, 1352 MSDC_PAD_TUNE_CMDRDLY, i); 1353 mmc_send_tuning(mmc, opcode, &cmd_err); 1354 if (!cmd_err) 1355 fall_delay |= (1 << i); 1356 } 1357 final_fall_delay = get_best_delay(host, fall_delay); 1358 1359 skip_fall: 1360 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1361 if (final_maxlen == final_rise_delay.maxlen) { 1362 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1363 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1364 final_rise_delay.final_phase); 1365 final_delay = final_rise_delay.final_phase; 1366 } else { 1367 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); 1368 sdr_set_field(host->base + MSDC_PAD_TUNE, MSDC_PAD_TUNE_CMDRDLY, 1369 final_fall_delay.final_phase); 1370 final_delay = final_fall_delay.final_phase; 1371 } 1372 1373 return final_delay == 0xff ? -EIO : 0; 1374 } 1375 1376 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) 1377 { 1378 struct msdc_host *host = mmc_priv(mmc); 1379 u32 rise_delay = 0, fall_delay = 0; 1380 struct msdc_delay_phase final_rise_delay, final_fall_delay = { 0,}; 1381 u8 final_delay, final_maxlen; 1382 int i, ret; 1383 1384 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1385 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1386 for (i = 0 ; i < PAD_DELAY_MAX; i++) { 1387 sdr_set_field(host->base + MSDC_PAD_TUNE, 1388 MSDC_PAD_TUNE_DATRRDLY, i); 1389 ret = mmc_send_tuning(mmc, opcode, NULL); 1390 if (!ret) 1391 rise_delay |= (1 << i); 1392 } 1393 final_rise_delay = get_best_delay(host, rise_delay); 1394 /* if rising edge has enough margin, then do not scan falling edge */ 1395 if (final_rise_delay.maxlen >= 10 || 1396 (final_rise_delay.start == 0 && final_rise_delay.maxlen >= 4)) 1397 goto skip_fall; 1398 1399 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1400 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1401 for (i = 0; i < PAD_DELAY_MAX; i++) { 1402 sdr_set_field(host->base + MSDC_PAD_TUNE, 1403 MSDC_PAD_TUNE_DATRRDLY, i); 1404 ret = mmc_send_tuning(mmc, opcode, NULL); 1405 if (!ret) 1406 fall_delay |= (1 << i); 1407 } 1408 final_fall_delay = get_best_delay(host, fall_delay); 1409 1410 skip_fall: 1411 final_maxlen = max(final_rise_delay.maxlen, final_fall_delay.maxlen); 1412 if (final_maxlen == final_rise_delay.maxlen) { 1413 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1414 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1415 sdr_set_field(host->base + MSDC_PAD_TUNE, 1416 MSDC_PAD_TUNE_DATRRDLY, 1417 final_rise_delay.final_phase); 1418 final_delay = final_rise_delay.final_phase; 1419 } else { 1420 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); 1421 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); 1422 sdr_set_field(host->base + MSDC_PAD_TUNE, 1423 MSDC_PAD_TUNE_DATRRDLY, 1424 final_fall_delay.final_phase); 1425 final_delay = final_fall_delay.final_phase; 1426 } 1427 1428 return final_delay == 0xff ? -EIO : 0; 1429 } 1430 1431 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) 1432 { 1433 struct msdc_host *host = mmc_priv(mmc); 1434 int ret; 1435 1436 ret = msdc_tune_response(mmc, opcode); 1437 if (ret == -EIO) { 1438 dev_err(host->dev, "Tune response fail!\n"); 1439 return ret; 1440 } 1441 if (host->hs400_mode == false) { 1442 ret = msdc_tune_data(mmc, opcode); 1443 if (ret == -EIO) 1444 dev_err(host->dev, "Tune data fail!\n"); 1445 } 1446 1447 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); 1448 host->saved_tune_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1449 return ret; 1450 } 1451 1452 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) 1453 { 1454 struct msdc_host *host = mmc_priv(mmc); 1455 host->hs400_mode = true; 1456 1457 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); 1458 return 0; 1459 } 1460 1461 static void msdc_hw_reset(struct mmc_host *mmc) 1462 { 1463 struct msdc_host *host = mmc_priv(mmc); 1464 1465 sdr_set_bits(host->base + EMMC_IOCON, 1); 1466 udelay(10); /* 10us is enough */ 1467 sdr_clr_bits(host->base + EMMC_IOCON, 1); 1468 } 1469 1470 static struct mmc_host_ops mt_msdc_ops = { 1471 .post_req = msdc_post_req, 1472 .pre_req = msdc_pre_req, 1473 .request = msdc_ops_request, 1474 .set_ios = msdc_ops_set_ios, 1475 .get_ro = mmc_gpio_get_ro, 1476 .start_signal_voltage_switch = msdc_ops_switch_volt, 1477 .card_busy = msdc_card_busy, 1478 .execute_tuning = msdc_execute_tuning, 1479 .prepare_hs400_tuning = msdc_prepare_hs400_tuning, 1480 .hw_reset = msdc_hw_reset, 1481 }; 1482 1483 static int msdc_drv_probe(struct platform_device *pdev) 1484 { 1485 struct mmc_host *mmc; 1486 struct msdc_host *host; 1487 struct resource *res; 1488 int ret; 1489 1490 if (!pdev->dev.of_node) { 1491 dev_err(&pdev->dev, "No DT found\n"); 1492 return -EINVAL; 1493 } 1494 /* Allocate MMC host for this device */ 1495 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); 1496 if (!mmc) 1497 return -ENOMEM; 1498 1499 host = mmc_priv(mmc); 1500 ret = mmc_of_parse(mmc); 1501 if (ret) 1502 goto host_free; 1503 1504 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1505 host->base = devm_ioremap_resource(&pdev->dev, res); 1506 if (IS_ERR(host->base)) { 1507 ret = PTR_ERR(host->base); 1508 goto host_free; 1509 } 1510 1511 ret = mmc_regulator_get_supply(mmc); 1512 if (ret == -EPROBE_DEFER) 1513 goto host_free; 1514 1515 host->src_clk = devm_clk_get(&pdev->dev, "source"); 1516 if (IS_ERR(host->src_clk)) { 1517 ret = PTR_ERR(host->src_clk); 1518 goto host_free; 1519 } 1520 1521 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); 1522 if (IS_ERR(host->h_clk)) { 1523 ret = PTR_ERR(host->h_clk); 1524 goto host_free; 1525 } 1526 1527 host->irq = platform_get_irq(pdev, 0); 1528 if (host->irq < 0) { 1529 ret = -EINVAL; 1530 goto host_free; 1531 } 1532 1533 host->pinctrl = devm_pinctrl_get(&pdev->dev); 1534 if (IS_ERR(host->pinctrl)) { 1535 ret = PTR_ERR(host->pinctrl); 1536 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); 1537 goto host_free; 1538 } 1539 1540 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); 1541 if (IS_ERR(host->pins_default)) { 1542 ret = PTR_ERR(host->pins_default); 1543 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); 1544 goto host_free; 1545 } 1546 1547 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); 1548 if (IS_ERR(host->pins_uhs)) { 1549 ret = PTR_ERR(host->pins_uhs); 1550 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); 1551 goto host_free; 1552 } 1553 1554 if (!of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", 1555 &host->hs400_ds_delay)) 1556 dev_dbg(&pdev->dev, "hs400-ds-delay: %x\n", 1557 host->hs400_ds_delay); 1558 1559 host->dev = &pdev->dev; 1560 host->mmc = mmc; 1561 host->src_clk_freq = clk_get_rate(host->src_clk); 1562 /* Set host parameters to mmc */ 1563 mmc->ops = &mt_msdc_ops; 1564 mmc->f_min = host->src_clk_freq / (4 * 255); 1565 1566 mmc->caps |= MMC_CAP_ERASE | MMC_CAP_CMD23; 1567 /* MMC core transfer sizes tunable parameters */ 1568 mmc->max_segs = MAX_BD_NUM; 1569 mmc->max_seg_size = BDMA_DESC_BUFLEN; 1570 mmc->max_blk_size = 2048; 1571 mmc->max_req_size = 512 * 1024; 1572 mmc->max_blk_count = mmc->max_req_size / 512; 1573 host->dma_mask = DMA_BIT_MASK(32); 1574 mmc_dev(mmc)->dma_mask = &host->dma_mask; 1575 1576 host->timeout_clks = 3 * 1048576; 1577 host->dma.gpd = dma_alloc_coherent(&pdev->dev, 1578 2 * sizeof(struct mt_gpdma_desc), 1579 &host->dma.gpd_addr, GFP_KERNEL); 1580 host->dma.bd = dma_alloc_coherent(&pdev->dev, 1581 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1582 &host->dma.bd_addr, GFP_KERNEL); 1583 if (!host->dma.gpd || !host->dma.bd) { 1584 ret = -ENOMEM; 1585 goto release_mem; 1586 } 1587 msdc_init_gpd_bd(host, &host->dma); 1588 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); 1589 spin_lock_init(&host->lock); 1590 1591 platform_set_drvdata(pdev, mmc); 1592 msdc_ungate_clock(host); 1593 msdc_init_hw(host); 1594 1595 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, 1596 IRQF_TRIGGER_LOW | IRQF_ONESHOT, pdev->name, host); 1597 if (ret) 1598 goto release; 1599 1600 pm_runtime_set_active(host->dev); 1601 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); 1602 pm_runtime_use_autosuspend(host->dev); 1603 pm_runtime_enable(host->dev); 1604 ret = mmc_add_host(mmc); 1605 1606 if (ret) 1607 goto end; 1608 1609 return 0; 1610 end: 1611 pm_runtime_disable(host->dev); 1612 release: 1613 platform_set_drvdata(pdev, NULL); 1614 msdc_deinit_hw(host); 1615 msdc_gate_clock(host); 1616 release_mem: 1617 if (host->dma.gpd) 1618 dma_free_coherent(&pdev->dev, 1619 2 * sizeof(struct mt_gpdma_desc), 1620 host->dma.gpd, host->dma.gpd_addr); 1621 if (host->dma.bd) 1622 dma_free_coherent(&pdev->dev, 1623 MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1624 host->dma.bd, host->dma.bd_addr); 1625 host_free: 1626 mmc_free_host(mmc); 1627 1628 return ret; 1629 } 1630 1631 static int msdc_drv_remove(struct platform_device *pdev) 1632 { 1633 struct mmc_host *mmc; 1634 struct msdc_host *host; 1635 1636 mmc = platform_get_drvdata(pdev); 1637 host = mmc_priv(mmc); 1638 1639 pm_runtime_get_sync(host->dev); 1640 1641 platform_set_drvdata(pdev, NULL); 1642 mmc_remove_host(host->mmc); 1643 msdc_deinit_hw(host); 1644 msdc_gate_clock(host); 1645 1646 pm_runtime_disable(host->dev); 1647 pm_runtime_put_noidle(host->dev); 1648 dma_free_coherent(&pdev->dev, 1649 sizeof(struct mt_gpdma_desc), 1650 host->dma.gpd, host->dma.gpd_addr); 1651 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), 1652 host->dma.bd, host->dma.bd_addr); 1653 1654 mmc_free_host(host->mmc); 1655 1656 return 0; 1657 } 1658 1659 #ifdef CONFIG_PM 1660 static void msdc_save_reg(struct msdc_host *host) 1661 { 1662 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); 1663 host->save_para.iocon = readl(host->base + MSDC_IOCON); 1664 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); 1665 host->save_para.pad_tune = readl(host->base + MSDC_PAD_TUNE); 1666 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); 1667 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); 1668 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); 1669 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); 1670 } 1671 1672 static void msdc_restore_reg(struct msdc_host *host) 1673 { 1674 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); 1675 writel(host->save_para.iocon, host->base + MSDC_IOCON); 1676 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); 1677 writel(host->save_para.pad_tune, host->base + MSDC_PAD_TUNE); 1678 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); 1679 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); 1680 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); 1681 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); 1682 } 1683 1684 static int msdc_runtime_suspend(struct device *dev) 1685 { 1686 struct mmc_host *mmc = dev_get_drvdata(dev); 1687 struct msdc_host *host = mmc_priv(mmc); 1688 1689 msdc_save_reg(host); 1690 msdc_gate_clock(host); 1691 return 0; 1692 } 1693 1694 static int msdc_runtime_resume(struct device *dev) 1695 { 1696 struct mmc_host *mmc = dev_get_drvdata(dev); 1697 struct msdc_host *host = mmc_priv(mmc); 1698 1699 msdc_ungate_clock(host); 1700 msdc_restore_reg(host); 1701 return 0; 1702 } 1703 #endif 1704 1705 static const struct dev_pm_ops msdc_dev_pm_ops = { 1706 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1707 pm_runtime_force_resume) 1708 SET_RUNTIME_PM_OPS(msdc_runtime_suspend, msdc_runtime_resume, NULL) 1709 }; 1710 1711 static const struct of_device_id msdc_of_ids[] = { 1712 { .compatible = "mediatek,mt8135-mmc", }, 1713 {} 1714 }; 1715 MODULE_DEVICE_TABLE(of, msdc_of_ids); 1716 1717 static struct platform_driver mt_msdc_driver = { 1718 .probe = msdc_drv_probe, 1719 .remove = msdc_drv_remove, 1720 .driver = { 1721 .name = "mtk-msdc", 1722 .of_match_table = msdc_of_ids, 1723 .pm = &msdc_dev_pm_ops, 1724 }, 1725 }; 1726 1727 module_platform_driver(mt_msdc_driver); 1728 MODULE_LICENSE("GPL v2"); 1729 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver"); 1730