1 /* 2 * MOXA ART MMC host driver. 3 * 4 * Copyright (C) 2014 Jonas Jensen 5 * 6 * Jonas Jensen <jonas.jensen@gmail.com> 7 * 8 * Based on code from 9 * Moxa Technologies Co., Ltd. <www.moxa.com> 10 * 11 * This file is licensed under the terms of the GNU General Public 12 * License version 2. This program is licensed "as is" without any 13 * warranty of any kind, whether express or implied. 14 */ 15 16 #include <linux/module.h> 17 #include <linux/init.h> 18 #include <linux/platform_device.h> 19 #include <linux/delay.h> 20 #include <linux/errno.h> 21 #include <linux/interrupt.h> 22 #include <linux/blkdev.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/dmaengine.h> 25 #include <linux/mmc/host.h> 26 #include <linux/mmc/sd.h> 27 #include <linux/sched.h> 28 #include <linux/io.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/clk.h> 32 #include <linux/bitops.h> 33 #include <linux/of_dma.h> 34 #include <linux/spinlock.h> 35 36 #define REG_COMMAND 0 37 #define REG_ARGUMENT 4 38 #define REG_RESPONSE0 8 39 #define REG_RESPONSE1 12 40 #define REG_RESPONSE2 16 41 #define REG_RESPONSE3 20 42 #define REG_RESPONSE_COMMAND 24 43 #define REG_DATA_CONTROL 28 44 #define REG_DATA_TIMER 32 45 #define REG_DATA_LENGTH 36 46 #define REG_STATUS 40 47 #define REG_CLEAR 44 48 #define REG_INTERRUPT_MASK 48 49 #define REG_POWER_CONTROL 52 50 #define REG_CLOCK_CONTROL 56 51 #define REG_BUS_WIDTH 60 52 #define REG_DATA_WINDOW 64 53 #define REG_FEATURE 68 54 #define REG_REVISION 72 55 56 /* REG_COMMAND */ 57 #define CMD_SDC_RESET BIT(10) 58 #define CMD_EN BIT(9) 59 #define CMD_APP_CMD BIT(8) 60 #define CMD_LONG_RSP BIT(7) 61 #define CMD_NEED_RSP BIT(6) 62 #define CMD_IDX_MASK 0x3f 63 64 /* REG_RESPONSE_COMMAND */ 65 #define RSP_CMD_APP BIT(6) 66 #define RSP_CMD_IDX_MASK 0x3f 67 68 /* REG_DATA_CONTROL */ 69 #define DCR_DATA_FIFO_RESET BIT(8) 70 #define DCR_DATA_THRES BIT(7) 71 #define DCR_DATA_EN BIT(6) 72 #define DCR_DMA_EN BIT(5) 73 #define DCR_DATA_WRITE BIT(4) 74 #define DCR_BLK_SIZE 0x0f 75 76 /* REG_DATA_LENGTH */ 77 #define DATA_LEN_MASK 0xffffff 78 79 /* REG_STATUS */ 80 #define WRITE_PROT BIT(12) 81 #define CARD_DETECT BIT(11) 82 /* 1-10 below can be sent to either registers, interrupt or clear. */ 83 #define CARD_CHANGE BIT(10) 84 #define FIFO_ORUN BIT(9) 85 #define FIFO_URUN BIT(8) 86 #define DATA_END BIT(7) 87 #define CMD_SENT BIT(6) 88 #define DATA_CRC_OK BIT(5) 89 #define RSP_CRC_OK BIT(4) 90 #define DATA_TIMEOUT BIT(3) 91 #define RSP_TIMEOUT BIT(2) 92 #define DATA_CRC_FAIL BIT(1) 93 #define RSP_CRC_FAIL BIT(0) 94 95 #define MASK_RSP (RSP_TIMEOUT | RSP_CRC_FAIL | \ 96 RSP_CRC_OK | CARD_DETECT | CMD_SENT) 97 98 #define MASK_DATA (DATA_CRC_OK | DATA_END | \ 99 DATA_CRC_FAIL | DATA_TIMEOUT) 100 101 #define MASK_INTR_PIO (FIFO_URUN | FIFO_ORUN | CARD_CHANGE) 102 103 /* REG_POWER_CONTROL */ 104 #define SD_POWER_ON BIT(4) 105 #define SD_POWER_MASK 0x0f 106 107 /* REG_CLOCK_CONTROL */ 108 #define CLK_HISPD BIT(9) 109 #define CLK_OFF BIT(8) 110 #define CLK_SD BIT(7) 111 #define CLK_DIV_MASK 0x7f 112 113 /* REG_BUS_WIDTH */ 114 #define BUS_WIDTH_4_SUPPORT BIT(3) 115 #define BUS_WIDTH_4 BIT(2) 116 #define BUS_WIDTH_1 BIT(0) 117 118 #define MMC_VDD_360 23 119 #define MIN_POWER (MMC_VDD_360 - SD_POWER_MASK) 120 #define MAX_RETRIES 500000 121 122 struct moxart_host { 123 spinlock_t lock; 124 125 void __iomem *base; 126 127 phys_addr_t reg_phys; 128 129 struct dma_chan *dma_chan_tx; 130 struct dma_chan *dma_chan_rx; 131 struct dma_async_tx_descriptor *tx_desc; 132 struct mmc_host *mmc; 133 struct mmc_request *mrq; 134 struct completion dma_complete; 135 struct completion pio_complete; 136 137 struct sg_mapping_iter sg_miter; 138 u32 data_len; 139 u32 fifo_width; 140 u32 timeout; 141 u32 rate; 142 143 long sysclk; 144 145 bool have_dma; 146 bool is_removed; 147 }; 148 149 static int moxart_wait_for_status(struct moxart_host *host, 150 u32 mask, u32 *status) 151 { 152 int ret = -ETIMEDOUT; 153 u32 i; 154 155 for (i = 0; i < MAX_RETRIES; i++) { 156 *status = readl(host->base + REG_STATUS); 157 if (!(*status & mask)) { 158 udelay(5); 159 continue; 160 } 161 writel(*status & mask, host->base + REG_CLEAR); 162 ret = 0; 163 break; 164 } 165 166 if (ret) 167 dev_err(mmc_dev(host->mmc), "timed out waiting for status\n"); 168 169 return ret; 170 } 171 172 173 static void moxart_send_command(struct moxart_host *host, 174 struct mmc_command *cmd) 175 { 176 u32 status, cmdctrl; 177 178 writel(RSP_TIMEOUT | RSP_CRC_OK | 179 RSP_CRC_FAIL | CMD_SENT, host->base + REG_CLEAR); 180 writel(cmd->arg, host->base + REG_ARGUMENT); 181 182 cmdctrl = cmd->opcode & CMD_IDX_MASK; 183 if (cmdctrl == SD_APP_SET_BUS_WIDTH || cmdctrl == SD_APP_OP_COND || 184 cmdctrl == SD_APP_SEND_SCR || cmdctrl == SD_APP_SD_STATUS || 185 cmdctrl == SD_APP_SEND_NUM_WR_BLKS) 186 cmdctrl |= CMD_APP_CMD; 187 188 if (cmd->flags & MMC_RSP_PRESENT) 189 cmdctrl |= CMD_NEED_RSP; 190 191 if (cmd->flags & MMC_RSP_136) 192 cmdctrl |= CMD_LONG_RSP; 193 194 writel(cmdctrl | CMD_EN, host->base + REG_COMMAND); 195 196 if (moxart_wait_for_status(host, MASK_RSP, &status) == -ETIMEDOUT) 197 cmd->error = -ETIMEDOUT; 198 199 if (status & RSP_TIMEOUT) { 200 cmd->error = -ETIMEDOUT; 201 return; 202 } 203 if (status & RSP_CRC_FAIL) { 204 cmd->error = -EIO; 205 return; 206 } 207 if (status & RSP_CRC_OK) { 208 if (cmd->flags & MMC_RSP_136) { 209 cmd->resp[3] = readl(host->base + REG_RESPONSE0); 210 cmd->resp[2] = readl(host->base + REG_RESPONSE1); 211 cmd->resp[1] = readl(host->base + REG_RESPONSE2); 212 cmd->resp[0] = readl(host->base + REG_RESPONSE3); 213 } else { 214 cmd->resp[0] = readl(host->base + REG_RESPONSE0); 215 } 216 } 217 } 218 219 static void moxart_dma_complete(void *param) 220 { 221 struct moxart_host *host = param; 222 223 complete(&host->dma_complete); 224 } 225 226 static bool moxart_use_dma(struct moxart_host *host) 227 { 228 return (host->data_len > host->fifo_width) && host->have_dma; 229 } 230 231 static void moxart_transfer_dma(struct mmc_data *data, struct moxart_host *host) 232 { 233 u32 len, dir_slave; 234 struct dma_async_tx_descriptor *desc = NULL; 235 struct dma_chan *dma_chan; 236 237 if (host->data_len == data->bytes_xfered) 238 return; 239 240 if (data->flags & MMC_DATA_WRITE) { 241 dma_chan = host->dma_chan_tx; 242 dir_slave = DMA_MEM_TO_DEV; 243 } else { 244 dma_chan = host->dma_chan_rx; 245 dir_slave = DMA_DEV_TO_MEM; 246 } 247 248 len = dma_map_sg(dma_chan->device->dev, data->sg, 249 data->sg_len, mmc_get_dma_dir(data)); 250 251 if (len > 0) { 252 desc = dmaengine_prep_slave_sg(dma_chan, data->sg, 253 len, dir_slave, 254 DMA_PREP_INTERRUPT | 255 DMA_CTRL_ACK); 256 } else { 257 dev_err(mmc_dev(host->mmc), "dma_map_sg returned zero length\n"); 258 } 259 260 if (desc) { 261 host->tx_desc = desc; 262 desc->callback = moxart_dma_complete; 263 desc->callback_param = host; 264 dmaengine_submit(desc); 265 dma_async_issue_pending(dma_chan); 266 } 267 268 wait_for_completion_interruptible_timeout(&host->dma_complete, 269 host->timeout); 270 271 data->bytes_xfered = host->data_len; 272 273 dma_unmap_sg(dma_chan->device->dev, 274 data->sg, data->sg_len, 275 mmc_get_dma_dir(data)); 276 } 277 278 279 static void moxart_transfer_pio(struct moxart_host *host) 280 { 281 struct sg_mapping_iter *sgm = &host->sg_miter; 282 struct mmc_data *data = host->mrq->cmd->data; 283 u32 *sgp, len = 0, remain, status; 284 285 if (host->data_len == data->bytes_xfered) 286 return; 287 288 /* 289 * By updating sgm->consumes this will get a proper pointer into the 290 * buffer at any time. 291 */ 292 if (!sg_miter_next(sgm)) { 293 /* This shold not happen */ 294 dev_err(mmc_dev(host->mmc), "ran out of scatterlist prematurely\n"); 295 data->error = -EINVAL; 296 complete(&host->pio_complete); 297 return; 298 } 299 sgp = sgm->addr; 300 remain = sgm->length; 301 if (remain > host->data_len) 302 remain = host->data_len; 303 sgm->consumed = 0; 304 305 if (data->flags & MMC_DATA_WRITE) { 306 while (remain > 0) { 307 if (moxart_wait_for_status(host, FIFO_URUN, &status) 308 == -ETIMEDOUT) { 309 data->error = -ETIMEDOUT; 310 complete(&host->pio_complete); 311 return; 312 } 313 for (len = 0; len < remain && len < host->fifo_width;) { 314 iowrite32(*sgp, host->base + REG_DATA_WINDOW); 315 sgp++; 316 len += 4; 317 } 318 sgm->consumed += len; 319 remain -= len; 320 } 321 322 } else { 323 while (remain > 0) { 324 if (moxart_wait_for_status(host, FIFO_ORUN, &status) 325 == -ETIMEDOUT) { 326 data->error = -ETIMEDOUT; 327 complete(&host->pio_complete); 328 return; 329 } 330 for (len = 0; len < remain && len < host->fifo_width;) { 331 *sgp = ioread32(host->base + REG_DATA_WINDOW); 332 sgp++; 333 len += 4; 334 } 335 sgm->consumed += len; 336 remain -= len; 337 } 338 } 339 340 data->bytes_xfered += sgm->consumed; 341 if (host->data_len == data->bytes_xfered) { 342 complete(&host->pio_complete); 343 return; 344 } 345 } 346 347 static void moxart_prepare_data(struct moxart_host *host) 348 { 349 struct mmc_data *data = host->mrq->cmd->data; 350 unsigned int flags = SG_MITER_ATOMIC; /* Used from IRQ */ 351 u32 datactrl; 352 int blksz_bits; 353 354 if (!data) 355 return; 356 357 host->data_len = data->blocks * data->blksz; 358 blksz_bits = ffs(data->blksz) - 1; 359 BUG_ON(1 << blksz_bits != data->blksz); 360 361 datactrl = DCR_DATA_EN | (blksz_bits & DCR_BLK_SIZE); 362 363 if (data->flags & MMC_DATA_WRITE) { 364 flags |= SG_MITER_FROM_SG; 365 datactrl |= DCR_DATA_WRITE; 366 } else { 367 flags |= SG_MITER_TO_SG; 368 } 369 370 if (moxart_use_dma(host)) 371 datactrl |= DCR_DMA_EN; 372 else 373 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); 374 375 writel(DCR_DATA_FIFO_RESET, host->base + REG_DATA_CONTROL); 376 writel(MASK_DATA | FIFO_URUN | FIFO_ORUN, host->base + REG_CLEAR); 377 writel(host->rate, host->base + REG_DATA_TIMER); 378 writel(host->data_len, host->base + REG_DATA_LENGTH); 379 writel(datactrl, host->base + REG_DATA_CONTROL); 380 } 381 382 static void moxart_request(struct mmc_host *mmc, struct mmc_request *mrq) 383 { 384 struct moxart_host *host = mmc_priv(mmc); 385 unsigned long flags; 386 u32 status; 387 388 spin_lock_irqsave(&host->lock, flags); 389 390 init_completion(&host->dma_complete); 391 init_completion(&host->pio_complete); 392 393 host->mrq = mrq; 394 395 if (readl(host->base + REG_STATUS) & CARD_DETECT) { 396 mrq->cmd->error = -ETIMEDOUT; 397 goto request_done; 398 } 399 400 moxart_prepare_data(host); 401 moxart_send_command(host, host->mrq->cmd); 402 403 if (mrq->cmd->data) { 404 if (moxart_use_dma(host)) { 405 406 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); 407 408 spin_unlock_irqrestore(&host->lock, flags); 409 410 moxart_transfer_dma(mrq->cmd->data, host); 411 412 spin_lock_irqsave(&host->lock, flags); 413 } else { 414 415 writel(MASK_INTR_PIO, host->base + REG_INTERRUPT_MASK); 416 417 spin_unlock_irqrestore(&host->lock, flags); 418 419 /* PIO transfers start from interrupt. */ 420 wait_for_completion_interruptible_timeout(&host->pio_complete, 421 host->timeout); 422 423 spin_lock_irqsave(&host->lock, flags); 424 } 425 426 if (host->is_removed) { 427 dev_err(mmc_dev(host->mmc), "card removed\n"); 428 mrq->cmd->error = -ETIMEDOUT; 429 goto request_done; 430 } 431 432 if (moxart_wait_for_status(host, MASK_DATA, &status) 433 == -ETIMEDOUT) { 434 mrq->cmd->data->error = -ETIMEDOUT; 435 goto request_done; 436 } 437 438 if (status & DATA_CRC_FAIL) 439 mrq->cmd->data->error = -ETIMEDOUT; 440 441 if (mrq->cmd->data->stop) 442 moxart_send_command(host, mrq->cmd->data->stop); 443 } 444 445 request_done: 446 if (!moxart_use_dma(host)) 447 sg_miter_stop(&host->sg_miter); 448 449 spin_unlock_irqrestore(&host->lock, flags); 450 mmc_request_done(host->mmc, mrq); 451 } 452 453 static irqreturn_t moxart_irq(int irq, void *devid) 454 { 455 struct moxart_host *host = (struct moxart_host *)devid; 456 u32 status; 457 458 spin_lock(&host->lock); 459 460 status = readl(host->base + REG_STATUS); 461 if (status & CARD_CHANGE) { 462 host->is_removed = status & CARD_DETECT; 463 if (host->is_removed && host->have_dma) { 464 dmaengine_terminate_all(host->dma_chan_tx); 465 dmaengine_terminate_all(host->dma_chan_rx); 466 } 467 host->mrq = NULL; 468 writel(MASK_INTR_PIO, host->base + REG_CLEAR); 469 writel(CARD_CHANGE, host->base + REG_INTERRUPT_MASK); 470 mmc_detect_change(host->mmc, 0); 471 } 472 if (status & (FIFO_ORUN | FIFO_URUN) && host->mrq) 473 moxart_transfer_pio(host); 474 475 spin_unlock(&host->lock); 476 477 return IRQ_HANDLED; 478 } 479 480 static void moxart_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 481 { 482 struct moxart_host *host = mmc_priv(mmc); 483 unsigned long flags; 484 u8 power, div; 485 u32 ctrl; 486 487 spin_lock_irqsave(&host->lock, flags); 488 489 if (ios->clock) { 490 for (div = 0; div < CLK_DIV_MASK; ++div) { 491 if (ios->clock >= host->sysclk / (2 * (div + 1))) 492 break; 493 } 494 ctrl = CLK_SD | div; 495 host->rate = host->sysclk / (2 * (div + 1)); 496 if (host->rate > host->sysclk) 497 ctrl |= CLK_HISPD; 498 writel(ctrl, host->base + REG_CLOCK_CONTROL); 499 } 500 501 if (ios->power_mode == MMC_POWER_OFF) { 502 writel(readl(host->base + REG_POWER_CONTROL) & ~SD_POWER_ON, 503 host->base + REG_POWER_CONTROL); 504 } else { 505 if (ios->vdd < MIN_POWER) 506 power = 0; 507 else 508 power = ios->vdd - MIN_POWER; 509 510 writel(SD_POWER_ON | (u32) power, 511 host->base + REG_POWER_CONTROL); 512 } 513 514 switch (ios->bus_width) { 515 case MMC_BUS_WIDTH_4: 516 writel(BUS_WIDTH_4, host->base + REG_BUS_WIDTH); 517 break; 518 default: 519 writel(BUS_WIDTH_1, host->base + REG_BUS_WIDTH); 520 break; 521 } 522 523 spin_unlock_irqrestore(&host->lock, flags); 524 } 525 526 527 static int moxart_get_ro(struct mmc_host *mmc) 528 { 529 struct moxart_host *host = mmc_priv(mmc); 530 531 return !!(readl(host->base + REG_STATUS) & WRITE_PROT); 532 } 533 534 static const struct mmc_host_ops moxart_ops = { 535 .request = moxart_request, 536 .set_ios = moxart_set_ios, 537 .get_ro = moxart_get_ro, 538 }; 539 540 static int moxart_probe(struct platform_device *pdev) 541 { 542 struct device *dev = &pdev->dev; 543 struct device_node *node = dev->of_node; 544 struct resource res_mmc; 545 struct mmc_host *mmc; 546 struct moxart_host *host = NULL; 547 struct dma_slave_config cfg; 548 struct clk *clk; 549 void __iomem *reg_mmc; 550 int irq, ret; 551 u32 i; 552 553 mmc = mmc_alloc_host(sizeof(struct moxart_host), dev); 554 if (!mmc) { 555 dev_err(dev, "mmc_alloc_host failed\n"); 556 ret = -ENOMEM; 557 goto out_mmc; 558 } 559 560 ret = of_address_to_resource(node, 0, &res_mmc); 561 if (ret) { 562 dev_err(dev, "of_address_to_resource failed\n"); 563 goto out_mmc; 564 } 565 566 irq = irq_of_parse_and_map(node, 0); 567 if (irq <= 0) { 568 dev_err(dev, "irq_of_parse_and_map failed\n"); 569 ret = -EINVAL; 570 goto out_mmc; 571 } 572 573 clk = devm_clk_get(dev, NULL); 574 if (IS_ERR(clk)) { 575 ret = PTR_ERR(clk); 576 goto out_mmc; 577 } 578 579 reg_mmc = devm_ioremap_resource(dev, &res_mmc); 580 if (IS_ERR(reg_mmc)) { 581 ret = PTR_ERR(reg_mmc); 582 goto out_mmc; 583 } 584 585 ret = mmc_of_parse(mmc); 586 if (ret) 587 goto out_mmc; 588 589 host = mmc_priv(mmc); 590 host->mmc = mmc; 591 host->base = reg_mmc; 592 host->reg_phys = res_mmc.start; 593 host->timeout = msecs_to_jiffies(1000); 594 host->sysclk = clk_get_rate(clk); 595 host->fifo_width = readl(host->base + REG_FEATURE) << 2; 596 host->dma_chan_tx = dma_request_chan(dev, "tx"); 597 host->dma_chan_rx = dma_request_chan(dev, "rx"); 598 599 spin_lock_init(&host->lock); 600 601 mmc->ops = &moxart_ops; 602 mmc->f_max = DIV_ROUND_CLOSEST(host->sysclk, 2); 603 mmc->f_min = DIV_ROUND_CLOSEST(host->sysclk, CLK_DIV_MASK * 2); 604 mmc->ocr_avail = 0xffff00; /* Support 2.0v - 3.6v power. */ 605 mmc->max_blk_size = 2048; /* Max. block length in REG_DATA_CONTROL */ 606 mmc->max_req_size = DATA_LEN_MASK; /* bits 0-23 in REG_DATA_LENGTH */ 607 mmc->max_blk_count = mmc->max_req_size / 512; 608 609 if (IS_ERR(host->dma_chan_tx) || IS_ERR(host->dma_chan_rx)) { 610 if (PTR_ERR(host->dma_chan_tx) == -EPROBE_DEFER || 611 PTR_ERR(host->dma_chan_rx) == -EPROBE_DEFER) { 612 ret = -EPROBE_DEFER; 613 goto out; 614 } 615 if (!IS_ERR(host->dma_chan_tx)) { 616 dma_release_channel(host->dma_chan_tx); 617 host->dma_chan_tx = NULL; 618 } 619 if (!IS_ERR(host->dma_chan_rx)) { 620 dma_release_channel(host->dma_chan_rx); 621 host->dma_chan_rx = NULL; 622 } 623 dev_dbg(dev, "PIO mode transfer enabled\n"); 624 host->have_dma = false; 625 626 mmc->max_seg_size = mmc->max_req_size; 627 } else { 628 dev_dbg(dev, "DMA channels found (%p,%p)\n", 629 host->dma_chan_tx, host->dma_chan_rx); 630 host->have_dma = true; 631 632 memset(&cfg, 0, sizeof(cfg)); 633 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 634 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 635 636 cfg.direction = DMA_MEM_TO_DEV; 637 cfg.src_addr = 0; 638 cfg.dst_addr = host->reg_phys + REG_DATA_WINDOW; 639 dmaengine_slave_config(host->dma_chan_tx, &cfg); 640 641 cfg.direction = DMA_DEV_TO_MEM; 642 cfg.src_addr = host->reg_phys + REG_DATA_WINDOW; 643 cfg.dst_addr = 0; 644 dmaengine_slave_config(host->dma_chan_rx, &cfg); 645 646 mmc->max_seg_size = min3(mmc->max_req_size, 647 dma_get_max_seg_size(host->dma_chan_rx->device->dev), 648 dma_get_max_seg_size(host->dma_chan_tx->device->dev)); 649 } 650 651 if (readl(host->base + REG_BUS_WIDTH) & BUS_WIDTH_4_SUPPORT) 652 mmc->caps |= MMC_CAP_4_BIT_DATA; 653 654 writel(0, host->base + REG_INTERRUPT_MASK); 655 656 writel(CMD_SDC_RESET, host->base + REG_COMMAND); 657 for (i = 0; i < MAX_RETRIES; i++) { 658 if (!(readl(host->base + REG_COMMAND) & CMD_SDC_RESET)) 659 break; 660 udelay(5); 661 } 662 663 ret = devm_request_irq(dev, irq, moxart_irq, 0, "moxart-mmc", host); 664 if (ret) 665 goto out; 666 667 dev_set_drvdata(dev, mmc); 668 ret = mmc_add_host(mmc); 669 if (ret) 670 goto out; 671 672 dev_dbg(dev, "IRQ=%d, FIFO is %d bytes\n", irq, host->fifo_width); 673 674 return 0; 675 676 out: 677 if (!IS_ERR_OR_NULL(host->dma_chan_tx)) 678 dma_release_channel(host->dma_chan_tx); 679 if (!IS_ERR_OR_NULL(host->dma_chan_rx)) 680 dma_release_channel(host->dma_chan_rx); 681 out_mmc: 682 if (mmc) 683 mmc_free_host(mmc); 684 return ret; 685 } 686 687 static void moxart_remove(struct platform_device *pdev) 688 { 689 struct mmc_host *mmc = dev_get_drvdata(&pdev->dev); 690 struct moxart_host *host = mmc_priv(mmc); 691 692 if (!IS_ERR_OR_NULL(host->dma_chan_tx)) 693 dma_release_channel(host->dma_chan_tx); 694 if (!IS_ERR_OR_NULL(host->dma_chan_rx)) 695 dma_release_channel(host->dma_chan_rx); 696 mmc_remove_host(mmc); 697 698 writel(0, host->base + REG_INTERRUPT_MASK); 699 writel(0, host->base + REG_POWER_CONTROL); 700 writel(readl(host->base + REG_CLOCK_CONTROL) | CLK_OFF, 701 host->base + REG_CLOCK_CONTROL); 702 mmc_free_host(mmc); 703 } 704 705 static const struct of_device_id moxart_mmc_match[] = { 706 { .compatible = "moxa,moxart-mmc" }, 707 { .compatible = "faraday,ftsdc010" }, 708 { } 709 }; 710 MODULE_DEVICE_TABLE(of, moxart_mmc_match); 711 712 static struct platform_driver moxart_mmc_driver = { 713 .probe = moxart_probe, 714 .remove_new = moxart_remove, 715 .driver = { 716 .name = "mmc-moxart", 717 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 718 .of_match_table = moxart_mmc_match, 719 }, 720 }; 721 module_platform_driver(moxart_mmc_driver); 722 723 MODULE_ALIAS("platform:mmc-moxart"); 724 MODULE_DESCRIPTION("MOXA ART MMC driver"); 725 MODULE_LICENSE("GPL v2"); 726 MODULE_AUTHOR("Jonas Jensen <jonas.jensen@gmail.com>"); 727